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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #ifndef __RADEON_ASIC_H__ |
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29 | #define __RADEON_ASIC_H__ |
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30 | |||
31 | /* |
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32 | * common functions |
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33 | */ |
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34 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
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35 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
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36 | |||
37 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
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38 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
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39 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
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40 | |||
41 | /* |
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42 | * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
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43 | */ |
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1221 | serge | 44 | extern int r100_init(struct radeon_device *rdev); |
45 | extern void r100_fini(struct radeon_device *rdev); |
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46 | extern int r100_suspend(struct radeon_device *rdev); |
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47 | extern int r100_resume(struct radeon_device *rdev); |
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1117 | serge | 48 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
49 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1179 | serge | 50 | void r100_vga_set_state(struct radeon_device *rdev, bool state); |
1117 | serge | 51 | int r100_gpu_reset(struct radeon_device *rdev); |
1179 | serge | 52 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
1117 | serge | 53 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
54 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
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1179 | serge | 55 | void r100_cp_commit(struct radeon_device *rdev); |
1117 | serge | 56 | void r100_ring_start(struct radeon_device *rdev); |
57 | int r100_irq_set(struct radeon_device *rdev); |
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58 | int r100_irq_process(struct radeon_device *rdev); |
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1128 | serge | 59 | void r100_fence_ring_emit(struct radeon_device *rdev, |
60 | struct radeon_fence *fence); |
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61 | int r100_cs_parse(struct radeon_cs_parser *p); |
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1117 | serge | 62 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
63 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); |
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1128 | serge | 64 | int r100_copy_blit(struct radeon_device *rdev, |
65 | uint64_t src_offset, |
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66 | uint64_t dst_offset, |
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67 | unsigned num_pages, |
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68 | struct radeon_fence *fence); |
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1179 | serge | 69 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
70 | uint32_t tiling_flags, uint32_t pitch, |
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71 | uint32_t offset, uint32_t obj_size); |
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72 | int r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
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73 | void r100_bandwidth_update(struct radeon_device *rdev); |
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74 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
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75 | int r100_ring_test(struct radeon_device *rdev); |
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1117 | serge | 76 | |
77 | static struct radeon_asic r100_asic = { |
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78 | .init = &r100_init, |
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1221 | serge | 79 | // .fini = &r100_fini, |
80 | // .suspend = &r100_suspend, |
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81 | // .resume = &r100_resume, |
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82 | // .vga_set_state = &r100_vga_set_state, |
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1117 | serge | 83 | .gpu_reset = &r100_gpu_reset, |
84 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
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85 | .gart_set_page = &r100_pci_gart_set_page, |
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1221 | serge | 86 | .cp_commit = &r100_cp_commit, |
87 | // .ring_start = &r100_ring_start, |
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88 | // .ring_test = &r100_ring_test, |
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89 | // .ring_ib_execute = &r100_ring_ib_execute, |
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90 | // .irq_set = &r100_irq_set, |
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91 | // .irq_process = &r100_irq_process, |
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92 | // .get_vblank_counter = &r100_get_vblank_counter, |
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93 | // .fence_ring_emit = &r100_fence_ring_emit, |
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94 | // .cs_parse = &r100_cs_parse, |
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95 | // .copy_blit = &r100_copy_blit, |
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96 | // .copy_dma = NULL, |
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97 | // .copy = &r100_copy_blit, |
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98 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
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99 | .set_memory_clock = NULL, |
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100 | .set_pcie_lanes = NULL, |
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101 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
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1179 | serge | 102 | .set_surface_reg = r100_set_surface_reg, |
103 | .clear_surface_reg = r100_clear_surface_reg, |
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104 | .bandwidth_update = &r100_bandwidth_update, |
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1117 | serge | 105 | }; |
106 | |||
107 | |||
108 | /* |
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109 | * r300,r350,rv350,rv380 |
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110 | */ |
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1221 | serge | 111 | extern int r300_init(struct radeon_device *rdev); |
112 | extern void r300_fini(struct radeon_device *rdev); |
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113 | extern int r300_suspend(struct radeon_device *rdev); |
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114 | extern int r300_resume(struct radeon_device *rdev); |
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115 | extern int r300_gpu_reset(struct radeon_device *rdev); |
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116 | extern void r300_ring_start(struct radeon_device *rdev); |
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117 | extern void r300_fence_ring_emit(struct radeon_device *rdev, |
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1128 | serge | 118 | struct radeon_fence *fence); |
1221 | serge | 119 | extern int r300_cs_parse(struct radeon_cs_parser *p); |
120 | extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
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121 | extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
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122 | extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
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123 | extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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124 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
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125 | extern int r300_copy_dma(struct radeon_device *rdev, |
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1128 | serge | 126 | uint64_t src_offset, |
127 | uint64_t dst_offset, |
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128 | unsigned num_pages, |
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129 | struct radeon_fence *fence); |
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1117 | serge | 130 | static struct radeon_asic r300_asic = { |
131 | .init = &r300_init, |
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1221 | serge | 132 | // .fini = &r300_fini, |
133 | // .suspend = &r300_suspend, |
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134 | // .resume = &r300_resume, |
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135 | // .vga_set_state = &r100_vga_set_state, |
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1117 | serge | 136 | .gpu_reset = &r300_gpu_reset, |
137 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
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138 | .gart_set_page = &r100_pci_gart_set_page, |
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1221 | serge | 139 | // .cp_commit = &r100_cp_commit, |
140 | // .ring_start = &r300_ring_start, |
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141 | // .ring_test = &r100_ring_test, |
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142 | // .ring_ib_execute = &r100_ring_ib_execute, |
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143 | // .irq_set = &r100_irq_set, |
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144 | // .irq_process = &r100_irq_process, |
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145 | // .get_vblank_counter = &r100_get_vblank_counter, |
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146 | // .fence_ring_emit = &r300_fence_ring_emit, |
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147 | // .cs_parse = &r300_cs_parse, |
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148 | // .copy_blit = &r100_copy_blit, |
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149 | // .copy_dma = &r300_copy_dma, |
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150 | // .copy = &r100_copy_blit, |
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151 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
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152 | .set_memory_clock = NULL, |
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153 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
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154 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
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1179 | serge | 155 | .set_surface_reg = r100_set_surface_reg, |
156 | .clear_surface_reg = r100_clear_surface_reg, |
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157 | .bandwidth_update = &r100_bandwidth_update, |
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1117 | serge | 158 | }; |
159 | |||
160 | /* |
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161 | * r420,r423,rv410 |
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162 | */ |
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1179 | serge | 163 | extern int r420_init(struct radeon_device *rdev); |
164 | extern void r420_fini(struct radeon_device *rdev); |
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165 | extern int r420_suspend(struct radeon_device *rdev); |
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166 | extern int r420_resume(struct radeon_device *rdev); |
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1117 | serge | 167 | static struct radeon_asic r420_asic = { |
1179 | serge | 168 | .init = &r420_init, |
1221 | serge | 169 | // .fini = &r420_fini, |
170 | // .suspend = &r420_suspend, |
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171 | // .resume = &r420_resume, |
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172 | // .vga_set_state = &r100_vga_set_state, |
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1117 | serge | 173 | .gpu_reset = &r300_gpu_reset, |
174 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
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175 | .gart_set_page = &rv370_pcie_gart_set_page, |
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1221 | serge | 176 | // .cp_commit = &r100_cp_commit, |
177 | // .ring_start = &r300_ring_start, |
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178 | // .ring_test = &r100_ring_test, |
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179 | // .ring_ib_execute = &r100_ring_ib_execute, |
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180 | // .irq_set = &r100_irq_set, |
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181 | // .irq_process = &r100_irq_process, |
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182 | // .get_vblank_counter = &r100_get_vblank_counter, |
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183 | // .fence_ring_emit = &r300_fence_ring_emit, |
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184 | // .cs_parse = &r300_cs_parse, |
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185 | // .copy_blit = &r100_copy_blit, |
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186 | // .copy_dma = &r300_copy_dma, |
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187 | // .copy = &r100_copy_blit, |
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188 | .set_engine_clock = &radeon_atom_set_engine_clock, |
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189 | .set_memory_clock = &radeon_atom_set_memory_clock, |
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190 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
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191 | .set_clock_gating = &radeon_atom_set_clock_gating, |
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1179 | serge | 192 | .set_surface_reg = r100_set_surface_reg, |
193 | .clear_surface_reg = r100_clear_surface_reg, |
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194 | .bandwidth_update = &r100_bandwidth_update, |
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1117 | serge | 195 | }; |
196 | |||
197 | |||
198 | /* |
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199 | * rs400,rs480 |
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200 | */ |
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1221 | serge | 201 | extern int rs400_init(struct radeon_device *rdev); |
202 | extern void rs400_fini(struct radeon_device *rdev); |
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203 | extern int rs400_suspend(struct radeon_device *rdev); |
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204 | extern int rs400_resume(struct radeon_device *rdev); |
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1117 | serge | 205 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
206 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
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207 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
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208 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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209 | static struct radeon_asic rs400_asic = { |
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1221 | serge | 210 | .init = &rs400_init, |
211 | // .fini = &rs400_fini, |
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212 | // .suspend = &rs400_suspend, |
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213 | // .resume = &rs400_resume, |
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214 | // .vga_set_state = &r100_vga_set_state, |
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1117 | serge | 215 | .gpu_reset = &r300_gpu_reset, |
216 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
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217 | .gart_set_page = &rs400_gart_set_page, |
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1221 | serge | 218 | // .cp_commit = &r100_cp_commit, |
219 | // .ring_start = &r300_ring_start, |
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220 | // .ring_test = &r100_ring_test, |
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221 | // .ring_ib_execute = &r100_ring_ib_execute, |
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222 | // .irq_set = &r100_irq_set, |
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223 | // .irq_process = &r100_irq_process, |
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224 | // .get_vblank_counter = &r100_get_vblank_counter, |
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225 | // .fence_ring_emit = &r300_fence_ring_emit, |
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226 | // .cs_parse = &r300_cs_parse, |
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227 | // .copy_blit = &r100_copy_blit, |
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228 | // .copy_dma = &r300_copy_dma, |
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229 | // .copy = &r100_copy_blit, |
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230 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
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231 | .set_memory_clock = NULL, |
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232 | .set_pcie_lanes = NULL, |
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233 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
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1179 | serge | 234 | .set_surface_reg = r100_set_surface_reg, |
235 | .clear_surface_reg = r100_clear_surface_reg, |
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236 | .bandwidth_update = &r100_bandwidth_update, |
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1117 | serge | 237 | }; |
238 | |||
239 | |||
240 | /* |
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241 | * rs600. |
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242 | */ |
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1221 | serge | 243 | extern int rs600_init(struct radeon_device *rdev); |
244 | extern void rs600_fini(struct radeon_device *rdev); |
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245 | extern int rs600_suspend(struct radeon_device *rdev); |
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246 | extern int rs600_resume(struct radeon_device *rdev); |
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1117 | serge | 247 | int rs600_irq_set(struct radeon_device *rdev); |
1179 | serge | 248 | int rs600_irq_process(struct radeon_device *rdev); |
249 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
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1117 | serge | 250 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
251 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
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252 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
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253 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1179 | serge | 254 | void rs600_bandwidth_update(struct radeon_device *rdev); |
1117 | serge | 255 | static struct radeon_asic rs600_asic = { |
1179 | serge | 256 | .init = &rs600_init, |
1221 | serge | 257 | // .fini = &rs600_fini, |
258 | // .suspend = &rs600_suspend, |
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259 | // .resume = &rs600_resume, |
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260 | // .vga_set_state = &r100_vga_set_state, |
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1117 | serge | 261 | .gpu_reset = &r300_gpu_reset, |
262 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
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263 | .gart_set_page = &rs600_gart_set_page, |
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1221 | serge | 264 | // .cp_commit = &r100_cp_commit, |
265 | // .ring_start = &r300_ring_start, |
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266 | // .ring_test = &r100_ring_test, |
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267 | // .ring_ib_execute = &r100_ring_ib_execute, |
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268 | // .irq_set = &rs600_irq_set, |
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269 | // .irq_process = &rs600_irq_process, |
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270 | // .get_vblank_counter = &rs600_get_vblank_counter, |
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1117 | serge | 271 | // .fence_ring_emit = &r300_fence_ring_emit, |
272 | // .cs_parse = &r300_cs_parse, |
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273 | // .copy_blit = &r100_copy_blit, |
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274 | // .copy_dma = &r300_copy_dma, |
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275 | // .copy = &r100_copy_blit, |
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1221 | serge | 276 | .set_engine_clock = &radeon_atom_set_engine_clock, |
277 | .set_memory_clock = &radeon_atom_set_memory_clock, |
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278 | .set_pcie_lanes = NULL, |
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279 | .set_clock_gating = &radeon_atom_set_clock_gating, |
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1179 | serge | 280 | .bandwidth_update = &rs600_bandwidth_update, |
1117 | serge | 281 | }; |
282 | |||
283 | |||
284 | /* |
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285 | * rs690,rs740 |
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286 | */ |
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1221 | serge | 287 | int rs690_init(struct radeon_device *rdev); |
288 | void rs690_fini(struct radeon_device *rdev); |
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289 | int rs690_resume(struct radeon_device *rdev); |
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290 | int rs690_suspend(struct radeon_device *rdev); |
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1117 | serge | 291 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
292 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1179 | serge | 293 | void rs690_bandwidth_update(struct radeon_device *rdev); |
1117 | serge | 294 | static struct radeon_asic rs690_asic = { |
1221 | serge | 295 | .init = &rs690_init, |
296 | // .fini = &rs690_fini, |
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297 | // .suspend = &rs690_suspend, |
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298 | // .resume = &rs690_resume, |
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299 | // .vga_set_state = &r100_vga_set_state, |
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1117 | serge | 300 | .gpu_reset = &r300_gpu_reset, |
301 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
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302 | .gart_set_page = &rs400_gart_set_page, |
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1221 | serge | 303 | // .cp_commit = &r100_cp_commit, |
304 | // .ring_start = &r300_ring_start, |
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305 | // .ring_test = &r100_ring_test, |
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306 | // .ring_ib_execute = &r100_ring_ib_execute, |
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307 | // .irq_set = &rs600_irq_set, |
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308 | // .irq_process = &rs600_irq_process, |
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309 | // .get_vblank_counter = &rs600_get_vblank_counter, |
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310 | // .fence_ring_emit = &r300_fence_ring_emit, |
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311 | // .cs_parse = &r300_cs_parse, |
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312 | // .copy_blit = &r100_copy_blit, |
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313 | // .copy_dma = &r300_copy_dma, |
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314 | // .copy = &r300_copy_dma, |
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315 | .set_engine_clock = &radeon_atom_set_engine_clock, |
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316 | .set_memory_clock = &radeon_atom_set_memory_clock, |
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317 | .set_pcie_lanes = NULL, |
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318 | .set_clock_gating = &radeon_atom_set_clock_gating, |
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1179 | serge | 319 | .set_surface_reg = r100_set_surface_reg, |
320 | .clear_surface_reg = r100_clear_surface_reg, |
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321 | .bandwidth_update = &rs690_bandwidth_update, |
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1117 | serge | 322 | }; |
323 | |||
1179 | serge | 324 | |
1117 | serge | 325 | /* |
326 | * rv515 |
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327 | */ |
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328 | int rv515_init(struct radeon_device *rdev); |
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1221 | serge | 329 | void rv515_fini(struct radeon_device *rdev); |
1117 | serge | 330 | int rv515_gpu_reset(struct radeon_device *rdev); |
331 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
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332 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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333 | void rv515_ring_start(struct radeon_device *rdev); |
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334 | uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
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335 | void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1179 | serge | 336 | void rv515_bandwidth_update(struct radeon_device *rdev); |
1221 | serge | 337 | int rv515_resume(struct radeon_device *rdev); |
338 | int rv515_suspend(struct radeon_device *rdev); |
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1117 | serge | 339 | static struct radeon_asic rv515_asic = { |
340 | .init = &rv515_init, |
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1221 | serge | 341 | // .fini = &rv515_fini, |
342 | // .suspend = &rv515_suspend, |
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343 | // .resume = &rv515_resume, |
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344 | // .vga_set_state = &r100_vga_set_state, |
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1117 | serge | 345 | .gpu_reset = &rv515_gpu_reset, |
346 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
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347 | .gart_set_page = &rv370_pcie_gart_set_page, |
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1221 | serge | 348 | // .cp_commit = &r100_cp_commit, |
349 | // .ring_start = &rv515_ring_start, |
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350 | // .ring_test = &r100_ring_test, |
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351 | // .ring_ib_execute = &r100_ring_ib_execute, |
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352 | // .irq_set = &rs600_irq_set, |
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353 | // .irq_process = &rs600_irq_process, |
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354 | // .get_vblank_counter = &rs600_get_vblank_counter, |
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355 | // .fence_ring_emit = &r300_fence_ring_emit, |
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356 | // .cs_parse = &r300_cs_parse, |
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357 | // .copy_blit = &r100_copy_blit, |
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358 | // .copy_dma = &r300_copy_dma, |
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359 | // .copy = &r100_copy_blit, |
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360 | .set_engine_clock = &radeon_atom_set_engine_clock, |
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361 | .set_memory_clock = &radeon_atom_set_memory_clock, |
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362 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
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363 | .set_clock_gating = &radeon_atom_set_clock_gating, |
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1179 | serge | 364 | .set_surface_reg = r100_set_surface_reg, |
365 | .clear_surface_reg = r100_clear_surface_reg, |
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366 | .bandwidth_update = &rv515_bandwidth_update, |
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1117 | serge | 367 | }; |
368 | |||
369 | |||
370 | /* |
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371 | * r520,rv530,rv560,rv570,r580 |
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372 | */ |
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1221 | serge | 373 | int r520_init(struct radeon_device *rdev); |
374 | int r520_resume(struct radeon_device *rdev); |
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1117 | serge | 375 | static struct radeon_asic r520_asic = { |
1221 | serge | 376 | .init = &r520_init, |
377 | // .fini = &rv515_fini, |
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378 | // .suspend = &rv515_suspend, |
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379 | // .resume = &r520_resume, |
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380 | // .vga_set_state = &r100_vga_set_state, |
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1117 | serge | 381 | .gpu_reset = &rv515_gpu_reset, |
1119 | serge | 382 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
383 | .gart_set_page = &rv370_pcie_gart_set_page, |
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1221 | serge | 384 | // .cp_commit = &r100_cp_commit, |
385 | // .ring_start = &rv515_ring_start, |
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386 | // .ring_test = &r100_ring_test, |
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387 | // .ring_ib_execute = &r100_ring_ib_execute, |
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388 | // .irq_set = &rs600_irq_set, |
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389 | // .irq_process = &rs600_irq_process, |
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390 | // .get_vblank_counter = &rs600_get_vblank_counter, |
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391 | // .fence_ring_emit = &r300_fence_ring_emit, |
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392 | // .cs_parse = &r300_cs_parse, |
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393 | // .copy_blit = &r100_copy_blit, |
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394 | // .copy_dma = &r300_copy_dma, |
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395 | // .copy = &r100_copy_blit, |
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396 | .set_engine_clock = &radeon_atom_set_engine_clock, |
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397 | .set_memory_clock = &radeon_atom_set_memory_clock, |
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398 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
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399 | .set_clock_gating = &radeon_atom_set_clock_gating, |
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1179 | serge | 400 | .set_surface_reg = r100_set_surface_reg, |
401 | .clear_surface_reg = r100_clear_surface_reg, |
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1221 | serge | 402 | .bandwidth_update = &rv515_bandwidth_update, |
1117 | serge | 403 | }; |
404 | |||
405 | /* |
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1221 | serge | 406 | * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 |
1117 | serge | 407 | */ |
1179 | serge | 408 | int r600_init(struct radeon_device *rdev); |
409 | void r600_fini(struct radeon_device *rdev); |
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410 | int r600_suspend(struct radeon_device *rdev); |
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411 | int r600_resume(struct radeon_device *rdev); |
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412 | void r600_vga_set_state(struct radeon_device *rdev, bool state); |
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413 | int r600_wb_init(struct radeon_device *rdev); |
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414 | void r600_wb_fini(struct radeon_device *rdev); |
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415 | void r600_cp_commit(struct radeon_device *rdev); |
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416 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
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1117 | serge | 417 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
418 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1233 | serge | 419 | int r600_cs_parse(struct radeon_cs_parser *p); |
420 | void r600_fence_ring_emit(struct radeon_device *rdev, |
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421 | struct radeon_fence *fence); |
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422 | int r600_copy_dma(struct radeon_device *rdev, |
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423 | uint64_t src_offset, |
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424 | uint64_t dst_offset, |
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425 | unsigned num_pages, |
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426 | struct radeon_fence *fence); |
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427 | int r600_irq_process(struct radeon_device *rdev); |
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428 | int r600_irq_set(struct radeon_device *rdev); |
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429 | int r600_gpu_reset(struct radeon_device *rdev); |
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430 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
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431 | uint32_t tiling_flags, uint32_t pitch, |
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432 | uint32_t offset, uint32_t obj_size); |
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433 | int r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
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434 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
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435 | int r600_ring_test(struct radeon_device *rdev); |
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436 | int r600_copy_blit(struct radeon_device *rdev, |
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437 | uint64_t src_offset, uint64_t dst_offset, |
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438 | unsigned num_pages, struct radeon_fence *fence); |
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1117 | serge | 439 | |
1233 | serge | 440 | static struct radeon_asic r600_asic = { |
441 | .init = &r600_init, |
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442 | // .fini = &r600_fini, |
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443 | // .suspend = &r600_suspend, |
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444 | // .resume = &r600_resume, |
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445 | // .cp_commit = &r600_cp_commit, |
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446 | .vga_set_state = &r600_vga_set_state, |
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447 | .gpu_reset = &r600_gpu_reset, |
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448 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
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449 | .gart_set_page = &rs600_gart_set_page, |
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450 | // .ring_test = &r600_ring_test, |
||
451 | // .ring_ib_execute = &r600_ring_ib_execute, |
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452 | // .irq_set = &r600_irq_set, |
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453 | // .irq_process = &r600_irq_process, |
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454 | // .fence_ring_emit = &r600_fence_ring_emit, |
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455 | // .cs_parse = &r600_cs_parse, |
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456 | // .copy_blit = &r600_copy_blit, |
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457 | // .copy_dma = &r600_copy_blit, |
||
458 | // .copy = &r600_copy_blit, |
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459 | .set_engine_clock = &radeon_atom_set_engine_clock, |
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460 | .set_memory_clock = &radeon_atom_set_memory_clock, |
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461 | .set_pcie_lanes = NULL, |
||
462 | .set_clock_gating = &radeon_atom_set_clock_gating, |
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463 | .set_surface_reg = r600_set_surface_reg, |
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464 | .clear_surface_reg = r600_clear_surface_reg, |
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465 | .bandwidth_update = &rv515_bandwidth_update, |
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466 | }; |
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467 | |||
468 | /* |
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469 | * rv770,rv730,rv710,rv740 |
||
470 | */ |
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471 | int rv770_init(struct radeon_device *rdev); |
||
472 | void rv770_fini(struct radeon_device *rdev); |
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473 | int rv770_suspend(struct radeon_device *rdev); |
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474 | int rv770_resume(struct radeon_device *rdev); |
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475 | int rv770_gpu_reset(struct radeon_device *rdev); |
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476 | |||
477 | static struct radeon_asic rv770_asic = { |
||
478 | .init = &rv770_init, |
||
479 | // .fini = &rv770_fini, |
||
480 | // .suspend = &rv770_suspend, |
||
481 | // .resume = &rv770_resume, |
||
482 | // .cp_commit = &r600_cp_commit, |
||
483 | .gpu_reset = &rv770_gpu_reset, |
||
484 | .vga_set_state = &r600_vga_set_state, |
||
485 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
||
486 | .gart_set_page = &rs600_gart_set_page, |
||
487 | // .ring_test = &r600_ring_test, |
||
488 | // .ring_ib_execute = &r600_ring_ib_execute, |
||
489 | // .irq_set = &r600_irq_set, |
||
490 | // .irq_process = &r600_irq_process, |
||
491 | // .fence_ring_emit = &r600_fence_ring_emit, |
||
492 | // .cs_parse = &r600_cs_parse, |
||
493 | // .copy_blit = &r600_copy_blit, |
||
494 | // .copy_dma = &r600_copy_blit, |
||
495 | // .copy = &r600_copy_blit, |
||
496 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
497 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
498 | .set_pcie_lanes = NULL, |
||
499 | .set_clock_gating = &radeon_atom_set_clock_gating, |
||
500 | .set_surface_reg = r600_set_surface_reg, |
||
501 | .clear_surface_reg = r600_clear_surface_reg, |
||
502 | .bandwidth_update = &rv515_bandwidth_update, |
||
503 | }; |
||
504 | |||
1117 | serge | 505 | #endif |