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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #ifndef __RADEON_ASIC_H__ |
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29 | #define __RADEON_ASIC_H__ |
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30 | |||
31 | /* |
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32 | * common functions |
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33 | */ |
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34 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
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35 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
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36 | |||
37 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
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38 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
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39 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
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40 | |||
41 | /* |
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42 | * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
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43 | */ |
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44 | int r100_init(struct radeon_device *rdev); |
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45 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
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46 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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47 | void r100_errata(struct radeon_device *rdev); |
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48 | void r100_vram_info(struct radeon_device *rdev); |
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49 | int r100_gpu_reset(struct radeon_device *rdev); |
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50 | int r100_mc_init(struct radeon_device *rdev); |
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51 | void r100_mc_fini(struct radeon_device *rdev); |
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52 | int r100_wb_init(struct radeon_device *rdev); |
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53 | void r100_wb_fini(struct radeon_device *rdev); |
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54 | int r100_gart_enable(struct radeon_device *rdev); |
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55 | void r100_pci_gart_disable(struct radeon_device *rdev); |
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56 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
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57 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
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58 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
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59 | void r100_cp_fini(struct radeon_device *rdev); |
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60 | void r100_cp_disable(struct radeon_device *rdev); |
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61 | void r100_ring_start(struct radeon_device *rdev); |
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62 | int r100_irq_set(struct radeon_device *rdev); |
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63 | int r100_irq_process(struct radeon_device *rdev); |
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1128 | serge | 64 | void r100_fence_ring_emit(struct radeon_device *rdev, |
65 | struct radeon_fence *fence); |
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66 | int r100_cs_parse(struct radeon_cs_parser *p); |
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1117 | serge | 67 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
68 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); |
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1128 | serge | 69 | int r100_copy_blit(struct radeon_device *rdev, |
70 | uint64_t src_offset, |
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71 | uint64_t dst_offset, |
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72 | unsigned num_pages, |
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73 | struct radeon_fence *fence); |
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1117 | serge | 74 | |
75 | |||
76 | static struct radeon_asic r100_asic = { |
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77 | .init = &r100_init, |
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78 | .errata = &r100_errata, |
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79 | .vram_info = &r100_vram_info, |
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80 | .gpu_reset = &r100_gpu_reset, |
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81 | .mc_init = &r100_mc_init, |
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82 | .mc_fini = &r100_mc_fini, |
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1128 | serge | 83 | // .wb_init = &r100_wb_init, |
84 | // .wb_fini = &r100_wb_fini, |
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1117 | serge | 85 | .gart_enable = &r100_gart_enable, |
86 | .gart_disable = &r100_pci_gart_disable, |
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87 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
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88 | .gart_set_page = &r100_pci_gart_set_page, |
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89 | .cp_init = &r100_cp_init, |
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1128 | serge | 90 | // .cp_fini = &r100_cp_fini, |
91 | // .cp_disable = &r100_cp_disable, |
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1117 | serge | 92 | .ring_start = &r100_ring_start, |
1128 | serge | 93 | // .irq_set = &r100_irq_set, |
94 | // .irq_process = &r100_irq_process, |
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1117 | serge | 95 | // .fence_ring_emit = &r100_fence_ring_emit, |
96 | // .cs_parse = &r100_cs_parse, |
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97 | // .copy_blit = &r100_copy_blit, |
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98 | // .copy_dma = NULL, |
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99 | // .copy = &r100_copy_blit, |
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1128 | serge | 100 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
101 | // .set_memory_clock = NULL, |
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102 | // .set_pcie_lanes = NULL, |
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103 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
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1117 | serge | 104 | }; |
105 | |||
106 | |||
107 | /* |
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108 | * r300,r350,rv350,rv380 |
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109 | */ |
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110 | int r300_init(struct radeon_device *rdev); |
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111 | void r300_errata(struct radeon_device *rdev); |
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112 | void r300_vram_info(struct radeon_device *rdev); |
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113 | int r300_gpu_reset(struct radeon_device *rdev); |
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114 | int r300_mc_init(struct radeon_device *rdev); |
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115 | void r300_mc_fini(struct radeon_device *rdev); |
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116 | void r300_ring_start(struct radeon_device *rdev); |
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1128 | serge | 117 | void r300_fence_ring_emit(struct radeon_device *rdev, |
118 | struct radeon_fence *fence); |
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119 | int r300_cs_parse(struct radeon_cs_parser *p); |
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1117 | serge | 120 | int r300_gart_enable(struct radeon_device *rdev); |
121 | void rv370_pcie_gart_disable(struct radeon_device *rdev); |
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122 | void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
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123 | int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
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124 | uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
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125 | void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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126 | void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
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1128 | serge | 127 | int r300_copy_dma(struct radeon_device *rdev, |
128 | uint64_t src_offset, |
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129 | uint64_t dst_offset, |
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130 | unsigned num_pages, |
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131 | struct radeon_fence *fence); |
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1117 | serge | 132 | |
133 | |||
134 | static struct radeon_asic r300_asic = { |
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135 | .init = &r300_init, |
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136 | .errata = &r300_errata, |
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137 | .vram_info = &r300_vram_info, |
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138 | .gpu_reset = &r300_gpu_reset, |
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139 | .mc_init = &r300_mc_init, |
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140 | .mc_fini = &r300_mc_fini, |
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1128 | serge | 141 | // .wb_init = &r100_wb_init, |
142 | // .wb_fini = &r100_wb_fini, |
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1117 | serge | 143 | .gart_enable = &r300_gart_enable, |
144 | .gart_disable = &r100_pci_gart_disable, |
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145 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
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146 | .gart_set_page = &r100_pci_gart_set_page, |
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147 | .cp_init = &r100_cp_init, |
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1128 | serge | 148 | // .cp_fini = &r100_cp_fini, |
149 | // .cp_disable = &r100_cp_disable, |
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1117 | serge | 150 | .ring_start = &r300_ring_start, |
1128 | serge | 151 | // .irq_set = &r100_irq_set, |
152 | // .irq_process = &r100_irq_process, |
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1117 | serge | 153 | // .fence_ring_emit = &r300_fence_ring_emit, |
154 | // .cs_parse = &r300_cs_parse, |
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155 | // .copy_blit = &r100_copy_blit, |
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156 | // .copy_dma = &r300_copy_dma, |
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157 | // .copy = &r100_copy_blit, |
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1128 | serge | 158 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
159 | // .set_memory_clock = NULL, |
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160 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
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161 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
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1117 | serge | 162 | }; |
163 | |||
1128 | serge | 164 | |
1117 | serge | 165 | /* |
166 | * r420,r423,rv410 |
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167 | */ |
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168 | void r420_errata(struct radeon_device *rdev); |
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169 | void r420_vram_info(struct radeon_device *rdev); |
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170 | int r420_mc_init(struct radeon_device *rdev); |
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171 | void r420_mc_fini(struct radeon_device *rdev); |
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172 | static struct radeon_asic r420_asic = { |
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173 | .init = &r300_init, |
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174 | .errata = &r420_errata, |
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175 | .vram_info = &r420_vram_info, |
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176 | .gpu_reset = &r300_gpu_reset, |
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177 | .mc_init = &r420_mc_init, |
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178 | .mc_fini = &r420_mc_fini, |
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1128 | serge | 179 | // .wb_init = &r100_wb_init, |
180 | // .wb_fini = &r100_wb_fini, |
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1117 | serge | 181 | .gart_enable = &r300_gart_enable, |
182 | .gart_disable = &rv370_pcie_gart_disable, |
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183 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
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184 | .gart_set_page = &rv370_pcie_gart_set_page, |
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185 | .cp_init = &r100_cp_init, |
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1128 | serge | 186 | // .cp_fini = &r100_cp_fini, |
187 | // .cp_disable = &r100_cp_disable, |
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1117 | serge | 188 | .ring_start = &r300_ring_start, |
1128 | serge | 189 | // .irq_set = &r100_irq_set, |
190 | // .irq_process = &r100_irq_process, |
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1117 | serge | 191 | // .fence_ring_emit = &r300_fence_ring_emit, |
192 | // .cs_parse = &r300_cs_parse, |
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193 | // .copy_blit = &r100_copy_blit, |
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194 | // .copy_dma = &r300_copy_dma, |
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195 | // .copy = &r100_copy_blit, |
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1128 | serge | 196 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
197 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
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198 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
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199 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
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1117 | serge | 200 | }; |
201 | |||
202 | |||
203 | /* |
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204 | * rs400,rs480 |
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205 | */ |
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206 | void rs400_errata(struct radeon_device *rdev); |
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207 | void rs400_vram_info(struct radeon_device *rdev); |
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208 | int rs400_mc_init(struct radeon_device *rdev); |
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209 | void rs400_mc_fini(struct radeon_device *rdev); |
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210 | int rs400_gart_enable(struct radeon_device *rdev); |
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211 | void rs400_gart_disable(struct radeon_device *rdev); |
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212 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
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213 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
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214 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
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215 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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216 | static struct radeon_asic rs400_asic = { |
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217 | .init = &r300_init, |
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218 | .errata = &rs400_errata, |
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219 | .vram_info = &rs400_vram_info, |
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220 | .gpu_reset = &r300_gpu_reset, |
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221 | .mc_init = &rs400_mc_init, |
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222 | .mc_fini = &rs400_mc_fini, |
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1128 | serge | 223 | // .wb_init = &r100_wb_init, |
224 | // .wb_fini = &r100_wb_fini, |
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1117 | serge | 225 | .gart_enable = &rs400_gart_enable, |
226 | .gart_disable = &rs400_gart_disable, |
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227 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
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228 | .gart_set_page = &rs400_gart_set_page, |
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229 | .cp_init = &r100_cp_init, |
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1128 | serge | 230 | // .cp_fini = &r100_cp_fini, |
231 | // .cp_disable = &r100_cp_disable, |
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1117 | serge | 232 | .ring_start = &r300_ring_start, |
1128 | serge | 233 | // .irq_set = &r100_irq_set, |
234 | // .irq_process = &r100_irq_process, |
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1117 | serge | 235 | // .fence_ring_emit = &r300_fence_ring_emit, |
236 | // .cs_parse = &r300_cs_parse, |
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237 | // .copy_blit = &r100_copy_blit, |
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238 | // .copy_dma = &r300_copy_dma, |
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239 | // .copy = &r100_copy_blit, |
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1128 | serge | 240 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
241 | // .set_memory_clock = NULL, |
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242 | // .set_pcie_lanes = NULL, |
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243 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
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1117 | serge | 244 | }; |
245 | |||
246 | |||
247 | /* |
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248 | * rs600. |
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249 | */ |
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250 | void rs600_errata(struct radeon_device *rdev); |
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251 | void rs600_vram_info(struct radeon_device *rdev); |
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252 | int rs600_mc_init(struct radeon_device *rdev); |
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253 | void rs600_mc_fini(struct radeon_device *rdev); |
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254 | int rs600_irq_set(struct radeon_device *rdev); |
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255 | int rs600_gart_enable(struct radeon_device *rdev); |
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256 | void rs600_gart_disable(struct radeon_device *rdev); |
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257 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
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258 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
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259 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
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260 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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1128 | serge | 261 | |
1117 | serge | 262 | static struct radeon_asic rs600_asic = { |
263 | .init = &r300_init, |
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264 | .errata = &rs600_errata, |
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265 | .vram_info = &rs600_vram_info, |
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266 | .gpu_reset = &r300_gpu_reset, |
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267 | .mc_init = &rs600_mc_init, |
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268 | .mc_fini = &rs600_mc_fini, |
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1128 | serge | 269 | // .wb_init = &r100_wb_init, |
270 | // .wb_fini = &r100_wb_fini, |
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1117 | serge | 271 | .gart_enable = &rs600_gart_enable, |
272 | .gart_disable = &rs600_gart_disable, |
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273 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
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274 | .gart_set_page = &rs600_gart_set_page, |
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275 | .cp_init = &r100_cp_init, |
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1128 | serge | 276 | // .cp_fini = &r100_cp_fini, |
277 | // .cp_disable = &r100_cp_disable, |
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1117 | serge | 278 | .ring_start = &r300_ring_start, |
1128 | serge | 279 | // .irq_set = &rs600_irq_set, |
280 | // .irq_process = &r100_irq_process, |
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1117 | serge | 281 | // .fence_ring_emit = &r300_fence_ring_emit, |
282 | // .cs_parse = &r300_cs_parse, |
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283 | // .copy_blit = &r100_copy_blit, |
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284 | // .copy_dma = &r300_copy_dma, |
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285 | // .copy = &r100_copy_blit, |
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1128 | serge | 286 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
287 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
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288 | // .set_pcie_lanes = NULL, |
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289 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
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1117 | serge | 290 | }; |
291 | |||
292 | |||
293 | /* |
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294 | * rs690,rs740 |
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295 | */ |
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296 | void rs690_errata(struct radeon_device *rdev); |
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297 | void rs690_vram_info(struct radeon_device *rdev); |
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298 | int rs690_mc_init(struct radeon_device *rdev); |
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299 | void rs690_mc_fini(struct radeon_device *rdev); |
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300 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
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301 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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302 | static struct radeon_asic rs690_asic = { |
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303 | .init = &r300_init, |
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304 | .errata = &rs690_errata, |
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305 | .vram_info = &rs690_vram_info, |
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306 | .gpu_reset = &r300_gpu_reset, |
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307 | .mc_init = &rs690_mc_init, |
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308 | .mc_fini = &rs690_mc_fini, |
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1128 | serge | 309 | // .wb_init = &r100_wb_init, |
310 | // .wb_fini = &r100_wb_fini, |
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1117 | serge | 311 | .gart_enable = &rs400_gart_enable, |
312 | .gart_disable = &rs400_gart_disable, |
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313 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
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314 | .gart_set_page = &rs400_gart_set_page, |
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315 | .cp_init = &r100_cp_init, |
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1128 | serge | 316 | // .cp_fini = &r100_cp_fini, |
317 | // .cp_disable = &r100_cp_disable, |
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1117 | serge | 318 | .ring_start = &r300_ring_start, |
1128 | serge | 319 | // .irq_set = &rs600_irq_set, |
320 | // .irq_process = &r100_irq_process, |
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1117 | serge | 321 | // .fence_ring_emit = &r300_fence_ring_emit, |
322 | // .cs_parse = &r300_cs_parse, |
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323 | // .copy_blit = &r100_copy_blit, |
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324 | // .copy_dma = &r300_copy_dma, |
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325 | // .copy = &r300_copy_dma, |
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1128 | serge | 326 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
327 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
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328 | // .set_pcie_lanes = NULL, |
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329 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
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1117 | serge | 330 | }; |
331 | |||
332 | /* |
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333 | * rv515 |
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334 | */ |
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335 | int rv515_init(struct radeon_device *rdev); |
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336 | void rv515_errata(struct radeon_device *rdev); |
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337 | void rv515_vram_info(struct radeon_device *rdev); |
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338 | int rv515_gpu_reset(struct radeon_device *rdev); |
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339 | int rv515_mc_init(struct radeon_device *rdev); |
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340 | void rv515_mc_fini(struct radeon_device *rdev); |
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341 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
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342 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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343 | void rv515_ring_start(struct radeon_device *rdev); |
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344 | uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
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345 | void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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346 | |||
1128 | serge | 347 | |
1117 | serge | 348 | static struct radeon_asic rv515_asic = { |
349 | .init = &rv515_init, |
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350 | .errata = &rv515_errata, |
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351 | .vram_info = &rv515_vram_info, |
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352 | .gpu_reset = &rv515_gpu_reset, |
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353 | .mc_init = &rv515_mc_init, |
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354 | .mc_fini = &rv515_mc_fini, |
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1128 | serge | 355 | // .wb_init = &r100_wb_init, |
356 | // .wb_fini = &r100_wb_fini, |
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1117 | serge | 357 | .gart_enable = &r300_gart_enable, |
358 | .gart_disable = &rv370_pcie_gart_disable, |
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359 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
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360 | .gart_set_page = &rv370_pcie_gart_set_page, |
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361 | .cp_init = &r100_cp_init, |
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1128 | serge | 362 | // .cp_fini = &r100_cp_fini, |
363 | // .cp_disable = &r100_cp_disable, |
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364 | .ring_start = &rv515_ring_start, |
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365 | // .irq_set = &r100_irq_set, |
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366 | // .irq_process = &r100_irq_process, |
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1117 | serge | 367 | // .fence_ring_emit = &r300_fence_ring_emit, |
368 | // .cs_parse = &r300_cs_parse, |
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369 | // .copy_blit = &r100_copy_blit, |
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370 | // .copy_dma = &r300_copy_dma, |
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371 | // .copy = &r100_copy_blit, |
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1128 | serge | 372 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
373 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
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374 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
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375 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
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1117 | serge | 376 | }; |
377 | |||
378 | |||
379 | /* |
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380 | * r520,rv530,rv560,rv570,r580 |
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381 | */ |
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382 | void r520_errata(struct radeon_device *rdev); |
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383 | void r520_vram_info(struct radeon_device *rdev); |
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384 | int r520_mc_init(struct radeon_device *rdev); |
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385 | void r520_mc_fini(struct radeon_device *rdev); |
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386 | |||
387 | static struct radeon_asic r520_asic = { |
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388 | .init = &rv515_init, |
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389 | .errata = &r520_errata, |
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390 | .vram_info = &r520_vram_info, |
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391 | .gpu_reset = &rv515_gpu_reset, |
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1119 | serge | 392 | .mc_init = &r520_mc_init, |
393 | .mc_fini = &r520_mc_fini, |
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1125 | serge | 394 | // .wb_init = &r100_wb_init, |
395 | // .wb_fini = &r100_wb_fini, |
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1119 | serge | 396 | .gart_enable = &r300_gart_enable, |
397 | .gart_disable = &rv370_pcie_gart_disable, |
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398 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
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399 | .gart_set_page = &rv370_pcie_gart_set_page, |
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400 | .cp_init = &r100_cp_init, |
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401 | // .cp_fini = &r100_cp_fini, |
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1117 | serge | 402 | // .cp_disable = &r100_cp_disable, |
1119 | serge | 403 | .ring_start = &rv515_ring_start, |
1117 | serge | 404 | // .irq_set = &r100_irq_set, |
405 | // .irq_process = &r100_irq_process, |
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406 | // .fence_ring_emit = &r300_fence_ring_emit, |
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407 | // .cs_parse = &r300_cs_parse, |
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408 | // .copy_blit = &r100_copy_blit, |
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409 | // .copy_dma = &r300_copy_dma, |
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410 | // .copy = &r100_copy_blit, |
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411 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
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412 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
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413 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
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414 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
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415 | }; |
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416 | |||
417 | /* |
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418 | * r600,rv610,rv630,rv620,rv635,rv670,rs780,rv770,rv730,rv710 |
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419 | */ |
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420 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
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421 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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422 | |||
423 | #endif |