WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_asic.c

Rev	Author	Line No.	Line
1963	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28
		29	//#include
		30	#include
		31	#include
		32	#include
		33	//#include
		34	//#include
		35	#include "radeon_reg.h"
		36	#include "radeon.h"
		37	#include "radeon_asic.h"
		38	#include "atom.h"
		39
		40	/*
		41	* Registers accessors functions.
		42	*/
2997	Serge	43	/**
		44	* radeon_invalid_rreg - dummy reg read function
		45	*
		46	* @rdev: radeon device pointer
		47	* @reg: offset of register
		48	*
		49	* Dummy register read function. Used for register blocks
		50	* that certain asics don't have (all asics).
		51	* Returns the value in the register.
		52	*/
1963	serge	53	static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
		54	{
		55	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
		56	BUG_ON(1);
		57	return 0;
		58	}
		59
2997	Serge	60	/**
		61	* radeon_invalid_wreg - dummy reg write function
		62	*
		63	* @rdev: radeon device pointer
		64	* @reg: offset of register
		65	* @v: value to write to the register
		66	*
		67	* Dummy register read function. Used for register blocks
		68	* that certain asics don't have (all asics).
		69	*/
1963	serge	70	static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		71	{
		72	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
		73	reg, v);
		74	BUG_ON(1);
		75	}
		76
2997	Serge	77	/**
		78	* radeon_register_accessor_init - sets up the register accessor callbacks
		79	*
		80	* @rdev: radeon device pointer
		81	*
		82	* Sets up the register accessor callbacks for various register
		83	* apertures. Not all asics have all apertures (all asics).
		84	*/
1963	serge	85	static void radeon_register_accessor_init(struct radeon_device *rdev)
		86	{
		87	rdev->mc_rreg = &radeon_invalid_rreg;
		88	rdev->mc_wreg = &radeon_invalid_wreg;
		89	rdev->pll_rreg = &radeon_invalid_rreg;
		90	rdev->pll_wreg = &radeon_invalid_wreg;
		91	rdev->pciep_rreg = &radeon_invalid_rreg;
		92	rdev->pciep_wreg = &radeon_invalid_wreg;
		93
		94	/* Don't change order as we are overridding accessor. */
		95	if (rdev->family < CHIP_RV515) {
		96	rdev->pcie_reg_mask = 0xff;
		97	} else {
		98	rdev->pcie_reg_mask = 0x7ff;
		99	}
		100	/* FIXME: not sure here */
		101	if (rdev->family <= CHIP_R580) {
		102	rdev->pll_rreg = &r100_pll_rreg;
		103	rdev->pll_wreg = &r100_pll_wreg;
		104	}
		105	if (rdev->family >= CHIP_R420) {
		106	rdev->mc_rreg = &r420_mc_rreg;
		107	rdev->mc_wreg = &r420_mc_wreg;
		108	}
		109	if (rdev->family >= CHIP_RV515) {
		110	rdev->mc_rreg = &rv515_mc_rreg;
		111	rdev->mc_wreg = &rv515_mc_wreg;
		112	}
		113	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
		114	rdev->mc_rreg = &rs400_mc_rreg;
		115	rdev->mc_wreg = &rs400_mc_wreg;
		116	}
		117	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
		118	rdev->mc_rreg = &rs690_mc_rreg;
		119	rdev->mc_wreg = &rs690_mc_wreg;
		120	}
		121	if (rdev->family == CHIP_RS600) {
		122	rdev->mc_rreg = &rs600_mc_rreg;
		123	rdev->mc_wreg = &rs600_mc_wreg;
		124	}
3764	Serge	125	if (rdev->family == CHIP_RS780 \|\| rdev->family == CHIP_RS880) {
		126	rdev->mc_rreg = &rs780_mc_rreg;
		127	rdev->mc_wreg = &rs780_mc_wreg;
		128	}
1963	serge	129	if (rdev->family >= CHIP_R600) {
		130	rdev->pciep_rreg = &r600_pciep_rreg;
		131	rdev->pciep_wreg = &r600_pciep_wreg;
		132	}
		133	}
		134
		135
		136	/* helper to disable agp */
2997	Serge	137	/**
		138	* radeon_agp_disable - AGP disable helper function
		139	*
		140	* @rdev: radeon device pointer
		141	*
		142	* Removes AGP flags and changes the gart callbacks on AGP
		143	* cards when using the internal gart rather than AGP (all asics).
		144	*/
1963	serge	145	void radeon_agp_disable(struct radeon_device *rdev)
		146	{
		147	rdev->flags &= ~RADEON_IS_AGP;
		148	if (rdev->family >= CHIP_R600) {
		149	DRM_INFO("Forcing AGP to PCIE mode\n");
		150	rdev->flags \|= RADEON_IS_PCIE;
		151	} else if (rdev->family >= CHIP_RV515 \|\|
		152	rdev->family == CHIP_RV380 \|\|
		153	rdev->family == CHIP_RV410 \|\|
		154	rdev->family == CHIP_R423) {
		155	DRM_INFO("Forcing AGP to PCIE mode\n");
		156	rdev->flags \|= RADEON_IS_PCIE;
2997	Serge	157	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
		158	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
1963	serge	159	} else {
		160	DRM_INFO("Forcing AGP to PCI mode\n");
		161	rdev->flags \|= RADEON_IS_PCI;
2997	Serge	162	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
		163	rdev->asic->gart.set_page = &r100_pci_gart_set_page;
1963	serge	164	}
		165	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		166	}
		167
		168	/*
		169	* ASIC
		170	*/
		171	static struct radeon_asic r100_asic = {
		172	.init = &r100_init,
		173	// .fini = &r100_fini,
		174	// .suspend = &r100_suspend,
		175	// .resume = &r100_resume,
		176	// .vga_set_state = &r100_vga_set_state,
		177	.asic_reset = &r100_asic_reset,
3192	Serge	178	.ioctl_wait_idle = NULL,
2997	Serge	179	.gui_idle = &r100_gui_idle,
		180	.mc_wait_for_idle = &r100_mc_wait_for_idle,
		181	.gart = {
		182	.tlb_flush = &r100_pci_gart_tlb_flush,
		183	.set_page = &r100_pci_gart_set_page,
		184	},
		185	.ring = {
		186	[RADEON_RING_TYPE_GFX_INDEX] = {
		187	.ib_execute = &r100_ring_ib_execute,
		188	.emit_fence = &r100_fence_ring_emit,
		189	.emit_semaphore = &r100_semaphore_ring_emit,
		190	// .cs_parse = &r100_cs_parse,
		191	.ring_start = &r100_ring_start,
		192	.ring_test = &r100_ring_test,
		193	.ib_test = &r100_ib_test,
		194	.is_lockup = &r100_gpu_is_lockup,
		195	}
		196	},
		197	.irq = {
		198	.set = &r100_irq_set,
		199	.process = &r100_irq_process,
		200	},
		201	.display = {
		202	.bandwidth_update = &r100_bandwidth_update,
		203	.get_vblank_counter = &r100_get_vblank_counter,
		204	.wait_for_vblank = &r100_wait_for_vblank,
		205	// .set_backlight_level = &radeon_legacy_set_backlight_level,
		206	// .get_backlight_level = &radeon_legacy_get_backlight_level,
		207	},
		208	.copy = {
		209	.blit = &r100_copy_blit,
		210	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		211	.dma = NULL,
		212	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2005	serge	213	.copy = &r100_copy_blit,
2997	Serge	214	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		215	},
		216	.surface = {
		217	.set_reg = r100_set_surface_reg,
		218	.clear_reg = r100_clear_surface_reg,
		219	},
		220	.hpd = {
		221	// .init = &r100_hpd_init,
		222	// .fini = &r100_hpd_fini,
		223	// .sense = &r100_hpd_sense,
		224	// .set_polarity = &r100_hpd_set_polarity,
		225	},
		226	.pm = {
		227	// .misc = &r100_pm_misc,
		228	// .prepare = &r100_pm_prepare,
		229	// .finish = &r100_pm_finish,
		230	// .init_profile = &r100_pm_init_profile,
		231	// .get_dynpm_state = &r100_pm_get_dynpm_state,
		232	// .get_engine_clock = &radeon_legacy_get_engine_clock,
		233	// .set_engine_clock = &radeon_legacy_set_engine_clock,
		234	// .get_memory_clock = &radeon_legacy_get_memory_clock,
3192	Serge	235	.set_memory_clock = NULL,
		236	.get_pcie_lanes = NULL,
		237	.set_pcie_lanes = NULL,
2997	Serge	238	// .set_clock_gating = &radeon_legacy_set_clock_gating,
		239	},
		240	.pflip = {
		241	// .pre_page_flip = &r100_pre_page_flip,
		242	// .page_flip = &r100_page_flip,
		243	// .post_page_flip = &r100_post_page_flip,
		244	},
1963	serge	245	};
		246
		247	static struct radeon_asic r200_asic = {
		248	.init = &r100_init,
		249	// .fini = &r100_fini,
		250	// .suspend = &r100_suspend,
		251	// .resume = &r100_resume,
		252	// .vga_set_state = &r100_vga_set_state,
		253	.asic_reset = &r100_asic_reset,
3192	Serge	254	.ioctl_wait_idle = NULL,
2007	serge	255	.gui_idle = &r100_gui_idle,
2997	Serge	256	.mc_wait_for_idle = &r100_mc_wait_for_idle,
		257	.gart = {
		258	.tlb_flush = &r100_pci_gart_tlb_flush,
		259	.set_page = &r100_pci_gart_set_page,
		260	},
		261	.ring = {
		262	[RADEON_RING_TYPE_GFX_INDEX] = {
		263	.ib_execute = &r100_ring_ib_execute,
		264	.emit_fence = &r100_fence_ring_emit,
		265	.emit_semaphore = &r100_semaphore_ring_emit,
		266	// .cs_parse = &r100_cs_parse,
		267	.ring_start = &r100_ring_start,
		268	.ring_test = &r100_ring_test,
		269	.ib_test = &r100_ib_test,
		270	.is_lockup = &r100_gpu_is_lockup,
		271	}
		272	},
		273	.irq = {
		274	.set = &r100_irq_set,
		275	.process = &r100_irq_process,
		276	},
		277	.display = {
		278	.bandwidth_update = &r100_bandwidth_update,
		279	.get_vblank_counter = &r100_get_vblank_counter,
		280	.wait_for_vblank = &r100_wait_for_vblank,
		281	// .set_backlight_level = &radeon_legacy_set_backlight_level,
		282	// .get_backlight_level = &radeon_legacy_get_backlight_level,
		283	},
		284	.copy = {
		285	.blit = &r100_copy_blit,
		286	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		287	.dma = &r200_copy_dma,
		288	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		289	.copy = &r100_copy_blit,
		290	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		291	},
		292	.surface = {
		293	.set_reg = r100_set_surface_reg,
		294	.clear_reg = r100_clear_surface_reg,
		295	},
		296	.hpd = {
		297	// .init = &r100_hpd_init,
		298	// .fini = &r100_hpd_fini,
		299	// .sense = &r100_hpd_sense,
		300	// .set_polarity = &r100_hpd_set_polarity,
		301	},
		302	.pm = {
		303	// .misc = &r100_pm_misc,
		304	// .prepare = &r100_pm_prepare,
		305	// .finish = &r100_pm_finish,
		306	// .init_profile = &r100_pm_init_profile,
		307	// .get_dynpm_state = &r100_pm_get_dynpm_state,
		308	// .get_engine_clock = &radeon_legacy_get_engine_clock,
		309	// .set_engine_clock = &radeon_legacy_set_engine_clock,
		310	// .get_memory_clock = &radeon_legacy_get_memory_clock,
3192	Serge	311	.set_memory_clock = NULL,
		312	.get_pcie_lanes = NULL,
		313	.set_pcie_lanes = NULL,
2997	Serge	314	// .set_clock_gating = &radeon_legacy_set_clock_gating,
		315	},
		316	.pflip = {
		317	// .pre_page_flip = &r100_pre_page_flip,
		318	// .page_flip = &r100_page_flip,
		319	// .post_page_flip = &r100_post_page_flip,
		320	},
1963	serge	321	};
		322
		323	static struct radeon_asic r300_asic = {
		324	.init = &r300_init,
		325	// .fini = &r300_fini,
		326	// .suspend = &r300_suspend,
		327	// .resume = &r300_resume,
		328	// .vga_set_state = &r100_vga_set_state,
		329	.asic_reset = &r300_asic_reset,
3192	Serge	330	.ioctl_wait_idle = NULL,
2007	serge	331	.gui_idle = &r100_gui_idle,
2997	Serge	332	.mc_wait_for_idle = &r300_mc_wait_for_idle,
		333	.gart = {
		334	.tlb_flush = &r100_pci_gart_tlb_flush,
		335	.set_page = &r100_pci_gart_set_page,
		336	},
		337	.ring = {
		338	[RADEON_RING_TYPE_GFX_INDEX] = {
		339	.ib_execute = &r100_ring_ib_execute,
		340	.emit_fence = &r300_fence_ring_emit,
		341	.emit_semaphore = &r100_semaphore_ring_emit,
		342	// .cs_parse = &r300_cs_parse,
		343	.ring_start = &r300_ring_start,
		344	.ring_test = &r100_ring_test,
		345	.ib_test = &r100_ib_test,
		346	.is_lockup = &r100_gpu_is_lockup,
		347	}
		348	},
		349	.irq = {
		350	.set = &r100_irq_set,
		351	.process = &r100_irq_process,
		352	},
		353	.display = {
		354	.bandwidth_update = &r100_bandwidth_update,
		355	.get_vblank_counter = &r100_get_vblank_counter,
		356	.wait_for_vblank = &r100_wait_for_vblank,
		357	// .set_backlight_level = &radeon_legacy_set_backlight_level,
		358	// .get_backlight_level = &radeon_legacy_get_backlight_level,
		359	},
		360	.copy = {
		361	.blit = &r100_copy_blit,
		362	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		363	.dma = &r200_copy_dma,
		364	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		365	.copy = &r100_copy_blit,
		366	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		367	},
		368	.surface = {
		369	.set_reg = r100_set_surface_reg,
		370	.clear_reg = r100_clear_surface_reg,
		371	},
		372	.hpd = {
		373	// .init = &r100_hpd_init,
		374	// .fini = &r100_hpd_fini,
		375	// .sense = &r100_hpd_sense,
		376	// .set_polarity = &r100_hpd_set_polarity,
		377	},
		378	.pm = {
		379	// .misc = &r100_pm_misc,
		380	// .prepare = &r100_pm_prepare,
		381	// .finish = &r100_pm_finish,
		382	// .init_profile = &r100_pm_init_profile,
		383	// .get_dynpm_state = &r100_pm_get_dynpm_state,
		384	// .get_engine_clock = &radeon_legacy_get_engine_clock,
		385	// .set_engine_clock = &radeon_legacy_set_engine_clock,
		386	// .get_memory_clock = &radeon_legacy_get_memory_clock,
		387	// .set_memory_clock = NULL,
		388	// .get_pcie_lanes = &rv370_get_pcie_lanes,
		389	// .set_pcie_lanes = &rv370_set_pcie_lanes,
		390	// .set_clock_gating = &radeon_legacy_set_clock_gating,
		391	},
		392	.pflip = {
		393	// .pre_page_flip = &r100_pre_page_flip,
		394	// .page_flip = &r100_page_flip,
		395	// .post_page_flip = &r100_post_page_flip,
		396	},
1963	serge	397	};
		398
		399	static struct radeon_asic r300_asic_pcie = {
		400	.init = &r300_init,
		401	// .fini = &r300_fini,
		402	// .suspend = &r300_suspend,
		403	// .resume = &r300_resume,
		404	// .vga_set_state = &r100_vga_set_state,
		405	.asic_reset = &r300_asic_reset,
3192	Serge	406	.ioctl_wait_idle = NULL,
2007	serge	407	.gui_idle = &r100_gui_idle,
2997	Serge	408	.mc_wait_for_idle = &r300_mc_wait_for_idle,
		409	.gart = {
		410	.tlb_flush = &rv370_pcie_gart_tlb_flush,
		411	.set_page = &rv370_pcie_gart_set_page,
		412	},
		413	.ring = {
		414	[RADEON_RING_TYPE_GFX_INDEX] = {
		415	.ib_execute = &r100_ring_ib_execute,
		416	.emit_fence = &r300_fence_ring_emit,
		417	.emit_semaphore = &r100_semaphore_ring_emit,
		418	// .cs_parse = &r300_cs_parse,
		419	.ring_start = &r300_ring_start,
		420	.ring_test = &r100_ring_test,
		421	.ib_test = &r100_ib_test,
		422	.is_lockup = &r100_gpu_is_lockup,
		423	}
		424	},
		425	.irq = {
		426	.set = &r100_irq_set,
		427	.process = &r100_irq_process,
		428	},
		429	.display = {
		430	.bandwidth_update = &r100_bandwidth_update,
		431	.get_vblank_counter = &r100_get_vblank_counter,
		432	.wait_for_vblank = &r100_wait_for_vblank,
		433	// .set_backlight_level = &radeon_legacy_set_backlight_level,
		434	// .get_backlight_level = &radeon_legacy_get_backlight_level,
		435	},
		436	.copy = {
		437	.blit = &r100_copy_blit,
		438	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		439	.dma = &r200_copy_dma,
		440	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		441	.copy = &r100_copy_blit,
		442	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		443	},
		444	.surface = {
		445	.set_reg = r100_set_surface_reg,
		446	.clear_reg = r100_clear_surface_reg,
		447	},
		448	.hpd = {
		449	.init = &r100_hpd_init,
		450	.fini = &r100_hpd_fini,
		451	.sense = &r100_hpd_sense,
		452	.set_polarity = &r100_hpd_set_polarity,
		453	},
		454	.pm = {
		455	// .misc = &r100_pm_misc,
		456	// .prepare = &r100_pm_prepare,
		457	// .finish = &r100_pm_finish,
		458	// .init_profile = &r100_pm_init_profile,
		459	// .get_dynpm_state = &r100_pm_get_dynpm_state,
		460	// .get_engine_clock = &radeon_legacy_get_engine_clock,
		461	// .set_engine_clock = &radeon_legacy_set_engine_clock,
		462	// .get_memory_clock = &radeon_legacy_get_memory_clock,
		463	// .set_memory_clock = NULL,
		464	// .get_pcie_lanes = &rv370_get_pcie_lanes,
		465	// .set_pcie_lanes = &rv370_set_pcie_lanes,
		466	// .set_clock_gating = &radeon_legacy_set_clock_gating,
		467	},
		468	.pflip = {
		469	// .pre_page_flip = &r100_pre_page_flip,
		470	// .page_flip = &r100_page_flip,
		471	// .post_page_flip = &r100_post_page_flip,
		472	},
1963	serge	473	};
		474
		475	static struct radeon_asic r420_asic = {
		476	.init = &r420_init,
		477	// .fini = &r420_fini,
		478	// .suspend = &r420_suspend,
		479	// .resume = &r420_resume,
		480	// .vga_set_state = &r100_vga_set_state,
		481	.asic_reset = &r300_asic_reset,
3192	Serge	482	.ioctl_wait_idle = NULL,
2160	serge	483	.gui_idle = &r100_gui_idle,
2997	Serge	484	.mc_wait_for_idle = &r300_mc_wait_for_idle,
		485	.gart = {
		486	.tlb_flush = &rv370_pcie_gart_tlb_flush,
		487	.set_page = &rv370_pcie_gart_set_page,
		488	},
		489	.ring = {
		490	[RADEON_RING_TYPE_GFX_INDEX] = {
		491	.ib_execute = &r100_ring_ib_execute,
		492	.emit_fence = &r300_fence_ring_emit,
		493	.emit_semaphore = &r100_semaphore_ring_emit,
		494	// .cs_parse = &r300_cs_parse,
		495	.ring_start = &r300_ring_start,
		496	.ring_test = &r100_ring_test,
		497	.ib_test = &r100_ib_test,
		498	.is_lockup = &r100_gpu_is_lockup,
		499	}
		500	},
		501	.irq = {
		502	.set = &r100_irq_set,
		503	.process = &r100_irq_process,
		504	},
		505	.display = {
		506	.bandwidth_update = &r100_bandwidth_update,
		507	.get_vblank_counter = &r100_get_vblank_counter,
		508	.wait_for_vblank = &r100_wait_for_vblank,
		509	// .set_backlight_level = &atombios_set_backlight_level,
		510	// .get_backlight_level = &atombios_get_backlight_level,
		511	},
		512	.copy = {
		513	.blit = &r100_copy_blit,
		514	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		515	.dma = &r200_copy_dma,
		516	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		517	.copy = &r100_copy_blit,
		518	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		519	},
		520	.surface = {
		521	.set_reg = r100_set_surface_reg,
		522	.clear_reg = r100_clear_surface_reg,
		523	},
		524	.hpd = {
		525	// .init = &r100_hpd_init,
		526	// .fini = &r100_hpd_fini,
		527	// .sense = &r100_hpd_sense,
		528	// .set_polarity = &r100_hpd_set_polarity,
		529	},
		530	.pm = {
		531	// .misc = &r100_pm_misc,
		532	// .prepare = &r100_pm_prepare,
		533	// .finish = &r100_pm_finish,
		534	// .init_profile = &r420_pm_init_profile,
		535	// .get_dynpm_state = &r100_pm_get_dynpm_state,
		536	// .get_engine_clock = &radeon_atom_get_engine_clock,
		537	// .set_engine_clock = &radeon_atom_set_engine_clock,
		538	// .get_memory_clock = &radeon_atom_get_memory_clock,
		539	// .set_memory_clock = &radeon_atom_set_memory_clock,
		540	// .get_pcie_lanes = &rv370_get_pcie_lanes,
		541	// .set_pcie_lanes = &rv370_set_pcie_lanes,
		542	// .set_clock_gating = &radeon_atom_set_clock_gating,
		543	},
		544	.pflip = {
		545	// .pre_page_flip = &r100_pre_page_flip,
		546	// .page_flip = &r100_page_flip,
		547	// .post_page_flip = &r100_post_page_flip,
		548	},
1963	serge	549	};
		550
		551	static struct radeon_asic rs400_asic = {
		552	.init = &rs400_init,
		553	// .fini = &rs400_fini,
		554	// .suspend = &rs400_suspend,
		555	// .resume = &rs400_resume,
		556	// .vga_set_state = &r100_vga_set_state,
		557	.asic_reset = &r300_asic_reset,
3192	Serge	558	.ioctl_wait_idle = NULL,
2160	serge	559	.gui_idle = &r100_gui_idle,
2997	Serge	560	.mc_wait_for_idle = &rs400_mc_wait_for_idle,
		561	.gart = {
		562	.tlb_flush = &rs400_gart_tlb_flush,
		563	.set_page = &rs400_gart_set_page,
		564	},
		565	.ring = {
		566	[RADEON_RING_TYPE_GFX_INDEX] = {
		567	.ib_execute = &r100_ring_ib_execute,
		568	.emit_fence = &r300_fence_ring_emit,
		569	.emit_semaphore = &r100_semaphore_ring_emit,
		570	// .cs_parse = &r300_cs_parse,
		571	.ring_start = &r300_ring_start,
		572	.ring_test = &r100_ring_test,
		573	.ib_test = &r100_ib_test,
		574	.is_lockup = &r100_gpu_is_lockup,
		575	}
		576	},
		577	.irq = {
		578	.set = &r100_irq_set,
		579	.process = &r100_irq_process,
		580	},
		581	.display = {
		582	.bandwidth_update = &r100_bandwidth_update,
		583	.get_vblank_counter = &r100_get_vblank_counter,
		584	.wait_for_vblank = &r100_wait_for_vblank,
		585	// .set_backlight_level = &radeon_legacy_set_backlight_level,
		586	// .get_backlight_level = &radeon_legacy_get_backlight_level,
		587	},
		588	.copy = {
		589	.blit = &r100_copy_blit,
		590	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		591	.dma = &r200_copy_dma,
		592	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		593	.copy = &r100_copy_blit,
		594	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		595	},
		596	.surface = {
		597	.set_reg = r100_set_surface_reg,
		598	.clear_reg = r100_clear_surface_reg,
		599	},
		600	.hpd = {
		601	// .init = &r100_hpd_init,
		602	// .fini = &r100_hpd_fini,
		603	// .sense = &r100_hpd_sense,
		604	// .set_polarity = &r100_hpd_set_polarity,
		605	},
		606	.pm = {
		607	// .misc = &r100_pm_misc,
		608	// .prepare = &r100_pm_prepare,
		609	// .finish = &r100_pm_finish,
		610	// .init_profile = &r100_pm_init_profile,
		611	// .get_dynpm_state = &r100_pm_get_dynpm_state,
		612	// .get_engine_clock = &radeon_legacy_get_engine_clock,
		613	// .set_engine_clock = &radeon_legacy_set_engine_clock,
		614	// .get_memory_clock = &radeon_legacy_get_memory_clock,
		615	// .set_memory_clock = NULL,
		616	// .get_pcie_lanes = NULL,
		617	// .set_pcie_lanes = NULL,
		618	// .set_clock_gating = &radeon_legacy_set_clock_gating,
		619	},
		620	.pflip = {
		621	// .pre_page_flip = &r100_pre_page_flip,
		622	// .page_flip = &r100_page_flip,
		623	// .post_page_flip = &r100_post_page_flip,
		624	},
1963	serge	625	};
		626
		627	static struct radeon_asic rs600_asic = {
		628	.init = &rs600_init,
		629	// .fini = &rs600_fini,
		630	// .suspend = &rs600_suspend,
		631	// .resume = &rs600_resume,
		632	// .vga_set_state = &r100_vga_set_state,
		633	.asic_reset = &rs600_asic_reset,
3192	Serge	634	.ioctl_wait_idle = NULL,
2160	serge	635	.gui_idle = &r100_gui_idle,
2997	Serge	636	.mc_wait_for_idle = &rs600_mc_wait_for_idle,
		637	.gart = {
		638	.tlb_flush = &rs600_gart_tlb_flush,
		639	.set_page = &rs600_gart_set_page,
		640	},
		641	.ring = {
		642	[RADEON_RING_TYPE_GFX_INDEX] = {
		643	.ib_execute = &r100_ring_ib_execute,
		644	.emit_fence = &r300_fence_ring_emit,
		645	.emit_semaphore = &r100_semaphore_ring_emit,
		646	// .cs_parse = &r300_cs_parse,
		647	.ring_start = &r300_ring_start,
		648	.ring_test = &r100_ring_test,
		649	.ib_test = &r100_ib_test,
		650	.is_lockup = &r100_gpu_is_lockup,
		651	}
		652	},
		653	.irq = {
		654	.set = &rs600_irq_set,
		655	.process = &rs600_irq_process,
		656	},
		657	.display = {
		658	.bandwidth_update = &rs600_bandwidth_update,
		659	.get_vblank_counter = &rs600_get_vblank_counter,
		660	.wait_for_vblank = &avivo_wait_for_vblank,
		661	// .set_backlight_level = &atombios_set_backlight_level,
		662	// .get_backlight_level = &atombios_get_backlight_level,
		663	},
		664	.copy = {
		665	.blit = &r100_copy_blit,
		666	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		667	.dma = &r200_copy_dma,
		668	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		669	.copy = &r100_copy_blit,
		670	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		671	},
		672	.surface = {
		673	.set_reg = r100_set_surface_reg,
		674	.clear_reg = r100_clear_surface_reg,
		675	},
		676	.hpd = {
		677	// .init = &rs600_hpd_init,
		678	// .fini = &rs600_hpd_fini,
		679	// .sense = &rs600_hpd_sense,
		680	// .set_polarity = &rs600_hpd_set_polarity,
		681	},
		682	.pm = {
		683	// .misc = &rs600_pm_misc,
		684	// .prepare = &rs600_pm_prepare,
		685	// .finish = &rs600_pm_finish,
		686	// .init_profile = &r420_pm_init_profile,
		687	// .get_dynpm_state = &r100_pm_get_dynpm_state,
		688	// .get_engine_clock = &radeon_atom_get_engine_clock,
		689	// .set_engine_clock = &radeon_atom_set_engine_clock,
		690	// .get_memory_clock = &radeon_atom_get_memory_clock,
		691	// .set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	692	.get_pcie_lanes = NULL,
		693	.set_pcie_lanes = NULL,
2997	Serge	694	// .set_clock_gating = &radeon_atom_set_clock_gating,
		695	},
		696	.pflip = {
		697	// .pre_page_flip = &rs600_pre_page_flip,
		698	// .page_flip = &rs600_page_flip,
		699	// .post_page_flip = &rs600_post_page_flip,
		700	},
1963	serge	701	};
		702
		703	static struct radeon_asic rs690_asic = {
		704	.init = &rs690_init,
		705	// .fini = &rs690_fini,
		706	// .suspend = &rs690_suspend,
		707	// .resume = &rs690_resume,
		708	// .vga_set_state = &r100_vga_set_state,
		709	.asic_reset = &rs600_asic_reset,
3192	Serge	710	.ioctl_wait_idle = NULL,
2160	serge	711	.gui_idle = &r100_gui_idle,
2997	Serge	712	.mc_wait_for_idle = &rs690_mc_wait_for_idle,
		713	.gart = {
		714	.tlb_flush = &rs400_gart_tlb_flush,
		715	.set_page = &rs400_gart_set_page,
		716	},
		717	.ring = {
		718	[RADEON_RING_TYPE_GFX_INDEX] = {
		719	.ib_execute = &r100_ring_ib_execute,
		720	.emit_fence = &r300_fence_ring_emit,
		721	.emit_semaphore = &r100_semaphore_ring_emit,
		722	// .cs_parse = &r300_cs_parse,
		723	.ring_start = &r300_ring_start,
		724	.ring_test = &r100_ring_test,
		725	.ib_test = &r100_ib_test,
		726	.is_lockup = &r100_gpu_is_lockup,
		727	}
		728	},
		729	.irq = {
		730	.set = &rs600_irq_set,
		731	.process = &rs600_irq_process,
		732	},
		733	.display = {
		734	.get_vblank_counter = &rs600_get_vblank_counter,
		735	.bandwidth_update = &rs690_bandwidth_update,
		736	.wait_for_vblank = &avivo_wait_for_vblank,
		737	// .set_backlight_level = &atombios_set_backlight_level,
		738	// .get_backlight_level = &atombios_get_backlight_level,
		739	},
		740	.copy = {
		741	.blit = &r100_copy_blit,
		742	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		743	.dma = &r200_copy_dma,
		744	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		745	.copy = &r200_copy_dma,
		746	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		747	},
		748	.surface = {
		749	.set_reg = r100_set_surface_reg,
		750	.clear_reg = r100_clear_surface_reg,
		751	},
		752	.hpd = {
		753	// .init = &rs600_hpd_init,
		754	// .fini = &rs600_hpd_fini,
		755	.sense = &rs600_hpd_sense,
		756	.set_polarity = &rs600_hpd_set_polarity,
		757	},
		758	.pm = {
		759	// .misc = &rs600_pm_misc,
		760	// .prepare = &rs600_pm_prepare,
		761	// .finish = &rs600_pm_finish,
		762	// .init_profile = &r420_pm_init_profile,
		763	// .get_dynpm_state = &r100_pm_get_dynpm_state,
		764	// .get_engine_clock = &radeon_atom_get_engine_clock,
		765	// .set_engine_clock = &radeon_atom_set_engine_clock,
		766	// .get_memory_clock = &radeon_atom_get_memory_clock,
		767	// .set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	768	.get_pcie_lanes = NULL,
		769	.set_pcie_lanes = NULL,
2997	Serge	770	// .set_clock_gating = &radeon_atom_set_clock_gating,
		771	},
		772	.pflip = {
		773	// .pre_page_flip = &rs600_pre_page_flip,
		774	// .page_flip = &rs600_page_flip,
		775	// .post_page_flip = &rs600_post_page_flip,
		776	},
1963	serge	777	};
		778
		779	static struct radeon_asic rv515_asic = {
		780	.init = &rv515_init,
		781	// .fini = &rv515_fini,
		782	// .suspend = &rv515_suspend,
		783	// .resume = &rv515_resume,
		784	// .vga_set_state = &r100_vga_set_state,
		785	.asic_reset = &rs600_asic_reset,
3192	Serge	786	.ioctl_wait_idle = NULL,
2160	serge	787	.gui_idle = &r100_gui_idle,
2997	Serge	788	.mc_wait_for_idle = &rv515_mc_wait_for_idle,
		789	.gart = {
		790	.tlb_flush = &rv370_pcie_gart_tlb_flush,
		791	.set_page = &rv370_pcie_gart_set_page,
		792	},
		793	.ring = {
		794	[RADEON_RING_TYPE_GFX_INDEX] = {
		795	.ib_execute = &r100_ring_ib_execute,
		796	.emit_fence = &r300_fence_ring_emit,
		797	.emit_semaphore = &r100_semaphore_ring_emit,
		798	// .cs_parse = &r300_cs_parse,
		799	.ring_start = &rv515_ring_start,
		800	.ring_test = &r100_ring_test,
		801	.ib_test = &r100_ib_test,
		802	.is_lockup = &r100_gpu_is_lockup,
		803	}
		804	},
		805	.irq = {
		806	.set = &rs600_irq_set,
		807	.process = &rs600_irq_process,
		808	},
		809	.display = {
		810	.get_vblank_counter = &rs600_get_vblank_counter,
		811	.bandwidth_update = &rv515_bandwidth_update,
		812	.wait_for_vblank = &avivo_wait_for_vblank,
		813	// .set_backlight_level = &atombios_set_backlight_level,
		814	// .get_backlight_level = &atombios_get_backlight_level,
		815	},
		816	.copy = {
		817	.blit = &r100_copy_blit,
		818	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		819	.dma = &r200_copy_dma,
		820	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		821	.copy = &r100_copy_blit,
		822	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		823	},
		824	.surface = {
		825	.set_reg = r100_set_surface_reg,
		826	.clear_reg = r100_clear_surface_reg,
		827	},
		828	.hpd = {
		829	// .init = &rs600_hpd_init,
		830	// .fini = &rs600_hpd_fini,
		831	// .sense = &rs600_hpd_sense,
		832	// .set_polarity = &rs600_hpd_set_polarity,
		833	},
		834	.pm = {
		835	// .misc = &rs600_pm_misc,
		836	// .prepare = &rs600_pm_prepare,
		837	// .finish = &rs600_pm_finish,
		838	// .init_profile = &r420_pm_init_profile,
		839	// .get_dynpm_state = &r100_pm_get_dynpm_state,
		840	// .get_engine_clock = &radeon_atom_get_engine_clock,
		841	// .set_engine_clock = &radeon_atom_set_engine_clock,
		842	// .get_memory_clock = &radeon_atom_get_memory_clock,
		843	// .set_memory_clock = &radeon_atom_set_memory_clock,
		844	// .get_pcie_lanes = &rv370_get_pcie_lanes,
		845	// .set_pcie_lanes = &rv370_set_pcie_lanes,
		846	// .set_clock_gating = &radeon_atom_set_clock_gating,
		847	},
		848	.pflip = {
		849	// .pre_page_flip = &rs600_pre_page_flip,
		850	// .page_flip = &rs600_page_flip,
		851	// .post_page_flip = &rs600_post_page_flip,
		852	},
1963	serge	853	};
		854
		855	static struct radeon_asic r520_asic = {
		856	.init = &r520_init,
		857	// .fini = &rv515_fini,
		858	// .suspend = &rv515_suspend,
		859	// .resume = &r520_resume,
		860	// .vga_set_state = &r100_vga_set_state,
		861	.asic_reset = &rs600_asic_reset,
3192	Serge	862	.ioctl_wait_idle = NULL,
2160	serge	863	.gui_idle = &r100_gui_idle,
2997	Serge	864	.mc_wait_for_idle = &r520_mc_wait_for_idle,
		865	.gart = {
		866	.tlb_flush = &rv370_pcie_gart_tlb_flush,
		867	.set_page = &rv370_pcie_gart_set_page,
		868	},
		869	.ring = {
		870	[RADEON_RING_TYPE_GFX_INDEX] = {
		871	.ib_execute = &r100_ring_ib_execute,
		872	.emit_fence = &r300_fence_ring_emit,
		873	.emit_semaphore = &r100_semaphore_ring_emit,
		874	// .cs_parse = &r300_cs_parse,
		875	.ring_start = &rv515_ring_start,
		876	.ring_test = &r100_ring_test,
		877	.ib_test = &r100_ib_test,
		878	.is_lockup = &r100_gpu_is_lockup,
		879	}
		880	},
		881	.irq = {
		882	.set = &rs600_irq_set,
		883	.process = &rs600_irq_process,
		884	},
		885	.display = {
		886	.bandwidth_update = &rv515_bandwidth_update,
		887	.get_vblank_counter = &rs600_get_vblank_counter,
		888	.wait_for_vblank = &avivo_wait_for_vblank,
		889	// .set_backlight_level = &atombios_set_backlight_level,
		890	// .get_backlight_level = &atombios_get_backlight_level,
		891	},
		892	.copy = {
		893	.blit = &r100_copy_blit,
		894	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		895	.dma = &r200_copy_dma,
		896	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		897	.copy = &r100_copy_blit,
		898	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		899	},
		900	.surface = {
		901	.set_reg = r100_set_surface_reg,
		902	.clear_reg = r100_clear_surface_reg,
		903	},
		904	.hpd = {
		905	// .init = &rs600_hpd_init,
		906	// .fini = &rs600_hpd_fini,
		907	// .sense = &rs600_hpd_sense,
		908	// .set_polarity = &rs600_hpd_set_polarity,
		909	},
		910	.pm = {
		911	// .misc = &rs600_pm_misc,
		912	// .prepare = &rs600_pm_prepare,
		913	// .finish = &rs600_pm_finish,
		914	// .init_profile = &r420_pm_init_profile,
		915	// .get_dynpm_state = &r100_pm_get_dynpm_state,
		916	// .get_engine_clock = &radeon_atom_get_engine_clock,
		917	// .set_engine_clock = &radeon_atom_set_engine_clock,
		918	// .get_memory_clock = &radeon_atom_get_memory_clock,
		919	// .set_memory_clock = &radeon_atom_set_memory_clock,
		920	// .get_pcie_lanes = &rv370_get_pcie_lanes,
		921	// .set_pcie_lanes = &rv370_set_pcie_lanes,
		922	// .set_clock_gating = &radeon_atom_set_clock_gating,
		923	},
		924	.pflip = {
		925	// .pre_page_flip = &rs600_pre_page_flip,
		926	// .page_flip = &rs600_page_flip,
		927	// .post_page_flip = &rs600_post_page_flip,
		928	},
1963	serge	929	};
		930
		931	static struct radeon_asic r600_asic = {
		932	.init = &r600_init,
		933	// .fini = &r600_fini,
		934	// .suspend = &r600_suspend,
		935	// .resume = &r600_resume,
2997	Serge	936	// .vga_set_state = &r600_vga_set_state,
1963	serge	937	.asic_reset = &r600_asic_reset,
		938	// .ioctl_wait_idle = r600_ioctl_wait_idle,
2997	Serge	939	.gui_idle = &r600_gui_idle,
		940	.mc_wait_for_idle = &r600_mc_wait_for_idle,
3764	Serge	941	.get_xclk = &r600_get_xclk,
		942	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	943	.gart = {
		944	.tlb_flush = &r600_pcie_gart_tlb_flush,
		945	.set_page = &rs600_gart_set_page,
		946	},
		947	.ring = {
		948	[RADEON_RING_TYPE_GFX_INDEX] = {
		949	.ib_execute = &r600_ring_ib_execute,
		950	.emit_fence = &r600_fence_ring_emit,
		951	.emit_semaphore = &r600_semaphore_ring_emit,
		952	// .cs_parse = &r600_cs_parse,
		953	.ring_test = &r600_ring_test,
		954	.ib_test = &r600_ib_test,
3764	Serge	955	.is_lockup = &r600_gfx_is_lockup,
3192	Serge	956	},
		957	[R600_RING_TYPE_DMA_INDEX] = {
		958	.ib_execute = &r600_dma_ring_ib_execute,
		959	.emit_fence = &r600_dma_fence_ring_emit,
		960	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		961	// .cs_parse = &r600_dma_cs_parse,
		962	.ring_test = &r600_dma_ring_test,
		963	.ib_test = &r600_dma_ib_test,
		964	.is_lockup = &r600_dma_is_lockup,
2997	Serge	965	}
		966	},
		967	.irq = {
		968	.set = &r600_irq_set,
		969	.process = &r600_irq_process,
		970	},
		971	.display = {
		972	.bandwidth_update = &rv515_bandwidth_update,
		973	.get_vblank_counter = &rs600_get_vblank_counter,
		974	.wait_for_vblank = &avivo_wait_for_vblank,
		975	// .set_backlight_level = &atombios_set_backlight_level,
		976	// .get_backlight_level = &atombios_get_backlight_level,
		977	},
		978	.copy = {
		979	.blit = &r600_copy_blit,
		980	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	981	.dma = &r600_copy_dma,
		982	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		983	.copy = &r600_copy_dma,
		984	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	985	},
		986	.surface = {
		987	.set_reg = r600_set_surface_reg,
		988	.clear_reg = r600_clear_surface_reg,
		989	},
		990	.hpd = {
		991	// .init = &r600_hpd_init,
		992	// .fini = &r600_hpd_fini,
		993	// .sense = &r600_hpd_sense,
		994	// .set_polarity = &r600_hpd_set_polarity,
		995	},
		996	.pm = {
		997	// .misc = &r600_pm_misc,
		998	// .prepare = &rs600_pm_prepare,
		999	// .finish = &rs600_pm_finish,
		1000	// .init_profile = &r600_pm_init_profile,
		1001	// .get_dynpm_state = &r600_pm_get_dynpm_state,
		1002	// .get_engine_clock = &radeon_atom_get_engine_clock,
		1003	// .set_engine_clock = &radeon_atom_set_engine_clock,
		1004	// .get_memory_clock = &radeon_atom_get_memory_clock,
		1005	// .set_memory_clock = &radeon_atom_set_memory_clock,
		1006	// .get_pcie_lanes = &r600_get_pcie_lanes,
		1007	// .set_pcie_lanes = &r600_set_pcie_lanes,
3120	serge	1008	.set_clock_gating = NULL,
2997	Serge	1009	},
		1010	.pflip = {
		1011	// .pre_page_flip = &rs600_pre_page_flip,
		1012	// .page_flip = &rs600_page_flip,
		1013	// .post_page_flip = &rs600_post_page_flip,
		1014	},
1963	serge	1015	};
		1016
		1017	static struct radeon_asic rs780_asic = {
		1018	.init = &r600_init,
		1019	// .fini = &r600_fini,
		1020	// .suspend = &r600_suspend,
		1021	// .resume = &r600_resume,
2997	Serge	1022	// .vga_set_state = &r600_vga_set_state,
1963	serge	1023	.asic_reset = &r600_asic_reset,
2997	Serge	1024	// .ioctl_wait_idle = r600_ioctl_wait_idle,
		1025	.gui_idle = &r600_gui_idle,
		1026	.mc_wait_for_idle = &r600_mc_wait_for_idle,
3764	Serge	1027	.get_xclk = &r600_get_xclk,
		1028	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1029	.gart = {
		1030	.tlb_flush = &r600_pcie_gart_tlb_flush,
		1031	.set_page = &rs600_gart_set_page,
		1032	},
		1033	.ring = {
		1034	[RADEON_RING_TYPE_GFX_INDEX] = {
		1035	.ib_execute = &r600_ring_ib_execute,
		1036	.emit_fence = &r600_fence_ring_emit,
		1037	.emit_semaphore = &r600_semaphore_ring_emit,
		1038	// .cs_parse = &r600_cs_parse,
		1039	.ring_test = &r600_ring_test,
		1040	.ib_test = &r600_ib_test,
3764	Serge	1041	.is_lockup = &r600_gfx_is_lockup,
3192	Serge	1042	},
		1043	[R600_RING_TYPE_DMA_INDEX] = {
		1044	.ib_execute = &r600_dma_ring_ib_execute,
		1045	.emit_fence = &r600_dma_fence_ring_emit,
		1046	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1047	// .cs_parse = &r600_dma_cs_parse,
		1048	.ring_test = &r600_dma_ring_test,
		1049	.ib_test = &r600_dma_ib_test,
		1050	.is_lockup = &r600_dma_is_lockup,
2997	Serge	1051	}
		1052	},
		1053	.irq = {
		1054	.set = &r600_irq_set,
		1055	.process = &r600_irq_process,
		1056	},
		1057	.display = {
		1058	.bandwidth_update = &rs690_bandwidth_update,
		1059	.get_vblank_counter = &rs600_get_vblank_counter,
		1060	.wait_for_vblank = &avivo_wait_for_vblank,
		1061	// .set_backlight_level = &atombios_set_backlight_level,
		1062	// .get_backlight_level = &atombios_get_backlight_level,
		1063	},
		1064	.copy = {
		1065	.blit = &r600_copy_blit,
		1066	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1067	.dma = &r600_copy_dma,
		1068	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1069	.copy = &r600_copy_dma,
		1070	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1071	},
		1072	.surface = {
		1073	.set_reg = r600_set_surface_reg,
		1074	.clear_reg = r600_clear_surface_reg,
		1075	},
		1076	.hpd = {
		1077	// .init = &r600_hpd_init,
		1078	// .fini = &r600_hpd_fini,
		1079	// .sense = &r600_hpd_sense,
		1080	// .set_polarity = &r600_hpd_set_polarity,
		1081	},
		1082	.pm = {
		1083	// .misc = &r600_pm_misc,
		1084	// .prepare = &rs600_pm_prepare,
		1085	// .finish = &rs600_pm_finish,
		1086	// .init_profile = &rs780_pm_init_profile,
		1087	// .get_dynpm_state = &r600_pm_get_dynpm_state,
		1088	// .get_engine_clock = &radeon_atom_get_engine_clock,
		1089	// .set_engine_clock = &radeon_atom_set_engine_clock,
3120	serge	1090	.get_memory_clock = NULL,
		1091	.set_memory_clock = NULL,
		1092	.get_pcie_lanes = NULL,
		1093	.set_pcie_lanes = NULL,
		1094	.set_clock_gating = NULL,
2997	Serge	1095	},
		1096	.pflip = {
		1097	// .pre_page_flip = &rs600_pre_page_flip,
		1098	// .page_flip = &rs600_page_flip,
		1099	// .post_page_flip = &rs600_post_page_flip,
		1100	},
1963	serge	1101	};
		1102
		1103	static struct radeon_asic rv770_asic = {
		1104	.init = &rv770_init,
		1105	// .fini = &rv770_fini,
		1106	// .suspend = &rv770_suspend,
		1107	// .resume = &rv770_resume,
		1108	.asic_reset = &r600_asic_reset,
2997	Serge	1109	// .vga_set_state = &r600_vga_set_state,
		1110	// .ioctl_wait_idle = r600_ioctl_wait_idle,
		1111	.gui_idle = &r600_gui_idle,
		1112	.mc_wait_for_idle = &r600_mc_wait_for_idle,
3764	Serge	1113	.get_xclk = &rv770_get_xclk,
		1114	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1115	.gart = {
		1116	.tlb_flush = &r600_pcie_gart_tlb_flush,
		1117	.set_page = &rs600_gart_set_page,
		1118	},
		1119	.ring = {
		1120	[RADEON_RING_TYPE_GFX_INDEX] = {
		1121	.ib_execute = &r600_ring_ib_execute,
		1122	.emit_fence = &r600_fence_ring_emit,
		1123	.emit_semaphore = &r600_semaphore_ring_emit,
		1124	// .cs_parse = &r600_cs_parse,
		1125	.ring_test = &r600_ring_test,
		1126	.ib_test = &r600_ib_test,
3764	Serge	1127	.is_lockup = &r600_gfx_is_lockup,
3192	Serge	1128	},
		1129	[R600_RING_TYPE_DMA_INDEX] = {
		1130	.ib_execute = &r600_dma_ring_ib_execute,
		1131	.emit_fence = &r600_dma_fence_ring_emit,
		1132	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1133	// .cs_parse = &r600_dma_cs_parse,
		1134	.ring_test = &r600_dma_ring_test,
		1135	.ib_test = &r600_dma_ib_test,
		1136	.is_lockup = &r600_dma_is_lockup,
3764	Serge	1137	},
		1138	[R600_RING_TYPE_UVD_INDEX] = {
		1139	// .ib_execute = &r600_uvd_ib_execute,
		1140	// .emit_fence = &r600_uvd_fence_emit,
		1141	// .emit_semaphore = &r600_uvd_semaphore_emit,
		1142	// .cs_parse = &radeon_uvd_cs_parse,
		1143	// .ring_test = &r600_uvd_ring_test,
		1144	// .ib_test = &r600_uvd_ib_test,
		1145	// .is_lockup = &radeon_ring_test_lockup,
2997	Serge	1146	}
		1147	},
		1148	.irq = {
		1149	.set = &r600_irq_set,
		1150	.process = &r600_irq_process,
		1151	},
		1152	.display = {
		1153	.bandwidth_update = &rv515_bandwidth_update,
		1154	.get_vblank_counter = &rs600_get_vblank_counter,
		1155	.wait_for_vblank = &avivo_wait_for_vblank,
		1156	// .set_backlight_level = &atombios_set_backlight_level,
		1157	// .get_backlight_level = &atombios_get_backlight_level,
		1158	},
		1159	.copy = {
		1160	.blit = &r600_copy_blit,
		1161	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3764	Serge	1162	.dma = &rv770_copy_dma,
3192	Serge	1163	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
3764	Serge	1164	.copy = &rv770_copy_dma,
3192	Serge	1165	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1166	},
		1167	.surface = {
		1168	.set_reg = r600_set_surface_reg,
		1169	.clear_reg = r600_clear_surface_reg,
		1170	},
		1171	.hpd = {
		1172	// .init = &r600_hpd_init,
		1173	// .fini = &r600_hpd_fini,
		1174	// .sense = &r600_hpd_sense,
		1175	// .set_polarity = &r600_hpd_set_polarity,
		1176	},
		1177	.pm = {
		1178	// .misc = &rv770_pm_misc,
		1179	// .prepare = &rs600_pm_prepare,
		1180	// .finish = &rs600_pm_finish,
		1181	// .init_profile = &r600_pm_init_profile,
		1182	// .get_dynpm_state = &r600_pm_get_dynpm_state,
		1183	// .get_engine_clock = &radeon_atom_get_engine_clock,
		1184	// .set_engine_clock = &radeon_atom_set_engine_clock,
		1185	// .get_memory_clock = &radeon_atom_get_memory_clock,
		1186	// .set_memory_clock = &radeon_atom_set_memory_clock,
		1187	// .get_pcie_lanes = &r600_get_pcie_lanes,
		1188	// .set_pcie_lanes = &r600_set_pcie_lanes,
		1189	// .set_clock_gating = &radeon_atom_set_clock_gating,
3764	Serge	1190	.set_uvd_clocks = &rv770_set_uvd_clocks,
2997	Serge	1191	},
		1192	.pflip = {
		1193	// .pre_page_flip = &rs600_pre_page_flip,
		1194	// .page_flip = &rv770_page_flip,
		1195	// .post_page_flip = &rs600_post_page_flip,
		1196	},
1963	serge	1197	};
1986	serge	1198
1963	serge	1199	static struct radeon_asic evergreen_asic = {
		1200	.init = &evergreen_init,
		1201	// .fini = &evergreen_fini,
		1202	// .suspend = &evergreen_suspend,
		1203	// .resume = &evergreen_resume,
		1204	.asic_reset = &evergreen_asic_reset,
2997	Serge	1205	// .vga_set_state = &r600_vga_set_state,
		1206	// .ioctl_wait_idle = r600_ioctl_wait_idle,
		1207	.gui_idle = &r600_gui_idle,
		1208	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1209	.get_xclk = &rv770_get_xclk,
		1210	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1211	.gart = {
		1212	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
		1213	.set_page = &rs600_gart_set_page,
		1214	},
		1215	.ring = {
		1216	[RADEON_RING_TYPE_GFX_INDEX] = {
		1217	.ib_execute = &evergreen_ring_ib_execute,
		1218	.emit_fence = &r600_fence_ring_emit,
		1219	.emit_semaphore = &r600_semaphore_ring_emit,
		1220	// .cs_parse = &evergreen_cs_parse,
		1221	.ring_test = &r600_ring_test,
		1222	.ib_test = &r600_ib_test,
3764	Serge	1223	.is_lockup = &evergreen_gfx_is_lockup,
3192	Serge	1224	},
		1225	[R600_RING_TYPE_DMA_INDEX] = {
		1226	.ib_execute = &evergreen_dma_ring_ib_execute,
		1227	.emit_fence = &evergreen_dma_fence_ring_emit,
		1228	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1229	// .cs_parse = &evergreen_dma_cs_parse,
		1230	.ring_test = &r600_dma_ring_test,
		1231	.ib_test = &r600_dma_ib_test,
3764	Serge	1232	.is_lockup = &evergreen_dma_is_lockup,
		1233	},
		1234	[R600_RING_TYPE_UVD_INDEX] = {
		1235	// .ib_execute = &r600_uvd_ib_execute,
		1236	// .emit_fence = &r600_uvd_fence_emit,
		1237	// .emit_semaphore = &r600_uvd_semaphore_emit,
		1238	// .cs_parse = &radeon_uvd_cs_parse,
		1239	// .ring_test = &r600_uvd_ring_test,
		1240	// .ib_test = &r600_uvd_ib_test,
		1241	// .is_lockup = &radeon_ring_test_lockup,
2997	Serge	1242	}
		1243	},
		1244	.irq = {
		1245	.set = &evergreen_irq_set,
		1246	.process = &evergreen_irq_process,
		1247	},
		1248	.display = {
		1249	.bandwidth_update = &evergreen_bandwidth_update,
		1250	.get_vblank_counter = &evergreen_get_vblank_counter,
		1251	.wait_for_vblank = &dce4_wait_for_vblank,
		1252	// .set_backlight_level = &atombios_set_backlight_level,
		1253	// .get_backlight_level = &atombios_get_backlight_level,
		1254	},
		1255	.copy = {
		1256	.blit = &r600_copy_blit,
		1257	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1258	.dma = &evergreen_copy_dma,
		1259	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1260	.copy = &evergreen_copy_dma,
		1261	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1262	},
		1263	.surface = {
		1264	.set_reg = r600_set_surface_reg,
		1265	.clear_reg = r600_clear_surface_reg,
		1266	},
		1267	.hpd = {
		1268	// .init = &evergreen_hpd_init,
		1269	// .fini = &evergreen_hpd_fini,
		1270	// .sense = &evergreen_hpd_sense,
		1271	// .set_polarity = &evergreen_hpd_set_polarity,
		1272	},
		1273	.pm = {
		1274	// .misc = &evergreen_pm_misc,
		1275	// .prepare = &evergreen_pm_prepare,
		1276	// .finish = &evergreen_pm_finish,
		1277	// .init_profile = &r600_pm_init_profile,
		1278	// .get_dynpm_state = &r600_pm_get_dynpm_state,
		1279	// .get_engine_clock = &radeon_atom_get_engine_clock,
		1280	// .set_engine_clock = &radeon_atom_set_engine_clock,
		1281	// .get_memory_clock = &radeon_atom_get_memory_clock,
		1282	// .set_memory_clock = &radeon_atom_set_memory_clock,
		1283	// .get_pcie_lanes = &r600_get_pcie_lanes,
		1284	// .set_pcie_lanes = &r600_set_pcie_lanes,
		1285	// .set_clock_gating = NULL,
3764	Serge	1286	.set_uvd_clocks = &evergreen_set_uvd_clocks,
2997	Serge	1287	},
		1288	.pflip = {
		1289	// .pre_page_flip = &evergreen_pre_page_flip,
		1290	// .page_flip = &evergreen_page_flip,
		1291	// .post_page_flip = &evergreen_post_page_flip,
		1292	},
1986	serge	1293	};
1990	serge	1294
1986	serge	1295	static struct radeon_asic sumo_asic = {
		1296	.init = &evergreen_init,
1990	serge	1297	// .fini = &evergreen_fini,
		1298	// .suspend = &evergreen_suspend,
		1299	// .resume = &evergreen_resume,
1986	serge	1300	.asic_reset = &evergreen_asic_reset,
2997	Serge	1301	// .vga_set_state = &r600_vga_set_state,
		1302	// .ioctl_wait_idle = r600_ioctl_wait_idle,
		1303	.gui_idle = &r600_gui_idle,
		1304	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1305	.get_xclk = &r600_get_xclk,
		1306	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1307	.gart = {
		1308	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
		1309	.set_page = &rs600_gart_set_page,
		1310	},
		1311	.ring = {
		1312	[RADEON_RING_TYPE_GFX_INDEX] = {
		1313	.ib_execute = &evergreen_ring_ib_execute,
		1314	.emit_fence = &r600_fence_ring_emit,
		1315	.emit_semaphore = &r600_semaphore_ring_emit,
		1316	// .cs_parse = &evergreen_cs_parse,
		1317	.ring_test = &r600_ring_test,
		1318	.ib_test = &r600_ib_test,
3764	Serge	1319	.is_lockup = &evergreen_gfx_is_lockup,
2997	Serge	1320	},
3192	Serge	1321	[R600_RING_TYPE_DMA_INDEX] = {
		1322	.ib_execute = &evergreen_dma_ring_ib_execute,
		1323	.emit_fence = &evergreen_dma_fence_ring_emit,
		1324	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1325	// .cs_parse = &evergreen_dma_cs_parse,
		1326	.ring_test = &r600_dma_ring_test,
		1327	.ib_test = &r600_dma_ib_test,
3764	Serge	1328	.is_lockup = &evergreen_dma_is_lockup,
		1329	},
		1330	[R600_RING_TYPE_UVD_INDEX] = {
		1331	// .ib_execute = &r600_uvd_ib_execute,
		1332	// .emit_fence = &r600_uvd_fence_emit,
		1333	// .emit_semaphore = &r600_uvd_semaphore_emit,
		1334	// .cs_parse = &radeon_uvd_cs_parse,
		1335	// .ring_test = &r600_uvd_ring_test,
		1336	// .ib_test = &r600_uvd_ib_test,
		1337	// .is_lockup = &radeon_ring_test_lockup,
3192	Serge	1338	}
2997	Serge	1339	},
		1340	.irq = {
		1341	.set = &evergreen_irq_set,
		1342	.process = &evergreen_irq_process,
		1343	},
		1344	.display = {
		1345	.bandwidth_update = &evergreen_bandwidth_update,
		1346	.get_vblank_counter = &evergreen_get_vblank_counter,
		1347	.wait_for_vblank = &dce4_wait_for_vblank,
		1348	// .set_backlight_level = &atombios_set_backlight_level,
		1349	// .get_backlight_level = &atombios_get_backlight_level,
		1350	},
		1351	.copy = {
		1352	.blit = &r600_copy_blit,
		1353	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1354	.dma = &evergreen_copy_dma,
		1355	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1356	.copy = &evergreen_copy_dma,
		1357	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1358	},
		1359	.surface = {
		1360	.set_reg = r600_set_surface_reg,
		1361	.clear_reg = r600_clear_surface_reg,
		1362	},
		1363	.hpd = {
		1364	// .init = &evergreen_hpd_init,
		1365	// .fini = &evergreen_hpd_fini,
		1366	// .sense = &evergreen_hpd_sense,
		1367	// .set_polarity = &evergreen_hpd_set_polarity,
		1368	},
		1369	.pm = {
		1370	// .misc = &evergreen_pm_misc,
		1371	// .prepare = &evergreen_pm_prepare,
		1372	// .finish = &evergreen_pm_finish,
		1373	// .init_profile = &sumo_pm_init_profile,
		1374	// .get_dynpm_state = &r600_pm_get_dynpm_state,
		1375	// .get_engine_clock = &radeon_atom_get_engine_clock,
		1376	// .set_engine_clock = &radeon_atom_set_engine_clock,
3120	serge	1377	.get_memory_clock = NULL,
		1378	.set_memory_clock = NULL,
		1379	.get_pcie_lanes = NULL,
		1380	.set_pcie_lanes = NULL,
		1381	.set_clock_gating = NULL,
3764	Serge	1382	.set_uvd_clocks = &sumo_set_uvd_clocks,
2997	Serge	1383	},
		1384	.pflip = {
		1385	// .pre_page_flip = &evergreen_pre_page_flip,
		1386	// .page_flip = &evergreen_page_flip,
		1387	// .post_page_flip = &evergreen_post_page_flip,
		1388	},
1986	serge	1389	};
		1390
		1391	static struct radeon_asic btc_asic = {
		1392	.init = &evergreen_init,
1990	serge	1393	// .fini = &evergreen_fini,
		1394	// .suspend = &evergreen_suspend,
		1395	// .resume = &evergreen_resume,
1986	serge	1396	.asic_reset = &evergreen_asic_reset,
2997	Serge	1397	// .vga_set_state = &r600_vga_set_state,
		1398	// .ioctl_wait_idle = r600_ioctl_wait_idle,
		1399	.gui_idle = &r600_gui_idle,
		1400	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1401	.get_xclk = &rv770_get_xclk,
		1402	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1403	.gart = {
		1404	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
		1405	.set_page = &rs600_gart_set_page,
		1406	},
		1407	.ring = {
		1408	[RADEON_RING_TYPE_GFX_INDEX] = {
		1409	.ib_execute = &evergreen_ring_ib_execute,
		1410	.emit_fence = &r600_fence_ring_emit,
		1411	.emit_semaphore = &r600_semaphore_ring_emit,
		1412	// .cs_parse = &evergreen_cs_parse,
		1413	.ring_test = &r600_ring_test,
		1414	.ib_test = &r600_ib_test,
3764	Serge	1415	.is_lockup = &evergreen_gfx_is_lockup,
3192	Serge	1416	},
		1417	[R600_RING_TYPE_DMA_INDEX] = {
		1418	.ib_execute = &evergreen_dma_ring_ib_execute,
		1419	.emit_fence = &evergreen_dma_fence_ring_emit,
		1420	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1421	// .cs_parse = &evergreen_dma_cs_parse,
		1422	.ring_test = &r600_dma_ring_test,
		1423	.ib_test = &r600_dma_ib_test,
3764	Serge	1424	.is_lockup = &evergreen_dma_is_lockup,
		1425	},
		1426	[R600_RING_TYPE_UVD_INDEX] = {
		1427	// .ib_execute = &r600_uvd_ib_execute,
		1428	// .emit_fence = &r600_uvd_fence_emit,
		1429	// .emit_semaphore = &r600_uvd_semaphore_emit,
		1430	// .cs_parse = &radeon_uvd_cs_parse,
		1431	// .ring_test = &r600_uvd_ring_test,
		1432	// .ib_test = &r600_uvd_ib_test,
		1433	// .is_lockup = &radeon_ring_test_lockup,
2997	Serge	1434	}
		1435	},
		1436	.irq = {
		1437	.set = &evergreen_irq_set,
		1438	.process = &evergreen_irq_process,
		1439	},
		1440	.display = {
		1441	.bandwidth_update = &evergreen_bandwidth_update,
		1442	.get_vblank_counter = &evergreen_get_vblank_counter,
		1443	.wait_for_vblank = &dce4_wait_for_vblank,
		1444	// .set_backlight_level = &atombios_set_backlight_level,
		1445	// .get_backlight_level = &atombios_get_backlight_level,
		1446	},
		1447	.copy = {
		1448	.blit = &r600_copy_blit,
		1449	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1450	.dma = &evergreen_copy_dma,
		1451	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1452	.copy = &evergreen_copy_dma,
		1453	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1454	},
		1455	.surface = {
		1456	.set_reg = r600_set_surface_reg,
		1457	.clear_reg = r600_clear_surface_reg,
		1458	},
		1459	.hpd = {
		1460	// .init = &evergreen_hpd_init,
		1461	// .fini = &evergreen_hpd_fini,
		1462	// .sense = &evergreen_hpd_sense,
		1463	// .set_polarity = &evergreen_hpd_set_polarity,
		1464	},
		1465	.pm = {
		1466	// .misc = &evergreen_pm_misc,
		1467	// .prepare = &evergreen_pm_prepare,
		1468	// .finish = &evergreen_pm_finish,
		1469	// .init_profile = &btc_pm_init_profile,
		1470	// .get_dynpm_state = &r600_pm_get_dynpm_state,
		1471	// .get_engine_clock = &radeon_atom_get_engine_clock,
		1472	// .set_engine_clock = &radeon_atom_set_engine_clock,
		1473	// .get_memory_clock = &radeon_atom_get_memory_clock,
		1474	// .set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	1475	.get_pcie_lanes = NULL,
		1476	.set_pcie_lanes = NULL,
		1477	.set_clock_gating = NULL,
3764	Serge	1478	.set_uvd_clocks = &evergreen_set_uvd_clocks,
2997	Serge	1479	},
		1480	.pflip = {
		1481	// .pre_page_flip = &evergreen_pre_page_flip,
		1482	// .page_flip = &evergreen_page_flip,
		1483	// .post_page_flip = &evergreen_post_page_flip,
		1484	},
1986	serge	1485	};
		1486
		1487	static struct radeon_asic cayman_asic = {
		1488	.init = &cayman_init,
2997	Serge	1489	// .fini = &cayman_fini,
		1490	// .suspend = &cayman_suspend,
		1491	// .resume = &cayman_resume,
1986	serge	1492	.asic_reset = &cayman_asic_reset,
2997	Serge	1493	// .vga_set_state = &r600_vga_set_state,
		1494	// .ioctl_wait_idle = r600_ioctl_wait_idle,
		1495	.gui_idle = &r600_gui_idle,
		1496	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1497	.get_xclk = &rv770_get_xclk,
		1498	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1499	.gart = {
		1500	.tlb_flush = &cayman_pcie_gart_tlb_flush,
		1501	.set_page = &rs600_gart_set_page,
		1502	},
		1503	.vm = {
		1504	.init = &cayman_vm_init,
		1505	.fini = &cayman_vm_fini,
3192	Serge	1506	.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1507	.set_page = &cayman_vm_set_page,
		1508	},
		1509	.ring = {
		1510	[RADEON_RING_TYPE_GFX_INDEX] = {
		1511	.ib_execute = &cayman_ring_ib_execute,
		1512	// .ib_parse = &evergreen_ib_parse,
		1513	.emit_fence = &cayman_fence_ring_emit,
		1514	.emit_semaphore = &r600_semaphore_ring_emit,
		1515	// .cs_parse = &evergreen_cs_parse,
		1516	.ring_test = &r600_ring_test,
		1517	.ib_test = &r600_ib_test,
3764	Serge	1518	.is_lockup = &cayman_gfx_is_lockup,
2997	Serge	1519	.vm_flush = &cayman_vm_flush,
		1520	},
		1521	[CAYMAN_RING_TYPE_CP1_INDEX] = {
		1522	.ib_execute = &cayman_ring_ib_execute,
		1523	// .ib_parse = &evergreen_ib_parse,
		1524	.emit_fence = &cayman_fence_ring_emit,
		1525	.emit_semaphore = &r600_semaphore_ring_emit,
		1526	// .cs_parse = &evergreen_cs_parse,
		1527	.ring_test = &r600_ring_test,
		1528	.ib_test = &r600_ib_test,
3764	Serge	1529	.is_lockup = &cayman_gfx_is_lockup,
2997	Serge	1530	.vm_flush = &cayman_vm_flush,
		1531	},
		1532	[CAYMAN_RING_TYPE_CP2_INDEX] = {
		1533	.ib_execute = &cayman_ring_ib_execute,
		1534	// .ib_parse = &evergreen_ib_parse,
		1535	.emit_fence = &cayman_fence_ring_emit,
		1536	.emit_semaphore = &r600_semaphore_ring_emit,
		1537	// .cs_parse = &evergreen_cs_parse,
		1538	.ring_test = &r600_ring_test,
		1539	.ib_test = &r600_ib_test,
3764	Serge	1540	.is_lockup = &cayman_gfx_is_lockup,
2997	Serge	1541	.vm_flush = &cayman_vm_flush,
3192	Serge	1542	},
		1543	[R600_RING_TYPE_DMA_INDEX] = {
		1544	.ib_execute = &cayman_dma_ring_ib_execute,
		1545	// .ib_parse = &evergreen_dma_ib_parse,
		1546	.emit_fence = &evergreen_dma_fence_ring_emit,
		1547	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1548	// .cs_parse = &evergreen_dma_cs_parse,
		1549	.ring_test = &r600_dma_ring_test,
		1550	.ib_test = &r600_dma_ib_test,
		1551	.is_lockup = &cayman_dma_is_lockup,
		1552	.vm_flush = &cayman_dma_vm_flush,
		1553	},
		1554	[CAYMAN_RING_TYPE_DMA1_INDEX] = {
		1555	.ib_execute = &cayman_dma_ring_ib_execute,
		1556	// .ib_parse = &evergreen_dma_ib_parse,
		1557	.emit_fence = &evergreen_dma_fence_ring_emit,
		1558	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1559	// .cs_parse = &evergreen_dma_cs_parse,
		1560	.ring_test = &r600_dma_ring_test,
		1561	.ib_test = &r600_dma_ib_test,
		1562	.is_lockup = &cayman_dma_is_lockup,
		1563	.vm_flush = &cayman_dma_vm_flush,
3764	Serge	1564	},
		1565	[R600_RING_TYPE_UVD_INDEX] = {
		1566	// .ib_execute = &r600_uvd_ib_execute,
		1567	// .emit_fence = &r600_uvd_fence_emit,
		1568	// .emit_semaphore = &cayman_uvd_semaphore_emit,
		1569	// .cs_parse = &radeon_uvd_cs_parse,
		1570	// .ring_test = &r600_uvd_ring_test,
		1571	// .ib_test = &r600_uvd_ib_test,
		1572	// .is_lockup = &radeon_ring_test_lockup,
2997	Serge	1573	}
		1574	},
		1575	.irq = {
		1576	.set = &evergreen_irq_set,
		1577	.process = &evergreen_irq_process,
		1578	},
		1579	.display = {
		1580	.bandwidth_update = &evergreen_bandwidth_update,
		1581	.get_vblank_counter = &evergreen_get_vblank_counter,
		1582	.wait_for_vblank = &dce4_wait_for_vblank,
		1583	// .set_backlight_level = &atombios_set_backlight_level,
		1584	// .get_backlight_level = &atombios_get_backlight_level,
		1585	},
		1586	.copy = {
		1587	.blit = &r600_copy_blit,
		1588	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1589	.dma = &evergreen_copy_dma,
		1590	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1591	.copy = &evergreen_copy_dma,
		1592	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1593	},
		1594	.surface = {
		1595	.set_reg = r600_set_surface_reg,
		1596	.clear_reg = r600_clear_surface_reg,
		1597	},
		1598	.hpd = {
		1599	// .init = &evergreen_hpd_init,
		1600	// .fini = &evergreen_hpd_fini,
		1601	// .sense = &evergreen_hpd_sense,
		1602	// .set_polarity = &evergreen_hpd_set_polarity,
		1603	},
		1604	.pm = {
		1605	// .misc = &evergreen_pm_misc,
		1606	// .prepare = &evergreen_pm_prepare,
		1607	// .finish = &evergreen_pm_finish,
		1608	// .init_profile = &btc_pm_init_profile,
		1609	// .get_dynpm_state = &r600_pm_get_dynpm_state,
		1610	// .get_engine_clock = &radeon_atom_get_engine_clock,
		1611	// .set_engine_clock = &radeon_atom_set_engine_clock,
		1612	// .get_memory_clock = &radeon_atom_get_memory_clock,
		1613	// .set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	1614	.get_pcie_lanes = NULL,
		1615	.set_pcie_lanes = NULL,
		1616	.set_clock_gating = NULL,
3764	Serge	1617	.set_uvd_clocks = &evergreen_set_uvd_clocks,
2997	Serge	1618	},
		1619	.pflip = {
		1620	// .pre_page_flip = &evergreen_pre_page_flip,
		1621	// .page_flip = &evergreen_page_flip,
		1622	// .post_page_flip = &evergreen_post_page_flip,
		1623	},
1963	serge	1624	};
		1625
2997	Serge	1626	static struct radeon_asic trinity_asic = {
		1627	.init = &cayman_init,
		1628	// .fini = &cayman_fini,
		1629	// .suspend = &cayman_suspend,
		1630	// .resume = &cayman_resume,
		1631	.asic_reset = &cayman_asic_reset,
		1632	// .vga_set_state = &r600_vga_set_state,
		1633	// .ioctl_wait_idle = r600_ioctl_wait_idle,
		1634	.gui_idle = &r600_gui_idle,
		1635	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1636	.get_xclk = &r600_get_xclk,
		1637	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1638	.gart = {
		1639	.tlb_flush = &cayman_pcie_gart_tlb_flush,
		1640	.set_page = &rs600_gart_set_page,
		1641	},
		1642	.vm = {
		1643	.init = &cayman_vm_init,
		1644	.fini = &cayman_vm_fini,
3192	Serge	1645	.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1646	.set_page = &cayman_vm_set_page,
		1647	},
		1648	.ring = {
		1649	[RADEON_RING_TYPE_GFX_INDEX] = {
		1650	.ib_execute = &cayman_ring_ib_execute,
		1651	// .ib_parse = &evergreen_ib_parse,
		1652	.emit_fence = &cayman_fence_ring_emit,
		1653	.emit_semaphore = &r600_semaphore_ring_emit,
		1654	// .cs_parse = &evergreen_cs_parse,
		1655	.ring_test = &r600_ring_test,
		1656	.ib_test = &r600_ib_test,
3764	Serge	1657	.is_lockup = &cayman_gfx_is_lockup,
2997	Serge	1658	.vm_flush = &cayman_vm_flush,
		1659	},
		1660	[CAYMAN_RING_TYPE_CP1_INDEX] = {
		1661	.ib_execute = &cayman_ring_ib_execute,
		1662	// .ib_parse = &evergreen_ib_parse,
		1663	.emit_fence = &cayman_fence_ring_emit,
		1664	.emit_semaphore = &r600_semaphore_ring_emit,
		1665	// .cs_parse = &evergreen_cs_parse,
		1666	.ring_test = &r600_ring_test,
		1667	.ib_test = &r600_ib_test,
3764	Serge	1668	.is_lockup = &cayman_gfx_is_lockup,
2997	Serge	1669	.vm_flush = &cayman_vm_flush,
		1670	},
		1671	[CAYMAN_RING_TYPE_CP2_INDEX] = {
		1672	.ib_execute = &cayman_ring_ib_execute,
		1673	// .ib_parse = &evergreen_ib_parse,
		1674	.emit_fence = &cayman_fence_ring_emit,
		1675	.emit_semaphore = &r600_semaphore_ring_emit,
		1676	// .cs_parse = &evergreen_cs_parse,
		1677	.ring_test = &r600_ring_test,
		1678	.ib_test = &r600_ib_test,
3764	Serge	1679	.is_lockup = &cayman_gfx_is_lockup,
2997	Serge	1680	.vm_flush = &cayman_vm_flush,
3192	Serge	1681	},
		1682	[R600_RING_TYPE_DMA_INDEX] = {
		1683	.ib_execute = &cayman_dma_ring_ib_execute,
		1684	// .ib_parse = &evergreen_dma_ib_parse,
		1685	.emit_fence = &evergreen_dma_fence_ring_emit,
		1686	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1687	// .cs_parse = &evergreen_dma_cs_parse,
		1688	.ring_test = &r600_dma_ring_test,
		1689	.ib_test = &r600_dma_ib_test,
		1690	.is_lockup = &cayman_dma_is_lockup,
		1691	.vm_flush = &cayman_dma_vm_flush,
		1692	},
		1693	[CAYMAN_RING_TYPE_DMA1_INDEX] = {
		1694	.ib_execute = &cayman_dma_ring_ib_execute,
		1695	// .ib_parse = &evergreen_dma_ib_parse,
		1696	.emit_fence = &evergreen_dma_fence_ring_emit,
		1697	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1698	// .cs_parse = &evergreen_dma_cs_parse,
		1699	.ring_test = &r600_dma_ring_test,
		1700	.ib_test = &r600_dma_ib_test,
		1701	.is_lockup = &cayman_dma_is_lockup,
		1702	.vm_flush = &cayman_dma_vm_flush,
3764	Serge	1703	},
		1704	[R600_RING_TYPE_UVD_INDEX] = {
		1705	// .ib_execute = &r600_uvd_ib_execute,
		1706	// .emit_fence = &r600_uvd_fence_emit,
		1707	// .emit_semaphore = &cayman_uvd_semaphore_emit,
		1708	// .cs_parse = &radeon_uvd_cs_parse,
		1709	// .ring_test = &r600_uvd_ring_test,
		1710	// .ib_test = &r600_uvd_ib_test,
		1711	// .is_lockup = &radeon_ring_test_lockup,
2997	Serge	1712	}
		1713	},
		1714	.irq = {
		1715	.set = &evergreen_irq_set,
		1716	.process = &evergreen_irq_process,
		1717	},
		1718	.display = {
		1719	.bandwidth_update = &dce6_bandwidth_update,
		1720	.get_vblank_counter = &evergreen_get_vblank_counter,
		1721	.wait_for_vblank = &dce4_wait_for_vblank,
		1722	// .set_backlight_level = &atombios_set_backlight_level,
		1723	// .get_backlight_level = &atombios_get_backlight_level,
		1724	},
		1725	.copy = {
		1726	.blit = &r600_copy_blit,
		1727	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1728	.dma = &evergreen_copy_dma,
		1729	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1730	.copy = &evergreen_copy_dma,
		1731	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1732	},
		1733	.surface = {
		1734	.set_reg = r600_set_surface_reg,
		1735	.clear_reg = r600_clear_surface_reg,
		1736	},
		1737	.hpd = {
		1738	// .init = &evergreen_hpd_init,
		1739	// .fini = &evergreen_hpd_fini,
		1740	// .sense = &evergreen_hpd_sense,
		1741	// .set_polarity = &evergreen_hpd_set_polarity,
		1742	},
		1743	.pm = {
		1744	// .misc = &evergreen_pm_misc,
		1745	// .prepare = &evergreen_pm_prepare,
		1746	// .finish = &evergreen_pm_finish,
		1747	// .init_profile = &sumo_pm_init_profile,
		1748	// .get_dynpm_state = &r600_pm_get_dynpm_state,
		1749	// .get_engine_clock = &radeon_atom_get_engine_clock,
		1750	// .set_engine_clock = &radeon_atom_set_engine_clock,
3120	serge	1751	.get_memory_clock = NULL,
		1752	.set_memory_clock = NULL,
		1753	.get_pcie_lanes = NULL,
		1754	.set_pcie_lanes = NULL,
		1755	.set_clock_gating = NULL,
3764	Serge	1756	.set_uvd_clocks = &sumo_set_uvd_clocks,
2997	Serge	1757	},
		1758	.pflip = {
		1759	// .pre_page_flip = &evergreen_pre_page_flip,
		1760	// .page_flip = &evergreen_page_flip,
		1761	// .post_page_flip = &evergreen_post_page_flip,
		1762	},
		1763	};
		1764
		1765	static struct radeon_asic si_asic = {
		1766	.init = &si_init,
		1767	// .fini = &si_fini,
		1768	// .suspend = &si_suspend,
		1769	// .resume = &si_resume,
		1770	.asic_reset = &si_asic_reset,
		1771	// .vga_set_state = &r600_vga_set_state,
		1772	// .ioctl_wait_idle = r600_ioctl_wait_idle,
		1773	.gui_idle = &r600_gui_idle,
		1774	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1775	.get_xclk = &si_get_xclk,
		1776	.get_gpu_clock_counter = &si_get_gpu_clock_counter,
2997	Serge	1777	.gart = {
		1778	.tlb_flush = &si_pcie_gart_tlb_flush,
		1779	.set_page = &rs600_gart_set_page,
		1780	},
		1781	.vm = {
		1782	.init = &si_vm_init,
		1783	.fini = &si_vm_fini,
3192	Serge	1784	.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1785	.set_page = &si_vm_set_page,
		1786	},
		1787	.ring = {
		1788	[RADEON_RING_TYPE_GFX_INDEX] = {
		1789	.ib_execute = &si_ring_ib_execute,
		1790	// .ib_parse = &si_ib_parse,
		1791	.emit_fence = &si_fence_ring_emit,
		1792	.emit_semaphore = &r600_semaphore_ring_emit,
3120	serge	1793	.cs_parse = NULL,
2997	Serge	1794	.ring_test = &r600_ring_test,
		1795	.ib_test = &r600_ib_test,
3764	Serge	1796	.is_lockup = &si_gfx_is_lockup,
2997	Serge	1797	.vm_flush = &si_vm_flush,
		1798	},
		1799	[CAYMAN_RING_TYPE_CP1_INDEX] = {
		1800	.ib_execute = &si_ring_ib_execute,
		1801	// .ib_parse = &si_ib_parse,
		1802	.emit_fence = &si_fence_ring_emit,
		1803	.emit_semaphore = &r600_semaphore_ring_emit,
3120	serge	1804	.cs_parse = NULL,
2997	Serge	1805	.ring_test = &r600_ring_test,
		1806	.ib_test = &r600_ib_test,
3764	Serge	1807	.is_lockup = &si_gfx_is_lockup,
2997	Serge	1808	.vm_flush = &si_vm_flush,
		1809	},
		1810	[CAYMAN_RING_TYPE_CP2_INDEX] = {
		1811	.ib_execute = &si_ring_ib_execute,
		1812	// .ib_parse = &si_ib_parse,
		1813	.emit_fence = &si_fence_ring_emit,
		1814	.emit_semaphore = &r600_semaphore_ring_emit,
3120	serge	1815	.cs_parse = NULL,
2997	Serge	1816	.ring_test = &r600_ring_test,
		1817	.ib_test = &r600_ib_test,
3764	Serge	1818	.is_lockup = &si_gfx_is_lockup,
2997	Serge	1819	.vm_flush = &si_vm_flush,
3192	Serge	1820	},
		1821	[R600_RING_TYPE_DMA_INDEX] = {
		1822	.ib_execute = &cayman_dma_ring_ib_execute,
		1823	// .ib_parse = &evergreen_dma_ib_parse,
		1824	.emit_fence = &evergreen_dma_fence_ring_emit,
		1825	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1826	.cs_parse = NULL,
		1827	.ring_test = &r600_dma_ring_test,
		1828	.ib_test = &r600_dma_ib_test,
3764	Serge	1829	.is_lockup = &si_dma_is_lockup,
3192	Serge	1830	.vm_flush = &si_dma_vm_flush,
		1831	},
		1832	[CAYMAN_RING_TYPE_DMA1_INDEX] = {
		1833	.ib_execute = &cayman_dma_ring_ib_execute,
		1834	// .ib_parse = &evergreen_dma_ib_parse,
		1835	.emit_fence = &evergreen_dma_fence_ring_emit,
		1836	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1837	.cs_parse = NULL,
		1838	.ring_test = &r600_dma_ring_test,
		1839	.ib_test = &r600_dma_ib_test,
3764	Serge	1840	.is_lockup = &si_dma_is_lockup,
3192	Serge	1841	.vm_flush = &si_dma_vm_flush,
3764	Serge	1842	},
		1843	[R600_RING_TYPE_UVD_INDEX] = {
		1844	// .ib_execute = &r600_uvd_ib_execute,
		1845	// .emit_fence = &r600_uvd_fence_emit,
		1846	// .emit_semaphore = &cayman_uvd_semaphore_emit,
		1847	// .cs_parse = &radeon_uvd_cs_parse,
		1848	// .ring_test = &r600_uvd_ring_test,
		1849	// .ib_test = &r600_uvd_ib_test,
		1850	// .is_lockup = &radeon_ring_test_lockup,
2997	Serge	1851	}
		1852	},
		1853	.irq = {
		1854	.set = &si_irq_set,
		1855	.process = &si_irq_process,
		1856	},
		1857	.display = {
		1858	.bandwidth_update = &dce6_bandwidth_update,
		1859	.get_vblank_counter = &evergreen_get_vblank_counter,
		1860	.wait_for_vblank = &dce4_wait_for_vblank,
		1861	// .set_backlight_level = &atombios_set_backlight_level,
		1862	// .get_backlight_level = &atombios_get_backlight_level,
		1863	},
		1864	.copy = {
		1865	.blit = NULL,
		1866	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1867	.dma = &si_copy_dma,
		1868	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1869	.copy = &si_copy_dma,
		1870	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1871	},
		1872	.surface = {
		1873	.set_reg = r600_set_surface_reg,
		1874	.clear_reg = r600_clear_surface_reg,
		1875	},
		1876	.hpd = {
		1877	.init = &evergreen_hpd_init,
		1878	.fini = &evergreen_hpd_fini,
		1879	.sense = &evergreen_hpd_sense,
		1880	.set_polarity = &evergreen_hpd_set_polarity,
		1881	},
		1882	.pm = {
		1883	// .misc = &evergreen_pm_misc,
		1884	// .prepare = &evergreen_pm_prepare,
		1885	// .finish = &evergreen_pm_finish,
		1886	// .init_profile = &sumo_pm_init_profile,
		1887	// .get_dynpm_state = &r600_pm_get_dynpm_state,
		1888	// .get_engine_clock = &radeon_atom_get_engine_clock,
		1889	// .set_engine_clock = &radeon_atom_set_engine_clock,
		1890	// .get_memory_clock = &radeon_atom_get_memory_clock,
		1891	// .set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	1892	.get_pcie_lanes = NULL,
		1893	.set_pcie_lanes = NULL,
		1894	.set_clock_gating = NULL,
3764	Serge	1895	// .set_uvd_clocks = &si_set_uvd_clocks,
2997	Serge	1896	},
		1897	.pflip = {
		1898	// .pre_page_flip = &evergreen_pre_page_flip,
		1899	// .page_flip = &evergreen_page_flip,
		1900	// .post_page_flip = &evergreen_post_page_flip,
		1901	},
		1902	};
		1903
		1904	/**
		1905	* radeon_asic_init - register asic specific callbacks
		1906	*
		1907	* @rdev: radeon device pointer
		1908	*
		1909	* Registers the appropriate asic specific callbacks for each
		1910	* chip family. Also sets other asics specific info like the number
		1911	* of crtcs and the register aperture accessors (all asics).
		1912	* Returns 0 for success.
		1913	*/
1963	serge	1914	int radeon_asic_init(struct radeon_device *rdev)
		1915	{
		1916	radeon_register_accessor_init(rdev);
1986	serge	1917
		1918	/* set the number of crtcs */
		1919	if (rdev->flags & RADEON_SINGLE_CRTC)
		1920	rdev->num_crtc = 1;
		1921	else
		1922	rdev->num_crtc = 2;
		1923
3764	Serge	1924	rdev->has_uvd = false;
		1925
1963	serge	1926	switch (rdev->family) {
		1927	case CHIP_R100:
		1928	case CHIP_RV100:
		1929	case CHIP_RS100:
		1930	case CHIP_RV200:
		1931	case CHIP_RS200:
		1932	rdev->asic = &r100_asic;
		1933	break;
		1934	case CHIP_R200:
		1935	case CHIP_RV250:
		1936	case CHIP_RS300:
		1937	case CHIP_RV280:
		1938	rdev->asic = &r200_asic;
		1939	break;
		1940	case CHIP_R300:
		1941	case CHIP_R350:
		1942	case CHIP_RV350:
		1943	case CHIP_RV380:
		1944	if (rdev->flags & RADEON_IS_PCIE)
		1945	rdev->asic = &r300_asic_pcie;
		1946	else
		1947	rdev->asic = &r300_asic;
		1948	break;
		1949	case CHIP_R420:
		1950	case CHIP_R423:
		1951	case CHIP_RV410:
		1952	rdev->asic = &r420_asic;
		1953	/* handle macs */
		1954	if (rdev->bios == NULL) {
2997	Serge	1955	rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
		1956	rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
		1957	rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
		1958	rdev->asic->pm.set_memory_clock = NULL;
		1959	rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
1963	serge	1960	}
		1961	break;
		1962	case CHIP_RS400:
		1963	case CHIP_RS480:
		1964	rdev->asic = &rs400_asic;
		1965	break;
		1966	case CHIP_RS600:
		1967	rdev->asic = &rs600_asic;
		1968	break;
		1969	case CHIP_RS690:
		1970	case CHIP_RS740:
		1971	rdev->asic = &rs690_asic;
		1972	break;
		1973	case CHIP_RV515:
		1974	rdev->asic = &rv515_asic;
		1975	break;
		1976	case CHIP_R520:
		1977	case CHIP_RV530:
		1978	case CHIP_RV560:
		1979	case CHIP_RV570:
		1980	case CHIP_R580:
		1981	rdev->asic = &r520_asic;
		1982	break;
		1983	case CHIP_R600:
		1984	case CHIP_RV610:
		1985	case CHIP_RV630:
		1986	case CHIP_RV620:
		1987	case CHIP_RV635:
		1988	case CHIP_RV670:
		1989	rdev->asic = &r600_asic;
3764	Serge	1990	if (rdev->family == CHIP_R600)
		1991	rdev->has_uvd = false;
		1992	else
		1993	rdev->has_uvd = true;
1963	serge	1994	break;
		1995	case CHIP_RS780:
		1996	case CHIP_RS880:
		1997	rdev->asic = &rs780_asic;
3764	Serge	1998	rdev->has_uvd = true;
1963	serge	1999	break;
		2000	case CHIP_RV770:
		2001	case CHIP_RV730:
		2002	case CHIP_RV710:
		2003	case CHIP_RV740:
		2004	rdev->asic = &rv770_asic;
3764	Serge	2005	rdev->has_uvd = true;
1963	serge	2006	break;
1986	serge	2007	case CHIP_CEDAR:
		2008	case CHIP_REDWOOD:
		2009	case CHIP_JUNIPER:
		2010	case CHIP_CYPRESS:
		2011	case CHIP_HEMLOCK:
		2012	/* set num crtcs */
		2013	if (rdev->family == CHIP_CEDAR)
		2014	rdev->num_crtc = 4;
		2015	else
		2016	rdev->num_crtc = 6;
		2017	rdev->asic = &evergreen_asic;
3764	Serge	2018	rdev->has_uvd = true;
1986	serge	2019	break;
1990	serge	2020	case CHIP_PALM:
		2021	case CHIP_SUMO:
		2022	case CHIP_SUMO2:
		2023	rdev->asic = &sumo_asic;
3764	Serge	2024	rdev->has_uvd = true;
1990	serge	2025	break;
		2026	case CHIP_BARTS:
		2027	case CHIP_TURKS:
		2028	case CHIP_CAICOS:
		2029	/* set num crtcs */
		2030	if (rdev->family == CHIP_CAICOS)
		2031	rdev->num_crtc = 4;
		2032	else
		2033	rdev->num_crtc = 6;
		2034	rdev->asic = &btc_asic;
3764	Serge	2035	rdev->has_uvd = true;
1990	serge	2036	break;
2004	serge	2037	case CHIP_CAYMAN:
		2038	rdev->asic = &cayman_asic;
		2039	/* set num crtcs */
		2040	rdev->num_crtc = 6;
3764	Serge	2041	rdev->has_uvd = true;
2004	serge	2042	break;
2997	Serge	2043	case CHIP_ARUBA:
		2044	rdev->asic = &trinity_asic;
		2045	/* set num crtcs */
		2046	rdev->num_crtc = 4;
3764	Serge	2047	rdev->has_uvd = true;
2997	Serge	2048	break;
		2049	case CHIP_TAHITI:
		2050	case CHIP_PITCAIRN:
		2051	case CHIP_VERDE:
3764	Serge	2052	case CHIP_OLAND:
		2053	case CHIP_HAINAN:
2997	Serge	2054	rdev->asic = &si_asic;
		2055	/* set num crtcs */
3764	Serge	2056	if (rdev->family == CHIP_HAINAN)
		2057	rdev->num_crtc = 0;
		2058	else if (rdev->family == CHIP_OLAND)
		2059	rdev->num_crtc = 2;
		2060	else
2997	Serge	2061	rdev->num_crtc = 6;
3764	Serge	2062	if (rdev->family == CHIP_HAINAN)
		2063	rdev->has_uvd = false;
		2064	else
		2065	rdev->has_uvd = true;
2997	Serge	2066	break;
1963	serge	2067	default:
		2068	/* FIXME: not supported yet */
		2069	return -EINVAL;
		2070	}
		2071
		2072	if (rdev->flags & RADEON_IS_IGP) {
2997	Serge	2073	rdev->asic->pm.get_memory_clock = NULL;
		2074	rdev->asic->pm.set_memory_clock = NULL;
1963	serge	2075	}
		2076
		2077	return 0;
		2078	}
		2079

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_asic.c – Rev 3764