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1963 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | |||
29 | //#include |
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30 | #include |
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31 | #include |
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32 | #include |
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33 | //#include |
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34 | //#include |
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35 | #include "radeon_reg.h" |
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36 | #include "radeon.h" |
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37 | #include "radeon_asic.h" |
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38 | #include "atom.h" |
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39 | |||
40 | /* |
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41 | * Registers accessors functions. |
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42 | */ |
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2997 | Serge | 43 | /** |
44 | * radeon_invalid_rreg - dummy reg read function |
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45 | * |
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46 | * @rdev: radeon device pointer |
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47 | * @reg: offset of register |
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48 | * |
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49 | * Dummy register read function. Used for register blocks |
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50 | * that certain asics don't have (all asics). |
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51 | * Returns the value in the register. |
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52 | */ |
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1963 | serge | 53 | static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
54 | { |
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55 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); |
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56 | BUG_ON(1); |
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57 | return 0; |
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58 | } |
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59 | |||
2997 | Serge | 60 | /** |
61 | * radeon_invalid_wreg - dummy reg write function |
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62 | * |
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63 | * @rdev: radeon device pointer |
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64 | * @reg: offset of register |
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65 | * @v: value to write to the register |
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66 | * |
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67 | * Dummy register read function. Used for register blocks |
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68 | * that certain asics don't have (all asics). |
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69 | */ |
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1963 | serge | 70 | static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
71 | { |
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72 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", |
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73 | reg, v); |
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74 | BUG_ON(1); |
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75 | } |
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76 | |||
2997 | Serge | 77 | /** |
78 | * radeon_register_accessor_init - sets up the register accessor callbacks |
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79 | * |
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80 | * @rdev: radeon device pointer |
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81 | * |
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82 | * Sets up the register accessor callbacks for various register |
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83 | * apertures. Not all asics have all apertures (all asics). |
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84 | */ |
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1963 | serge | 85 | static void radeon_register_accessor_init(struct radeon_device *rdev) |
86 | { |
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87 | rdev->mc_rreg = &radeon_invalid_rreg; |
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88 | rdev->mc_wreg = &radeon_invalid_wreg; |
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89 | rdev->pll_rreg = &radeon_invalid_rreg; |
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90 | rdev->pll_wreg = &radeon_invalid_wreg; |
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91 | rdev->pciep_rreg = &radeon_invalid_rreg; |
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92 | rdev->pciep_wreg = &radeon_invalid_wreg; |
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93 | |||
94 | /* Don't change order as we are overridding accessor. */ |
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95 | if (rdev->family < CHIP_RV515) { |
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96 | rdev->pcie_reg_mask = 0xff; |
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97 | } else { |
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98 | rdev->pcie_reg_mask = 0x7ff; |
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99 | } |
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100 | /* FIXME: not sure here */ |
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101 | if (rdev->family <= CHIP_R580) { |
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102 | rdev->pll_rreg = &r100_pll_rreg; |
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103 | rdev->pll_wreg = &r100_pll_wreg; |
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104 | } |
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105 | if (rdev->family >= CHIP_R420) { |
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106 | rdev->mc_rreg = &r420_mc_rreg; |
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107 | rdev->mc_wreg = &r420_mc_wreg; |
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108 | } |
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109 | if (rdev->family >= CHIP_RV515) { |
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110 | rdev->mc_rreg = &rv515_mc_rreg; |
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111 | rdev->mc_wreg = &rv515_mc_wreg; |
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112 | } |
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113 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
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114 | rdev->mc_rreg = &rs400_mc_rreg; |
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115 | rdev->mc_wreg = &rs400_mc_wreg; |
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116 | } |
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117 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
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118 | rdev->mc_rreg = &rs690_mc_rreg; |
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119 | rdev->mc_wreg = &rs690_mc_wreg; |
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120 | } |
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121 | if (rdev->family == CHIP_RS600) { |
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122 | rdev->mc_rreg = &rs600_mc_rreg; |
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123 | rdev->mc_wreg = &rs600_mc_wreg; |
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124 | } |
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125 | if (rdev->family >= CHIP_R600) { |
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126 | rdev->pciep_rreg = &r600_pciep_rreg; |
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127 | rdev->pciep_wreg = &r600_pciep_wreg; |
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128 | } |
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129 | } |
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130 | |||
131 | |||
132 | /* helper to disable agp */ |
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2997 | Serge | 133 | /** |
134 | * radeon_agp_disable - AGP disable helper function |
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135 | * |
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136 | * @rdev: radeon device pointer |
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137 | * |
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138 | * Removes AGP flags and changes the gart callbacks on AGP |
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139 | * cards when using the internal gart rather than AGP (all asics). |
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140 | */ |
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1963 | serge | 141 | void radeon_agp_disable(struct radeon_device *rdev) |
142 | { |
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143 | rdev->flags &= ~RADEON_IS_AGP; |
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144 | if (rdev->family >= CHIP_R600) { |
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145 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
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146 | rdev->flags |= RADEON_IS_PCIE; |
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147 | } else if (rdev->family >= CHIP_RV515 || |
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148 | rdev->family == CHIP_RV380 || |
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149 | rdev->family == CHIP_RV410 || |
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150 | rdev->family == CHIP_R423) { |
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151 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
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152 | rdev->flags |= RADEON_IS_PCIE; |
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2997 | Serge | 153 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; |
154 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; |
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1963 | serge | 155 | } else { |
156 | DRM_INFO("Forcing AGP to PCI mode\n"); |
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157 | rdev->flags |= RADEON_IS_PCI; |
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2997 | Serge | 158 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
159 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; |
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1963 | serge | 160 | } |
161 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
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162 | } |
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163 | |||
164 | /* |
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165 | * ASIC |
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166 | */ |
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167 | static struct radeon_asic r100_asic = { |
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168 | .init = &r100_init, |
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169 | // .fini = &r100_fini, |
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170 | // .suspend = &r100_suspend, |
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171 | // .resume = &r100_resume, |
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172 | // .vga_set_state = &r100_vga_set_state, |
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173 | .asic_reset = &r100_asic_reset, |
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2997 | Serge | 174 | // .ioctl_wait_idle = NULL, |
175 | .gui_idle = &r100_gui_idle, |
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176 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
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177 | .gart = { |
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178 | .tlb_flush = &r100_pci_gart_tlb_flush, |
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179 | .set_page = &r100_pci_gart_set_page, |
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180 | }, |
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181 | .ring = { |
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182 | [RADEON_RING_TYPE_GFX_INDEX] = { |
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183 | .ib_execute = &r100_ring_ib_execute, |
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184 | .emit_fence = &r100_fence_ring_emit, |
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185 | .emit_semaphore = &r100_semaphore_ring_emit, |
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186 | // .cs_parse = &r100_cs_parse, |
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187 | .ring_start = &r100_ring_start, |
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188 | .ring_test = &r100_ring_test, |
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189 | .ib_test = &r100_ib_test, |
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190 | .is_lockup = &r100_gpu_is_lockup, |
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191 | } |
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192 | }, |
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193 | .irq = { |
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194 | .set = &r100_irq_set, |
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195 | .process = &r100_irq_process, |
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196 | }, |
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197 | .display = { |
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198 | .bandwidth_update = &r100_bandwidth_update, |
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199 | .get_vblank_counter = &r100_get_vblank_counter, |
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200 | .wait_for_vblank = &r100_wait_for_vblank, |
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201 | // .set_backlight_level = &radeon_legacy_set_backlight_level, |
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202 | // .get_backlight_level = &radeon_legacy_get_backlight_level, |
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203 | }, |
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204 | .copy = { |
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205 | .blit = &r100_copy_blit, |
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206 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
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207 | .dma = NULL, |
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208 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
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2005 | serge | 209 | .copy = &r100_copy_blit, |
2997 | Serge | 210 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
211 | }, |
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212 | .surface = { |
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213 | .set_reg = r100_set_surface_reg, |
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214 | .clear_reg = r100_clear_surface_reg, |
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215 | }, |
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216 | .hpd = { |
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217 | // .init = &r100_hpd_init, |
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218 | // .fini = &r100_hpd_fini, |
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219 | // .sense = &r100_hpd_sense, |
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220 | // .set_polarity = &r100_hpd_set_polarity, |
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221 | }, |
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222 | .pm = { |
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223 | // .misc = &r100_pm_misc, |
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224 | // .prepare = &r100_pm_prepare, |
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225 | // .finish = &r100_pm_finish, |
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226 | // .init_profile = &r100_pm_init_profile, |
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227 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
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228 | // .get_engine_clock = &radeon_legacy_get_engine_clock, |
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229 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
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230 | // .get_memory_clock = &radeon_legacy_get_memory_clock, |
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231 | // .set_memory_clock = NULL, |
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232 | // .get_pcie_lanes = NULL, |
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233 | // .set_pcie_lanes = NULL, |
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234 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
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235 | }, |
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236 | .pflip = { |
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237 | // .pre_page_flip = &r100_pre_page_flip, |
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238 | // .page_flip = &r100_page_flip, |
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239 | // .post_page_flip = &r100_post_page_flip, |
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240 | }, |
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1963 | serge | 241 | }; |
242 | |||
243 | static struct radeon_asic r200_asic = { |
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244 | .init = &r100_init, |
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245 | // .fini = &r100_fini, |
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246 | // .suspend = &r100_suspend, |
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247 | // .resume = &r100_resume, |
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248 | // .vga_set_state = &r100_vga_set_state, |
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249 | .asic_reset = &r100_asic_reset, |
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2997 | Serge | 250 | // .ioctl_wait_idle = NULL, |
2007 | serge | 251 | .gui_idle = &r100_gui_idle, |
2997 | Serge | 252 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
253 | .gart = { |
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254 | .tlb_flush = &r100_pci_gart_tlb_flush, |
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255 | .set_page = &r100_pci_gart_set_page, |
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256 | }, |
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257 | .ring = { |
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258 | [RADEON_RING_TYPE_GFX_INDEX] = { |
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259 | .ib_execute = &r100_ring_ib_execute, |
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260 | .emit_fence = &r100_fence_ring_emit, |
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261 | .emit_semaphore = &r100_semaphore_ring_emit, |
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262 | // .cs_parse = &r100_cs_parse, |
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263 | .ring_start = &r100_ring_start, |
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264 | .ring_test = &r100_ring_test, |
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265 | .ib_test = &r100_ib_test, |
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266 | .is_lockup = &r100_gpu_is_lockup, |
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267 | } |
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268 | }, |
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269 | .irq = { |
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270 | .set = &r100_irq_set, |
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271 | .process = &r100_irq_process, |
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272 | }, |
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273 | .display = { |
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274 | .bandwidth_update = &r100_bandwidth_update, |
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275 | .get_vblank_counter = &r100_get_vblank_counter, |
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276 | .wait_for_vblank = &r100_wait_for_vblank, |
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277 | // .set_backlight_level = &radeon_legacy_set_backlight_level, |
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278 | // .get_backlight_level = &radeon_legacy_get_backlight_level, |
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279 | }, |
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280 | .copy = { |
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281 | .blit = &r100_copy_blit, |
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282 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
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283 | .dma = &r200_copy_dma, |
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284 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
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285 | .copy = &r100_copy_blit, |
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286 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
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287 | }, |
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288 | .surface = { |
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289 | .set_reg = r100_set_surface_reg, |
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290 | .clear_reg = r100_clear_surface_reg, |
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291 | }, |
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292 | .hpd = { |
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293 | // .init = &r100_hpd_init, |
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294 | // .fini = &r100_hpd_fini, |
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295 | // .sense = &r100_hpd_sense, |
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296 | // .set_polarity = &r100_hpd_set_polarity, |
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297 | }, |
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298 | .pm = { |
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299 | // .misc = &r100_pm_misc, |
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300 | // .prepare = &r100_pm_prepare, |
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301 | // .finish = &r100_pm_finish, |
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302 | // .init_profile = &r100_pm_init_profile, |
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303 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
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304 | // .get_engine_clock = &radeon_legacy_get_engine_clock, |
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305 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
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306 | // .get_memory_clock = &radeon_legacy_get_memory_clock, |
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307 | // .set_memory_clock = NULL, |
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308 | // .get_pcie_lanes = NULL, |
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309 | // .set_pcie_lanes = NULL, |
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310 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
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311 | }, |
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312 | .pflip = { |
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313 | // .pre_page_flip = &r100_pre_page_flip, |
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314 | // .page_flip = &r100_page_flip, |
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315 | // .post_page_flip = &r100_post_page_flip, |
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316 | }, |
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1963 | serge | 317 | }; |
318 | |||
319 | static struct radeon_asic r300_asic = { |
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320 | .init = &r300_init, |
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321 | // .fini = &r300_fini, |
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322 | // .suspend = &r300_suspend, |
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323 | // .resume = &r300_resume, |
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324 | // .vga_set_state = &r100_vga_set_state, |
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325 | .asic_reset = &r300_asic_reset, |
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2997 | Serge | 326 | // .ioctl_wait_idle = NULL, |
2007 | serge | 327 | .gui_idle = &r100_gui_idle, |
2997 | Serge | 328 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
329 | .gart = { |
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330 | .tlb_flush = &r100_pci_gart_tlb_flush, |
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331 | .set_page = &r100_pci_gart_set_page, |
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332 | }, |
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333 | .ring = { |
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334 | [RADEON_RING_TYPE_GFX_INDEX] = { |
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335 | .ib_execute = &r100_ring_ib_execute, |
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336 | .emit_fence = &r300_fence_ring_emit, |
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337 | .emit_semaphore = &r100_semaphore_ring_emit, |
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338 | // .cs_parse = &r300_cs_parse, |
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339 | .ring_start = &r300_ring_start, |
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340 | .ring_test = &r100_ring_test, |
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341 | .ib_test = &r100_ib_test, |
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342 | .is_lockup = &r100_gpu_is_lockup, |
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343 | } |
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344 | }, |
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345 | .irq = { |
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346 | .set = &r100_irq_set, |
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347 | .process = &r100_irq_process, |
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348 | }, |
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349 | .display = { |
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350 | .bandwidth_update = &r100_bandwidth_update, |
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351 | .get_vblank_counter = &r100_get_vblank_counter, |
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352 | .wait_for_vblank = &r100_wait_for_vblank, |
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353 | // .set_backlight_level = &radeon_legacy_set_backlight_level, |
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354 | // .get_backlight_level = &radeon_legacy_get_backlight_level, |
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355 | }, |
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356 | .copy = { |
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357 | .blit = &r100_copy_blit, |
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358 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
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359 | .dma = &r200_copy_dma, |
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360 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
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361 | .copy = &r100_copy_blit, |
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362 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
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363 | }, |
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364 | .surface = { |
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365 | .set_reg = r100_set_surface_reg, |
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366 | .clear_reg = r100_clear_surface_reg, |
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367 | }, |
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368 | .hpd = { |
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369 | // .init = &r100_hpd_init, |
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370 | // .fini = &r100_hpd_fini, |
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371 | // .sense = &r100_hpd_sense, |
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372 | // .set_polarity = &r100_hpd_set_polarity, |
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373 | }, |
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374 | .pm = { |
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375 | // .misc = &r100_pm_misc, |
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376 | // .prepare = &r100_pm_prepare, |
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377 | // .finish = &r100_pm_finish, |
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378 | // .init_profile = &r100_pm_init_profile, |
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379 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
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380 | // .get_engine_clock = &radeon_legacy_get_engine_clock, |
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381 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
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382 | // .get_memory_clock = &radeon_legacy_get_memory_clock, |
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383 | // .set_memory_clock = NULL, |
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384 | // .get_pcie_lanes = &rv370_get_pcie_lanes, |
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385 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
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386 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
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387 | }, |
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388 | .pflip = { |
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389 | // .pre_page_flip = &r100_pre_page_flip, |
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390 | // .page_flip = &r100_page_flip, |
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391 | // .post_page_flip = &r100_post_page_flip, |
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392 | }, |
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1963 | serge | 393 | }; |
394 | |||
395 | static struct radeon_asic r300_asic_pcie = { |
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396 | .init = &r300_init, |
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397 | // .fini = &r300_fini, |
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398 | // .suspend = &r300_suspend, |
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399 | // .resume = &r300_resume, |
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400 | // .vga_set_state = &r100_vga_set_state, |
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401 | .asic_reset = &r300_asic_reset, |
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2997 | Serge | 402 | // .ioctl_wait_idle = NULL, |
2007 | serge | 403 | .gui_idle = &r100_gui_idle, |
2997 | Serge | 404 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
405 | .gart = { |
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406 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
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407 | .set_page = &rv370_pcie_gart_set_page, |
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408 | }, |
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409 | .ring = { |
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410 | [RADEON_RING_TYPE_GFX_INDEX] = { |
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411 | .ib_execute = &r100_ring_ib_execute, |
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412 | .emit_fence = &r300_fence_ring_emit, |
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413 | .emit_semaphore = &r100_semaphore_ring_emit, |
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414 | // .cs_parse = &r300_cs_parse, |
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415 | .ring_start = &r300_ring_start, |
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416 | .ring_test = &r100_ring_test, |
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417 | .ib_test = &r100_ib_test, |
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418 | .is_lockup = &r100_gpu_is_lockup, |
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419 | } |
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420 | }, |
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421 | .irq = { |
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422 | .set = &r100_irq_set, |
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423 | .process = &r100_irq_process, |
||
424 | }, |
||
425 | .display = { |
||
426 | .bandwidth_update = &r100_bandwidth_update, |
||
427 | .get_vblank_counter = &r100_get_vblank_counter, |
||
428 | .wait_for_vblank = &r100_wait_for_vblank, |
||
429 | // .set_backlight_level = &radeon_legacy_set_backlight_level, |
||
430 | // .get_backlight_level = &radeon_legacy_get_backlight_level, |
||
431 | }, |
||
432 | .copy = { |
||
433 | .blit = &r100_copy_blit, |
||
434 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
435 | .dma = &r200_copy_dma, |
||
436 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
437 | .copy = &r100_copy_blit, |
||
438 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
439 | }, |
||
440 | .surface = { |
||
441 | .set_reg = r100_set_surface_reg, |
||
442 | .clear_reg = r100_clear_surface_reg, |
||
443 | }, |
||
444 | .hpd = { |
||
445 | .init = &r100_hpd_init, |
||
446 | .fini = &r100_hpd_fini, |
||
447 | .sense = &r100_hpd_sense, |
||
448 | .set_polarity = &r100_hpd_set_polarity, |
||
449 | }, |
||
450 | .pm = { |
||
451 | // .misc = &r100_pm_misc, |
||
452 | // .prepare = &r100_pm_prepare, |
||
453 | // .finish = &r100_pm_finish, |
||
454 | // .init_profile = &r100_pm_init_profile, |
||
455 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
||
456 | // .get_engine_clock = &radeon_legacy_get_engine_clock, |
||
457 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
||
458 | // .get_memory_clock = &radeon_legacy_get_memory_clock, |
||
459 | // .set_memory_clock = NULL, |
||
460 | // .get_pcie_lanes = &rv370_get_pcie_lanes, |
||
461 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
||
462 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
||
463 | }, |
||
464 | .pflip = { |
||
465 | // .pre_page_flip = &r100_pre_page_flip, |
||
466 | // .page_flip = &r100_page_flip, |
||
467 | // .post_page_flip = &r100_post_page_flip, |
||
468 | }, |
||
1963 | serge | 469 | }; |
470 | |||
471 | static struct radeon_asic r420_asic = { |
||
472 | .init = &r420_init, |
||
473 | // .fini = &r420_fini, |
||
474 | // .suspend = &r420_suspend, |
||
475 | // .resume = &r420_resume, |
||
476 | // .vga_set_state = &r100_vga_set_state, |
||
477 | .asic_reset = &r300_asic_reset, |
||
2997 | Serge | 478 | // .ioctl_wait_idle = NULL, |
2160 | serge | 479 | .gui_idle = &r100_gui_idle, |
2997 | Serge | 480 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
481 | .gart = { |
||
482 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
||
483 | .set_page = &rv370_pcie_gart_set_page, |
||
484 | }, |
||
485 | .ring = { |
||
486 | [RADEON_RING_TYPE_GFX_INDEX] = { |
||
487 | .ib_execute = &r100_ring_ib_execute, |
||
488 | .emit_fence = &r300_fence_ring_emit, |
||
489 | .emit_semaphore = &r100_semaphore_ring_emit, |
||
490 | // .cs_parse = &r300_cs_parse, |
||
491 | .ring_start = &r300_ring_start, |
||
492 | .ring_test = &r100_ring_test, |
||
493 | .ib_test = &r100_ib_test, |
||
494 | .is_lockup = &r100_gpu_is_lockup, |
||
495 | } |
||
496 | }, |
||
497 | .irq = { |
||
498 | .set = &r100_irq_set, |
||
499 | .process = &r100_irq_process, |
||
500 | }, |
||
501 | .display = { |
||
502 | .bandwidth_update = &r100_bandwidth_update, |
||
503 | .get_vblank_counter = &r100_get_vblank_counter, |
||
504 | .wait_for_vblank = &r100_wait_for_vblank, |
||
505 | // .set_backlight_level = &atombios_set_backlight_level, |
||
506 | // .get_backlight_level = &atombios_get_backlight_level, |
||
507 | }, |
||
508 | .copy = { |
||
509 | .blit = &r100_copy_blit, |
||
510 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
511 | .dma = &r200_copy_dma, |
||
512 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
513 | .copy = &r100_copy_blit, |
||
514 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
515 | }, |
||
516 | .surface = { |
||
517 | .set_reg = r100_set_surface_reg, |
||
518 | .clear_reg = r100_clear_surface_reg, |
||
519 | }, |
||
520 | .hpd = { |
||
521 | // .init = &r100_hpd_init, |
||
522 | // .fini = &r100_hpd_fini, |
||
523 | // .sense = &r100_hpd_sense, |
||
524 | // .set_polarity = &r100_hpd_set_polarity, |
||
525 | }, |
||
526 | .pm = { |
||
527 | // .misc = &r100_pm_misc, |
||
528 | // .prepare = &r100_pm_prepare, |
||
529 | // .finish = &r100_pm_finish, |
||
530 | // .init_profile = &r420_pm_init_profile, |
||
531 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
||
532 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
||
533 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
||
534 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
||
535 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
||
536 | // .get_pcie_lanes = &rv370_get_pcie_lanes, |
||
537 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
||
538 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
||
539 | }, |
||
540 | .pflip = { |
||
541 | // .pre_page_flip = &r100_pre_page_flip, |
||
542 | // .page_flip = &r100_page_flip, |
||
543 | // .post_page_flip = &r100_post_page_flip, |
||
544 | }, |
||
1963 | serge | 545 | }; |
546 | |||
547 | static struct radeon_asic rs400_asic = { |
||
548 | .init = &rs400_init, |
||
549 | // .fini = &rs400_fini, |
||
550 | // .suspend = &rs400_suspend, |
||
551 | // .resume = &rs400_resume, |
||
552 | // .vga_set_state = &r100_vga_set_state, |
||
553 | .asic_reset = &r300_asic_reset, |
||
2997 | Serge | 554 | // .ioctl_wait_idle = NULL, |
2160 | serge | 555 | .gui_idle = &r100_gui_idle, |
2997 | Serge | 556 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, |
557 | .gart = { |
||
558 | .tlb_flush = &rs400_gart_tlb_flush, |
||
559 | .set_page = &rs400_gart_set_page, |
||
560 | }, |
||
561 | .ring = { |
||
562 | [RADEON_RING_TYPE_GFX_INDEX] = { |
||
563 | .ib_execute = &r100_ring_ib_execute, |
||
564 | .emit_fence = &r300_fence_ring_emit, |
||
565 | .emit_semaphore = &r100_semaphore_ring_emit, |
||
566 | // .cs_parse = &r300_cs_parse, |
||
567 | .ring_start = &r300_ring_start, |
||
568 | .ring_test = &r100_ring_test, |
||
569 | .ib_test = &r100_ib_test, |
||
570 | .is_lockup = &r100_gpu_is_lockup, |
||
571 | } |
||
572 | }, |
||
573 | .irq = { |
||
574 | .set = &r100_irq_set, |
||
575 | .process = &r100_irq_process, |
||
576 | }, |
||
577 | .display = { |
||
578 | .bandwidth_update = &r100_bandwidth_update, |
||
579 | .get_vblank_counter = &r100_get_vblank_counter, |
||
580 | .wait_for_vblank = &r100_wait_for_vblank, |
||
581 | // .set_backlight_level = &radeon_legacy_set_backlight_level, |
||
582 | // .get_backlight_level = &radeon_legacy_get_backlight_level, |
||
583 | }, |
||
584 | .copy = { |
||
585 | .blit = &r100_copy_blit, |
||
586 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
587 | .dma = &r200_copy_dma, |
||
588 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
589 | .copy = &r100_copy_blit, |
||
590 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
591 | }, |
||
592 | .surface = { |
||
593 | .set_reg = r100_set_surface_reg, |
||
594 | .clear_reg = r100_clear_surface_reg, |
||
595 | }, |
||
596 | .hpd = { |
||
597 | // .init = &r100_hpd_init, |
||
598 | // .fini = &r100_hpd_fini, |
||
599 | // .sense = &r100_hpd_sense, |
||
600 | // .set_polarity = &r100_hpd_set_polarity, |
||
601 | }, |
||
602 | .pm = { |
||
603 | // .misc = &r100_pm_misc, |
||
604 | // .prepare = &r100_pm_prepare, |
||
605 | // .finish = &r100_pm_finish, |
||
606 | // .init_profile = &r100_pm_init_profile, |
||
607 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
||
608 | // .get_engine_clock = &radeon_legacy_get_engine_clock, |
||
609 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
||
610 | // .get_memory_clock = &radeon_legacy_get_memory_clock, |
||
611 | // .set_memory_clock = NULL, |
||
612 | // .get_pcie_lanes = NULL, |
||
613 | // .set_pcie_lanes = NULL, |
||
614 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
||
615 | }, |
||
616 | .pflip = { |
||
617 | // .pre_page_flip = &r100_pre_page_flip, |
||
618 | // .page_flip = &r100_page_flip, |
||
619 | // .post_page_flip = &r100_post_page_flip, |
||
620 | }, |
||
1963 | serge | 621 | }; |
622 | |||
623 | static struct radeon_asic rs600_asic = { |
||
624 | .init = &rs600_init, |
||
625 | // .fini = &rs600_fini, |
||
626 | // .suspend = &rs600_suspend, |
||
627 | // .resume = &rs600_resume, |
||
628 | // .vga_set_state = &r100_vga_set_state, |
||
629 | .asic_reset = &rs600_asic_reset, |
||
2997 | Serge | 630 | // .ioctl_wait_idle = NULL, |
2160 | serge | 631 | .gui_idle = &r100_gui_idle, |
2997 | Serge | 632 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, |
633 | .gart = { |
||
634 | .tlb_flush = &rs600_gart_tlb_flush, |
||
635 | .set_page = &rs600_gart_set_page, |
||
636 | }, |
||
637 | .ring = { |
||
638 | [RADEON_RING_TYPE_GFX_INDEX] = { |
||
639 | .ib_execute = &r100_ring_ib_execute, |
||
640 | .emit_fence = &r300_fence_ring_emit, |
||
641 | .emit_semaphore = &r100_semaphore_ring_emit, |
||
642 | // .cs_parse = &r300_cs_parse, |
||
643 | .ring_start = &r300_ring_start, |
||
644 | .ring_test = &r100_ring_test, |
||
645 | .ib_test = &r100_ib_test, |
||
646 | .is_lockup = &r100_gpu_is_lockup, |
||
647 | } |
||
648 | }, |
||
649 | .irq = { |
||
650 | .set = &rs600_irq_set, |
||
651 | .process = &rs600_irq_process, |
||
652 | }, |
||
653 | .display = { |
||
654 | .bandwidth_update = &rs600_bandwidth_update, |
||
655 | .get_vblank_counter = &rs600_get_vblank_counter, |
||
656 | .wait_for_vblank = &avivo_wait_for_vblank, |
||
657 | // .set_backlight_level = &atombios_set_backlight_level, |
||
658 | // .get_backlight_level = &atombios_get_backlight_level, |
||
659 | }, |
||
660 | .copy = { |
||
661 | .blit = &r100_copy_blit, |
||
662 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
663 | .dma = &r200_copy_dma, |
||
664 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
665 | .copy = &r100_copy_blit, |
||
666 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
667 | }, |
||
668 | .surface = { |
||
669 | .set_reg = r100_set_surface_reg, |
||
670 | .clear_reg = r100_clear_surface_reg, |
||
671 | }, |
||
672 | .hpd = { |
||
673 | // .init = &rs600_hpd_init, |
||
674 | // .fini = &rs600_hpd_fini, |
||
675 | // .sense = &rs600_hpd_sense, |
||
676 | // .set_polarity = &rs600_hpd_set_polarity, |
||
677 | }, |
||
678 | .pm = { |
||
679 | // .misc = &rs600_pm_misc, |
||
680 | // .prepare = &rs600_pm_prepare, |
||
681 | // .finish = &rs600_pm_finish, |
||
682 | // .init_profile = &r420_pm_init_profile, |
||
683 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
||
684 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
||
685 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
||
686 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
||
687 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
||
688 | // .get_pcie_lanes = NULL, |
||
689 | // .set_pcie_lanes = NULL, |
||
690 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
||
691 | }, |
||
692 | .pflip = { |
||
693 | // .pre_page_flip = &rs600_pre_page_flip, |
||
694 | // .page_flip = &rs600_page_flip, |
||
695 | // .post_page_flip = &rs600_post_page_flip, |
||
696 | }, |
||
1963 | serge | 697 | }; |
698 | |||
699 | static struct radeon_asic rs690_asic = { |
||
700 | .init = &rs690_init, |
||
701 | // .fini = &rs690_fini, |
||
702 | // .suspend = &rs690_suspend, |
||
703 | // .resume = &rs690_resume, |
||
704 | // .vga_set_state = &r100_vga_set_state, |
||
705 | .asic_reset = &rs600_asic_reset, |
||
2997 | Serge | 706 | // .ioctl_wait_idle = NULL, |
2160 | serge | 707 | .gui_idle = &r100_gui_idle, |
2997 | Serge | 708 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, |
709 | .gart = { |
||
710 | .tlb_flush = &rs400_gart_tlb_flush, |
||
711 | .set_page = &rs400_gart_set_page, |
||
712 | }, |
||
713 | .ring = { |
||
714 | [RADEON_RING_TYPE_GFX_INDEX] = { |
||
715 | .ib_execute = &r100_ring_ib_execute, |
||
716 | .emit_fence = &r300_fence_ring_emit, |
||
717 | .emit_semaphore = &r100_semaphore_ring_emit, |
||
718 | // .cs_parse = &r300_cs_parse, |
||
719 | .ring_start = &r300_ring_start, |
||
720 | .ring_test = &r100_ring_test, |
||
721 | .ib_test = &r100_ib_test, |
||
722 | .is_lockup = &r100_gpu_is_lockup, |
||
723 | } |
||
724 | }, |
||
725 | .irq = { |
||
726 | .set = &rs600_irq_set, |
||
727 | .process = &rs600_irq_process, |
||
728 | }, |
||
729 | .display = { |
||
730 | .get_vblank_counter = &rs600_get_vblank_counter, |
||
731 | .bandwidth_update = &rs690_bandwidth_update, |
||
732 | .wait_for_vblank = &avivo_wait_for_vblank, |
||
733 | // .set_backlight_level = &atombios_set_backlight_level, |
||
734 | // .get_backlight_level = &atombios_get_backlight_level, |
||
735 | }, |
||
736 | .copy = { |
||
737 | .blit = &r100_copy_blit, |
||
738 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
739 | .dma = &r200_copy_dma, |
||
740 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
741 | .copy = &r200_copy_dma, |
||
742 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
743 | }, |
||
744 | .surface = { |
||
745 | .set_reg = r100_set_surface_reg, |
||
746 | .clear_reg = r100_clear_surface_reg, |
||
747 | }, |
||
748 | .hpd = { |
||
749 | // .init = &rs600_hpd_init, |
||
750 | // .fini = &rs600_hpd_fini, |
||
751 | .sense = &rs600_hpd_sense, |
||
752 | .set_polarity = &rs600_hpd_set_polarity, |
||
753 | }, |
||
754 | .pm = { |
||
755 | // .misc = &rs600_pm_misc, |
||
756 | // .prepare = &rs600_pm_prepare, |
||
757 | // .finish = &rs600_pm_finish, |
||
758 | // .init_profile = &r420_pm_init_profile, |
||
759 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
||
760 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
||
761 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
||
762 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
||
763 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
||
764 | // .get_pcie_lanes = NULL, |
||
765 | // .set_pcie_lanes = NULL, |
||
766 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
||
767 | }, |
||
768 | .pflip = { |
||
769 | // .pre_page_flip = &rs600_pre_page_flip, |
||
770 | // .page_flip = &rs600_page_flip, |
||
771 | // .post_page_flip = &rs600_post_page_flip, |
||
772 | }, |
||
1963 | serge | 773 | }; |
774 | |||
775 | static struct radeon_asic rv515_asic = { |
||
776 | .init = &rv515_init, |
||
777 | // .fini = &rv515_fini, |
||
778 | // .suspend = &rv515_suspend, |
||
779 | // .resume = &rv515_resume, |
||
780 | // .vga_set_state = &r100_vga_set_state, |
||
781 | .asic_reset = &rs600_asic_reset, |
||
2997 | Serge | 782 | // .ioctl_wait_idle = NULL, |
2160 | serge | 783 | .gui_idle = &r100_gui_idle, |
2997 | Serge | 784 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, |
785 | .gart = { |
||
786 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
||
787 | .set_page = &rv370_pcie_gart_set_page, |
||
788 | }, |
||
789 | .ring = { |
||
790 | [RADEON_RING_TYPE_GFX_INDEX] = { |
||
791 | .ib_execute = &r100_ring_ib_execute, |
||
792 | .emit_fence = &r300_fence_ring_emit, |
||
793 | .emit_semaphore = &r100_semaphore_ring_emit, |
||
794 | // .cs_parse = &r300_cs_parse, |
||
795 | .ring_start = &rv515_ring_start, |
||
796 | .ring_test = &r100_ring_test, |
||
797 | .ib_test = &r100_ib_test, |
||
798 | .is_lockup = &r100_gpu_is_lockup, |
||
799 | } |
||
800 | }, |
||
801 | .irq = { |
||
802 | .set = &rs600_irq_set, |
||
803 | .process = &rs600_irq_process, |
||
804 | }, |
||
805 | .display = { |
||
806 | .get_vblank_counter = &rs600_get_vblank_counter, |
||
807 | .bandwidth_update = &rv515_bandwidth_update, |
||
808 | .wait_for_vblank = &avivo_wait_for_vblank, |
||
809 | // .set_backlight_level = &atombios_set_backlight_level, |
||
810 | // .get_backlight_level = &atombios_get_backlight_level, |
||
811 | }, |
||
812 | .copy = { |
||
813 | .blit = &r100_copy_blit, |
||
814 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
815 | .dma = &r200_copy_dma, |
||
816 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
817 | .copy = &r100_copy_blit, |
||
818 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
819 | }, |
||
820 | .surface = { |
||
821 | .set_reg = r100_set_surface_reg, |
||
822 | .clear_reg = r100_clear_surface_reg, |
||
823 | }, |
||
824 | .hpd = { |
||
825 | // .init = &rs600_hpd_init, |
||
826 | // .fini = &rs600_hpd_fini, |
||
827 | // .sense = &rs600_hpd_sense, |
||
828 | // .set_polarity = &rs600_hpd_set_polarity, |
||
829 | }, |
||
830 | .pm = { |
||
831 | // .misc = &rs600_pm_misc, |
||
832 | // .prepare = &rs600_pm_prepare, |
||
833 | // .finish = &rs600_pm_finish, |
||
834 | // .init_profile = &r420_pm_init_profile, |
||
835 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
||
836 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
||
837 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
||
838 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
||
839 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
||
840 | // .get_pcie_lanes = &rv370_get_pcie_lanes, |
||
841 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
||
842 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
||
843 | }, |
||
844 | .pflip = { |
||
845 | // .pre_page_flip = &rs600_pre_page_flip, |
||
846 | // .page_flip = &rs600_page_flip, |
||
847 | // .post_page_flip = &rs600_post_page_flip, |
||
848 | }, |
||
1963 | serge | 849 | }; |
850 | |||
851 | static struct radeon_asic r520_asic = { |
||
852 | .init = &r520_init, |
||
853 | // .fini = &rv515_fini, |
||
854 | // .suspend = &rv515_suspend, |
||
855 | // .resume = &r520_resume, |
||
856 | // .vga_set_state = &r100_vga_set_state, |
||
857 | .asic_reset = &rs600_asic_reset, |
||
2997 | Serge | 858 | // .ioctl_wait_idle = NULL, |
2160 | serge | 859 | .gui_idle = &r100_gui_idle, |
2997 | Serge | 860 | .mc_wait_for_idle = &r520_mc_wait_for_idle, |
861 | .gart = { |
||
862 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
||
863 | .set_page = &rv370_pcie_gart_set_page, |
||
864 | }, |
||
865 | .ring = { |
||
866 | [RADEON_RING_TYPE_GFX_INDEX] = { |
||
867 | .ib_execute = &r100_ring_ib_execute, |
||
868 | .emit_fence = &r300_fence_ring_emit, |
||
869 | .emit_semaphore = &r100_semaphore_ring_emit, |
||
870 | // .cs_parse = &r300_cs_parse, |
||
871 | .ring_start = &rv515_ring_start, |
||
872 | .ring_test = &r100_ring_test, |
||
873 | .ib_test = &r100_ib_test, |
||
874 | .is_lockup = &r100_gpu_is_lockup, |
||
875 | } |
||
876 | }, |
||
877 | .irq = { |
||
878 | .set = &rs600_irq_set, |
||
879 | .process = &rs600_irq_process, |
||
880 | }, |
||
881 | .display = { |
||
882 | .bandwidth_update = &rv515_bandwidth_update, |
||
883 | .get_vblank_counter = &rs600_get_vblank_counter, |
||
884 | .wait_for_vblank = &avivo_wait_for_vblank, |
||
885 | // .set_backlight_level = &atombios_set_backlight_level, |
||
886 | // .get_backlight_level = &atombios_get_backlight_level, |
||
887 | }, |
||
888 | .copy = { |
||
889 | .blit = &r100_copy_blit, |
||
890 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
891 | .dma = &r200_copy_dma, |
||
892 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
893 | .copy = &r100_copy_blit, |
||
894 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
895 | }, |
||
896 | .surface = { |
||
897 | .set_reg = r100_set_surface_reg, |
||
898 | .clear_reg = r100_clear_surface_reg, |
||
899 | }, |
||
900 | .hpd = { |
||
901 | // .init = &rs600_hpd_init, |
||
902 | // .fini = &rs600_hpd_fini, |
||
903 | // .sense = &rs600_hpd_sense, |
||
904 | // .set_polarity = &rs600_hpd_set_polarity, |
||
905 | }, |
||
906 | .pm = { |
||
907 | // .misc = &rs600_pm_misc, |
||
908 | // .prepare = &rs600_pm_prepare, |
||
909 | // .finish = &rs600_pm_finish, |
||
910 | // .init_profile = &r420_pm_init_profile, |
||
911 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
||
912 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
||
913 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
||
914 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
||
915 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
||
916 | // .get_pcie_lanes = &rv370_get_pcie_lanes, |
||
917 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
||
918 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
||
919 | }, |
||
920 | .pflip = { |
||
921 | // .pre_page_flip = &rs600_pre_page_flip, |
||
922 | // .page_flip = &rs600_page_flip, |
||
923 | // .post_page_flip = &rs600_post_page_flip, |
||
924 | }, |
||
1963 | serge | 925 | }; |
926 | |||
927 | static struct radeon_asic r600_asic = { |
||
928 | .init = &r600_init, |
||
929 | // .fini = &r600_fini, |
||
930 | // .suspend = &r600_suspend, |
||
931 | // .resume = &r600_resume, |
||
2997 | Serge | 932 | // .vga_set_state = &r600_vga_set_state, |
1963 | serge | 933 | .asic_reset = &r600_asic_reset, |
934 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
||
2997 | Serge | 935 | .gui_idle = &r600_gui_idle, |
936 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
||
937 | .gart = { |
||
938 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
||
939 | .set_page = &rs600_gart_set_page, |
||
940 | }, |
||
941 | .ring = { |
||
942 | [RADEON_RING_TYPE_GFX_INDEX] = { |
||
943 | .ib_execute = &r600_ring_ib_execute, |
||
944 | .emit_fence = &r600_fence_ring_emit, |
||
945 | .emit_semaphore = &r600_semaphore_ring_emit, |
||
946 | // .cs_parse = &r600_cs_parse, |
||
947 | .ring_test = &r600_ring_test, |
||
948 | .ib_test = &r600_ib_test, |
||
949 | .is_lockup = &r600_gpu_is_lockup, |
||
950 | } |
||
951 | }, |
||
952 | .irq = { |
||
953 | .set = &r600_irq_set, |
||
954 | .process = &r600_irq_process, |
||
955 | }, |
||
956 | .display = { |
||
957 | .bandwidth_update = &rv515_bandwidth_update, |
||
958 | .get_vblank_counter = &rs600_get_vblank_counter, |
||
959 | .wait_for_vblank = &avivo_wait_for_vblank, |
||
960 | // .set_backlight_level = &atombios_set_backlight_level, |
||
961 | // .get_backlight_level = &atombios_get_backlight_level, |
||
962 | }, |
||
963 | .copy = { |
||
964 | .blit = &r600_copy_blit, |
||
965 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
966 | .dma = NULL, |
||
967 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
968 | .copy = &r600_copy_blit, |
||
969 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
970 | }, |
||
971 | .surface = { |
||
972 | .set_reg = r600_set_surface_reg, |
||
973 | .clear_reg = r600_clear_surface_reg, |
||
974 | }, |
||
975 | .hpd = { |
||
976 | // .init = &r600_hpd_init, |
||
977 | // .fini = &r600_hpd_fini, |
||
978 | // .sense = &r600_hpd_sense, |
||
979 | // .set_polarity = &r600_hpd_set_polarity, |
||
980 | }, |
||
981 | .pm = { |
||
982 | // .misc = &r600_pm_misc, |
||
983 | // .prepare = &rs600_pm_prepare, |
||
984 | // .finish = &rs600_pm_finish, |
||
985 | // .init_profile = &r600_pm_init_profile, |
||
986 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
||
987 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
||
988 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
||
989 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
||
990 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
||
991 | // .get_pcie_lanes = &r600_get_pcie_lanes, |
||
992 | // .set_pcie_lanes = &r600_set_pcie_lanes, |
||
993 | // .set_clock_gating = NULL, |
||
994 | }, |
||
995 | .pflip = { |
||
996 | // .pre_page_flip = &rs600_pre_page_flip, |
||
997 | // .page_flip = &rs600_page_flip, |
||
998 | // .post_page_flip = &rs600_post_page_flip, |
||
999 | }, |
||
1963 | serge | 1000 | }; |
1001 | |||
1002 | static struct radeon_asic rs780_asic = { |
||
1003 | .init = &r600_init, |
||
1004 | // .fini = &r600_fini, |
||
1005 | // .suspend = &r600_suspend, |
||
1006 | // .resume = &r600_resume, |
||
2997 | Serge | 1007 | // .vga_set_state = &r600_vga_set_state, |
1963 | serge | 1008 | .asic_reset = &r600_asic_reset, |
2997 | Serge | 1009 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
1010 | .gui_idle = &r600_gui_idle, |
||
1011 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
||
1012 | .gart = { |
||
1013 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
||
1014 | .set_page = &rs600_gart_set_page, |
||
1015 | }, |
||
1016 | .ring = { |
||
1017 | [RADEON_RING_TYPE_GFX_INDEX] = { |
||
1018 | .ib_execute = &r600_ring_ib_execute, |
||
1019 | .emit_fence = &r600_fence_ring_emit, |
||
1020 | .emit_semaphore = &r600_semaphore_ring_emit, |
||
1021 | // .cs_parse = &r600_cs_parse, |
||
1022 | .ring_test = &r600_ring_test, |
||
1023 | .ib_test = &r600_ib_test, |
||
1024 | .is_lockup = &r600_gpu_is_lockup, |
||
1025 | } |
||
1026 | }, |
||
1027 | .irq = { |
||
1028 | .set = &r600_irq_set, |
||
1029 | .process = &r600_irq_process, |
||
1030 | }, |
||
1031 | .display = { |
||
1032 | .bandwidth_update = &rs690_bandwidth_update, |
||
1033 | .get_vblank_counter = &rs600_get_vblank_counter, |
||
1034 | .wait_for_vblank = &avivo_wait_for_vblank, |
||
1035 | // .set_backlight_level = &atombios_set_backlight_level, |
||
1036 | // .get_backlight_level = &atombios_get_backlight_level, |
||
1037 | }, |
||
1038 | .copy = { |
||
1039 | .blit = &r600_copy_blit, |
||
1040 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1041 | .dma = NULL, |
||
1042 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1043 | .copy = &r600_copy_blit, |
||
1044 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1045 | }, |
||
1046 | .surface = { |
||
1047 | .set_reg = r600_set_surface_reg, |
||
1048 | .clear_reg = r600_clear_surface_reg, |
||
1049 | }, |
||
1050 | .hpd = { |
||
1051 | // .init = &r600_hpd_init, |
||
1052 | // .fini = &r600_hpd_fini, |
||
1053 | // .sense = &r600_hpd_sense, |
||
1054 | // .set_polarity = &r600_hpd_set_polarity, |
||
1055 | }, |
||
1056 | .pm = { |
||
1057 | // .misc = &r600_pm_misc, |
||
1058 | // .prepare = &rs600_pm_prepare, |
||
1059 | // .finish = &rs600_pm_finish, |
||
1060 | // .init_profile = &rs780_pm_init_profile, |
||
1061 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
||
1062 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
||
1063 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
||
1064 | // .get_memory_clock = NULL, |
||
1065 | // .set_memory_clock = NULL, |
||
1066 | // .get_pcie_lanes = NULL, |
||
1067 | // .set_pcie_lanes = NULL, |
||
1068 | // .set_clock_gating = NULL, |
||
1069 | }, |
||
1070 | .pflip = { |
||
1071 | // .pre_page_flip = &rs600_pre_page_flip, |
||
1072 | // .page_flip = &rs600_page_flip, |
||
1073 | // .post_page_flip = &rs600_post_page_flip, |
||
1074 | }, |
||
1963 | serge | 1075 | }; |
1076 | |||
1077 | static struct radeon_asic rv770_asic = { |
||
1078 | .init = &rv770_init, |
||
1079 | // .fini = &rv770_fini, |
||
1080 | // .suspend = &rv770_suspend, |
||
1081 | // .resume = &rv770_resume, |
||
1082 | .asic_reset = &r600_asic_reset, |
||
2997 | Serge | 1083 | // .vga_set_state = &r600_vga_set_state, |
1084 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
||
1085 | .gui_idle = &r600_gui_idle, |
||
1086 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
||
1087 | .gart = { |
||
1088 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
||
1089 | .set_page = &rs600_gart_set_page, |
||
1090 | }, |
||
1091 | .ring = { |
||
1092 | [RADEON_RING_TYPE_GFX_INDEX] = { |
||
1093 | .ib_execute = &r600_ring_ib_execute, |
||
1094 | .emit_fence = &r600_fence_ring_emit, |
||
1095 | .emit_semaphore = &r600_semaphore_ring_emit, |
||
1096 | // .cs_parse = &r600_cs_parse, |
||
1097 | .ring_test = &r600_ring_test, |
||
1098 | .ib_test = &r600_ib_test, |
||
1099 | .is_lockup = &r600_gpu_is_lockup, |
||
1100 | } |
||
1101 | }, |
||
1102 | .irq = { |
||
1103 | .set = &r600_irq_set, |
||
1104 | .process = &r600_irq_process, |
||
1105 | }, |
||
1106 | .display = { |
||
1107 | .bandwidth_update = &rv515_bandwidth_update, |
||
1108 | .get_vblank_counter = &rs600_get_vblank_counter, |
||
1109 | .wait_for_vblank = &avivo_wait_for_vblank, |
||
1110 | // .set_backlight_level = &atombios_set_backlight_level, |
||
1111 | // .get_backlight_level = &atombios_get_backlight_level, |
||
1112 | }, |
||
1113 | .copy = { |
||
1114 | .blit = &r600_copy_blit, |
||
1115 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1116 | .dma = NULL, |
||
1117 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1118 | .copy = &r600_copy_blit, |
||
1119 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1120 | }, |
||
1121 | .surface = { |
||
1122 | .set_reg = r600_set_surface_reg, |
||
1123 | .clear_reg = r600_clear_surface_reg, |
||
1124 | }, |
||
1125 | .hpd = { |
||
1126 | // .init = &r600_hpd_init, |
||
1127 | // .fini = &r600_hpd_fini, |
||
1128 | // .sense = &r600_hpd_sense, |
||
1129 | // .set_polarity = &r600_hpd_set_polarity, |
||
1130 | }, |
||
1131 | .pm = { |
||
1132 | // .misc = &rv770_pm_misc, |
||
1133 | // .prepare = &rs600_pm_prepare, |
||
1134 | // .finish = &rs600_pm_finish, |
||
1135 | // .init_profile = &r600_pm_init_profile, |
||
1136 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
||
1137 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
||
1138 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
||
1139 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
||
1140 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
||
1141 | // .get_pcie_lanes = &r600_get_pcie_lanes, |
||
1142 | // .set_pcie_lanes = &r600_set_pcie_lanes, |
||
1143 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
||
1144 | }, |
||
1145 | .pflip = { |
||
1146 | // .pre_page_flip = &rs600_pre_page_flip, |
||
1147 | // .page_flip = &rv770_page_flip, |
||
1148 | // .post_page_flip = &rs600_post_page_flip, |
||
1149 | }, |
||
1963 | serge | 1150 | }; |
1986 | serge | 1151 | |
1963 | serge | 1152 | static struct radeon_asic evergreen_asic = { |
1153 | .init = &evergreen_init, |
||
1154 | // .fini = &evergreen_fini, |
||
1155 | // .suspend = &evergreen_suspend, |
||
1156 | // .resume = &evergreen_resume, |
||
1157 | .asic_reset = &evergreen_asic_reset, |
||
2997 | Serge | 1158 | // .vga_set_state = &r600_vga_set_state, |
1159 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
||
1160 | .gui_idle = &r600_gui_idle, |
||
1161 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
||
1162 | .gart = { |
||
1163 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
||
1164 | .set_page = &rs600_gart_set_page, |
||
1165 | }, |
||
1166 | .ring = { |
||
1167 | [RADEON_RING_TYPE_GFX_INDEX] = { |
||
1168 | .ib_execute = &evergreen_ring_ib_execute, |
||
1169 | .emit_fence = &r600_fence_ring_emit, |
||
1170 | .emit_semaphore = &r600_semaphore_ring_emit, |
||
1171 | // .cs_parse = &evergreen_cs_parse, |
||
1172 | .ring_test = &r600_ring_test, |
||
1173 | .ib_test = &r600_ib_test, |
||
1174 | .is_lockup = &evergreen_gpu_is_lockup, |
||
1175 | } |
||
1176 | }, |
||
1177 | .irq = { |
||
1178 | .set = &evergreen_irq_set, |
||
1179 | .process = &evergreen_irq_process, |
||
1180 | }, |
||
1181 | .display = { |
||
1182 | .bandwidth_update = &evergreen_bandwidth_update, |
||
1183 | .get_vblank_counter = &evergreen_get_vblank_counter, |
||
1184 | .wait_for_vblank = &dce4_wait_for_vblank, |
||
1185 | // .set_backlight_level = &atombios_set_backlight_level, |
||
1186 | // .get_backlight_level = &atombios_get_backlight_level, |
||
1187 | }, |
||
1188 | .copy = { |
||
1189 | .blit = &r600_copy_blit, |
||
1190 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1191 | .dma = NULL, |
||
1192 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1193 | .copy = &r600_copy_blit, |
||
1194 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1195 | }, |
||
1196 | .surface = { |
||
1197 | .set_reg = r600_set_surface_reg, |
||
1198 | .clear_reg = r600_clear_surface_reg, |
||
1199 | }, |
||
1200 | .hpd = { |
||
1201 | // .init = &evergreen_hpd_init, |
||
1202 | // .fini = &evergreen_hpd_fini, |
||
1203 | // .sense = &evergreen_hpd_sense, |
||
1204 | // .set_polarity = &evergreen_hpd_set_polarity, |
||
1205 | }, |
||
1206 | .pm = { |
||
1207 | // .misc = &evergreen_pm_misc, |
||
1208 | // .prepare = &evergreen_pm_prepare, |
||
1209 | // .finish = &evergreen_pm_finish, |
||
1210 | // .init_profile = &r600_pm_init_profile, |
||
1211 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
||
1212 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
||
1213 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
||
1214 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
||
1215 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
||
1216 | // .get_pcie_lanes = &r600_get_pcie_lanes, |
||
1217 | // .set_pcie_lanes = &r600_set_pcie_lanes, |
||
1218 | // .set_clock_gating = NULL, |
||
1219 | }, |
||
1220 | .pflip = { |
||
1221 | // .pre_page_flip = &evergreen_pre_page_flip, |
||
1222 | // .page_flip = &evergreen_page_flip, |
||
1223 | // .post_page_flip = &evergreen_post_page_flip, |
||
1224 | }, |
||
1986 | serge | 1225 | }; |
1990 | serge | 1226 | |
1986 | serge | 1227 | static struct radeon_asic sumo_asic = { |
1228 | .init = &evergreen_init, |
||
1990 | serge | 1229 | // .fini = &evergreen_fini, |
1230 | // .suspend = &evergreen_suspend, |
||
1231 | // .resume = &evergreen_resume, |
||
1986 | serge | 1232 | .asic_reset = &evergreen_asic_reset, |
2997 | Serge | 1233 | // .vga_set_state = &r600_vga_set_state, |
1234 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
||
1235 | .gui_idle = &r600_gui_idle, |
||
1236 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
||
1237 | .gart = { |
||
1238 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
||
1239 | .set_page = &rs600_gart_set_page, |
||
1240 | }, |
||
1241 | .ring = { |
||
1242 | [RADEON_RING_TYPE_GFX_INDEX] = { |
||
1243 | .ib_execute = &evergreen_ring_ib_execute, |
||
1244 | .emit_fence = &r600_fence_ring_emit, |
||
1245 | .emit_semaphore = &r600_semaphore_ring_emit, |
||
1246 | // .cs_parse = &evergreen_cs_parse, |
||
1247 | .ring_test = &r600_ring_test, |
||
1248 | .ib_test = &r600_ib_test, |
||
1249 | .is_lockup = &evergreen_gpu_is_lockup, |
||
1250 | }, |
||
1251 | }, |
||
1252 | .irq = { |
||
1253 | .set = &evergreen_irq_set, |
||
1254 | .process = &evergreen_irq_process, |
||
1255 | }, |
||
1256 | .display = { |
||
1257 | .bandwidth_update = &evergreen_bandwidth_update, |
||
1258 | .get_vblank_counter = &evergreen_get_vblank_counter, |
||
1259 | .wait_for_vblank = &dce4_wait_for_vblank, |
||
1260 | // .set_backlight_level = &atombios_set_backlight_level, |
||
1261 | // .get_backlight_level = &atombios_get_backlight_level, |
||
1262 | }, |
||
1263 | .copy = { |
||
1264 | .blit = &r600_copy_blit, |
||
1265 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1266 | .dma = NULL, |
||
1267 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1268 | .copy = &r600_copy_blit, |
||
1269 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1270 | }, |
||
1271 | .surface = { |
||
1272 | .set_reg = r600_set_surface_reg, |
||
1273 | .clear_reg = r600_clear_surface_reg, |
||
1274 | }, |
||
1275 | .hpd = { |
||
1276 | // .init = &evergreen_hpd_init, |
||
1277 | // .fini = &evergreen_hpd_fini, |
||
1278 | // .sense = &evergreen_hpd_sense, |
||
1279 | // .set_polarity = &evergreen_hpd_set_polarity, |
||
1280 | }, |
||
1281 | .pm = { |
||
1282 | // .misc = &evergreen_pm_misc, |
||
1283 | // .prepare = &evergreen_pm_prepare, |
||
1284 | // .finish = &evergreen_pm_finish, |
||
1285 | // .init_profile = &sumo_pm_init_profile, |
||
1286 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
||
1287 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
||
1288 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
||
1289 | // .get_memory_clock = NULL, |
||
1290 | // .set_memory_clock = NULL, |
||
1291 | // .get_pcie_lanes = NULL, |
||
1292 | // .set_pcie_lanes = NULL, |
||
1293 | // .set_clock_gating = NULL, |
||
1294 | }, |
||
1295 | .pflip = { |
||
1296 | // .pre_page_flip = &evergreen_pre_page_flip, |
||
1297 | // .page_flip = &evergreen_page_flip, |
||
1298 | // .post_page_flip = &evergreen_post_page_flip, |
||
1299 | }, |
||
1986 | serge | 1300 | }; |
1301 | |||
1302 | static struct radeon_asic btc_asic = { |
||
1303 | .init = &evergreen_init, |
||
1990 | serge | 1304 | // .fini = &evergreen_fini, |
1305 | // .suspend = &evergreen_suspend, |
||
1306 | // .resume = &evergreen_resume, |
||
1986 | serge | 1307 | .asic_reset = &evergreen_asic_reset, |
2997 | Serge | 1308 | // .vga_set_state = &r600_vga_set_state, |
1309 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
||
1310 | .gui_idle = &r600_gui_idle, |
||
1311 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
||
1312 | .gart = { |
||
1313 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
||
1314 | .set_page = &rs600_gart_set_page, |
||
1315 | }, |
||
1316 | .ring = { |
||
1317 | [RADEON_RING_TYPE_GFX_INDEX] = { |
||
1318 | .ib_execute = &evergreen_ring_ib_execute, |
||
1319 | .emit_fence = &r600_fence_ring_emit, |
||
1320 | .emit_semaphore = &r600_semaphore_ring_emit, |
||
1321 | // .cs_parse = &evergreen_cs_parse, |
||
1322 | .ring_test = &r600_ring_test, |
||
1323 | .ib_test = &r600_ib_test, |
||
1324 | .is_lockup = &evergreen_gpu_is_lockup, |
||
1325 | } |
||
1326 | }, |
||
1327 | .irq = { |
||
1328 | .set = &evergreen_irq_set, |
||
1329 | .process = &evergreen_irq_process, |
||
1330 | }, |
||
1331 | .display = { |
||
1332 | .bandwidth_update = &evergreen_bandwidth_update, |
||
1333 | .get_vblank_counter = &evergreen_get_vblank_counter, |
||
1334 | .wait_for_vblank = &dce4_wait_for_vblank, |
||
1335 | // .set_backlight_level = &atombios_set_backlight_level, |
||
1336 | // .get_backlight_level = &atombios_get_backlight_level, |
||
1337 | }, |
||
1338 | .copy = { |
||
1339 | .blit = &r600_copy_blit, |
||
1340 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1341 | .dma = NULL, |
||
1342 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1343 | .copy = &r600_copy_blit, |
||
1344 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1345 | }, |
||
1346 | .surface = { |
||
1347 | .set_reg = r600_set_surface_reg, |
||
1348 | .clear_reg = r600_clear_surface_reg, |
||
1349 | }, |
||
1350 | .hpd = { |
||
1351 | // .init = &evergreen_hpd_init, |
||
1352 | // .fini = &evergreen_hpd_fini, |
||
1353 | // .sense = &evergreen_hpd_sense, |
||
1354 | // .set_polarity = &evergreen_hpd_set_polarity, |
||
1355 | }, |
||
1356 | .pm = { |
||
1357 | // .misc = &evergreen_pm_misc, |
||
1358 | // .prepare = &evergreen_pm_prepare, |
||
1359 | // .finish = &evergreen_pm_finish, |
||
1360 | // .init_profile = &btc_pm_init_profile, |
||
1361 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
||
1362 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
||
1363 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
||
1364 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
||
1365 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
||
1366 | // .get_pcie_lanes = NULL, |
||
1367 | // .set_pcie_lanes = NULL, |
||
1368 | // .set_clock_gating = NULL, |
||
1369 | }, |
||
1370 | .pflip = { |
||
1371 | // .pre_page_flip = &evergreen_pre_page_flip, |
||
1372 | // .page_flip = &evergreen_page_flip, |
||
1373 | // .post_page_flip = &evergreen_post_page_flip, |
||
1374 | }, |
||
1986 | serge | 1375 | }; |
1376 | |||
1377 | static struct radeon_asic cayman_asic = { |
||
1378 | .init = &cayman_init, |
||
2997 | Serge | 1379 | // .fini = &cayman_fini, |
1380 | // .suspend = &cayman_suspend, |
||
1381 | // .resume = &cayman_resume, |
||
1986 | serge | 1382 | .asic_reset = &cayman_asic_reset, |
2997 | Serge | 1383 | // .vga_set_state = &r600_vga_set_state, |
1384 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
||
1385 | .gui_idle = &r600_gui_idle, |
||
1386 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
||
1387 | .gart = { |
||
1388 | .tlb_flush = &cayman_pcie_gart_tlb_flush, |
||
1389 | .set_page = &rs600_gart_set_page, |
||
1390 | }, |
||
1391 | .vm = { |
||
1392 | .init = &cayman_vm_init, |
||
1393 | .fini = &cayman_vm_fini, |
||
1394 | .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1395 | .set_page = &cayman_vm_set_page, |
||
1396 | }, |
||
1397 | .ring = { |
||
1398 | [RADEON_RING_TYPE_GFX_INDEX] = { |
||
1399 | .ib_execute = &cayman_ring_ib_execute, |
||
1400 | // .ib_parse = &evergreen_ib_parse, |
||
1401 | .emit_fence = &cayman_fence_ring_emit, |
||
1402 | .emit_semaphore = &r600_semaphore_ring_emit, |
||
1403 | // .cs_parse = &evergreen_cs_parse, |
||
1404 | .ring_test = &r600_ring_test, |
||
1405 | .ib_test = &r600_ib_test, |
||
1406 | .is_lockup = &evergreen_gpu_is_lockup, |
||
1407 | .vm_flush = &cayman_vm_flush, |
||
1408 | }, |
||
1409 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
||
1410 | .ib_execute = &cayman_ring_ib_execute, |
||
1411 | // .ib_parse = &evergreen_ib_parse, |
||
1412 | .emit_fence = &cayman_fence_ring_emit, |
||
1413 | .emit_semaphore = &r600_semaphore_ring_emit, |
||
1414 | // .cs_parse = &evergreen_cs_parse, |
||
1415 | .ring_test = &r600_ring_test, |
||
1416 | .ib_test = &r600_ib_test, |
||
1417 | .is_lockup = &evergreen_gpu_is_lockup, |
||
1418 | .vm_flush = &cayman_vm_flush, |
||
1419 | }, |
||
1420 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
||
1421 | .ib_execute = &cayman_ring_ib_execute, |
||
1422 | // .ib_parse = &evergreen_ib_parse, |
||
1423 | .emit_fence = &cayman_fence_ring_emit, |
||
1424 | .emit_semaphore = &r600_semaphore_ring_emit, |
||
1425 | // .cs_parse = &evergreen_cs_parse, |
||
1426 | .ring_test = &r600_ring_test, |
||
1427 | .ib_test = &r600_ib_test, |
||
1428 | .is_lockup = &evergreen_gpu_is_lockup, |
||
1429 | .vm_flush = &cayman_vm_flush, |
||
1430 | } |
||
1431 | }, |
||
1432 | .irq = { |
||
1433 | .set = &evergreen_irq_set, |
||
1434 | .process = &evergreen_irq_process, |
||
1435 | }, |
||
1436 | .display = { |
||
1437 | .bandwidth_update = &evergreen_bandwidth_update, |
||
1438 | .get_vblank_counter = &evergreen_get_vblank_counter, |
||
1439 | .wait_for_vblank = &dce4_wait_for_vblank, |
||
1440 | // .set_backlight_level = &atombios_set_backlight_level, |
||
1441 | // .get_backlight_level = &atombios_get_backlight_level, |
||
1442 | }, |
||
1443 | .copy = { |
||
1444 | .blit = &r600_copy_blit, |
||
1445 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1446 | .dma = NULL, |
||
1447 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1448 | .copy = &r600_copy_blit, |
||
1449 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1450 | }, |
||
1451 | .surface = { |
||
1452 | .set_reg = r600_set_surface_reg, |
||
1453 | .clear_reg = r600_clear_surface_reg, |
||
1454 | }, |
||
1455 | .hpd = { |
||
1456 | // .init = &evergreen_hpd_init, |
||
1457 | // .fini = &evergreen_hpd_fini, |
||
1458 | // .sense = &evergreen_hpd_sense, |
||
1459 | // .set_polarity = &evergreen_hpd_set_polarity, |
||
1460 | }, |
||
1461 | .pm = { |
||
1462 | // .misc = &evergreen_pm_misc, |
||
1463 | // .prepare = &evergreen_pm_prepare, |
||
1464 | // .finish = &evergreen_pm_finish, |
||
1465 | // .init_profile = &btc_pm_init_profile, |
||
1466 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
||
1467 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
||
1468 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
||
1469 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
||
1470 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
||
1471 | // .get_pcie_lanes = NULL, |
||
1472 | // .set_pcie_lanes = NULL, |
||
1473 | // .set_clock_gating = NULL, |
||
1474 | }, |
||
1475 | .pflip = { |
||
1476 | // .pre_page_flip = &evergreen_pre_page_flip, |
||
1477 | // .page_flip = &evergreen_page_flip, |
||
1478 | // .post_page_flip = &evergreen_post_page_flip, |
||
1479 | }, |
||
1963 | serge | 1480 | }; |
1481 | |||
2997 | Serge | 1482 | static struct radeon_asic trinity_asic = { |
1483 | .init = &cayman_init, |
||
1484 | // .fini = &cayman_fini, |
||
1485 | // .suspend = &cayman_suspend, |
||
1486 | // .resume = &cayman_resume, |
||
1487 | .asic_reset = &cayman_asic_reset, |
||
1488 | // .vga_set_state = &r600_vga_set_state, |
||
1489 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
||
1490 | .gui_idle = &r600_gui_idle, |
||
1491 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
||
1492 | .gart = { |
||
1493 | .tlb_flush = &cayman_pcie_gart_tlb_flush, |
||
1494 | .set_page = &rs600_gart_set_page, |
||
1495 | }, |
||
1496 | .vm = { |
||
1497 | .init = &cayman_vm_init, |
||
1498 | .fini = &cayman_vm_fini, |
||
1499 | .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1500 | .set_page = &cayman_vm_set_page, |
||
1501 | }, |
||
1502 | .ring = { |
||
1503 | [RADEON_RING_TYPE_GFX_INDEX] = { |
||
1504 | .ib_execute = &cayman_ring_ib_execute, |
||
1505 | // .ib_parse = &evergreen_ib_parse, |
||
1506 | .emit_fence = &cayman_fence_ring_emit, |
||
1507 | .emit_semaphore = &r600_semaphore_ring_emit, |
||
1508 | // .cs_parse = &evergreen_cs_parse, |
||
1509 | .ring_test = &r600_ring_test, |
||
1510 | .ib_test = &r600_ib_test, |
||
1511 | .is_lockup = &evergreen_gpu_is_lockup, |
||
1512 | .vm_flush = &cayman_vm_flush, |
||
1513 | }, |
||
1514 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
||
1515 | .ib_execute = &cayman_ring_ib_execute, |
||
1516 | // .ib_parse = &evergreen_ib_parse, |
||
1517 | .emit_fence = &cayman_fence_ring_emit, |
||
1518 | .emit_semaphore = &r600_semaphore_ring_emit, |
||
1519 | // .cs_parse = &evergreen_cs_parse, |
||
1520 | .ring_test = &r600_ring_test, |
||
1521 | .ib_test = &r600_ib_test, |
||
1522 | .is_lockup = &evergreen_gpu_is_lockup, |
||
1523 | .vm_flush = &cayman_vm_flush, |
||
1524 | }, |
||
1525 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
||
1526 | .ib_execute = &cayman_ring_ib_execute, |
||
1527 | // .ib_parse = &evergreen_ib_parse, |
||
1528 | .emit_fence = &cayman_fence_ring_emit, |
||
1529 | .emit_semaphore = &r600_semaphore_ring_emit, |
||
1530 | // .cs_parse = &evergreen_cs_parse, |
||
1531 | .ring_test = &r600_ring_test, |
||
1532 | .ib_test = &r600_ib_test, |
||
1533 | .is_lockup = &evergreen_gpu_is_lockup, |
||
1534 | .vm_flush = &cayman_vm_flush, |
||
1535 | } |
||
1536 | }, |
||
1537 | .irq = { |
||
1538 | .set = &evergreen_irq_set, |
||
1539 | .process = &evergreen_irq_process, |
||
1540 | }, |
||
1541 | .display = { |
||
1542 | .bandwidth_update = &dce6_bandwidth_update, |
||
1543 | .get_vblank_counter = &evergreen_get_vblank_counter, |
||
1544 | .wait_for_vblank = &dce4_wait_for_vblank, |
||
1545 | // .set_backlight_level = &atombios_set_backlight_level, |
||
1546 | // .get_backlight_level = &atombios_get_backlight_level, |
||
1547 | }, |
||
1548 | .copy = { |
||
1549 | .blit = &r600_copy_blit, |
||
1550 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1551 | .dma = NULL, |
||
1552 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1553 | .copy = &r600_copy_blit, |
||
1554 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1555 | }, |
||
1556 | .surface = { |
||
1557 | .set_reg = r600_set_surface_reg, |
||
1558 | .clear_reg = r600_clear_surface_reg, |
||
1559 | }, |
||
1560 | .hpd = { |
||
1561 | // .init = &evergreen_hpd_init, |
||
1562 | // .fini = &evergreen_hpd_fini, |
||
1563 | // .sense = &evergreen_hpd_sense, |
||
1564 | // .set_polarity = &evergreen_hpd_set_polarity, |
||
1565 | }, |
||
1566 | .pm = { |
||
1567 | // .misc = &evergreen_pm_misc, |
||
1568 | // .prepare = &evergreen_pm_prepare, |
||
1569 | // .finish = &evergreen_pm_finish, |
||
1570 | // .init_profile = &sumo_pm_init_profile, |
||
1571 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
||
1572 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
||
1573 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
||
1574 | // .get_memory_clock = NULL, |
||
1575 | // .set_memory_clock = NULL, |
||
1576 | // .get_pcie_lanes = NULL, |
||
1577 | // .set_pcie_lanes = NULL, |
||
1578 | // .set_clock_gating = NULL, |
||
1579 | }, |
||
1580 | .pflip = { |
||
1581 | // .pre_page_flip = &evergreen_pre_page_flip, |
||
1582 | // .page_flip = &evergreen_page_flip, |
||
1583 | // .post_page_flip = &evergreen_post_page_flip, |
||
1584 | }, |
||
1585 | }; |
||
1586 | |||
1587 | static struct radeon_asic si_asic = { |
||
1588 | .init = &si_init, |
||
1589 | // .fini = &si_fini, |
||
1590 | // .suspend = &si_suspend, |
||
1591 | // .resume = &si_resume, |
||
1592 | .asic_reset = &si_asic_reset, |
||
1593 | // .vga_set_state = &r600_vga_set_state, |
||
1594 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
||
1595 | .gui_idle = &r600_gui_idle, |
||
1596 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
||
1597 | .gart = { |
||
1598 | .tlb_flush = &si_pcie_gart_tlb_flush, |
||
1599 | .set_page = &rs600_gart_set_page, |
||
1600 | }, |
||
1601 | .vm = { |
||
1602 | .init = &si_vm_init, |
||
1603 | .fini = &si_vm_fini, |
||
1604 | .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1605 | .set_page = &si_vm_set_page, |
||
1606 | }, |
||
1607 | .ring = { |
||
1608 | [RADEON_RING_TYPE_GFX_INDEX] = { |
||
1609 | .ib_execute = &si_ring_ib_execute, |
||
1610 | // .ib_parse = &si_ib_parse, |
||
1611 | .emit_fence = &si_fence_ring_emit, |
||
1612 | .emit_semaphore = &r600_semaphore_ring_emit, |
||
1613 | // .cs_parse = NULL, |
||
1614 | .ring_test = &r600_ring_test, |
||
1615 | .ib_test = &r600_ib_test, |
||
1616 | .is_lockup = &si_gpu_is_lockup, |
||
1617 | .vm_flush = &si_vm_flush, |
||
1618 | }, |
||
1619 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
||
1620 | .ib_execute = &si_ring_ib_execute, |
||
1621 | // .ib_parse = &si_ib_parse, |
||
1622 | .emit_fence = &si_fence_ring_emit, |
||
1623 | .emit_semaphore = &r600_semaphore_ring_emit, |
||
1624 | // .cs_parse = NULL, |
||
1625 | .ring_test = &r600_ring_test, |
||
1626 | .ib_test = &r600_ib_test, |
||
1627 | .is_lockup = &si_gpu_is_lockup, |
||
1628 | .vm_flush = &si_vm_flush, |
||
1629 | }, |
||
1630 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
||
1631 | .ib_execute = &si_ring_ib_execute, |
||
1632 | // .ib_parse = &si_ib_parse, |
||
1633 | .emit_fence = &si_fence_ring_emit, |
||
1634 | .emit_semaphore = &r600_semaphore_ring_emit, |
||
1635 | // .cs_parse = NULL, |
||
1636 | .ring_test = &r600_ring_test, |
||
1637 | .ib_test = &r600_ib_test, |
||
1638 | .is_lockup = &si_gpu_is_lockup, |
||
1639 | .vm_flush = &si_vm_flush, |
||
1640 | } |
||
1641 | }, |
||
1642 | .irq = { |
||
1643 | .set = &si_irq_set, |
||
1644 | .process = &si_irq_process, |
||
1645 | }, |
||
1646 | .display = { |
||
1647 | .bandwidth_update = &dce6_bandwidth_update, |
||
1648 | .get_vblank_counter = &evergreen_get_vblank_counter, |
||
1649 | .wait_for_vblank = &dce4_wait_for_vblank, |
||
1650 | // .set_backlight_level = &atombios_set_backlight_level, |
||
1651 | // .get_backlight_level = &atombios_get_backlight_level, |
||
1652 | }, |
||
1653 | .copy = { |
||
1654 | .blit = NULL, |
||
1655 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1656 | .dma = NULL, |
||
1657 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1658 | .copy = NULL, |
||
1659 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
||
1660 | }, |
||
1661 | .surface = { |
||
1662 | .set_reg = r600_set_surface_reg, |
||
1663 | .clear_reg = r600_clear_surface_reg, |
||
1664 | }, |
||
1665 | .hpd = { |
||
1666 | .init = &evergreen_hpd_init, |
||
1667 | .fini = &evergreen_hpd_fini, |
||
1668 | .sense = &evergreen_hpd_sense, |
||
1669 | .set_polarity = &evergreen_hpd_set_polarity, |
||
1670 | }, |
||
1671 | .pm = { |
||
1672 | // .misc = &evergreen_pm_misc, |
||
1673 | // .prepare = &evergreen_pm_prepare, |
||
1674 | // .finish = &evergreen_pm_finish, |
||
1675 | // .init_profile = &sumo_pm_init_profile, |
||
1676 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
||
1677 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
||
1678 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
||
1679 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
||
1680 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
||
1681 | // .get_pcie_lanes = NULL, |
||
1682 | // .set_pcie_lanes = NULL, |
||
1683 | // .set_clock_gating = NULL, |
||
1684 | }, |
||
1685 | .pflip = { |
||
1686 | // .pre_page_flip = &evergreen_pre_page_flip, |
||
1687 | // .page_flip = &evergreen_page_flip, |
||
1688 | // .post_page_flip = &evergreen_post_page_flip, |
||
1689 | }, |
||
1690 | }; |
||
1691 | |||
1692 | /** |
||
1693 | * radeon_asic_init - register asic specific callbacks |
||
1694 | * |
||
1695 | * @rdev: radeon device pointer |
||
1696 | * |
||
1697 | * Registers the appropriate asic specific callbacks for each |
||
1698 | * chip family. Also sets other asics specific info like the number |
||
1699 | * of crtcs and the register aperture accessors (all asics). |
||
1700 | * Returns 0 for success. |
||
1701 | */ |
||
1963 | serge | 1702 | int radeon_asic_init(struct radeon_device *rdev) |
1703 | { |
||
1704 | radeon_register_accessor_init(rdev); |
||
1986 | serge | 1705 | |
1706 | /* set the number of crtcs */ |
||
1707 | if (rdev->flags & RADEON_SINGLE_CRTC) |
||
1708 | rdev->num_crtc = 1; |
||
1709 | else |
||
1710 | rdev->num_crtc = 2; |
||
1711 | |||
1963 | serge | 1712 | switch (rdev->family) { |
1713 | case CHIP_R100: |
||
1714 | case CHIP_RV100: |
||
1715 | case CHIP_RS100: |
||
1716 | case CHIP_RV200: |
||
1717 | case CHIP_RS200: |
||
1718 | rdev->asic = &r100_asic; |
||
1719 | break; |
||
1720 | case CHIP_R200: |
||
1721 | case CHIP_RV250: |
||
1722 | case CHIP_RS300: |
||
1723 | case CHIP_RV280: |
||
1724 | rdev->asic = &r200_asic; |
||
1725 | break; |
||
1726 | case CHIP_R300: |
||
1727 | case CHIP_R350: |
||
1728 | case CHIP_RV350: |
||
1729 | case CHIP_RV380: |
||
1730 | if (rdev->flags & RADEON_IS_PCIE) |
||
1731 | rdev->asic = &r300_asic_pcie; |
||
1732 | else |
||
1733 | rdev->asic = &r300_asic; |
||
1734 | break; |
||
1735 | case CHIP_R420: |
||
1736 | case CHIP_R423: |
||
1737 | case CHIP_RV410: |
||
1738 | rdev->asic = &r420_asic; |
||
1739 | /* handle macs */ |
||
1740 | if (rdev->bios == NULL) { |
||
2997 | Serge | 1741 | rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; |
1742 | rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; |
||
1743 | rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; |
||
1744 | rdev->asic->pm.set_memory_clock = NULL; |
||
1745 | rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; |
||
1963 | serge | 1746 | } |
1747 | break; |
||
1748 | case CHIP_RS400: |
||
1749 | case CHIP_RS480: |
||
1750 | rdev->asic = &rs400_asic; |
||
1751 | break; |
||
1752 | case CHIP_RS600: |
||
1753 | rdev->asic = &rs600_asic; |
||
1754 | break; |
||
1755 | case CHIP_RS690: |
||
1756 | case CHIP_RS740: |
||
1757 | rdev->asic = &rs690_asic; |
||
1758 | break; |
||
1759 | case CHIP_RV515: |
||
1760 | rdev->asic = &rv515_asic; |
||
1761 | break; |
||
1762 | case CHIP_R520: |
||
1763 | case CHIP_RV530: |
||
1764 | case CHIP_RV560: |
||
1765 | case CHIP_RV570: |
||
1766 | case CHIP_R580: |
||
1767 | rdev->asic = &r520_asic; |
||
1768 | break; |
||
1769 | case CHIP_R600: |
||
1770 | case CHIP_RV610: |
||
1771 | case CHIP_RV630: |
||
1772 | case CHIP_RV620: |
||
1773 | case CHIP_RV635: |
||
1774 | case CHIP_RV670: |
||
1775 | rdev->asic = &r600_asic; |
||
1776 | break; |
||
1777 | case CHIP_RS780: |
||
1778 | case CHIP_RS880: |
||
1779 | rdev->asic = &rs780_asic; |
||
1780 | break; |
||
1781 | case CHIP_RV770: |
||
1782 | case CHIP_RV730: |
||
1783 | case CHIP_RV710: |
||
1784 | case CHIP_RV740: |
||
1785 | rdev->asic = &rv770_asic; |
||
1786 | break; |
||
1986 | serge | 1787 | case CHIP_CEDAR: |
1788 | case CHIP_REDWOOD: |
||
1789 | case CHIP_JUNIPER: |
||
1790 | case CHIP_CYPRESS: |
||
1791 | case CHIP_HEMLOCK: |
||
1792 | /* set num crtcs */ |
||
1793 | if (rdev->family == CHIP_CEDAR) |
||
1794 | rdev->num_crtc = 4; |
||
1795 | else |
||
1796 | rdev->num_crtc = 6; |
||
1797 | rdev->asic = &evergreen_asic; |
||
1798 | break; |
||
1990 | serge | 1799 | case CHIP_PALM: |
1800 | case CHIP_SUMO: |
||
1801 | case CHIP_SUMO2: |
||
1802 | rdev->asic = &sumo_asic; |
||
1803 | break; |
||
1804 | case CHIP_BARTS: |
||
1805 | case CHIP_TURKS: |
||
1806 | case CHIP_CAICOS: |
||
1807 | /* set num crtcs */ |
||
1808 | if (rdev->family == CHIP_CAICOS) |
||
1809 | rdev->num_crtc = 4; |
||
1810 | else |
||
1811 | rdev->num_crtc = 6; |
||
1812 | rdev->asic = &btc_asic; |
||
1813 | break; |
||
2004 | serge | 1814 | case CHIP_CAYMAN: |
1815 | rdev->asic = &cayman_asic; |
||
1816 | /* set num crtcs */ |
||
1817 | rdev->num_crtc = 6; |
||
1818 | break; |
||
2997 | Serge | 1819 | case CHIP_ARUBA: |
1820 | rdev->asic = &trinity_asic; |
||
1821 | /* set num crtcs */ |
||
1822 | rdev->num_crtc = 4; |
||
1823 | break; |
||
1824 | case CHIP_TAHITI: |
||
1825 | case CHIP_PITCAIRN: |
||
1826 | case CHIP_VERDE: |
||
1827 | rdev->asic = &si_asic; |
||
1828 | /* set num crtcs */ |
||
1829 | rdev->num_crtc = 6; |
||
1830 | break; |
||
1963 | serge | 1831 | default: |
1832 | /* FIXME: not supported yet */ |
||
1833 | return -EINVAL; |
||
1834 | } |
||
1835 | |||
1836 | if (rdev->flags & RADEON_IS_IGP) { |
||
2997 | Serge | 1837 | rdev->asic->pm.get_memory_clock = NULL; |
1838 | rdev->asic->pm.set_memory_clock = NULL; |
||
1963 | serge | 1839 | } |
1840 | |||
1841 | return 0; |
||
1842 | }=>> |
||
1843 |