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1963 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | |||
29 | //#include |
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30 | #include |
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31 | #include |
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32 | #include |
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33 | //#include |
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34 | //#include |
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35 | #include "radeon_reg.h" |
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36 | #include "radeon.h" |
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37 | #include "radeon_asic.h" |
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38 | #include "atom.h" |
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39 | |||
40 | /* |
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41 | * Registers accessors functions. |
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42 | */ |
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43 | static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
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44 | { |
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45 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); |
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46 | BUG_ON(1); |
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47 | return 0; |
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48 | } |
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49 | |||
50 | static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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51 | { |
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52 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", |
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53 | reg, v); |
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54 | BUG_ON(1); |
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55 | } |
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56 | |||
57 | static void radeon_register_accessor_init(struct radeon_device *rdev) |
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58 | { |
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59 | rdev->mc_rreg = &radeon_invalid_rreg; |
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60 | rdev->mc_wreg = &radeon_invalid_wreg; |
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61 | rdev->pll_rreg = &radeon_invalid_rreg; |
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62 | rdev->pll_wreg = &radeon_invalid_wreg; |
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63 | rdev->pciep_rreg = &radeon_invalid_rreg; |
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64 | rdev->pciep_wreg = &radeon_invalid_wreg; |
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65 | |||
66 | /* Don't change order as we are overridding accessor. */ |
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67 | if (rdev->family < CHIP_RV515) { |
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68 | rdev->pcie_reg_mask = 0xff; |
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69 | } else { |
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70 | rdev->pcie_reg_mask = 0x7ff; |
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71 | } |
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72 | /* FIXME: not sure here */ |
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73 | if (rdev->family <= CHIP_R580) { |
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74 | rdev->pll_rreg = &r100_pll_rreg; |
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75 | rdev->pll_wreg = &r100_pll_wreg; |
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76 | } |
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77 | if (rdev->family >= CHIP_R420) { |
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78 | rdev->mc_rreg = &r420_mc_rreg; |
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79 | rdev->mc_wreg = &r420_mc_wreg; |
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80 | } |
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81 | if (rdev->family >= CHIP_RV515) { |
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82 | rdev->mc_rreg = &rv515_mc_rreg; |
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83 | rdev->mc_wreg = &rv515_mc_wreg; |
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84 | } |
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85 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
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86 | rdev->mc_rreg = &rs400_mc_rreg; |
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87 | rdev->mc_wreg = &rs400_mc_wreg; |
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88 | } |
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89 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
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90 | rdev->mc_rreg = &rs690_mc_rreg; |
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91 | rdev->mc_wreg = &rs690_mc_wreg; |
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92 | } |
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93 | if (rdev->family == CHIP_RS600) { |
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94 | rdev->mc_rreg = &rs600_mc_rreg; |
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95 | rdev->mc_wreg = &rs600_mc_wreg; |
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96 | } |
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97 | if (rdev->family >= CHIP_R600) { |
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98 | rdev->pciep_rreg = &r600_pciep_rreg; |
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99 | rdev->pciep_wreg = &r600_pciep_wreg; |
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100 | } |
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101 | } |
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102 | |||
103 | |||
104 | /* helper to disable agp */ |
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105 | void radeon_agp_disable(struct radeon_device *rdev) |
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106 | { |
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107 | rdev->flags &= ~RADEON_IS_AGP; |
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108 | if (rdev->family >= CHIP_R600) { |
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109 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
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110 | rdev->flags |= RADEON_IS_PCIE; |
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111 | } else if (rdev->family >= CHIP_RV515 || |
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112 | rdev->family == CHIP_RV380 || |
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113 | rdev->family == CHIP_RV410 || |
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114 | rdev->family == CHIP_R423) { |
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115 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
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116 | rdev->flags |= RADEON_IS_PCIE; |
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117 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
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118 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
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119 | } else { |
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120 | DRM_INFO("Forcing AGP to PCI mode\n"); |
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121 | rdev->flags |= RADEON_IS_PCI; |
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122 | rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; |
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123 | rdev->asic->gart_set_page = &r100_pci_gart_set_page; |
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124 | } |
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125 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
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126 | } |
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127 | |||
128 | /* |
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129 | * ASIC |
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130 | */ |
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131 | static struct radeon_asic r100_asic = { |
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132 | .init = &r100_init, |
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133 | // .fini = &r100_fini, |
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134 | // .suspend = &r100_suspend, |
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135 | // .resume = &r100_resume, |
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136 | // .vga_set_state = &r100_vga_set_state, |
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137 | .asic_reset = &r100_asic_reset, |
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138 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
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139 | .gart_set_page = &r100_pci_gart_set_page, |
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140 | .cp_commit = &r100_cp_commit, |
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141 | .ring_start = &r100_ring_start, |
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142 | .ring_test = &r100_ring_test, |
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143 | // .ring_ib_execute = &r100_ring_ib_execute, |
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144 | // .irq_set = &r100_irq_set, |
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145 | // .irq_process = &r100_irq_process, |
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146 | // .get_vblank_counter = &r100_get_vblank_counter, |
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147 | .fence_ring_emit = &r100_fence_ring_emit, |
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148 | // .cs_parse = &r100_cs_parse, |
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149 | // .copy_blit = &r100_copy_blit, |
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150 | // .copy_dma = NULL, |
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151 | // .copy = &r100_copy_blit, |
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152 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
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153 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
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154 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
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155 | .set_memory_clock = NULL, |
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156 | .get_pcie_lanes = NULL, |
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157 | .set_pcie_lanes = NULL, |
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158 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
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159 | .set_surface_reg = r100_set_surface_reg, |
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160 | .clear_surface_reg = r100_clear_surface_reg, |
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161 | .bandwidth_update = &r100_bandwidth_update, |
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162 | .hpd_init = &r100_hpd_init, |
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163 | .hpd_fini = &r100_hpd_fini, |
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164 | .hpd_sense = &r100_hpd_sense, |
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165 | .hpd_set_polarity = &r100_hpd_set_polarity, |
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166 | .ioctl_wait_idle = NULL, |
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167 | }; |
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168 | |||
169 | static struct radeon_asic r200_asic = { |
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170 | .init = &r100_init, |
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171 | // .fini = &r100_fini, |
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172 | // .suspend = &r100_suspend, |
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173 | // .resume = &r100_resume, |
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174 | // .vga_set_state = &r100_vga_set_state, |
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175 | .asic_reset = &r100_asic_reset, |
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176 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
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177 | .gart_set_page = &r100_pci_gart_set_page, |
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178 | .cp_commit = &r100_cp_commit, |
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179 | .ring_start = &r100_ring_start, |
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180 | .ring_test = &r100_ring_test, |
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181 | // .ring_ib_execute = &r100_ring_ib_execute, |
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182 | // .irq_set = &r100_irq_set, |
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183 | // .irq_process = &r100_irq_process, |
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184 | // .get_vblank_counter = &r100_get_vblank_counter, |
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185 | .fence_ring_emit = &r100_fence_ring_emit, |
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186 | // .cs_parse = &r100_cs_parse, |
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187 | // .copy_blit = &r100_copy_blit, |
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188 | // .copy_dma = NULL, |
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189 | // .copy = &r100_copy_blit, |
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190 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
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191 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
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192 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
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193 | .set_memory_clock = NULL, |
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194 | .set_pcie_lanes = NULL, |
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195 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
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196 | .set_surface_reg = r100_set_surface_reg, |
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197 | .clear_surface_reg = r100_clear_surface_reg, |
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198 | .bandwidth_update = &r100_bandwidth_update, |
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199 | .hpd_init = &r100_hpd_init, |
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200 | .hpd_fini = &r100_hpd_fini, |
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201 | .hpd_sense = &r100_hpd_sense, |
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202 | .hpd_set_polarity = &r100_hpd_set_polarity, |
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203 | .ioctl_wait_idle = NULL, |
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204 | }; |
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205 | |||
206 | static struct radeon_asic r300_asic = { |
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207 | .init = &r300_init, |
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208 | // .fini = &r300_fini, |
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209 | // .suspend = &r300_suspend, |
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210 | // .resume = &r300_resume, |
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211 | // .vga_set_state = &r100_vga_set_state, |
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212 | .asic_reset = &r300_asic_reset, |
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213 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
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214 | .gart_set_page = &r100_pci_gart_set_page, |
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215 | .cp_commit = &r100_cp_commit, |
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216 | .ring_start = &r300_ring_start, |
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217 | .ring_test = &r100_ring_test, |
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218 | // .ring_ib_execute = &r100_ring_ib_execute, |
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219 | // .irq_set = &r100_irq_set, |
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220 | // .irq_process = &r100_irq_process, |
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221 | // .get_vblank_counter = &r100_get_vblank_counter, |
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222 | .fence_ring_emit = &r300_fence_ring_emit, |
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223 | // .cs_parse = &r300_cs_parse, |
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224 | // .copy_blit = &r100_copy_blit, |
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225 | // .copy_dma = &r300_copy_dma, |
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226 | // .copy = &r100_copy_blit, |
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227 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
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228 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
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229 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
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230 | .set_memory_clock = NULL, |
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231 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
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232 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
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233 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
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234 | .set_surface_reg = r100_set_surface_reg, |
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235 | .clear_surface_reg = r100_clear_surface_reg, |
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236 | .bandwidth_update = &r100_bandwidth_update, |
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237 | .hpd_init = &r100_hpd_init, |
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238 | .hpd_fini = &r100_hpd_fini, |
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239 | .hpd_sense = &r100_hpd_sense, |
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240 | .hpd_set_polarity = &r100_hpd_set_polarity, |
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241 | .ioctl_wait_idle = NULL, |
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242 | }; |
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243 | |||
244 | static struct radeon_asic r300_asic_pcie = { |
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245 | .init = &r300_init, |
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246 | // .fini = &r300_fini, |
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247 | // .suspend = &r300_suspend, |
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248 | // .resume = &r300_resume, |
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249 | // .vga_set_state = &r100_vga_set_state, |
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250 | .asic_reset = &r300_asic_reset, |
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251 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
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252 | .gart_set_page = &rv370_pcie_gart_set_page, |
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253 | .cp_commit = &r100_cp_commit, |
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254 | .ring_start = &r300_ring_start, |
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255 | .ring_test = &r100_ring_test, |
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256 | // .ring_ib_execute = &r100_ring_ib_execute, |
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257 | // .irq_set = &r100_irq_set, |
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258 | // .irq_process = &r100_irq_process, |
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259 | // .get_vblank_counter = &r100_get_vblank_counter, |
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260 | .fence_ring_emit = &r300_fence_ring_emit, |
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261 | // .cs_parse = &r300_cs_parse, |
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262 | // .copy_blit = &r100_copy_blit, |
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263 | // .copy_dma = &r300_copy_dma, |
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264 | // .copy = &r100_copy_blit, |
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265 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
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266 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
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267 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
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268 | .set_memory_clock = NULL, |
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269 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
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270 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
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271 | .set_surface_reg = r100_set_surface_reg, |
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272 | .clear_surface_reg = r100_clear_surface_reg, |
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273 | .bandwidth_update = &r100_bandwidth_update, |
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274 | .hpd_init = &r100_hpd_init, |
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275 | .hpd_fini = &r100_hpd_fini, |
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276 | .hpd_sense = &r100_hpd_sense, |
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277 | .hpd_set_polarity = &r100_hpd_set_polarity, |
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278 | .ioctl_wait_idle = NULL, |
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279 | }; |
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280 | |||
281 | static struct radeon_asic r420_asic = { |
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282 | .init = &r420_init, |
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283 | // .fini = &r420_fini, |
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284 | // .suspend = &r420_suspend, |
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285 | // .resume = &r420_resume, |
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286 | // .vga_set_state = &r100_vga_set_state, |
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287 | .asic_reset = &r300_asic_reset, |
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288 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
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289 | .gart_set_page = &rv370_pcie_gart_set_page, |
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290 | .cp_commit = &r100_cp_commit, |
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291 | .ring_start = &r300_ring_start, |
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292 | .ring_test = &r100_ring_test, |
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293 | // .ring_ib_execute = &r100_ring_ib_execute, |
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294 | // .irq_set = &r100_irq_set, |
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295 | // .irq_process = &r100_irq_process, |
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296 | // .get_vblank_counter = &r100_get_vblank_counter, |
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297 | .fence_ring_emit = &r300_fence_ring_emit, |
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298 | // .cs_parse = &r300_cs_parse, |
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299 | // .copy_blit = &r100_copy_blit, |
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300 | // .copy_dma = &r300_copy_dma, |
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301 | // .copy = &r100_copy_blit, |
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302 | .get_engine_clock = &radeon_atom_get_engine_clock, |
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303 | .set_engine_clock = &radeon_atom_set_engine_clock, |
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304 | .get_memory_clock = &radeon_atom_get_memory_clock, |
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305 | .set_memory_clock = &radeon_atom_set_memory_clock, |
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306 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
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307 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
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308 | .set_clock_gating = &radeon_atom_set_clock_gating, |
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309 | .set_surface_reg = r100_set_surface_reg, |
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310 | .clear_surface_reg = r100_clear_surface_reg, |
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311 | .bandwidth_update = &r100_bandwidth_update, |
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312 | .hpd_init = &r100_hpd_init, |
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313 | .hpd_fini = &r100_hpd_fini, |
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314 | .hpd_sense = &r100_hpd_sense, |
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315 | .hpd_set_polarity = &r100_hpd_set_polarity, |
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316 | .ioctl_wait_idle = NULL, |
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317 | }; |
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318 | |||
319 | static struct radeon_asic rs400_asic = { |
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320 | .init = &rs400_init, |
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321 | // .fini = &rs400_fini, |
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322 | // .suspend = &rs400_suspend, |
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323 | // .resume = &rs400_resume, |
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324 | // .vga_set_state = &r100_vga_set_state, |
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325 | .asic_reset = &r300_asic_reset, |
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326 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
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327 | .gart_set_page = &rs400_gart_set_page, |
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328 | .cp_commit = &r100_cp_commit, |
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329 | .ring_start = &r300_ring_start, |
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330 | .ring_test = &r100_ring_test, |
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331 | // .ring_ib_execute = &r100_ring_ib_execute, |
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332 | // .irq_set = &r100_irq_set, |
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333 | // .irq_process = &r100_irq_process, |
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334 | // .get_vblank_counter = &r100_get_vblank_counter, |
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335 | .fence_ring_emit = &r300_fence_ring_emit, |
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336 | // .cs_parse = &r300_cs_parse, |
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337 | // .copy_blit = &r100_copy_blit, |
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338 | // .copy_dma = &r300_copy_dma, |
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339 | // .copy = &r100_copy_blit, |
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340 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
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341 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
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342 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
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343 | .set_memory_clock = NULL, |
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344 | .get_pcie_lanes = NULL, |
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345 | .set_pcie_lanes = NULL, |
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346 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
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347 | .set_surface_reg = r100_set_surface_reg, |
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348 | .clear_surface_reg = r100_clear_surface_reg, |
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349 | .bandwidth_update = &r100_bandwidth_update, |
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350 | .hpd_init = &r100_hpd_init, |
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351 | .hpd_fini = &r100_hpd_fini, |
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352 | .hpd_sense = &r100_hpd_sense, |
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353 | .hpd_set_polarity = &r100_hpd_set_polarity, |
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354 | .ioctl_wait_idle = NULL, |
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355 | }; |
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356 | |||
357 | static struct radeon_asic rs600_asic = { |
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358 | .init = &rs600_init, |
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359 | // .fini = &rs600_fini, |
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360 | // .suspend = &rs600_suspend, |
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361 | // .resume = &rs600_resume, |
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362 | // .vga_set_state = &r100_vga_set_state, |
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363 | .asic_reset = &rs600_asic_reset, |
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364 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
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365 | .gart_set_page = &rs600_gart_set_page, |
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366 | .cp_commit = &r100_cp_commit, |
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367 | .ring_start = &r300_ring_start, |
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368 | .ring_test = &r100_ring_test, |
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369 | // .ring_ib_execute = &r100_ring_ib_execute, |
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370 | // .irq_set = &rs600_irq_set, |
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371 | // .irq_process = &rs600_irq_process, |
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372 | // .get_vblank_counter = &rs600_get_vblank_counter, |
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373 | .fence_ring_emit = &r300_fence_ring_emit, |
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374 | // .cs_parse = &r300_cs_parse, |
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375 | // .copy_blit = &r100_copy_blit, |
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376 | // .copy_dma = &r300_copy_dma, |
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377 | // .copy = &r100_copy_blit, |
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378 | .get_engine_clock = &radeon_atom_get_engine_clock, |
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379 | .set_engine_clock = &radeon_atom_set_engine_clock, |
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380 | .get_memory_clock = &radeon_atom_get_memory_clock, |
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381 | .set_memory_clock = &radeon_atom_set_memory_clock, |
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382 | .get_pcie_lanes = NULL, |
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383 | .set_pcie_lanes = NULL, |
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384 | .set_clock_gating = &radeon_atom_set_clock_gating, |
||
385 | .set_surface_reg = r100_set_surface_reg, |
||
386 | .clear_surface_reg = r100_clear_surface_reg, |
||
387 | .bandwidth_update = &rs600_bandwidth_update, |
||
388 | .hpd_init = &rs600_hpd_init, |
||
389 | .hpd_fini = &rs600_hpd_fini, |
||
390 | .hpd_sense = &rs600_hpd_sense, |
||
391 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
||
392 | .ioctl_wait_idle = NULL, |
||
393 | }; |
||
394 | |||
395 | static struct radeon_asic rs690_asic = { |
||
396 | .init = &rs690_init, |
||
397 | // .fini = &rs690_fini, |
||
398 | // .suspend = &rs690_suspend, |
||
399 | // .resume = &rs690_resume, |
||
400 | // .vga_set_state = &r100_vga_set_state, |
||
401 | .asic_reset = &rs600_asic_reset, |
||
402 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
||
403 | .gart_set_page = &rs400_gart_set_page, |
||
404 | .cp_commit = &r100_cp_commit, |
||
405 | .ring_start = &r300_ring_start, |
||
406 | .ring_test = &r100_ring_test, |
||
407 | // .ring_ib_execute = &r100_ring_ib_execute, |
||
408 | // .irq_set = &rs600_irq_set, |
||
409 | // .irq_process = &rs600_irq_process, |
||
410 | // .get_vblank_counter = &rs600_get_vblank_counter, |
||
411 | .fence_ring_emit = &r300_fence_ring_emit, |
||
412 | // .cs_parse = &r300_cs_parse, |
||
413 | // .copy_blit = &r100_copy_blit, |
||
414 | // .copy_dma = &r300_copy_dma, |
||
415 | // .copy = &r300_copy_dma, |
||
416 | .get_engine_clock = &radeon_atom_get_engine_clock, |
||
417 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
418 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
419 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
420 | .get_pcie_lanes = NULL, |
||
421 | .set_pcie_lanes = NULL, |
||
422 | .set_clock_gating = &radeon_atom_set_clock_gating, |
||
423 | .set_surface_reg = r100_set_surface_reg, |
||
424 | .clear_surface_reg = r100_clear_surface_reg, |
||
425 | .bandwidth_update = &rs690_bandwidth_update, |
||
426 | .hpd_init = &rs600_hpd_init, |
||
427 | .hpd_fini = &rs600_hpd_fini, |
||
428 | .hpd_sense = &rs600_hpd_sense, |
||
429 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
||
430 | .ioctl_wait_idle = NULL, |
||
431 | }; |
||
432 | |||
433 | static struct radeon_asic rv515_asic = { |
||
434 | .init = &rv515_init, |
||
435 | // .fini = &rv515_fini, |
||
436 | // .suspend = &rv515_suspend, |
||
437 | // .resume = &rv515_resume, |
||
438 | // .vga_set_state = &r100_vga_set_state, |
||
439 | .asic_reset = &rs600_asic_reset, |
||
440 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
||
441 | .gart_set_page = &rv370_pcie_gart_set_page, |
||
442 | .cp_commit = &r100_cp_commit, |
||
443 | .ring_start = &rv515_ring_start, |
||
444 | .ring_test = &r100_ring_test, |
||
445 | // .ring_ib_execute = &r100_ring_ib_execute, |
||
446 | // .irq_set = &rs600_irq_set, |
||
447 | // .irq_process = &rs600_irq_process, |
||
448 | // .get_vblank_counter = &rs600_get_vblank_counter, |
||
449 | .fence_ring_emit = &r300_fence_ring_emit, |
||
450 | // .cs_parse = &r300_cs_parse, |
||
451 | // .copy_blit = &r100_copy_blit, |
||
452 | // .copy_dma = &r300_copy_dma, |
||
453 | // .copy = &r100_copy_blit, |
||
454 | .get_engine_clock = &radeon_atom_get_engine_clock, |
||
455 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
456 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
457 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
458 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
||
459 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
||
460 | .set_clock_gating = &radeon_atom_set_clock_gating, |
||
461 | .set_surface_reg = r100_set_surface_reg, |
||
462 | .clear_surface_reg = r100_clear_surface_reg, |
||
463 | .bandwidth_update = &rv515_bandwidth_update, |
||
464 | .hpd_init = &rs600_hpd_init, |
||
465 | .hpd_fini = &rs600_hpd_fini, |
||
466 | .hpd_sense = &rs600_hpd_sense, |
||
467 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
||
468 | .ioctl_wait_idle = NULL, |
||
469 | }; |
||
470 | |||
471 | static struct radeon_asic r520_asic = { |
||
472 | .init = &r520_init, |
||
473 | // .fini = &rv515_fini, |
||
474 | // .suspend = &rv515_suspend, |
||
475 | // .resume = &r520_resume, |
||
476 | // .vga_set_state = &r100_vga_set_state, |
||
477 | .asic_reset = &rs600_asic_reset, |
||
478 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
||
479 | .gart_set_page = &rv370_pcie_gart_set_page, |
||
480 | .cp_commit = &r100_cp_commit, |
||
481 | .ring_start = &rv515_ring_start, |
||
482 | .ring_test = &r100_ring_test, |
||
483 | // .ring_ib_execute = &r100_ring_ib_execute, |
||
484 | // .irq_set = &rs600_irq_set, |
||
485 | // .irq_process = &rs600_irq_process, |
||
486 | // .get_vblank_counter = &rs600_get_vblank_counter, |
||
487 | .fence_ring_emit = &r300_fence_ring_emit, |
||
488 | // .cs_parse = &r300_cs_parse, |
||
489 | // .copy_blit = &r100_copy_blit, |
||
490 | // .copy_dma = &r300_copy_dma, |
||
491 | // .copy = &r100_copy_blit, |
||
492 | .get_engine_clock = &radeon_atom_get_engine_clock, |
||
493 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
494 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
495 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
496 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
||
497 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
||
498 | .set_clock_gating = &radeon_atom_set_clock_gating, |
||
499 | .set_surface_reg = r100_set_surface_reg, |
||
500 | .clear_surface_reg = r100_clear_surface_reg, |
||
501 | .bandwidth_update = &rv515_bandwidth_update, |
||
502 | .hpd_init = &rs600_hpd_init, |
||
503 | .hpd_fini = &rs600_hpd_fini, |
||
504 | .hpd_sense = &rs600_hpd_sense, |
||
505 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
||
506 | .ioctl_wait_idle = NULL, |
||
507 | }; |
||
508 | |||
509 | static struct radeon_asic r600_asic = { |
||
510 | .init = &r600_init, |
||
511 | // .fini = &r600_fini, |
||
512 | // .suspend = &r600_suspend, |
||
513 | // .resume = &r600_resume, |
||
514 | .cp_commit = &r600_cp_commit, |
||
515 | .vga_set_state = &r600_vga_set_state, |
||
516 | .asic_reset = &r600_asic_reset, |
||
517 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
||
518 | .gart_set_page = &rs600_gart_set_page, |
||
519 | .ring_test = &r600_ring_test, |
||
520 | // .ring_ib_execute = &r600_ring_ib_execute, |
||
2004 | serge | 521 | .irq_set = &r600_irq_set, |
522 | .irq_process = &r600_irq_process, |
||
1963 | serge | 523 | .fence_ring_emit = &r600_fence_ring_emit, |
524 | // .cs_parse = &r600_cs_parse, |
||
525 | // .copy_blit = &r600_copy_blit, |
||
526 | // .copy_dma = &r600_copy_blit, |
||
527 | // .copy = &r600_copy_blit, |
||
528 | .get_engine_clock = &radeon_atom_get_engine_clock, |
||
529 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
530 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
531 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
532 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
||
533 | .set_pcie_lanes = NULL, |
||
534 | .set_clock_gating = NULL, |
||
535 | .set_surface_reg = r600_set_surface_reg, |
||
536 | .clear_surface_reg = r600_clear_surface_reg, |
||
537 | .bandwidth_update = &rv515_bandwidth_update, |
||
538 | .hpd_init = &r600_hpd_init, |
||
539 | .hpd_fini = &r600_hpd_fini, |
||
540 | .hpd_sense = &r600_hpd_sense, |
||
541 | .hpd_set_polarity = &r600_hpd_set_polarity, |
||
542 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
||
543 | }; |
||
544 | |||
545 | static struct radeon_asic rs780_asic = { |
||
546 | .init = &r600_init, |
||
547 | // .fini = &r600_fini, |
||
548 | // .suspend = &r600_suspend, |
||
549 | // .resume = &r600_resume, |
||
550 | .cp_commit = &r600_cp_commit, |
||
551 | .gpu_is_lockup = &r600_gpu_is_lockup, |
||
552 | .vga_set_state = &r600_vga_set_state, |
||
553 | .asic_reset = &r600_asic_reset, |
||
554 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
||
555 | .gart_set_page = &rs600_gart_set_page, |
||
556 | .ring_test = &r600_ring_test, |
||
557 | // .ring_ib_execute = &r600_ring_ib_execute, |
||
2004 | serge | 558 | .irq_set = &r600_irq_set, |
559 | .irq_process = &r600_irq_process, |
||
1963 | serge | 560 | .fence_ring_emit = &r600_fence_ring_emit, |
561 | // .cs_parse = &r600_cs_parse, |
||
562 | // .copy_blit = &r600_copy_blit, |
||
563 | // .copy_dma = &r600_copy_blit, |
||
564 | // .copy = &r600_copy_blit, |
||
565 | .get_engine_clock = &radeon_atom_get_engine_clock, |
||
566 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
567 | .get_memory_clock = NULL, |
||
568 | .set_memory_clock = NULL, |
||
569 | .get_pcie_lanes = NULL, |
||
570 | .set_pcie_lanes = NULL, |
||
571 | .set_clock_gating = NULL, |
||
572 | .set_surface_reg = r600_set_surface_reg, |
||
573 | .clear_surface_reg = r600_clear_surface_reg, |
||
574 | .bandwidth_update = &rs690_bandwidth_update, |
||
575 | .hpd_init = &r600_hpd_init, |
||
576 | .hpd_fini = &r600_hpd_fini, |
||
577 | .hpd_sense = &r600_hpd_sense, |
||
578 | .hpd_set_polarity = &r600_hpd_set_polarity, |
||
579 | }; |
||
580 | |||
581 | static struct radeon_asic rv770_asic = { |
||
582 | .init = &rv770_init, |
||
583 | // .fini = &rv770_fini, |
||
584 | // .suspend = &rv770_suspend, |
||
585 | // .resume = &rv770_resume, |
||
586 | .cp_commit = &r600_cp_commit, |
||
587 | .asic_reset = &r600_asic_reset, |
||
588 | .vga_set_state = &r600_vga_set_state, |
||
589 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
||
590 | .gart_set_page = &rs600_gart_set_page, |
||
591 | .ring_test = &r600_ring_test, |
||
2004 | serge | 592 | .ring_ib_execute = &r600_ring_ib_execute, |
593 | .irq_set = &r600_irq_set, |
||
594 | .irq_process = &r600_irq_process, |
||
1963 | serge | 595 | .fence_ring_emit = &r600_fence_ring_emit, |
596 | // .cs_parse = &r600_cs_parse, |
||
597 | // .copy_blit = &r600_copy_blit, |
||
598 | // .copy_dma = &r600_copy_blit, |
||
599 | // .copy = &r600_copy_blit, |
||
600 | .get_engine_clock = &radeon_atom_get_engine_clock, |
||
601 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
602 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
603 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
604 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
||
605 | .set_pcie_lanes = NULL, |
||
606 | .set_clock_gating = &radeon_atom_set_clock_gating, |
||
607 | .set_surface_reg = r600_set_surface_reg, |
||
608 | .clear_surface_reg = r600_clear_surface_reg, |
||
609 | .bandwidth_update = &rv515_bandwidth_update, |
||
610 | .hpd_init = &r600_hpd_init, |
||
611 | .hpd_fini = &r600_hpd_fini, |
||
612 | .hpd_sense = &r600_hpd_sense, |
||
613 | .hpd_set_polarity = &r600_hpd_set_polarity, |
||
614 | }; |
||
1986 | serge | 615 | |
1963 | serge | 616 | static struct radeon_asic evergreen_asic = { |
617 | .init = &evergreen_init, |
||
618 | // .fini = &evergreen_fini, |
||
619 | // .suspend = &evergreen_suspend, |
||
620 | // .resume = &evergreen_resume, |
||
1986 | serge | 621 | .cp_commit = &r600_cp_commit, |
1963 | serge | 622 | .asic_reset = &evergreen_asic_reset, |
623 | .vga_set_state = &r600_vga_set_state, |
||
1986 | serge | 624 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1963 | serge | 625 | .gart_set_page = &rs600_gart_set_page, |
1986 | serge | 626 | .ring_test = &r600_ring_test, |
627 | // .ring_ib_execute = &r600_ring_ib_execute, |
||
628 | // .irq_set = &r600_irq_set, |
||
629 | // .irq_process = &r600_irq_process, |
||
630 | .fence_ring_emit = &r600_fence_ring_emit, |
||
631 | // .cs_parse = &r600_cs_parse, |
||
632 | // .copy_blit = &r600_copy_blit, |
||
633 | // .copy_dma = &r600_copy_blit, |
||
634 | // .copy = &r600_copy_blit, |
||
635 | .get_engine_clock = &radeon_atom_get_engine_clock, |
||
636 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
637 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
638 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
639 | .get_pcie_lanes = &r600_get_pcie_lanes, |
||
640 | .set_pcie_lanes = &r600_set_pcie_lanes, |
||
641 | .set_clock_gating = NULL, |
||
642 | .set_surface_reg = r600_set_surface_reg, |
||
643 | .clear_surface_reg = r600_clear_surface_reg, |
||
644 | .bandwidth_update = &evergreen_bandwidth_update, |
||
645 | |||
646 | }; |
||
1990 | serge | 647 | |
1986 | serge | 648 | static struct radeon_asic sumo_asic = { |
649 | .init = &evergreen_init, |
||
1990 | serge | 650 | // .fini = &evergreen_fini, |
651 | // .suspend = &evergreen_suspend, |
||
652 | // .resume = &evergreen_resume, |
||
1986 | serge | 653 | .cp_commit = &r600_cp_commit, |
654 | .asic_reset = &evergreen_asic_reset, |
||
655 | .vga_set_state = &r600_vga_set_state, |
||
656 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
||
657 | .gart_set_page = &rs600_gart_set_page, |
||
658 | .ring_test = &r600_ring_test, |
||
1990 | serge | 659 | // .ring_ib_execute = &r600_ring_ib_execute, |
660 | // .irq_set = &r600_irq_set, |
||
661 | // .irq_process = &r600_irq_process, |
||
1986 | serge | 662 | .fence_ring_emit = &r600_fence_ring_emit, |
1990 | serge | 663 | // .cs_parse = &r600_cs_parse, |
664 | // .copy_blit = &r600_copy_blit, |
||
665 | // .copy_dma = &r600_copy_blit, |
||
666 | // .copy = &r600_copy_blit, |
||
1986 | serge | 667 | .get_engine_clock = &radeon_atom_get_engine_clock, |
668 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
669 | .get_memory_clock = NULL, |
||
670 | .set_memory_clock = NULL, |
||
671 | .get_pcie_lanes = NULL, |
||
672 | .set_pcie_lanes = NULL, |
||
673 | .set_clock_gating = NULL, |
||
674 | .set_surface_reg = r600_set_surface_reg, |
||
675 | .clear_surface_reg = r600_clear_surface_reg, |
||
676 | .bandwidth_update = &evergreen_bandwidth_update, |
||
677 | }; |
||
678 | |||
1990 | serge | 679 | |
1986 | serge | 680 | static struct radeon_asic btc_asic = { |
681 | .init = &evergreen_init, |
||
1990 | serge | 682 | // .fini = &evergreen_fini, |
683 | // .suspend = &evergreen_suspend, |
||
684 | // .resume = &evergreen_resume, |
||
1986 | serge | 685 | .cp_commit = &r600_cp_commit, |
686 | .asic_reset = &evergreen_asic_reset, |
||
687 | .vga_set_state = &r600_vga_set_state, |
||
688 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
||
689 | .gart_set_page = &rs600_gart_set_page, |
||
1990 | serge | 690 | .ring_test = &r600_ring_test, |
1963 | serge | 691 | // .ring_ib_execute = &r600_ring_ib_execute, |
692 | // .irq_set = &r600_irq_set, |
||
693 | // .irq_process = &r600_irq_process, |
||
694 | .fence_ring_emit = &r600_fence_ring_emit, |
||
1990 | serge | 695 | // .cs_parse = &r600_cs_parse, |
696 | // .copy_blit = &r600_copy_blit, |
||
697 | // .copy_dma = &r600_copy_blit, |
||
698 | // .copy = &r600_copy_blit, |
||
1986 | serge | 699 | .get_engine_clock = &radeon_atom_get_engine_clock, |
700 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
701 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
702 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
703 | .get_pcie_lanes = NULL, |
||
704 | .set_pcie_lanes = NULL, |
||
705 | .set_clock_gating = NULL, |
||
706 | .set_surface_reg = r600_set_surface_reg, |
||
707 | .clear_surface_reg = r600_clear_surface_reg, |
||
708 | .bandwidth_update = &evergreen_bandwidth_update, |
||
2004 | serge | 709 | .hpd_init = &evergreen_hpd_init, |
710 | .hpd_sense = &evergreen_hpd_sense, |
||
1986 | serge | 711 | }; |
712 | |||
713 | static struct radeon_asic cayman_asic = { |
||
714 | .init = &cayman_init, |
||
2004 | serge | 715 | // .fini = &evergreen_fini, |
716 | // .suspend = &evergreen_suspend, |
||
717 | // .resume = &evergreen_resume, |
||
1986 | serge | 718 | .cp_commit = &r600_cp_commit, |
719 | .asic_reset = &cayman_asic_reset, |
||
720 | .vga_set_state = &r600_vga_set_state, |
||
721 | .gart_tlb_flush = &cayman_pcie_gart_tlb_flush, |
||
722 | .gart_set_page = &rs600_gart_set_page, |
||
723 | .ring_test = &r600_ring_test, |
||
2004 | serge | 724 | // .ring_ib_execute = &r600_ring_ib_execute, |
725 | // .irq_set = &r600_irq_set, |
||
726 | // .irq_process = &r600_irq_process, |
||
1986 | serge | 727 | .fence_ring_emit = &r600_fence_ring_emit, |
1963 | serge | 728 | // .cs_parse = &r600_cs_parse, |
729 | // .copy_blit = &r600_copy_blit, |
||
730 | // .copy_dma = &r600_copy_blit, |
||
731 | // .copy = &r600_copy_blit, |
||
732 | .get_engine_clock = &radeon_atom_get_engine_clock, |
||
733 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
734 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
735 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
2004 | serge | 736 | .get_pcie_lanes = NULL, |
1963 | serge | 737 | .set_pcie_lanes = NULL, |
738 | .set_clock_gating = NULL, |
||
739 | .set_surface_reg = r600_set_surface_reg, |
||
740 | .clear_surface_reg = r600_clear_surface_reg, |
||
741 | .bandwidth_update = &evergreen_bandwidth_update, |
||
742 | }; |
||
743 | |||
744 | int radeon_asic_init(struct radeon_device *rdev) |
||
745 | { |
||
746 | radeon_register_accessor_init(rdev); |
||
1986 | serge | 747 | |
748 | /* set the number of crtcs */ |
||
749 | if (rdev->flags & RADEON_SINGLE_CRTC) |
||
750 | rdev->num_crtc = 1; |
||
751 | else |
||
752 | rdev->num_crtc = 2; |
||
753 | |||
1963 | serge | 754 | switch (rdev->family) { |
755 | case CHIP_R100: |
||
756 | case CHIP_RV100: |
||
757 | case CHIP_RS100: |
||
758 | case CHIP_RV200: |
||
759 | case CHIP_RS200: |
||
760 | rdev->asic = &r100_asic; |
||
761 | break; |
||
762 | case CHIP_R200: |
||
763 | case CHIP_RV250: |
||
764 | case CHIP_RS300: |
||
765 | case CHIP_RV280: |
||
766 | rdev->asic = &r200_asic; |
||
767 | break; |
||
768 | case CHIP_R300: |
||
769 | case CHIP_R350: |
||
770 | case CHIP_RV350: |
||
771 | case CHIP_RV380: |
||
772 | if (rdev->flags & RADEON_IS_PCIE) |
||
773 | rdev->asic = &r300_asic_pcie; |
||
774 | else |
||
775 | rdev->asic = &r300_asic; |
||
776 | break; |
||
777 | case CHIP_R420: |
||
778 | case CHIP_R423: |
||
779 | case CHIP_RV410: |
||
780 | rdev->asic = &r420_asic; |
||
781 | /* handle macs */ |
||
782 | if (rdev->bios == NULL) { |
||
783 | rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock; |
||
784 | rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock; |
||
785 | rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock; |
||
786 | rdev->asic->set_memory_clock = NULL; |
||
787 | } |
||
788 | break; |
||
789 | case CHIP_RS400: |
||
790 | case CHIP_RS480: |
||
791 | rdev->asic = &rs400_asic; |
||
792 | break; |
||
793 | case CHIP_RS600: |
||
794 | rdev->asic = &rs600_asic; |
||
795 | break; |
||
796 | case CHIP_RS690: |
||
797 | case CHIP_RS740: |
||
798 | rdev->asic = &rs690_asic; |
||
799 | break; |
||
800 | case CHIP_RV515: |
||
801 | rdev->asic = &rv515_asic; |
||
802 | break; |
||
803 | case CHIP_R520: |
||
804 | case CHIP_RV530: |
||
805 | case CHIP_RV560: |
||
806 | case CHIP_RV570: |
||
807 | case CHIP_R580: |
||
808 | rdev->asic = &r520_asic; |
||
809 | break; |
||
810 | case CHIP_R600: |
||
811 | case CHIP_RV610: |
||
812 | case CHIP_RV630: |
||
813 | case CHIP_RV620: |
||
814 | case CHIP_RV635: |
||
815 | case CHIP_RV670: |
||
816 | rdev->asic = &r600_asic; |
||
817 | break; |
||
818 | case CHIP_RS780: |
||
819 | case CHIP_RS880: |
||
820 | rdev->asic = &rs780_asic; |
||
821 | break; |
||
822 | case CHIP_RV770: |
||
823 | case CHIP_RV730: |
||
824 | case CHIP_RV710: |
||
825 | case CHIP_RV740: |
||
826 | rdev->asic = &rv770_asic; |
||
827 | break; |
||
1986 | serge | 828 | case CHIP_CEDAR: |
829 | case CHIP_REDWOOD: |
||
830 | case CHIP_JUNIPER: |
||
831 | case CHIP_CYPRESS: |
||
832 | case CHIP_HEMLOCK: |
||
833 | /* set num crtcs */ |
||
834 | if (rdev->family == CHIP_CEDAR) |
||
835 | rdev->num_crtc = 4; |
||
836 | else |
||
837 | rdev->num_crtc = 6; |
||
838 | rdev->asic = &evergreen_asic; |
||
839 | break; |
||
1990 | serge | 840 | case CHIP_PALM: |
841 | case CHIP_SUMO: |
||
842 | case CHIP_SUMO2: |
||
843 | rdev->asic = &sumo_asic; |
||
844 | break; |
||
845 | case CHIP_BARTS: |
||
846 | case CHIP_TURKS: |
||
847 | case CHIP_CAICOS: |
||
848 | /* set num crtcs */ |
||
849 | if (rdev->family == CHIP_CAICOS) |
||
850 | rdev->num_crtc = 4; |
||
851 | else |
||
852 | rdev->num_crtc = 6; |
||
853 | rdev->asic = &btc_asic; |
||
854 | break; |
||
2004 | serge | 855 | case CHIP_CAYMAN: |
856 | rdev->asic = &cayman_asic; |
||
857 | /* set num crtcs */ |
||
858 | rdev->num_crtc = 6; |
||
859 | break; |
||
1963 | serge | 860 | default: |
861 | /* FIXME: not supported yet */ |
||
862 | return -EINVAL; |
||
863 | } |
||
864 | |||
865 | if (rdev->flags & RADEON_IS_IGP) { |
||
866 | rdev->asic->get_memory_clock = NULL; |
||
867 | rdev->asic->set_memory_clock = NULL; |
||
868 | } |
||
869 | |||
870 | return 0; |
||
871 | }=>> |
||
872 |