Subversion Repositories Kolibri OS

/*

 * Copyright 2008 Advanced Micro Devices, Inc.

 * Copyright 2008 Red Hat Inc.

 * Copyright 2009 Jerome Glisse.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Dave Airlie

 *          Alex Deucher

 *          Jerome Glisse

 */

#ifndef __RADEON_H__

#define __RADEON_H__

/* TODO: Here are things that needs to be done :

 *	- surface allocator & initializer : (bit like scratch reg) should

 *	  initialize HDP_ stuff on RS600, R600, R700 hw, well anythings

 *	  related to surface

 *	- WB : write back stuff (do it bit like scratch reg things)

 *	- Vblank : look at Jesse's rework and what we should do

 *	- r600/r700: gart & cp

 *	- cs : clean cs ioctl use bitmap & things like that.

 *	- power management stuff

 *	- Barrier in gart code

 *	- Unmappabled vram ?

 *	- TESTING, TESTING, TESTING

 */

/* Initialization path:

 *  We expect that acceleration initialization might fail for various

 *  reasons even thought we work hard to make it works on most

 *  configurations. In order to still have a working userspace in such

 *  situation the init path must succeed up to the memory controller

 *  initialization point. Failure before this point are considered as

 *  fatal error. Here is the init callchain :

 *      radeon_device_init  perform common structure, mutex initialization

 *      asic_init           setup the GPU memory layout and perform all

 *                          one time initialization (failure in this

 *                          function are considered fatal)

 *      asic_startup        setup the GPU acceleration, in order to

 *                          follow guideline the first thing this

 *                          function should do is setting the GPU

 *                          memory controller (only MC setup failure

 *                          are considered as fatal)

 */

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include "radeon_family.h"

#include "radeon_mode.h"

#include "radeon_reg.h"

#include 

/*

 * Modules parameters.

 */

extern int radeon_no_wb;

extern int radeon_modeset;

extern int radeon_dynclks;

extern int radeon_r4xx_atom;

extern int radeon_agpmode;

extern int radeon_vram_limit;

extern int radeon_gart_size;

extern int radeon_benchmarking;

extern int radeon_testing;

extern int radeon_connector_table;

extern int radeon_tv;

extern int radeon_audio;

extern int radeon_disp_priority;

extern int radeon_hw_i2c;

extern int radeon_pcie_gen2;

extern int radeon_msi;

extern int radeon_lockup_timeout;

typedef struct pm_message {

    int event;

} pm_message_t;

typedef struct

{

  int width;

  int height;

  int bpp;

  int freq;

}videomode_t;

static inline u32 ioread32(const volatile void __iomem *addr)

{

    return in32((u32)addr);

}

static inline void iowrite32(uint32_t b, volatile void __iomem *addr)

{

    out32((u32)addr, b);

}

//struct __wait_queue_head {

//        spinlock_t lock;

//        struct list_head task_list;

//};

//typedef struct __wait_queue_head wait_queue_head_t;

/*

 * Copy from radeon_drv.h so we don't have to include both and have conflicting

 * symbol;

 */

#define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */

#define RADEON_FENCE_JIFFIES_TIMEOUT	(HZ / 2)

/* RADEON_IB_POOL_SIZE must be a power of 2 */

#define RADEON_IB_POOL_SIZE             16

#define RADEON_DEBUGFS_MAX_COMPONENTS	32

#define RADEONFB_CONN_LIMIT             4

#define RADEON_BIOS_NUM_SCRATCH		8

/* max number of rings */

#define RADEON_NUM_RINGS 3

/* fence seq are set to this number when signaled */

#define RADEON_FENCE_SIGNALED_SEQ		0LL

/* internal ring indices */

/* r1xx+ has gfx CP ring */

#define RADEON_RING_TYPE_GFX_INDEX  0

/* cayman has 2 compute CP rings */

#define CAYMAN_RING_TYPE_CP1_INDEX 1

#define CAYMAN_RING_TYPE_CP2_INDEX 2

/* hardcode those limit for now */

#define RADEON_VA_IB_OFFSET			(1 << 20)

#define RADEON_VA_RESERVED_SIZE		(8 << 20)

#define RADEON_IB_VM_MAX_SIZE		(64 << 10)

/*

 * Errata workarounds.

 */

enum radeon_pll_errata {

    CHIP_ERRATA_R300_CG             = 0x00000001,

    CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,

    CHIP_ERRATA_PLL_DELAY           = 0x00000004

};

struct radeon_device;

/*

 * BIOS.

 */

bool radeon_get_bios(struct radeon_device *rdev);

/*

 * Dummy page

 */

struct radeon_dummy_page {

	struct page	*page;

	dma_addr_t	addr;

};

int radeon_dummy_page_init(struct radeon_device *rdev);

void radeon_dummy_page_fini(struct radeon_device *rdev);

/*

 * Clocks

 */

struct radeon_clock {

	struct radeon_pll p1pll;

	struct radeon_pll p2pll;

	struct radeon_pll dcpll;

	struct radeon_pll spll;

	struct radeon_pll mpll;

	/* 10 Khz units */

	uint32_t default_mclk;

	uint32_t default_sclk;

	uint32_t default_dispclk;

	uint32_t dp_extclk;

	uint32_t max_pixel_clock;

};

/*

 * Power management

 */

int radeon_pm_init(struct radeon_device *rdev);

void radeon_pm_fini(struct radeon_device *rdev);

void radeon_pm_compute_clocks(struct radeon_device *rdev);

void radeon_pm_suspend(struct radeon_device *rdev);

void radeon_pm_resume(struct radeon_device *rdev);

void radeon_combios_get_power_modes(struct radeon_device *rdev);

void radeon_atombios_get_power_modes(struct radeon_device *rdev);

void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);

void rs690_pm_info(struct radeon_device *rdev);

extern int rv6xx_get_temp(struct radeon_device *rdev);

extern int rv770_get_temp(struct radeon_device *rdev);

extern int evergreen_get_temp(struct radeon_device *rdev);

extern int sumo_get_temp(struct radeon_device *rdev);

extern int si_get_temp(struct radeon_device *rdev);

extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,

				    unsigned *bankh, unsigned *mtaspect,

				    unsigned *tile_split);

/*

 * Fences.

 */

struct radeon_fence_driver {

	uint32_t			scratch_reg;

	uint64_t			gpu_addr;

	volatile uint32_t		*cpu_addr;

	/* sync_seq is protected by ring emission lock */

	uint64_t			sync_seq[RADEON_NUM_RINGS];

	atomic64_t			last_seq;

	unsigned long			last_activity;

	bool				initialized;

};

struct radeon_fence {

    struct radeon_device   *rdev;

    struct kref             kref;

	/* protected by radeon_fence.lock */

	uint64_t			seq;

	/* RB, DMA, etc. */

	unsigned			ring;

};

int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);

int radeon_fence_driver_init(struct radeon_device *rdev);

void radeon_fence_driver_fini(struct radeon_device *rdev);

int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);

void radeon_fence_process(struct radeon_device *rdev, int ring);

bool radeon_fence_signaled(struct radeon_fence *fence);

int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);

int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);

void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);

int radeon_fence_wait_any(struct radeon_device *rdev,

			  struct radeon_fence **fences,

			  bool intr);

struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);

void radeon_fence_unref(struct radeon_fence **fence);

unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);

bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);

void radeon_fence_note_sync(struct radeon_fence *fence, int ring);

static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,

						      struct radeon_fence *b)

{

	if (!a) {

		return b;

	}

	if (!b) {

		return a;

	}

	BUG_ON(a->ring != b->ring);

	if (a->seq > b->seq) {

		return a;

	} else {

		return b;

	}

}

static inline bool radeon_fence_is_earlier(struct radeon_fence *a,

					   struct radeon_fence *b)

{

	if (!a) {

		return false;

	}

	if (!b) {

		return true;

	}

	BUG_ON(a->ring != b->ring);

	return a->seq < b->seq;

}

/*

 * Tiling registers

 */

struct radeon_surface_reg {

	struct radeon_bo *bo;

};

#define RADEON_GEM_MAX_SURFACES 8

/*

 * TTM.

 */

struct radeon_mman {

	struct ttm_bo_global_ref        bo_global_ref;

//	struct drm_global_reference	mem_global_ref;

	struct ttm_bo_device		bdev;

	bool				mem_global_referenced;

	bool				initialized;

};

/* bo virtual address in a specific vm */

struct radeon_bo_va {

	/* protected by bo being reserved */

	struct list_head		bo_list;

	uint64_t			soffset;

	uint64_t			eoffset;

	uint32_t			flags;

	bool				valid;

	unsigned			ref_count;

	/* protected by vm mutex */

	struct list_head		vm_list;

	/* constant after initialization */

	struct radeon_vm		*vm;

	struct radeon_bo		*bo;

};

struct radeon_bo {

	/* Protected by gem.mutex */

	struct list_head		list;

	/* Protected by tbo.reserved */

	u32				placements[3];

	struct ttm_placement		placement;

	struct ttm_buffer_object	tbo;

	struct ttm_bo_kmap_obj		kmap;

    unsigned                    pin_count;

    void                       *kptr;

    void                       *uptr;

    u32                         cpu_addr;

    u32                         tiling_flags;

    u32                         pitch;

    int                         surface_reg;

	/* list of all virtual address to which this bo

	 * is associated to

	 */

	struct list_head		va;

	/* Constant after initialization */

	struct radeon_device		*rdev;

	struct drm_gem_object		gem_base;

    u32                          domain;

	int vmapping_count;

};

#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)

struct radeon_bo_list {

	struct radeon_bo	*bo;

	uint64_t		gpu_offset;

	unsigned		rdomain;

	unsigned		wdomain;

	u32			tiling_flags;

};

/* sub-allocation manager, it has to be protected by another lock.

 * By conception this is an helper for other part of the driver

 * like the indirect buffer or semaphore, which both have their

 * locking.

 *

 * Principe is simple, we keep a list of sub allocation in offset

 * order (first entry has offset == 0, last entry has the highest

 * offset).

 *

 * When allocating new object we first check if there is room at

 * the end total_size - (last_object_offset + last_object_size) >=

 * alloc_size. If so we allocate new object there.

 *

 * When there is not enough room at the end, we start waiting for

 * each sub object until we reach object_offset+object_size >=

 * alloc_size, this object then become the sub object we return.

 *

 * Alignment can't be bigger than page size.

 *

 * Hole are not considered for allocation to keep things simple.

 * Assumption is that there won't be hole (all object on same

 * alignment).

 */

struct radeon_sa_manager {

	wait_queue_head_t	wq;

	struct radeon_bo	*bo;

	struct list_head	*hole;

	struct list_head	flist[RADEON_NUM_RINGS];

	struct list_head	olist;

	unsigned		size;

	uint64_t		gpu_addr;

	void			*cpu_ptr;

	uint32_t		domain;

};

struct radeon_sa_bo;

/* sub-allocation buffer */

struct radeon_sa_bo {

	struct list_head		olist;

	struct list_head		flist;

	struct radeon_sa_manager	*manager;

	unsigned			soffset;

	unsigned			eoffset;

	struct radeon_fence		*fence;

};

/*

 * GEM objects.

 */

struct radeon_gem {

	struct mutex		mutex;

	struct list_head	objects;

};

int radeon_gem_init(struct radeon_device *rdev);

void radeon_gem_fini(struct radeon_device *rdev);

int radeon_gem_object_create(struct radeon_device *rdev, int size,

			     int alignment, int initial_domain,

			     bool discardable, bool kernel,

			     struct drm_gem_object **obj);

int radeon_mode_dumb_create(struct drm_file *file_priv,

			    struct drm_device *dev,

			    struct drm_mode_create_dumb *args);

int radeon_mode_dumb_mmap(struct drm_file *filp,

			  struct drm_device *dev,

			  uint32_t handle, uint64_t *offset_p);

int radeon_mode_dumb_destroy(struct drm_file *file_priv,

			     struct drm_device *dev,

			     uint32_t handle);

/*

 * Semaphores.

 */

/* everything here is constant */

struct radeon_semaphore {

	struct radeon_sa_bo		*sa_bo;

	signed				waiters;

	uint64_t			gpu_addr;

};

int radeon_semaphore_create(struct radeon_device *rdev,

			    struct radeon_semaphore **semaphore);

void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,

				  struct radeon_semaphore *semaphore);

void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,

				struct radeon_semaphore *semaphore);

int radeon_semaphore_sync_rings(struct radeon_device *rdev,

				struct radeon_semaphore *semaphore,

				int signaler, int waiter);

void radeon_semaphore_free(struct radeon_device *rdev,

			   struct radeon_semaphore **semaphore,

			   struct radeon_fence *fence);

/*

 * GART structures, functions & helpers

 */

struct radeon_mc;

#define RADEON_GPU_PAGE_SIZE 4096

#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)

#define RADEON_GPU_PAGE_SHIFT 12

#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)

struct radeon_gart {

    dma_addr_t          table_addr;

	struct radeon_bo		*robj;

	void				*ptr;

    unsigned            num_gpu_pages;

    unsigned            num_cpu_pages;

    unsigned            table_size;

    struct page         **pages;

    dma_addr_t          *pages_addr;

    bool                ready;

};

int radeon_gart_table_ram_alloc(struct radeon_device *rdev);

void radeon_gart_table_ram_free(struct radeon_device *rdev);

int radeon_gart_table_vram_alloc(struct radeon_device *rdev);

void radeon_gart_table_vram_free(struct radeon_device *rdev);

int radeon_gart_table_vram_pin(struct radeon_device *rdev);

void radeon_gart_table_vram_unpin(struct radeon_device *rdev);

int radeon_gart_init(struct radeon_device *rdev);

void radeon_gart_fini(struct radeon_device *rdev);

void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,

			int pages);

int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,

             int pages, u32 *pagelist,

		     dma_addr_t *dma_addr);

void radeon_gart_restore(struct radeon_device *rdev);

/*

 * GPU MC structures, functions & helpers

 */

struct radeon_mc {

    resource_size_t     aper_size;

    resource_size_t     aper_base;

    resource_size_t     agp_base;

	/* for some chips with <= 32MB we need to lie

	 * about vram size near mc fb location */

	u64			mc_vram_size;

	u64			visible_vram_size;

	u64			gtt_size;

	u64			gtt_start;

	u64			gtt_end;

	u64			vram_start;

	u64			vram_end;

    unsigned            vram_width;

	u64			real_vram_size;

    int                 vram_mtrr;

    bool                vram_is_ddr;

	bool                    igp_sideport_enabled;

	u64                     gtt_base_align;

};

bool radeon_combios_sideport_present(struct radeon_device *rdev);

bool radeon_atombios_sideport_present(struct radeon_device *rdev);

/*

 * GPU scratch registers structures, functions & helpers

 */

struct radeon_scratch {

    unsigned        num_reg;

	uint32_t                reg_base;

    bool            free[32];

    uint32_t        reg[32];

};

int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);

void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);

/*

 * IRQS.

 */

struct r500_irq_stat_regs {

	u32 disp_int;

	u32 hdmi0_status;

};

struct r600_irq_stat_regs {

	u32 disp_int;

	u32 disp_int_cont;

	u32 disp_int_cont2;

	u32 d1grph_int;

	u32 d2grph_int;

	u32 hdmi0_status;

	u32 hdmi1_status;

};

struct evergreen_irq_stat_regs {

	u32 disp_int;

	u32 disp_int_cont;

	u32 disp_int_cont2;

	u32 disp_int_cont3;

	u32 disp_int_cont4;

	u32 disp_int_cont5;

	u32 d1grph_int;

	u32 d2grph_int;

	u32 d3grph_int;

	u32 d4grph_int;

	u32 d5grph_int;

	u32 d6grph_int;

	u32 afmt_status1;

	u32 afmt_status2;

	u32 afmt_status3;

	u32 afmt_status4;

	u32 afmt_status5;

	u32 afmt_status6;

};

union radeon_irq_stat_regs {

	struct r500_irq_stat_regs r500;

	struct r600_irq_stat_regs r600;

	struct evergreen_irq_stat_regs evergreen;

};

#define RADEON_MAX_HPD_PINS 6

#define RADEON_MAX_CRTCS 6

#define RADEON_MAX_AFMT_BLOCKS 6

struct radeon_irq {

	bool		installed;

	spinlock_t			lock;

	atomic_t			ring_int[RADEON_NUM_RINGS];

	bool				crtc_vblank_int[RADEON_MAX_CRTCS];

	atomic_t			pflip[RADEON_MAX_CRTCS];

    wait_queue_head_t   vblank_queue;

	bool				hpd[RADEON_MAX_HPD_PINS];

	bool				afmt[RADEON_MAX_AFMT_BLOCKS];

	union radeon_irq_stat_regs stat_regs;

};

int radeon_irq_kms_init(struct radeon_device *rdev);

void radeon_irq_kms_fini(struct radeon_device *rdev);

void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);

void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);

void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);

void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);

void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);

void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);

void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);

void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);

/*

 * CP & rings.

 */

struct radeon_ib {

	struct radeon_sa_bo		*sa_bo;

	uint32_t		length_dw;

    uint64_t            gpu_addr;

	uint32_t		*ptr;

	int				ring;

	struct radeon_fence	*fence;

	struct radeon_vm		*vm;

	bool			is_const_ib;

	struct radeon_fence		*sync_to[RADEON_NUM_RINGS];

	struct radeon_semaphore		*semaphore;

};

struct radeon_ring {

	struct radeon_bo	*ring_obj;

	volatile uint32_t	*ring;

    unsigned            rptr;

	unsigned		rptr_offs;

	unsigned		rptr_reg;

	unsigned		rptr_save_reg;

	u64			next_rptr_gpu_addr;

	volatile u32		*next_rptr_cpu_addr;

    unsigned            wptr;

    unsigned            wptr_old;

	unsigned		wptr_reg;

    unsigned            ring_size;

    unsigned            ring_free_dw;

    int                 count_dw;

	unsigned long		last_activity;

	unsigned		last_rptr;

    uint64_t            gpu_addr;

    uint32_t            align_mask;

    uint32_t            ptr_mask;

    bool                ready;

	u32			ptr_reg_shift;

	u32			ptr_reg_mask;

	u32			nop;

	u32			idx;

};

/*

 * VM

 */

/* maximum number of VMIDs */

#define RADEON_NUM_VM	16

/* defines number of bits in page table versus page directory,

 * a page is 4KB so we have 12 bits offset, 9 bits in the page

 * table and the remaining 19 bits are in the page directory */

#define RADEON_VM_BLOCK_SIZE   9

/* number of entries in page table */

#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)

struct radeon_vm {

	struct list_head		list;

	struct list_head		va;

	unsigned			id;

	/* contains the page directory */

	struct radeon_sa_bo		*page_directory;

	uint64_t			pd_gpu_addr;

	/* array of page tables, one for each page directory entry */

	struct radeon_sa_bo		**page_tables;

	struct mutex			mutex;

	/* last fence for cs using this vm */

	struct radeon_fence		*fence;

	/* last flush or NULL if we still need to flush */

	struct radeon_fence		*last_flush;

};

struct radeon_vm_manager {

	struct mutex			lock;

	struct list_head		lru_vm;

	struct radeon_fence		*active[RADEON_NUM_VM];

	struct radeon_sa_manager	sa_manager;

	uint32_t			max_pfn;

	/* number of VMIDs */

	unsigned			nvm;

	/* vram base address for page table entry  */

	u64				vram_base_offset;

	/* is vm enabled? */

	bool				enabled;

};

/*

 * file private structure

 */

struct radeon_fpriv {

	struct radeon_vm		vm;

};

/*

 * R6xx+ IH ring

 */

struct r600_ih {

	struct radeon_bo	*ring_obj;

	volatile uint32_t	*ring;

    unsigned            rptr;

    unsigned            ring_size;

    uint64_t            gpu_addr;

    uint32_t            ptr_mask;

	atomic_t		lock;

    bool                enabled;

};

struct r600_blit_cp_primitives {

	void (*set_render_target)(struct radeon_device *rdev, int format,

				  int w, int h, u64 gpu_addr);

	void (*cp_set_surface_sync)(struct radeon_device *rdev,

				    u32 sync_type, u32 size,

				    u64 mc_addr);

	void (*set_shaders)(struct radeon_device *rdev);

	void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);

	void (*set_tex_resource)(struct radeon_device *rdev,

				 int format, int w, int h, int pitch,

				 u64 gpu_addr, u32 size);

	void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,

			     int x2, int y2);

	void (*draw_auto)(struct radeon_device *rdev);

	void (*set_default_state)(struct radeon_device *rdev);

};

struct r600_blit {

	struct radeon_bo	*shader_obj;

	struct r600_blit_cp_primitives primitives;

	int max_dim;

	int ring_size_common;

	int ring_size_per_loop;

	u64 shader_gpu_addr;

	u32 vs_offset, ps_offset;

	u32 state_offset;

	u32 state_len;

};

/*

 * SI RLC stuff

 */

struct si_rlc {

	/* for power gating */

	struct radeon_bo	*save_restore_obj;

	uint64_t		save_restore_gpu_addr;

	/* for clear state */

	struct radeon_bo	*clear_state_obj;

	uint64_t		clear_state_gpu_addr;

};

int radeon_ib_get(struct radeon_device *rdev, int ring,

		  struct radeon_ib *ib, struct radeon_vm *vm,

		  unsigned size);

void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);

int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,

		       struct radeon_ib *const_ib);

int radeon_ib_pool_init(struct radeon_device *rdev);

void radeon_ib_pool_fini(struct radeon_device *rdev);

int radeon_ib_ring_tests(struct radeon_device *rdev);

/* Ring access between begin & end cannot sleep */

bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,

				      struct radeon_ring *ring);

void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);

int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);

int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);

void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);

void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);

void radeon_ring_undo(struct radeon_ring *ring);

void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);

int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);

void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);

void radeon_ring_lockup_update(struct radeon_ring *ring);

bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);

unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,

			    uint32_t **data);

int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,

			unsigned size, uint32_t *data);

int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,

		     unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,

		     u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);

void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);

/*

 * CS.

 */

struct radeon_cs_reloc {

//	struct drm_gem_object		*gobj;

	struct radeon_bo		*robj;

	struct radeon_bo_list		lobj;

    uint32_t                handle;

    uint32_t                flags;

};

struct radeon_cs_chunk {

	uint32_t		chunk_id;

	uint32_t		length_dw;

	int kpage_idx[2];

	uint32_t                *kpage[2];

	uint32_t		*kdata;

	void __user *user_ptr;

	int last_copied_page;

	int last_page_index;

};

struct radeon_cs_parser {

	struct device		*dev;

	struct radeon_device	*rdev;

	struct drm_file		*filp;

	/* chunks */

	unsigned		nchunks;

	struct radeon_cs_chunk	*chunks;

	uint64_t		*chunks_array;

	/* IB */

	unsigned		idx;

	/* relocations */

	unsigned		nrelocs;

	struct radeon_cs_reloc	*relocs;

	struct radeon_cs_reloc	**relocs_ptr;

	struct list_head	validated;

	/* indices of various chunks */

	int			chunk_ib_idx;

	int			chunk_relocs_idx;

	int			chunk_flags_idx;

	int			chunk_const_ib_idx;

	struct radeon_ib	ib;

	struct radeon_ib	const_ib;

	void			*track;

	unsigned		family;

	int parser_error;

	u32			cs_flags;

	u32			ring;

	s32			priority;

};

extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);

extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);

struct radeon_cs_packet {

	unsigned	idx;

	unsigned	type;

	unsigned	reg;

	unsigned	opcode;

	int		count;

	unsigned	one_reg_wr;

};

typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,

				      struct radeon_cs_packet *pkt,

				      unsigned idx, unsigned reg);

typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,

				      struct radeon_cs_packet *pkt);

/*

 * AGP

 */

int radeon_agp_init(struct radeon_device *rdev);

void radeon_agp_resume(struct radeon_device *rdev);

void radeon_agp_suspend(struct radeon_device *rdev);

void radeon_agp_fini(struct radeon_device *rdev);

/*

 * Writeback

 */

struct radeon_wb {

	struct radeon_bo	*wb_obj;

	volatile uint32_t	*wb;

	uint64_t		gpu_addr;

	bool                    enabled;

	bool                    use_event;

};

#define RADEON_WB_SCRATCH_OFFSET 0

#define RADEON_WB_RING0_NEXT_RPTR 256

#define RADEON_WB_CP_RPTR_OFFSET 1024

#define RADEON_WB_CP1_RPTR_OFFSET 1280

#define RADEON_WB_CP2_RPTR_OFFSET 1536

#define R600_WB_IH_WPTR_OFFSET   2048

#define R600_WB_EVENT_OFFSET     3072

/**

 * struct radeon_pm - power management datas

 * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)

 * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)

 * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)

 * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)

 * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)

 * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)

 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)

 * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)

 * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)

 * @sclk:          	GPU clock Mhz (core bandwidth depends of this clock)

 * @needed_bandwidth:   current bandwidth needs

 *

 * It keeps track of various data needed to take powermanagement decision.

 * Bandwidth need is used to determine minimun clock of the GPU and memory.

 * Equation between gpu/memory clock and available bandwidth is hw dependent

 * (type of memory, bus size, efficiency, ...)

 */

enum radeon_pm_method {

	PM_METHOD_PROFILE,

	PM_METHOD_DYNPM,

};

enum radeon_dynpm_state {

	DYNPM_STATE_DISABLED,

	DYNPM_STATE_MINIMUM,

	DYNPM_STATE_PAUSED,

	DYNPM_STATE_ACTIVE,

	DYNPM_STATE_SUSPENDED,

};

enum radeon_dynpm_action {

	DYNPM_ACTION_NONE,

	DYNPM_ACTION_MINIMUM,

	DYNPM_ACTION_DOWNCLOCK,

	DYNPM_ACTION_UPCLOCK,

	DYNPM_ACTION_DEFAULT

};

enum radeon_voltage_type {

	VOLTAGE_NONE = 0,

	VOLTAGE_GPIO,

	VOLTAGE_VDDC,

	VOLTAGE_SW

};

enum radeon_pm_state_type {

	POWER_STATE_TYPE_DEFAULT,

	POWER_STATE_TYPE_POWERSAVE,

	POWER_STATE_TYPE_BATTERY,

	POWER_STATE_TYPE_BALANCED,

	POWER_STATE_TYPE_PERFORMANCE,

};

enum radeon_pm_profile_type {

	PM_PROFILE_DEFAULT,

	PM_PROFILE_AUTO,

	PM_PROFILE_LOW,

	PM_PROFILE_MID,

	PM_PROFILE_HIGH,

};

#define PM_PROFILE_DEFAULT_IDX 0

#define PM_PROFILE_LOW_SH_IDX  1

#define PM_PROFILE_MID_SH_IDX  2

#define PM_PROFILE_HIGH_SH_IDX 3

#define PM_PROFILE_LOW_MH_IDX  4

#define PM_PROFILE_MID_MH_IDX  5

#define PM_PROFILE_HIGH_MH_IDX 6

#define PM_PROFILE_MAX         7

struct radeon_pm_profile {

	int dpms_off_ps_idx;

	int dpms_on_ps_idx;

	int dpms_off_cm_idx;

	int dpms_on_cm_idx;

};

enum radeon_int_thermal_type {

	THERMAL_TYPE_NONE,

	THERMAL_TYPE_RV6XX,

	THERMAL_TYPE_RV770,

	THERMAL_TYPE_EVERGREEN,

	THERMAL_TYPE_SUMO,

	THERMAL_TYPE_NI,

	THERMAL_TYPE_SI,

};

struct radeon_voltage {

	enum radeon_voltage_type type;

	/* gpio voltage */

	struct radeon_gpio_rec gpio;

	u32 delay; /* delay in usec from voltage drop to sclk change */

	bool active_high; /* voltage drop is active when bit is high */

	/* VDDC voltage */

	u8 vddc_id; /* index into vddc voltage table */

	u8 vddci_id; /* index into vddci voltage table */

	bool vddci_enabled;

	/* r6xx+ sw */

	u16 voltage;

	/* evergreen+ vddci */

	u16 vddci;

};

/* clock mode flags */

#define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)

struct radeon_pm_clock_info {

	/* memory clock */

	u32 mclk;

	/* engine clock */

	u32 sclk;

	/* voltage info */

	struct radeon_voltage voltage;

	/* standardized clock flags */

	u32 flags;

};

/* state flags */

#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)

struct radeon_power_state {

	enum radeon_pm_state_type type;

	struct radeon_pm_clock_info *clock_info;

	/* number of valid clock modes in this power state */

	int num_clock_modes;

	struct radeon_pm_clock_info *default_clock_mode;

	/* standardized state flags */

	u32 flags;

	u32 misc; /* vbios specific flags */

	u32 misc2; /* vbios specific flags */

	int pcie_lanes; /* pcie lanes */

};

/*

 * Some modes are overclocked by very low value, accept them

 */

#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */

struct radeon_pm {

	struct mutex		mutex;

	/* write locked while reprogramming mclk */

	struct rw_semaphore	mclk_lock;

	u32			active_crtcs;

	int			active_crtc_count;

	int			req_vblank;

	bool			vblank_sync;

	fixed20_12		max_bandwidth;

	fixed20_12		igp_sideport_mclk;

	fixed20_12		igp_system_mclk;

	fixed20_12		igp_ht_link_clk;

	fixed20_12		igp_ht_link_width;

	fixed20_12		k8_bandwidth;

	fixed20_12		sideport_bandwidth;

	fixed20_12		ht_bandwidth;

	fixed20_12		core_bandwidth;

	fixed20_12		sclk;

	fixed20_12		mclk;

	fixed20_12		needed_bandwidth;

	struct radeon_power_state *power_state;

	/* number of valid power states */

	int                     num_power_states;

	int                     current_power_state_index;

	int                     current_clock_mode_index;

	int                     requested_power_state_index;

	int                     requested_clock_mode_index;

	int                     default_power_state_index;

	u32                     current_sclk;

	u32                     current_mclk;