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/*

 * Copyright 2008 Advanced Micro Devices, Inc.

 * Copyright 2008 Red Hat Inc.

 * Copyright 2009 Jerome Glisse.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Dave Airlie

 *          Alex Deucher

 *          Jerome Glisse

 */

#ifndef __RADEON_H__

#define __RADEON_H__

/* TODO: Here are things that needs to be done :

 *	- surface allocator & initializer : (bit like scratch reg) should

 *	  initialize HDP_ stuff on RS600, R600, R700 hw, well anythings

 *	  related to surface

 *	- WB : write back stuff (do it bit like scratch reg things)

 *	- Vblank : look at Jesse's rework and what we should do

 *	- r600/r700: gart & cp

 *	- cs : clean cs ioctl use bitmap & things like that.

 *	- power management stuff

 *	- Barrier in gart code

 *	- Unmappabled vram ?

 *	- TESTING, TESTING, TESTING

 */

/* Initialization path:

 *  We expect that acceleration initialization might fail for various

 *  reasons even thought we work hard to make it works on most

 *  configurations. In order to still have a working userspace in such

 *  situation the init path must succeed up to the memory controller

 *  initialization point. Failure before this point are considered as

 *  fatal error. Here is the init callchain :

 *      radeon_device_init  perform common structure, mutex initialization

 *      asic_init           setup the GPU memory layout and perform all

 *                          one time initialization (failure in this

 *                          function are considered fatal)

 *      asic_startup        setup the GPU acceleration, in order to

 *                          follow guideline the first thing this

 *                          function should do is setting the GPU

 *                          memory controller (only MC setup failure

 *                          are considered as fatal)

 */

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include 

#include "drm_edid.h"

#include "radeon_family.h"

#include "radeon_mode.h"

#include "radeon_reg.h"

#include 

extern unsigned long volatile jiffies;

/*

 * Modules parameters.

 */

extern int radeon_no_wb;

extern int radeon_modeset;

extern int radeon_dynclks;

extern int radeon_r4xx_atom;

extern int radeon_agpmode;

extern int radeon_vram_limit;

extern int radeon_gart_size;

extern int radeon_benchmarking;

extern int radeon_testing;

extern int radeon_connector_table;

extern int radeon_tv;

extern int radeon_audio;

extern int radeon_disp_priority;

extern int radeon_hw_i2c;

extern int radeon_pcie_gen2;

typedef struct pm_message {

    int event;

} pm_message_t;

typedef struct

{

  int width;

  int height;

  int bpp;

  int freq;

}videomode_t;

static inline uint8_t __raw_readb(const volatile void __iomem *addr)

{

    return *(const volatile uint8_t __force *) addr;

}

static inline uint16_t __raw_readw(const volatile void __iomem *addr)

{

    return *(const volatile uint16_t __force *) addr;

}

static inline uint32_t __raw_readl(const volatile void __iomem *addr)

{

    return *(const volatile uint32_t __force *) addr;

}

#define readb __raw_readb

#define readw __raw_readw

#define readl __raw_readl

static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)

{

    *(volatile uint8_t __force *) addr = b;

}

static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)

{

    *(volatile uint16_t __force *) addr = b;

}

static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)

{

    *(volatile uint32_t __force *) addr = b;

}

static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)

{

        *(volatile __u64 *)addr = b;

}

#define writeb __raw_writeb

#define writew __raw_writew

#define writel __raw_writel

#define writeq __raw_writeq

static inline u32 ioread32(const volatile void __iomem *addr)

{

    return in32((u32)addr);

}

static inline void iowrite32(uint32_t b, volatile void __iomem *addr)

{

    out32((u32)addr, b);

}

struct __wait_queue_head {

        spinlock_t lock;

        struct list_head task_list;

};

typedef struct __wait_queue_head wait_queue_head_t;

/*

 * Copy from radeon_drv.h so we don't have to include both and have conflicting

 * symbol;

 */

#define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */

#define RADEON_FENCE_JIFFIES_TIMEOUT	(HZ / 2)

/* RADEON_IB_POOL_SIZE must be a power of 2 */

#define RADEON_IB_POOL_SIZE             16

#define RADEON_DEBUGFS_MAX_NUM_FILES	32

#define RADEONFB_CONN_LIMIT             4

#define RADEON_BIOS_NUM_SCRATCH		8

/*

 * Errata workarounds.

 */

enum radeon_pll_errata {

    CHIP_ERRATA_R300_CG             = 0x00000001,

    CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,

    CHIP_ERRATA_PLL_DELAY           = 0x00000004

};

struct radeon_device;

/*

 * BIOS.

 */

#define ATRM_BIOS_PAGE 4096

#if defined(CONFIG_VGA_SWITCHEROO)

bool radeon_atrm_supported(struct pci_dev *pdev);

int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);

#else

static inline bool radeon_atrm_supported(struct pci_dev *pdev)

{

	return false;

}

static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){

	return -EINVAL;

}

#endif

bool radeon_get_bios(struct radeon_device *rdev);

/*

 * Dummy page

 */

struct radeon_dummy_page {

	struct page	*page;

	dma_addr_t	addr;

};

int radeon_dummy_page_init(struct radeon_device *rdev);

void radeon_dummy_page_fini(struct radeon_device *rdev);

/*

 * Clocks

 */

struct radeon_clock {

	struct radeon_pll p1pll;

	struct radeon_pll p2pll;

	struct radeon_pll dcpll;

	struct radeon_pll spll;

	struct radeon_pll mpll;

	/* 10 Khz units */

	uint32_t default_mclk;

	uint32_t default_sclk;

	uint32_t default_dispclk;

	uint32_t dp_extclk;

	uint32_t max_pixel_clock;

};

/*

 * Power management

 */

int radeon_pm_init(struct radeon_device *rdev);

void radeon_pm_fini(struct radeon_device *rdev);

void radeon_pm_compute_clocks(struct radeon_device *rdev);

void radeon_pm_suspend(struct radeon_device *rdev);

void radeon_pm_resume(struct radeon_device *rdev);

void radeon_combios_get_power_modes(struct radeon_device *rdev);

void radeon_atombios_get_power_modes(struct radeon_device *rdev);

void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);

int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);

void rs690_pm_info(struct radeon_device *rdev);

extern int rv6xx_get_temp(struct radeon_device *rdev);

extern int rv770_get_temp(struct radeon_device *rdev);

extern int evergreen_get_temp(struct radeon_device *rdev);

extern int sumo_get_temp(struct radeon_device *rdev);

/*

 * Fences.

 */

struct radeon_fence_driver {

	uint32_t			scratch_reg;

	atomic_t			seq;

	uint32_t			last_seq;

	unsigned long			last_jiffies;

	unsigned long			last_timeout;

	wait_queue_head_t		queue;

	rwlock_t			lock;

	struct list_head		created;

	struct list_head		emited;

	struct list_head		signaled;

	bool				initialized;

};

struct radeon_fence {

	struct radeon_device		*rdev;

	struct kref			kref;

	struct list_head		list;

	/* protected by radeon_fence.lock */

	uint32_t			seq;

	bool				emited;

	bool				signaled;

    evhandle_t              evnt;

};

int radeon_fence_driver_init(struct radeon_device *rdev);

void radeon_fence_driver_fini(struct radeon_device *rdev);

int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);

int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);

void radeon_fence_process(struct radeon_device *rdev);

bool radeon_fence_signaled(struct radeon_fence *fence);

int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);

int radeon_fence_wait_next(struct radeon_device *rdev);

int radeon_fence_wait_last(struct radeon_device *rdev);

struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);

void radeon_fence_unref(struct radeon_fence **fence);

/*

 * Tiling registers

 */

struct radeon_surface_reg {

	struct radeon_bo *bo;

};

#define RADEON_GEM_MAX_SURFACES 8

/*

 * TTM.

 */

struct radeon_mman {

	struct ttm_bo_global_ref        bo_global_ref;

//	struct drm_global_reference	mem_global_ref;

	struct ttm_bo_device		bdev;

	bool				mem_global_referenced;

	bool				initialized;

};

struct radeon_bo {

	/* Protected by gem.mutex */

	struct list_head		list;

	/* Protected by tbo.reserved */

	u32				placements[3];

	struct ttm_placement		placement;

	struct ttm_buffer_object	tbo;

	struct ttm_bo_kmap_obj		kmap;

    unsigned                    pin_count;

    void                       *kptr;

    void                       *uptr;

    u32                         cpu_addr;

    u32                         tiling_flags;

    u32                         pitch;

    int                         surface_reg;

	/* Constant after initialization */

	struct radeon_device		*rdev;

	struct drm_gem_object		gem_base;

    u32                          domain;

};

#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)

struct radeon_bo_list {

	struct radeon_bo	*bo;

	uint64_t		gpu_offset;

	unsigned		rdomain;

	unsigned		wdomain;

	u32			tiling_flags;

};

/*

 * GEM objects.

 */

struct radeon_gem {

	struct mutex		mutex;

	struct list_head	objects;

};

int radeon_gem_init(struct radeon_device *rdev);

void radeon_gem_fini(struct radeon_device *rdev);

int radeon_gem_object_create(struct radeon_device *rdev, int size,

			     int alignment, int initial_domain,

			     bool discardable, bool kernel,

			     struct drm_gem_object **obj);

int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,

			  uint64_t *gpu_addr);

void radeon_gem_object_unpin(struct drm_gem_object *obj);

int radeon_mode_dumb_create(struct drm_file *file_priv,

			    struct drm_device *dev,

			    struct drm_mode_create_dumb *args);

int radeon_mode_dumb_mmap(struct drm_file *filp,

			  struct drm_device *dev,

			  uint32_t handle, uint64_t *offset_p);

int radeon_mode_dumb_destroy(struct drm_file *file_priv,

			     struct drm_device *dev,

			     uint32_t handle);

/*

 * GART structures, functions & helpers

 */

struct radeon_mc;

struct radeon_gart_table_ram {

    volatile uint32_t       *ptr;

};

struct radeon_gart_table_vram {

	struct radeon_bo		*robj;

    volatile uint32_t       *ptr;

};

union radeon_gart_table {

    struct radeon_gart_table_ram    ram;

    struct radeon_gart_table_vram   vram;

};

#define RADEON_GPU_PAGE_SIZE 4096

#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)

struct radeon_gart {

    dma_addr_t          table_addr;

    unsigned            num_gpu_pages;

    unsigned            num_cpu_pages;

    unsigned            table_size;

    union radeon_gart_table     table;

    struct page         **pages;

    dma_addr_t          *pages_addr;

	bool				*ttm_alloced;

    bool                ready;

};

int radeon_gart_table_ram_alloc(struct radeon_device *rdev);

void radeon_gart_table_ram_free(struct radeon_device *rdev);

int radeon_gart_table_vram_alloc(struct radeon_device *rdev);

void radeon_gart_table_vram_free(struct radeon_device *rdev);

int radeon_gart_init(struct radeon_device *rdev);

void radeon_gart_fini(struct radeon_device *rdev);

void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,

			int pages);

int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,

            int pages, u32_t *pagelist);

/*

 * GPU MC structures, functions & helpers

 */

struct radeon_mc {

    resource_size_t     aper_size;

    resource_size_t     aper_base;

    resource_size_t     agp_base;

	/* for some chips with <= 32MB we need to lie

	 * about vram size near mc fb location */

	u64			mc_vram_size;

	u64			visible_vram_size;

	u64			gtt_size;

	u64			gtt_start;

	u64			gtt_end;

	u64			vram_start;

	u64			vram_end;

    unsigned            vram_width;

	u64			real_vram_size;

    int                 vram_mtrr;

    bool                vram_is_ddr;

	bool                    igp_sideport_enabled;

	u64                     gtt_base_align;

};

bool radeon_combios_sideport_present(struct radeon_device *rdev);

bool radeon_atombios_sideport_present(struct radeon_device *rdev);

/*

 * GPU scratch registers structures, functions & helpers

 */

struct radeon_scratch {

    unsigned        num_reg;

	uint32_t                reg_base;

    bool            free[32];

    uint32_t        reg[32];

};

int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);

void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);

/*

 * IRQS.

 */

struct r500_irq_stat_regs {

	u32 disp_int;

};

struct r600_irq_stat_regs {

	u32 disp_int;

	u32 disp_int_cont;

	u32 disp_int_cont2;

	u32 d1grph_int;

	u32 d2grph_int;

};

struct evergreen_irq_stat_regs {

	u32 disp_int;

	u32 disp_int_cont;

	u32 disp_int_cont2;

	u32 disp_int_cont3;

	u32 disp_int_cont4;

	u32 disp_int_cont5;

	u32 d1grph_int;

	u32 d2grph_int;

	u32 d3grph_int;

	u32 d4grph_int;

	u32 d5grph_int;

	u32 d6grph_int;

};

union radeon_irq_stat_regs {

	struct r500_irq_stat_regs r500;

	struct r600_irq_stat_regs r600;

	struct evergreen_irq_stat_regs evergreen;

};

struct radeon_irq {

	bool		installed;

	bool		sw_int;

	/* FIXME: use a define max crtc rather than hardcode it */

	bool		crtc_vblank_int[6];

	bool		pflip[6];

    wait_queue_head_t   vblank_queue;

	/* FIXME: use defines for max hpd/dacs */

	bool            hpd[6];

	bool            gui_idle;

	bool            gui_idle_acked;

   wait_queue_head_t   idle_queue;

	/* FIXME: use defines for max HDMI blocks */

	bool		hdmi[2];

    spinlock_t  sw_lock;

	int sw_refcount;

	union radeon_irq_stat_regs stat_regs;

	spinlock_t pflip_lock[6];

	int pflip_refcount[6];

};

int radeon_irq_kms_init(struct radeon_device *rdev);

void radeon_irq_kms_fini(struct radeon_device *rdev);

void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);

void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);

void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);

void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);

/*

 * CP & ring.

 */

struct radeon_ib {

    struct list_head    list;

	unsigned		idx;

    uint64_t            gpu_addr;

	struct radeon_fence	*fence;

    uint32_t            *ptr;

    uint32_t            length_dw;

	bool			free;

};

/*

 * locking -

 * mutex protects scheduled_ibs, ready, alloc_bm

 */

struct radeon_ib_pool {

	struct mutex		mutex;

	struct radeon_bo	*robj;

	struct list_head	bogus_ib;

	struct radeon_ib	ibs[RADEON_IB_POOL_SIZE];

    bool                ready;

	unsigned		head_id;

};

struct radeon_cp {

	struct radeon_bo	*ring_obj;

	volatile uint32_t	*ring;

    unsigned            rptr;

    unsigned            wptr;

    unsigned            wptr_old;

    unsigned            ring_size;

    unsigned            ring_free_dw;

    int                 count_dw;

    uint64_t            gpu_addr;

    uint32_t            align_mask;

    uint32_t            ptr_mask;

	struct mutex		mutex;

    bool                ready;

};

/*

 * R6xx+ IH ring

 */

struct r600_ih {

	struct radeon_bo	*ring_obj;

	volatile uint32_t	*ring;

    unsigned            rptr;

    unsigned            wptr;

    unsigned            wptr_old;

    unsigned            ring_size;

    uint64_t            gpu_addr;

    uint32_t            ptr_mask;

    spinlock_t              lock;

    bool                enabled;

};

struct r600_blit {

	struct mutex		mutex;

	struct radeon_bo	*shader_obj;

	u64 shader_gpu_addr;

	u32 vs_offset, ps_offset;

	u32 state_offset;

	u32 state_len;

	u32 vb_used, vb_total;

	struct radeon_ib *vb_ib;

};

int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);

void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);

int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);

int radeon_ib_pool_init(struct radeon_device *rdev);

void radeon_ib_pool_fini(struct radeon_device *rdev);

int radeon_ib_test(struct radeon_device *rdev);

extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);

/* Ring access between begin & end cannot sleep */

void radeon_ring_free_size(struct radeon_device *rdev);

int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);

int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);

void radeon_ring_commit(struct radeon_device *rdev);

void radeon_ring_unlock_commit(struct radeon_device *rdev);

void radeon_ring_unlock_undo(struct radeon_device *rdev);

int radeon_ring_test(struct radeon_device *rdev);

int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);

void radeon_ring_fini(struct radeon_device *rdev);

/*

 * CS.

 */

struct radeon_cs_reloc {

//	struct drm_gem_object		*gobj;

	struct radeon_bo		*robj;

	struct radeon_bo_list		lobj;

    uint32_t                handle;

    uint32_t                flags;

};

struct radeon_cs_chunk {

	uint32_t		chunk_id;

	uint32_t		length_dw;

	int kpage_idx[2];

	uint32_t                *kpage[2];

	uint32_t		*kdata;

	void __user *user_ptr;

	int last_copied_page;

	int last_page_index;

};

struct radeon_cs_parser {

	struct device		*dev;

	struct radeon_device	*rdev;

	struct drm_file		*filp;

	/* chunks */

	unsigned		nchunks;

	struct radeon_cs_chunk	*chunks;

	uint64_t		*chunks_array;

	/* IB */

	unsigned		idx;

	/* relocations */

	unsigned		nrelocs;

	struct radeon_cs_reloc	*relocs;

	struct radeon_cs_reloc	**relocs_ptr;

	struct list_head	validated;

	/* indices of various chunks */

	int			chunk_ib_idx;

	int			chunk_relocs_idx;

	struct radeon_ib	*ib;

	void			*track;

	unsigned		family;

	int parser_error;

};

extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);

extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);

static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)

{

	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];

	u32 pg_idx, pg_offset;

	u32 idx_value = 0;

	int new_page;

	pg_idx = (idx * 4) / PAGE_SIZE;

	pg_offset = (idx * 4) % PAGE_SIZE;

	if (ibc->kpage_idx[0] == pg_idx)

		return ibc->kpage[0][pg_offset/4];

	if (ibc->kpage_idx[1] == pg_idx)

		return ibc->kpage[1][pg_offset/4];

	new_page = radeon_cs_update_pages(p, pg_idx);

	if (new_page < 0) {

		p->parser_error = new_page;

		return 0;

	}

	idx_value = ibc->kpage[new_page][pg_offset/4];

	return idx_value;

}

struct radeon_cs_packet {

	unsigned	idx;

	unsigned	type;

	unsigned	reg;

	unsigned	opcode;

	int		count;

	unsigned	one_reg_wr;

};

typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,

				      struct radeon_cs_packet *pkt,

				      unsigned idx, unsigned reg);

typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,

				      struct radeon_cs_packet *pkt);

/*

 * AGP

 */

int radeon_agp_init(struct radeon_device *rdev);

void radeon_agp_resume(struct radeon_device *rdev);

void radeon_agp_suspend(struct radeon_device *rdev);

void radeon_agp_fini(struct radeon_device *rdev);

/*

 * Writeback

 */

struct radeon_wb {

	struct radeon_bo	*wb_obj;

	volatile uint32_t	*wb;

	uint64_t		gpu_addr;

	bool                    enabled;

	bool                    use_event;

};

#define RADEON_WB_SCRATCH_OFFSET 0

#define RADEON_WB_CP_RPTR_OFFSET 1024

#define RADEON_WB_CP1_RPTR_OFFSET 1280

#define RADEON_WB_CP2_RPTR_OFFSET 1536

#define R600_WB_IH_WPTR_OFFSET   2048

#define R600_WB_EVENT_OFFSET     3072

/**

 * struct radeon_pm - power management datas

 * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)

 * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)

 * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)

 * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)

 * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)

 * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)

 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)

 * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)

 * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)

 * @sclk:          	GPU clock Mhz (core bandwidth depends of this clock)

 * @needed_bandwidth:   current bandwidth needs

 *

 * It keeps track of various data needed to take powermanagement decision.

 * Bandwidth need is used to determine minimun clock of the GPU and memory.

 * Equation between gpu/memory clock and available bandwidth is hw dependent

 * (type of memory, bus size, efficiency, ...)

 */

enum radeon_pm_method {

	PM_METHOD_PROFILE,

	PM_METHOD_DYNPM,

};

enum radeon_dynpm_state {

	DYNPM_STATE_DISABLED,

	DYNPM_STATE_MINIMUM,

	DYNPM_STATE_PAUSED,

	DYNPM_STATE_ACTIVE,

	DYNPM_STATE_SUSPENDED,

};

enum radeon_dynpm_action {

	DYNPM_ACTION_NONE,

	DYNPM_ACTION_MINIMUM,

	DYNPM_ACTION_DOWNCLOCK,

	DYNPM_ACTION_UPCLOCK,

	DYNPM_ACTION_DEFAULT

};

enum radeon_voltage_type {

	VOLTAGE_NONE = 0,

	VOLTAGE_GPIO,

	VOLTAGE_VDDC,

	VOLTAGE_SW

};

enum radeon_pm_state_type {

	POWER_STATE_TYPE_DEFAULT,

	POWER_STATE_TYPE_POWERSAVE,

	POWER_STATE_TYPE_BATTERY,

	POWER_STATE_TYPE_BALANCED,

	POWER_STATE_TYPE_PERFORMANCE,

};

enum radeon_pm_profile_type {

	PM_PROFILE_DEFAULT,

	PM_PROFILE_AUTO,

	PM_PROFILE_LOW,

	PM_PROFILE_MID,

	PM_PROFILE_HIGH,

};

#define PM_PROFILE_DEFAULT_IDX 0

#define PM_PROFILE_LOW_SH_IDX  1

#define PM_PROFILE_MID_SH_IDX  2

#define PM_PROFILE_HIGH_SH_IDX 3

#define PM_PROFILE_LOW_MH_IDX  4

#define PM_PROFILE_MID_MH_IDX  5

#define PM_PROFILE_HIGH_MH_IDX 6

#define PM_PROFILE_MAX         7

struct radeon_pm_profile {

	int dpms_off_ps_idx;

	int dpms_on_ps_idx;

	int dpms_off_cm_idx;

	int dpms_on_cm_idx;

};

enum radeon_int_thermal_type {

	THERMAL_TYPE_NONE,

	THERMAL_TYPE_RV6XX,

	THERMAL_TYPE_RV770,

	THERMAL_TYPE_EVERGREEN,

	THERMAL_TYPE_SUMO,

	THERMAL_TYPE_NI,

};

struct radeon_voltage {

	enum radeon_voltage_type type;

	/* gpio voltage */

	struct radeon_gpio_rec gpio;

	u32 delay; /* delay in usec from voltage drop to sclk change */

	bool active_high; /* voltage drop is active when bit is high */

	/* VDDC voltage */

	u8 vddc_id; /* index into vddc voltage table */

	u8 vddci_id; /* index into vddci voltage table */

	bool vddci_enabled;

	/* r6xx+ sw */

	u16 voltage;

	/* evergreen+ vddci */

	u16 vddci;

};

/* clock mode flags */

#define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)

struct radeon_pm_clock_info {

	/* memory clock */

	u32 mclk;

	/* engine clock */

	u32 sclk;

	/* voltage info */

	struct radeon_voltage voltage;

	/* standardized clock flags */

	u32 flags;

};

/* state flags */

#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)

struct radeon_power_state {

	enum radeon_pm_state_type type;

	/* XXX: use a define for num clock modes */

	struct radeon_pm_clock_info clock_info[8];

	/* number of valid clock modes in this power state */

	int num_clock_modes;

	struct radeon_pm_clock_info *default_clock_mode;

	/* standardized state flags */

	u32 flags;

	u32 misc; /* vbios specific flags */

	u32 misc2; /* vbios specific flags */

	int pcie_lanes; /* pcie lanes */

};

/*

 * Some modes are overclocked by very low value, accept them

 */

#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */

struct radeon_pm {

	struct mutex		mutex;

	u32			active_crtcs;

	int			active_crtc_count;

	int			req_vblank;

	bool			vblank_sync;

	bool			gui_idle;

	fixed20_12		max_bandwidth;

	fixed20_12		igp_sideport_mclk;

	fixed20_12		igp_system_mclk;

	fixed20_12		igp_ht_link_clk;

	fixed20_12		igp_ht_link_width;

	fixed20_12		k8_bandwidth;

	fixed20_12		sideport_bandwidth;

	fixed20_12		ht_bandwidth;

	fixed20_12		core_bandwidth;

	fixed20_12		sclk;

	fixed20_12		mclk;

	fixed20_12		needed_bandwidth;

	struct radeon_power_state *power_state;

	/* number of valid power states */

	int                     num_power_states;

	int                     current_power_state_index;

	int                     current_clock_mode_index;

	int                     requested_power_state_index;

	int                     requested_clock_mode_index;

	int                     default_power_state_index;

	u32                     current_sclk;

	u32                     current_mclk;

	u16                     current_vddc;

	u16                     current_vddci;

	u32                     default_sclk;

	u32                     default_mclk;

	u16                     default_vddc;

	u16                     default_vddci;

	struct radeon_i2c_chan *i2c_bus;

	/* selected pm method */

	enum radeon_pm_method     pm_method;

	/* dynpm power management */

//   struct delayed_work dynpm_idle_work;

	enum radeon_dynpm_state	dynpm_state;

	enum radeon_dynpm_action	dynpm_planned_action;

	unsigned long		dynpm_action_timeout;

	bool                    dynpm_can_upclock;

	bool                    dynpm_can_downclock;

	/* profile-based power management */

	enum radeon_pm_profile_type profile;

	int                     profile_index;

	struct radeon_pm_profile profiles[PM_PROFILE_MAX];

	/* internal thermal controller on rv6xx+ */

	enum radeon_int_thermal_type int_thermal_type;

	struct device	        *int_hwmon_dev;

};

/*

 * ASIC specific functions.

 */

struct radeon_asic {

	int (*init)(struct radeon_device *rdev);

	void (*fini)(struct radeon_device *rdev);

	int (*resume)(struct radeon_device *rdev);

	int (*suspend)(struct radeon_device *rdev);

	void (*vga_set_state)(struct radeon_device *rdev, bool state);

	bool (*gpu_is_lockup)(struct radeon_device *rdev);

	int (*asic_reset)(struct radeon_device *rdev);

	void (*gart_tlb_flush)(struct radeon_device *rdev);

	int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);

	int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);

	void (*cp_fini)(struct radeon_device *rdev);

	void (*cp_disable)(struct radeon_device *rdev);

	void (*cp_commit)(struct radeon_device *rdev);

	void (*ring_start)(struct radeon_device *rdev);

	int (*ring_test)(struct radeon_device *rdev);

	void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);

	int (*irq_set)(struct radeon_device *rdev);

	int (*irq_process)(struct radeon_device *rdev);

	u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);

	void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);

	int (*cs_parse)(struct radeon_cs_parser *p);

	int (*copy_blit)(struct radeon_device *rdev,

			 uint64_t src_offset,

			 uint64_t dst_offset,

			 unsigned num_pages,

			 struct radeon_fence *fence);

	int (*copy_dma)(struct radeon_device *rdev,

			uint64_t src_offset,

			uint64_t dst_offset,

			unsigned num_pages,

			struct radeon_fence *fence);

	int (*copy)(struct radeon_device *rdev,

		    uint64_t src_offset,

		    uint64_t dst_offset,

		    unsigned num_pages,

		    struct radeon_fence *fence);

	uint32_t (*get_engine_clock)(struct radeon_device *rdev);

	void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);

	uint32_t (*get_memory_clock)(struct radeon_device *rdev);

	void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);

	int (*get_pcie_lanes)(struct radeon_device *rdev);

	void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);

	void (*set_clock_gating)(struct radeon_device *rdev, int enable);

	int (*set_surface_reg)(struct radeon_device *rdev, int reg,

			       uint32_t tiling_flags, uint32_t pitch,

			       uint32_t offset, uint32_t obj_size);

	void (*clear_surface_reg)(struct radeon_device *rdev, int reg);

	void (*bandwidth_update)(struct radeon_device *rdev);

	void (*hpd_init)(struct radeon_device *rdev);

	void (*hpd_fini)(struct radeon_device *rdev);

	bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);

	void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);

	/* ioctl hw specific callback. Some hw might want to perform special

	 * operation on specific ioctl. For instance on wait idle some hw

	 * might want to perform and HDP flush through MMIO as it seems that

	 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed

	 * through ring.

	 */

	void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);

	bool (*gui_idle)(struct radeon_device *rdev);

	/* power management */

	void (*pm_misc)(struct radeon_device *rdev);

	void (*pm_prepare)(struct radeon_device *rdev);

	void (*pm_finish)(struct radeon_device *rdev);

	void (*pm_init_profile)(struct radeon_device *rdev);

	void (*pm_get_dynpm_state)(struct radeon_device *rdev);

	/* pageflipping */

	void (*pre_page_flip)(struct radeon_device *rdev, int crtc);

	u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);

	void (*post_page_flip)(struct radeon_device *rdev, int crtc);

};

/*

 * Asic structures

 */

struct r100_gpu_lockup {

	unsigned long	last_jiffies;

	u32		last_cp_rptr;

};

struct r100_asic {

	const unsigned	*reg_safe_bm;

	unsigned	reg_safe_bm_size;

	u32		hdp_cntl;

	struct r100_gpu_lockup	lockup;

};

struct r300_asic {

	const unsigned	*reg_safe_bm;

	unsigned	reg_safe_bm_size;

	u32		resync_scratch;

	u32		hdp_cntl;

	struct r100_gpu_lockup	lockup;

};

struct r600_asic {

	unsigned max_pipes;

	unsigned max_tile_pipes;

	unsigned max_simds;

	unsigned max_backends;

	unsigned max_gprs;

	unsigned max_threads;

	unsigned max_stack_entries;

	unsigned max_hw_contexts;

	unsigned max_gs_threads;

	unsigned sx_max_export_size;

	unsigned sx_max_export_pos_size;

	unsigned sx_max_export_smx_size;

	unsigned sq_num_cf_insts;

	unsigned tiling_nbanks;

	unsigned tiling_npipes;

	unsigned tiling_group_size;

	unsigned		tile_config;

	unsigned		backend_map;

	struct r100_gpu_lockup	lockup;

};

struct rv770_asic {

	unsigned max_pipes;

	unsigned max_tile_pipes;

	unsigned max_simds;

	unsigned max_backends;

	unsigned max_gprs;

	unsigned max_threads;

	unsigned max_stack_entries;

	unsigned max_hw_contexts;

	unsigned max_gs_threads;

	unsigned sx_max_export_size;

	unsigned sx_max_export_pos_size;

	unsigned sx_max_export_smx_size;

	unsigned sq_num_cf_insts;

	unsigned sx_num_of_sets;

	unsigned sc_prim_fifo_size;

	unsigned sc_hiz_tile_fifo_size;

	unsigned sc_earlyz_tile_fifo_fize;

	unsigned tiling_nbanks;

	unsigned tiling_npipes;

	unsigned tiling_group_size;

	unsigned		tile_config;

	unsigned		backend_map;

	struct r100_gpu_lockup	lockup;

};