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1117 serge 1
/*
2
 * Copyright 2008 Advanced Micro Devices, Inc.
3
 * Copyright 2008 Red Hat Inc.
4
 * Copyright 2009 Jerome Glisse.
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a
7
 * copy of this software and associated documentation files (the "Software"),
8
 * to deal in the Software without restriction, including without limitation
9
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10
 * and/or sell copies of the Software, and to permit persons to whom the
11
 * Software is furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22
 * OTHER DEALINGS IN THE SOFTWARE.
23
 *
24
 * Authors: Dave Airlie
25
 *          Alex Deucher
26
 *          Jerome Glisse
27
 */
28
#ifndef __RADEON_H__
29
#define __RADEON_H__
30
 
31
/* TODO: Here are things that needs to be done :
32
 *	- surface allocator & initializer : (bit like scratch reg) should
33
 *	  initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34
 *	  related to surface
35
 *	- WB : write back stuff (do it bit like scratch reg things)
36
 *	- Vblank : look at Jesse's rework and what we should do
37
 *	- r600/r700: gart & cp
38
 *	- cs : clean cs ioctl use bitmap & things like that.
39
 *	- power management stuff
40
 *	- Barrier in gart code
41
 *	- Unmappabled vram ?
42
 *	- TESTING, TESTING, TESTING
43
 */
44
 
1221 serge 45
/* Initialization path:
46
 *  We expect that acceleration initialization might fail for various
47
 *  reasons even thought we work hard to make it works on most
48
 *  configurations. In order to still have a working userspace in such
49
 *  situation the init path must succeed up to the memory controller
50
 *  initialization point. Failure before this point are considered as
51
 *  fatal error. Here is the init callchain :
52
 *      radeon_device_init  perform common structure, mutex initialization
53
 *      asic_init           setup the GPU memory layout and perform all
54
 *                          one time initialization (failure in this
55
 *                          function are considered fatal)
56
 *      asic_startup        setup the GPU acceleration, in order to
57
 *                          follow guideline the first thing this
58
 *                          function should do is setting the GPU
59
 *                          memory controller (only MC setup failure
60
 *                          are considered as fatal)
61
 */
62
 
1321 serge 63
#include 
1221 serge 64
 
1321 serge 65
#include 
66
#include 
1221 serge 67
 
1321 serge 68
#include 
69
#include 
70
#include 
71
#include 
1221 serge 72
 
1117 serge 73
 
1120 serge 74
#include 
1117 serge 75
 
1120 serge 76
#include 
1123 serge 77
#include "drm_edid.h"
1179 serge 78
 
79
#include "radeon_family.h"
1117 serge 80
#include "radeon_mode.h"
81
#include "radeon_reg.h"
82
 
83
#include 
84
 
1179 serge 85
/*
86
 * Modules parameters.
87
 */
88
extern int radeon_no_wb;
1123 serge 89
extern int radeon_modeset;
1117 serge 90
extern int radeon_dynclks;
1123 serge 91
extern int radeon_r4xx_atom;
1128 serge 92
extern int radeon_agpmode;
93
extern int radeon_vram_limit;
1117 serge 94
extern int radeon_gart_size;
1128 serge 95
extern int radeon_benchmarking;
1179 serge 96
extern int radeon_testing;
1123 serge 97
extern int radeon_connector_table;
1179 serge 98
extern int radeon_tv;
1321 serge 99
extern int radeon_new_pll;
1430 serge 100
extern int radeon_dynpm;
1403 serge 101
extern int radeon_audio;
1117 serge 102
 
1430 serge 103
typedef struct pm_message {
104
    int event;
105
} pm_message_t;
106
 
1233 serge 107
typedef struct
108
{
109
  int width;
110
  int height;
111
  int bpp;
112
  int freq;
1321 serge 113
}videomode_t;
1179 serge 114
 
115
static inline uint8_t __raw_readb(const volatile void __iomem *addr)
116
{
117
    return *(const volatile uint8_t __force *) addr;
118
}
119
 
120
static inline uint16_t __raw_readw(const volatile void __iomem *addr)
121
{
122
    return *(const volatile uint16_t __force *) addr;
123
}
124
 
125
static inline uint32_t __raw_readl(const volatile void __iomem *addr)
126
{
127
    return *(const volatile uint32_t __force *) addr;
128
}
129
 
130
#define readb __raw_readb
131
#define readw __raw_readw
132
#define readl __raw_readl
133
 
134
 
135
 
136
static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)
137
{
138
    *(volatile uint8_t __force *) addr = b;
139
}
140
 
141
static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)
142
{
143
    *(volatile uint16_t __force *) addr = b;
144
}
145
 
146
static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)
147
{
148
    *(volatile uint32_t __force *) addr = b;
149
}
150
 
151
static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)
152
{
153
        *(volatile __u64 *)addr = b;
154
}
155
 
156
#define writeb __raw_writeb
157
#define writew __raw_writew
158
#define writel __raw_writel
159
#define writeq __raw_writeq
160
 
161
 
1117 serge 162
/*
163
 * Copy from radeon_drv.h so we don't have to include both and have conflicting
164
 * symbol;
165
 */
1120 serge 166
#define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
1428 serge 167
/* RADEON_IB_POOL_SIZE must be a power of 2 */
1120 serge 168
#define RADEON_IB_POOL_SIZE             16
1117 serge 169
#define RADEON_DEBUGFS_MAX_NUM_FILES	32
1120 serge 170
#define RADEONFB_CONN_LIMIT             4
1179 serge 171
#define RADEON_BIOS_NUM_SCRATCH		8
1117 serge 172
 
173
/*
174
 * Errata workarounds.
175
 */
176
enum radeon_pll_errata {
177
    CHIP_ERRATA_R300_CG             = 0x00000001,
178
    CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
179
    CHIP_ERRATA_PLL_DELAY           = 0x00000004
180
};
181
 
182
 
183
struct radeon_device;
184
 
185
 
186
/*
187
 * BIOS.
188
 */
1430 serge 189
#define ATRM_BIOS_PAGE 4096
190
 
191
#if defined(CONFIG_VGA_SWITCHEROO)
192
bool radeon_atrm_supported(struct pci_dev *pdev);
193
int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
194
#else
195
static inline bool radeon_atrm_supported(struct pci_dev *pdev)
196
{
197
	return false;
198
}
199
 
200
static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
201
	return -EINVAL;
202
}
203
#endif
1117 serge 204
bool radeon_get_bios(struct radeon_device *rdev);
205
 
1179 serge 206
 
1117 serge 207
/*
1179 serge 208
 * Dummy page
209
 */
210
struct radeon_dummy_page {
211
	struct page	*page;
212
	dma_addr_t	addr;
213
};
214
int radeon_dummy_page_init(struct radeon_device *rdev);
215
void radeon_dummy_page_fini(struct radeon_device *rdev);
216
 
217
 
218
/*
1117 serge 219
 * Clocks
220
 */
221
struct radeon_clock {
222
	struct radeon_pll p1pll;
223
	struct radeon_pll p2pll;
1430 serge 224
	struct radeon_pll dcpll;
1117 serge 225
	struct radeon_pll spll;
226
	struct radeon_pll mpll;
227
	/* 10 Khz units */
228
	uint32_t default_mclk;
229
	uint32_t default_sclk;
1430 serge 230
	uint32_t default_dispclk;
231
	uint32_t dp_extclk;
1117 serge 232
};
233
 
1268 serge 234
/*
235
 * Power management
236
 */
237
int radeon_pm_init(struct radeon_device *rdev);
1430 serge 238
void radeon_pm_compute_clocks(struct radeon_device *rdev);
239
void radeon_combios_get_power_modes(struct radeon_device *rdev);
240
void radeon_atombios_get_power_modes(struct radeon_device *rdev);
1179 serge 241
 
1117 serge 242
/*
243
 * Fences.
244
 */
245
struct radeon_fence_driver {
246
	uint32_t			scratch_reg;
1321 serge 247
	atomic_t			seq;
1117 serge 248
	uint32_t			last_seq;
249
	unsigned long			count_timeout;
250
//	wait_queue_head_t		queue;
1321 serge 251
	rwlock_t			lock;
1120 serge 252
	struct list_head		created;
253
	struct list_head		emited;
254
	struct list_head		signaled;
1403 serge 255
	bool				initialized;
1117 serge 256
};
257
 
258
struct radeon_fence {
259
	struct radeon_device		*rdev;
1321 serge 260
	struct kref			kref;
1120 serge 261
	struct list_head		list;
1117 serge 262
	/* protected by radeon_fence.lock */
263
	uint32_t			seq;
264
	unsigned long			timeout;
265
	bool				emited;
266
	bool				signaled;
267
};
268
 
269
int radeon_fence_driver_init(struct radeon_device *rdev);
270
void radeon_fence_driver_fini(struct radeon_device *rdev);
271
int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
272
int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
273
void radeon_fence_process(struct radeon_device *rdev);
274
bool radeon_fence_signaled(struct radeon_fence *fence);
275
int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
276
int radeon_fence_wait_next(struct radeon_device *rdev);
277
int radeon_fence_wait_last(struct radeon_device *rdev);
278
struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
279
void radeon_fence_unref(struct radeon_fence **fence);
280
 
1179 serge 281
/*
282
 * Tiling registers
283
 */
284
struct radeon_surface_reg {
1321 serge 285
	struct radeon_bo *bo;
1179 serge 286
};
1117 serge 287
 
1179 serge 288
#define RADEON_GEM_MAX_SURFACES 8
289
 
1117 serge 290
/*
1321 serge 291
 * TTM.
1117 serge 292
 */
1321 serge 293
struct radeon_mman {
294
	struct ttm_bo_global_ref        bo_global_ref;
295
	struct ttm_global_reference	mem_global_ref;
1403 serge 296
	struct ttm_bo_device		bdev;
1321 serge 297
	bool				mem_global_referenced;
1403 serge 298
	bool				initialized;
1321 serge 299
};
1117 serge 300
 
1321 serge 301
struct radeon_bo {
302
	/* Protected by gem.mutex */
303
	struct list_head		list;
304
	/* Protected by tbo.reserved */
305
	u32				placements[3];
306
	struct ttm_placement		placement;
307
	struct ttm_buffer_object	tbo;
308
	struct ttm_bo_kmap_obj		kmap;
1404 serge 309
    unsigned                    pin_count;
310
    void                       *kptr;
311
    u32                         cpu_addr;
312
    u32                         tiling_flags;
313
    u32                         pitch;
314
    int                         surface_reg;
1321 serge 315
	/* Constant after initialization */
316
	struct radeon_device		*rdev;
317
	struct drm_gem_object		*gobj;
1404 serge 318
    u32                          domain;
1321 serge 319
};
320
 
321
struct radeon_bo_list {
1120 serge 322
	struct list_head	list;
1321 serge 323
	struct radeon_bo	*bo;
1117 serge 324
	uint64_t		gpu_offset;
325
	unsigned		rdomain;
326
	unsigned		wdomain;
1321 serge 327
	u32			tiling_flags;
1117 serge 328
};
329
 
1123 serge 330
/*
331
 * GEM objects.
332
 */
333
struct radeon_gem {
334
	struct list_head	objects;
335
};
1117 serge 336
 
1126 serge 337
int radeon_gem_init(struct radeon_device *rdev);
338
void radeon_gem_fini(struct radeon_device *rdev);
339
int radeon_gem_object_create(struct radeon_device *rdev, int size,
340
			     int alignment, int initial_domain,
341
			     bool discardable, bool kernel,
342
			     struct drm_gem_object **obj);
343
int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
344
			  uint64_t *gpu_addr);
345
void radeon_gem_object_unpin(struct drm_gem_object *obj);
1117 serge 346
 
347
 
348
/*
349
 * GART structures, functions & helpers
350
 */
351
struct radeon_mc;
352
 
353
struct radeon_gart_table_ram {
354
    volatile uint32_t       *ptr;
355
};
356
 
357
struct radeon_gart_table_vram {
1321 serge 358
	struct radeon_bo		*robj;
1117 serge 359
    volatile uint32_t       *ptr;
360
};
361
 
362
union radeon_gart_table {
363
    struct radeon_gart_table_ram    ram;
364
    struct radeon_gart_table_vram   vram;
365
};
366
 
1268 serge 367
#define RADEON_GPU_PAGE_SIZE 4096
1430 serge 368
#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
1268 serge 369
 
1117 serge 370
struct radeon_gart {
371
    dma_addr_t          table_addr;
372
    unsigned            num_gpu_pages;
373
    unsigned            num_cpu_pages;
374
    unsigned            table_size;
375
    union radeon_gart_table     table;
376
    struct page         **pages;
377
    dma_addr_t          *pages_addr;
378
    bool                ready;
379
};
380
 
381
int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
382
void radeon_gart_table_ram_free(struct radeon_device *rdev);
383
int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
384
void radeon_gart_table_vram_free(struct radeon_device *rdev);
385
int radeon_gart_init(struct radeon_device *rdev);
386
void radeon_gart_fini(struct radeon_device *rdev);
387
void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
388
			int pages);
1120 serge 389
int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
390
            int pages, u32_t *pagelist);
1117 serge 391
 
392
 
393
/*
394
 * GPU MC structures, functions & helpers
395
 */
396
struct radeon_mc {
397
    resource_size_t     aper_size;
398
    resource_size_t     aper_base;
399
    resource_size_t     agp_base;
1179 serge 400
	/* for some chips with <= 32MB we need to lie
401
	 * about vram size near mc fb location */
402
	u64			mc_vram_size;
1430 serge 403
	u64			visible_vram_size;
1179 serge 404
	u64			gtt_size;
405
	u64			gtt_start;
406
	u64			gtt_end;
407
	u64			vram_start;
408
	u64			vram_end;
1117 serge 409
    unsigned            vram_width;
1179 serge 410
	u64			real_vram_size;
1117 serge 411
    int                 vram_mtrr;
412
    bool                vram_is_ddr;
1403 serge 413
	bool                    igp_sideport_enabled;
1117 serge 414
};
415
 
1403 serge 416
bool radeon_combios_sideport_present(struct radeon_device *rdev);
417
bool radeon_atombios_sideport_present(struct radeon_device *rdev);
1117 serge 418
 
419
/*
420
 * GPU scratch registers structures, functions & helpers
421
 */
422
struct radeon_scratch {
423
    unsigned        num_reg;
424
    bool            free[32];
425
    uint32_t        reg[32];
426
};
427
 
428
int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
429
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
430
 
431
 
432
/*
433
 * IRQS.
434
 */
435
struct radeon_irq {
436
	bool		installed;
437
	bool		sw_int;
438
	/* FIXME: use a define max crtc rather than hardcode it */
439
	bool		crtc_vblank_int[2];
1321 serge 440
	/* FIXME: use defines for max hpd/dacs */
441
	bool            hpd[6];
442
    spinlock_t  sw_lock;
443
	int sw_refcount;
1117 serge 444
};
445
 
446
int radeon_irq_kms_init(struct radeon_device *rdev);
447
void radeon_irq_kms_fini(struct radeon_device *rdev);
1321 serge 448
void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
449
void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
1117 serge 450
 
451
/*
452
 * CP & ring.
453
 */
454
struct radeon_ib {
1403 serge 455
    struct list_head    list;
1428 serge 456
	unsigned		idx;
1403 serge 457
    uint64_t            gpu_addr;
1117 serge 458
	struct radeon_fence	*fence;
1403 serge 459
    uint32_t            *ptr;
460
    uint32_t            length_dw;
1428 serge 461
	bool			free;
1117 serge 462
};
463
 
1179 serge 464
/*
465
 * locking -
466
 * mutex protects scheduled_ibs, ready, alloc_bm
467
 */
1117 serge 468
struct radeon_ib_pool {
1403 serge 469
//   struct mutex        mutex;
1321 serge 470
	struct radeon_bo	*robj;
1430 serge 471
	struct list_head	bogus_ib;
1117 serge 472
	struct radeon_ib	ibs[RADEON_IB_POOL_SIZE];
1403 serge 473
    bool                ready;
1428 serge 474
	unsigned		head_id;
1117 serge 475
};
476
 
477
struct radeon_cp {
1321 serge 478
	struct radeon_bo	*ring_obj;
1117 serge 479
	volatile uint32_t	*ring;
1403 serge 480
    unsigned            rptr;
481
    unsigned            wptr;
482
    unsigned            wptr_old;
483
    unsigned            ring_size;
484
    unsigned            ring_free_dw;
485
    int                 count_dw;
486
    uint64_t            gpu_addr;
487
    uint32_t            align_mask;
488
    uint32_t            ptr_mask;
1117 serge 489
//	struct mutex		mutex;
1403 serge 490
    bool                ready;
1117 serge 491
};
492
 
1321 serge 493
/*
494
 * R6xx+ IH ring
495
 */
496
struct r600_ih {
497
	struct radeon_bo	*ring_obj;
498
	volatile uint32_t	*ring;
499
    unsigned            rptr;
500
    unsigned            wptr;
501
    unsigned            wptr_old;
502
    unsigned            ring_size;
503
    uint64_t            gpu_addr;
504
    uint32_t            ptr_mask;
505
    spinlock_t              lock;
506
    bool                enabled;
507
};
508
 
1179 serge 509
struct r600_blit {
1321 serge 510
	struct radeon_bo	*shader_obj;
1179 serge 511
	u64 shader_gpu_addr;
512
	u32 vs_offset, ps_offset;
513
	u32 state_offset;
514
	u32 state_len;
515
	u32 vb_used, vb_total;
516
	struct radeon_ib *vb_ib;
517
};
518
 
1117 serge 519
int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
520
void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
521
int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
522
int radeon_ib_pool_init(struct radeon_device *rdev);
523
void radeon_ib_pool_fini(struct radeon_device *rdev);
524
int radeon_ib_test(struct radeon_device *rdev);
1430 serge 525
extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
1117 serge 526
/* Ring access between begin & end cannot sleep */
527
void radeon_ring_free_size(struct radeon_device *rdev);
528
int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
529
void radeon_ring_unlock_commit(struct radeon_device *rdev);
530
void radeon_ring_unlock_undo(struct radeon_device *rdev);
531
int radeon_ring_test(struct radeon_device *rdev);
532
int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
533
void radeon_ring_fini(struct radeon_device *rdev);
534
 
535
 
536
/*
537
 * CS.
538
 */
539
struct radeon_cs_reloc {
540
//	struct drm_gem_object		*gobj;
1321 serge 541
	struct radeon_bo		*robj;
542
//    struct radeon_bo_list   lobj;
1403 serge 543
    uint32_t                handle;
544
    uint32_t                flags;
1117 serge 545
};
546
 
547
struct radeon_cs_chunk {
548
	uint32_t		chunk_id;
549
	uint32_t		length_dw;
1221 serge 550
	int kpage_idx[2];
551
	uint32_t                *kpage[2];
1117 serge 552
	uint32_t		*kdata;
1221 serge 553
	void __user *user_ptr;
554
	int last_copied_page;
555
	int last_page_index;
1117 serge 556
};
557
 
558
struct radeon_cs_parser {
1430 serge 559
	struct device		*dev;
1117 serge 560
	struct radeon_device	*rdev;
561
//	struct drm_file		*filp;
562
	/* chunks */
563
	unsigned		nchunks;
564
	struct radeon_cs_chunk	*chunks;
565
	uint64_t		*chunks_array;
566
	/* IB */
567
	unsigned		idx;
568
	/* relocations */
569
	unsigned		nrelocs;
570
	struct radeon_cs_reloc	*relocs;
571
	struct radeon_cs_reloc	**relocs_ptr;
1120 serge 572
	struct list_head	validated;
1117 serge 573
	/* indices of various chunks */
574
	int			chunk_ib_idx;
575
	int			chunk_relocs_idx;
576
	struct radeon_ib	*ib;
577
	void			*track;
1179 serge 578
	unsigned		family;
1221 serge 579
	int parser_error;
1117 serge 580
};
581
 
1221 serge 582
extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
583
extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
584
 
585
 
586
static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
587
{
588
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
589
	u32 pg_idx, pg_offset;
590
	u32 idx_value = 0;
591
	int new_page;
592
 
593
	pg_idx = (idx * 4) / PAGE_SIZE;
594
	pg_offset = (idx * 4) % PAGE_SIZE;
595
 
596
	if (ibc->kpage_idx[0] == pg_idx)
597
		return ibc->kpage[0][pg_offset/4];
598
	if (ibc->kpage_idx[1] == pg_idx)
599
		return ibc->kpage[1][pg_offset/4];
600
 
601
	new_page = radeon_cs_update_pages(p, pg_idx);
602
	if (new_page < 0) {
603
		p->parser_error = new_page;
604
		return 0;
605
	}
606
 
607
	idx_value = ibc->kpage[new_page][pg_offset/4];
608
	return idx_value;
609
}
610
 
1117 serge 611
struct radeon_cs_packet {
612
	unsigned	idx;
613
	unsigned	type;
614
	unsigned	reg;
615
	unsigned	opcode;
616
	int		count;
617
	unsigned	one_reg_wr;
618
};
619
 
620
typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
621
				      struct radeon_cs_packet *pkt,
622
				      unsigned idx, unsigned reg);
623
typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
624
				      struct radeon_cs_packet *pkt);
625
 
626
 
627
/*
628
 * AGP
629
 */
630
int radeon_agp_init(struct radeon_device *rdev);
1321 serge 631
void radeon_agp_resume(struct radeon_device *rdev);
1117 serge 632
void radeon_agp_fini(struct radeon_device *rdev);
633
 
634
 
635
/*
636
 * Writeback
637
 */
638
struct radeon_wb {
1321 serge 639
	struct radeon_bo	*wb_obj;
1117 serge 640
	volatile uint32_t	*wb;
641
	uint64_t		gpu_addr;
642
};
643
 
1179 serge 644
/**
645
 * struct radeon_pm - power management datas
646
 * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
647
 * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
648
 * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
649
 * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
650
 * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
651
 * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
652
 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
653
 * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
654
 * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
655
 * @sclk:          	GPU clock Mhz (core bandwith depends of this clock)
656
 * @needed_bandwidth:   current bandwidth needs
657
 *
658
 * It keeps track of various data needed to take powermanagement decision.
659
 * Bandwith need is used to determine minimun clock of the GPU and memory.
660
 * Equation between gpu/memory clock and available bandwidth is hw dependent
661
 * (type of memory, bus size, efficiency, ...)
662
 */
1430 serge 663
enum radeon_pm_state {
664
	PM_STATE_DISABLED,
665
	PM_STATE_MINIMUM,
666
	PM_STATE_PAUSED,
667
	PM_STATE_ACTIVE
668
};
669
enum radeon_pm_action {
670
	PM_ACTION_NONE,
671
	PM_ACTION_MINIMUM,
672
	PM_ACTION_DOWNCLOCK,
673
	PM_ACTION_UPCLOCK
674
};
675
 
676
enum radeon_voltage_type {
677
	VOLTAGE_NONE = 0,
678
	VOLTAGE_GPIO,
679
	VOLTAGE_VDDC,
680
	VOLTAGE_SW
681
};
682
 
683
enum radeon_pm_state_type {
684
	POWER_STATE_TYPE_DEFAULT,
685
	POWER_STATE_TYPE_POWERSAVE,
686
	POWER_STATE_TYPE_BATTERY,
687
	POWER_STATE_TYPE_BALANCED,
688
	POWER_STATE_TYPE_PERFORMANCE,
689
};
690
 
691
enum radeon_pm_clock_mode_type {
692
	POWER_MODE_TYPE_DEFAULT,
693
	POWER_MODE_TYPE_LOW,
694
	POWER_MODE_TYPE_MID,
695
	POWER_MODE_TYPE_HIGH,
696
};
697
 
698
struct radeon_voltage {
699
	enum radeon_voltage_type type;
700
	/* gpio voltage */
701
	struct radeon_gpio_rec gpio;
702
	u32 delay; /* delay in usec from voltage drop to sclk change */
703
	bool active_high; /* voltage drop is active when bit is high */
704
	/* VDDC voltage */
705
	u8 vddc_id; /* index into vddc voltage table */
706
	u8 vddci_id; /* index into vddci voltage table */
707
	bool vddci_enabled;
708
	/* r6xx+ sw */
709
	u32 voltage;
710
};
711
 
712
struct radeon_pm_non_clock_info {
713
	/* pcie lanes */
714
	int pcie_lanes;
715
	/* standardized non-clock flags */
716
	u32 flags;
717
};
718
 
719
struct radeon_pm_clock_info {
720
	/* memory clock */
721
	u32 mclk;
722
	/* engine clock */
723
	u32 sclk;
724
	/* voltage info */
725
	struct radeon_voltage voltage;
726
	/* standardized clock flags - not sure we'll need these */
727
	u32 flags;
728
};
729
 
730
struct radeon_power_state {
731
	enum radeon_pm_state_type type;
732
	/* XXX: use a define for num clock modes */
733
	struct radeon_pm_clock_info clock_info[8];
734
	/* number of valid clock modes in this power state */
735
	int num_clock_modes;
736
	struct radeon_pm_clock_info *default_clock_mode;
737
	/* non clock info about this state */
738
	struct radeon_pm_non_clock_info non_clock_info;
739
	bool voltage_drop_active;
740
};
741
 
742
/*
743
 * Some modes are overclocked by very low value, accept them
744
 */
745
#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
746
 
1179 serge 747
struct radeon_pm {
1430 serge 748
//	struct mutex		mutex;
749
//	struct delayed_work	idle_work;
750
	enum radeon_pm_state	state;
751
	enum radeon_pm_action	planned_action;
752
	unsigned long		action_timeout;
753
	bool 			downclocked;
754
	int			active_crtcs;
755
	int			req_vblank;
1179 serge 756
	fixed20_12		max_bandwidth;
757
	fixed20_12		igp_sideport_mclk;
758
	fixed20_12		igp_system_mclk;
759
	fixed20_12		igp_ht_link_clk;
760
	fixed20_12		igp_ht_link_width;
761
	fixed20_12		k8_bandwidth;
762
	fixed20_12		sideport_bandwidth;
763
	fixed20_12		ht_bandwidth;
764
	fixed20_12		core_bandwidth;
765
	fixed20_12		sclk;
766
	fixed20_12		needed_bandwidth;
1430 serge 767
	/* XXX: use a define for num power modes */
768
	struct radeon_power_state power_state[8];
769
	/* number of valid power states */
770
	int                     num_power_states;
771
	struct radeon_power_state *current_power_state;
772
	struct radeon_pm_clock_info *current_clock_mode;
773
	struct radeon_power_state *requested_power_state;
774
	struct radeon_pm_clock_info *requested_clock_mode;
775
	struct radeon_power_state *default_power_state;
1179 serge 776
};
1117 serge 777
 
778
/*
779
 * ASIC specific functions.
780
 */
781
struct radeon_asic {
782
	int (*init)(struct radeon_device *rdev);
1179 serge 783
	void (*fini)(struct radeon_device *rdev);
784
	int (*resume)(struct radeon_device *rdev);
785
	int (*suspend)(struct radeon_device *rdev);
786
	void (*vga_set_state)(struct radeon_device *rdev, bool state);
1117 serge 787
	int (*gpu_reset)(struct radeon_device *rdev);
788
	void (*gart_tlb_flush)(struct radeon_device *rdev);
789
	int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
790
	int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
791
	void (*cp_fini)(struct radeon_device *rdev);
792
	void (*cp_disable)(struct radeon_device *rdev);
1179 serge 793
	void (*cp_commit)(struct radeon_device *rdev);
1117 serge 794
	void (*ring_start)(struct radeon_device *rdev);
1179 serge 795
	int (*ring_test)(struct radeon_device *rdev);
796
	void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1117 serge 797
	int (*irq_set)(struct radeon_device *rdev);
798
	int (*irq_process)(struct radeon_device *rdev);
1179 serge 799
	u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1117 serge 800
	void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
801
	int (*cs_parse)(struct radeon_cs_parser *p);
802
	int (*copy_blit)(struct radeon_device *rdev,
803
			 uint64_t src_offset,
804
			 uint64_t dst_offset,
805
			 unsigned num_pages,
806
			 struct radeon_fence *fence);
807
	int (*copy_dma)(struct radeon_device *rdev,
808
			uint64_t src_offset,
809
			uint64_t dst_offset,
810
			unsigned num_pages,
811
			struct radeon_fence *fence);
812
	int (*copy)(struct radeon_device *rdev,
813
		    uint64_t src_offset,
814
		    uint64_t dst_offset,
815
		    unsigned num_pages,
816
		    struct radeon_fence *fence);
1268 serge 817
	uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1117 serge 818
	void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1268 serge 819
	uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1117 serge 820
	void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1430 serge 821
	int (*get_pcie_lanes)(struct radeon_device *rdev);
1117 serge 822
	void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
823
	void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1179 serge 824
	int (*set_surface_reg)(struct radeon_device *rdev, int reg,
825
			       uint32_t tiling_flags, uint32_t pitch,
826
			       uint32_t offset, uint32_t obj_size);
827
	int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
828
	void (*bandwidth_update)(struct radeon_device *rdev);
1321 serge 829
	void (*hpd_init)(struct radeon_device *rdev);
830
	void (*hpd_fini)(struct radeon_device *rdev);
831
	bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
832
	void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1404 serge 833
	/* ioctl hw specific callback. Some hw might want to perform special
834
	 * operation on specific ioctl. For instance on wait idle some hw
835
	 * might want to perform and HDP flush through MMIO as it seems that
836
	 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
837
	 * through ring.
838
	 */
839
	void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1117 serge 840
};
841
 
1179 serge 842
/*
843
 * Asic structures
844
 */
845
struct r100_asic {
846
	const unsigned	*reg_safe_bm;
847
	unsigned	reg_safe_bm_size;
1403 serge 848
	u32		hdp_cntl;
1179 serge 849
};
850
 
851
struct r300_asic {
852
	const unsigned	*reg_safe_bm;
853
	unsigned	reg_safe_bm_size;
1403 serge 854
	u32		resync_scratch;
855
	u32		hdp_cntl;
1179 serge 856
};
857
 
858
struct r600_asic {
859
	unsigned max_pipes;
860
	unsigned max_tile_pipes;
861
	unsigned max_simds;
862
	unsigned max_backends;
863
	unsigned max_gprs;
864
	unsigned max_threads;
865
	unsigned max_stack_entries;
866
	unsigned max_hw_contexts;
867
	unsigned max_gs_threads;
868
	unsigned sx_max_export_size;
869
	unsigned sx_max_export_pos_size;
870
	unsigned sx_max_export_smx_size;
871
	unsigned sq_num_cf_insts;
1430 serge 872
	unsigned tiling_nbanks;
873
	unsigned tiling_npipes;
874
	unsigned tiling_group_size;
1179 serge 875
};
876
 
877
struct rv770_asic {
878
	unsigned max_pipes;
879
	unsigned max_tile_pipes;
880
	unsigned max_simds;
881
	unsigned max_backends;
882
	unsigned max_gprs;
883
	unsigned max_threads;
884
	unsigned max_stack_entries;
885
	unsigned max_hw_contexts;
886
	unsigned max_gs_threads;
887
	unsigned sx_max_export_size;
888
	unsigned sx_max_export_pos_size;
889
	unsigned sx_max_export_smx_size;
890
	unsigned sq_num_cf_insts;
891
	unsigned sx_num_of_sets;
892
	unsigned sc_prim_fifo_size;
893
	unsigned sc_hiz_tile_fifo_size;
894
	unsigned sc_earlyz_tile_fifo_fize;
1430 serge 895
	unsigned tiling_nbanks;
896
	unsigned tiling_npipes;
897
	unsigned tiling_group_size;
1179 serge 898
};
899
 
1117 serge 900
union radeon_asic_config {
901
	struct r300_asic	r300;
1179 serge 902
	struct r100_asic	r100;
903
	struct r600_asic	r600;
904
	struct rv770_asic	rv770;
1117 serge 905
};
906
 
907
 
908
/*
1179 serge 909
 
910
 
911
 
912
 
1117 serge 913
/*
914
 * Core structure, functions and helpers.
915
 */
916
typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
917
typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
918
 
919
struct radeon_device {
1413 serge 920
	struct device			*dev;
1117 serge 921
    struct drm_device          *ddev;
922
    struct pci_dev             *pdev;
923
    /* ASIC */
924
    union radeon_asic_config    config;
925
    enum radeon_family          family;
926
    unsigned long               flags;
927
    int                         usec_timeout;
928
    enum radeon_pll_errata      pll_errata;
929
    int                         num_gb_pipes;
1413 serge 930
	int				            num_z_pipes;
1117 serge 931
    int                         disp_priority;
932
    /* BIOS */
933
    uint8_t                     *bios;
934
    bool                        is_atom_bios;
935
    uint16_t                    bios_header_start;
1413 serge 936
	struct radeon_bo		    *stollen_vga_memory;
1126 serge 937
    struct fb_info              *fbdev_info;
1413 serge 938
	struct radeon_bo		    *fbdev_rbo;
1117 serge 939
    struct radeon_framebuffer   *fbdev_rfb;
940
    /* Register mmio */
941
    unsigned long               rmmio_base;
942
    unsigned long               rmmio_size;
943
    void                       *rmmio;
1120 serge 944
    radeon_rreg_t               mc_rreg;
945
    radeon_wreg_t               mc_wreg;
946
    radeon_rreg_t               pll_rreg;
947
    radeon_wreg_t               pll_wreg;
1179 serge 948
	uint32_t                        pcie_reg_mask;
1120 serge 949
    radeon_rreg_t               pciep_rreg;
950
    radeon_wreg_t               pciep_wreg;
951
    struct radeon_clock         clock;
1117 serge 952
    struct radeon_mc            mc;
953
    struct radeon_gart          gart;
954
	struct radeon_mode_info		mode_info;
955
    struct radeon_scratch       scratch;
1321 serge 956
    struct radeon_mman          mman;
1117 serge 957
	struct radeon_fence_driver	fence_drv;
1120 serge 958
    struct radeon_cp            cp;
1117 serge 959
    struct radeon_ib_pool       ib_pool;
960
//    struct radeon_irq       irq;
961
    struct radeon_asic         *asic;
1126 serge 962
    struct radeon_gem       gem;
1179 serge 963
	struct radeon_pm		pm;
964
	uint32_t			bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1117 serge 965
//    struct mutex            cs_mutex;
966
    struct radeon_wb        wb;
1179 serge 967
	struct radeon_dummy_page	dummy_page;
1117 serge 968
    bool                gpu_lockup;
969
    bool                shutdown;
970
    bool                suspend;
1179 serge 971
	bool				need_dma32;
972
	bool				accel_working;
973
	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
974
	const struct firmware *me_fw;	/* all family ME firmware */
975
	const struct firmware *pfp_fw;	/* r6/700 PFP firmware */
1403 serge 976
	const struct firmware *rlc_fw;	/* r6/700 RLC firmware */
1179 serge 977
	struct r600_blit r600_blit;
1268 serge 978
	int msi_enabled; /* msi enabled */
1430 serge 979
	int num_crtc; /* number of crtcs */
1403 serge 980
 
981
	/* audio stuff */
982
//   struct timer_list   audio_timer;
983
	int			audio_channels;
984
	int			audio_rate;
985
	int			audio_bits_per_sample;
986
	uint8_t			audio_status_bits;
987
	uint8_t			audio_category_code;
1430 serge 988
 
989
	bool powered_down;
1117 serge 990
};
991
 
992
int radeon_device_init(struct radeon_device *rdev,
993
		       struct drm_device *ddev,
994
		       struct pci_dev *pdev,
995
		       uint32_t flags);
996
void radeon_device_fini(struct radeon_device *rdev);
997
int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
998
 
1179 serge 999
/* r600 blit */
1000
int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1001
void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1002
void r600_kms_blit_copy(struct radeon_device *rdev,
1003
			u64 src_gpu_addr, u64 dst_gpu_addr,
1004
			int size_bytes);
1117 serge 1005
 
1179 serge 1006
static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1117 serge 1007
{
1403 serge 1008
	if (reg < rdev->rmmio_size)
1179 serge 1009
		return readl(((void __iomem *)rdev->rmmio) + reg);
1010
	else {
1011
		writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1012
		return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1013
	}
1117 serge 1014
}
1015
 
1179 serge 1016
static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1117 serge 1017
{
1403 serge 1018
	if (reg < rdev->rmmio_size)
1179 serge 1019
		writel(v, ((void __iomem *)rdev->rmmio) + reg);
1020
	else {
1021
		writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1022
		writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1023
	}
1117 serge 1024
}
1025
 
1321 serge 1026
/*
1027
 * Cast helper
1028
 */
1029
#define to_radeon_fence(p) ((struct radeon_fence *)(p))
1117 serge 1030
 
1031
/*
1032
 * Registers read & write functions.
1033
 */
1034
#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1035
#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1179 serge 1036
#define RREG32(reg) r100_mm_rreg(rdev, (reg))
1037
#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1117 serge 1038
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1039
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1040
#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1041
#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1042
#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1043
#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1179 serge 1044
#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1045
#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1430 serge 1046
#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1047
#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1117 serge 1048
#define WREG32_P(reg, val, mask)				\
1049
	do {							\
1050
		uint32_t tmp_ = RREG32(reg);			\
1051
		tmp_ &= (mask);					\
1052
		tmp_ |= ((val) & ~(mask));			\
1053
		WREG32(reg, tmp_);				\
1054
	} while (0)
1055
#define WREG32_PLL_P(reg, val, mask)				\
1056
	do {							\
1057
		uint32_t tmp_ = RREG32_PLL(reg);		\
1058
		tmp_ &= (mask);					\
1059
		tmp_ |= ((val) & ~(mask));			\
1060
		WREG32_PLL(reg, tmp_);				\
1061
	} while (0)
1062
 
1179 serge 1063
/*
1064
 * Indirect registers accessor
1065
 */
1066
static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1067
{
1068
	uint32_t r;
1117 serge 1069
 
1179 serge 1070
	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1071
	r = RREG32(RADEON_PCIE_DATA);
1072
	return r;
1073
}
1074
 
1075
static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1076
{
1077
	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1078
	WREG32(RADEON_PCIE_DATA, (v));
1079
}
1080
 
1081
void r100_pll_errata_after_index(struct radeon_device *rdev);
1082
 
1083
 
1117 serge 1084
/*
1085
 * ASICs helpers.
1086
 */
1179 serge 1087
#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1088
			    (rdev->pdev->device == 0x5969))
1117 serge 1089
#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1090
        (rdev->family == CHIP_RV200) || \
1091
        (rdev->family == CHIP_RS100) || \
1092
        (rdev->family == CHIP_RS200) || \
1093
        (rdev->family == CHIP_RV250) || \
1094
        (rdev->family == CHIP_RV280) || \
1095
        (rdev->family == CHIP_RS300))
1096
#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  || \
1097
        (rdev->family == CHIP_RV350) ||         \
1098
        (rdev->family == CHIP_R350)  ||         \
1099
        (rdev->family == CHIP_RV380) ||         \
1100
        (rdev->family == CHIP_R420)  ||         \
1101
        (rdev->family == CHIP_R423)  ||         \
1102
        (rdev->family == CHIP_RV410) ||         \
1103
        (rdev->family == CHIP_RS400) ||         \
1104
        (rdev->family == CHIP_RS480))
1105
#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1106
#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1107
#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1430 serge 1108
#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1117 serge 1109
 
1110
/*
1111
 * BIOS helpers.
1112
 */
1113
#define RBIOS8(i) (rdev->bios[i])
1114
#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1115
#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1116
 
1117
int radeon_combios_init(struct radeon_device *rdev);
1118
void radeon_combios_fini(struct radeon_device *rdev);
1119
int radeon_atombios_init(struct radeon_device *rdev);
1120
void radeon_atombios_fini(struct radeon_device *rdev);
1121
 
1122
 
1123
/*
1124
 * RING helpers.
1125
 */
1126
static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1127
{
1128
#if DRM_DEBUG_CODE
1129
	if (rdev->cp.count_dw <= 0) {
1130
		DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1131
	}
1132
#endif
1133
	rdev->cp.ring[rdev->cp.wptr++] = v;
1134
	rdev->cp.wptr &= rdev->cp.ptr_mask;
1135
	rdev->cp.count_dw--;
1136
	rdev->cp.ring_free_dw--;
1137
}
1138
 
1139
 
1140
/*
1141
 * ASICs macro.
1142
 */
1143
#define radeon_init(rdev) (rdev)->asic->init((rdev))
1179 serge 1144
#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1145
#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1146
#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1117 serge 1147
#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1179 serge 1148
#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1117 serge 1149
#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
1150
#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1151
#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1179 serge 1152
#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1117 serge 1153
#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1179 serge 1154
#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1155
#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1117 serge 1156
#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1157
#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1179 serge 1158
#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1117 serge 1159
#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1160
#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1161
#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1162
#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1268 serge 1163
#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1117 serge 1164
#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1268 serge 1165
#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1321 serge 1166
#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1430 serge 1167
#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1117 serge 1168
#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1169
#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1179 serge 1170
#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1171
#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1172
#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1321 serge 1173
#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1174
#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1175
#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1176
#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1117 serge 1177
 
1179 serge 1178
/* Common functions */
1403 serge 1179
/* AGP */
1180
extern void radeon_agp_disable(struct radeon_device *rdev);
1179 serge 1181
extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1430 serge 1182
extern void radeon_gart_restore(struct radeon_device *rdev);
1179 serge 1183
extern int radeon_modeset_init(struct radeon_device *rdev);
1184
extern void radeon_modeset_fini(struct radeon_device *rdev);
1185
extern bool radeon_card_posted(struct radeon_device *rdev);
1321 serge 1186
extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1179 serge 1187
extern int radeon_clocks_init(struct radeon_device *rdev);
1188
extern void radeon_clocks_fini(struct radeon_device *rdev);
1189
extern void radeon_scratch_init(struct radeon_device *rdev);
1190
extern void radeon_surface_init(struct radeon_device *rdev);
1191
extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1221 serge 1192
extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1193
extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1321 serge 1194
extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1403 serge 1195
extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1430 serge 1196
extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1197
extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1198
extern int radeon_resume_kms(struct drm_device *dev);
1199
extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1117 serge 1200
 
1179 serge 1201
/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1202
struct r100_mc_save {
1203
	u32	GENMO_WT;
1204
	u32	CRTC_EXT_CNTL;
1205
	u32	CRTC_GEN_CNTL;
1206
	u32	CRTC2_GEN_CNTL;
1207
	u32	CUR_OFFSET;
1208
	u32	CUR2_OFFSET;
1209
};
1210
extern void r100_cp_disable(struct radeon_device *rdev);
1211
extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1212
extern void r100_cp_fini(struct radeon_device *rdev);
1213
extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
1214
extern int r100_pci_gart_init(struct radeon_device *rdev);
1215
extern void r100_pci_gart_fini(struct radeon_device *rdev);
1216
extern int r100_pci_gart_enable(struct radeon_device *rdev);
1217
extern void r100_pci_gart_disable(struct radeon_device *rdev);
1218
extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
1219
extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1220
extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1221
extern void r100_ib_fini(struct radeon_device *rdev);
1222
extern int r100_ib_init(struct radeon_device *rdev);
1223
extern void r100_irq_disable(struct radeon_device *rdev);
1224
extern int r100_irq_set(struct radeon_device *rdev);
1225
extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1226
extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
1227
extern void r100_vram_init_sizes(struct radeon_device *rdev);
1228
extern void r100_wb_disable(struct radeon_device *rdev);
1229
extern void r100_wb_fini(struct radeon_device *rdev);
1230
extern int r100_wb_init(struct radeon_device *rdev);
1221 serge 1231
extern void r100_hdp_reset(struct radeon_device *rdev);
1232
extern int r100_rb2d_reset(struct radeon_device *rdev);
1233
extern int r100_cp_reset(struct radeon_device *rdev);
1234
extern void r100_vga_render_disable(struct radeon_device *rdev);
1235
extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1236
						struct radeon_cs_packet *pkt,
1321 serge 1237
						struct radeon_bo *robj);
1221 serge 1238
extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1239
				struct radeon_cs_packet *pkt,
1240
				const unsigned *auth, unsigned n,
1241
				radeon_packet0_check_t check);
1242
extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1243
				struct radeon_cs_packet *pkt,
1244
				unsigned idx);
1321 serge 1245
extern void r100_enable_bm(struct radeon_device *rdev);
1246
extern void r100_set_common_regs(struct radeon_device *rdev);
1179 serge 1247
 
1221 serge 1248
/* rv200,rv250,rv280 */
1249
extern void r200_set_safe_registers(struct radeon_device *rdev);
1250
 
1179 serge 1251
/* r300,r350,rv350,rv370,rv380 */
1252
extern void r300_set_reg_safe(struct radeon_device *rdev);
1253
extern void r300_mc_program(struct radeon_device *rdev);
1430 serge 1254
extern void r300_mc_init(struct radeon_device *rdev);
1221 serge 1255
extern void r300_clock_startup(struct radeon_device *rdev);
1256
extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1179 serge 1257
extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1258
extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1259
extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1260
extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1261
 
1262
/* r420,r423,rv410 */
1263
extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1264
extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1265
extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1221 serge 1266
extern void r420_pipes_init(struct radeon_device *rdev);
1179 serge 1267
 
1268
/* rv515 */
1221 serge 1269
struct rv515_mc_save {
1270
	u32 d1vga_control;
1271
	u32 d2vga_control;
1272
	u32 vga_render_control;
1273
	u32 vga_hdp_control;
1274
	u32 d1crtc_control;
1275
	u32 d2crtc_control;
1276
};
1179 serge 1277
extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1221 serge 1278
extern void rv515_vga_render_disable(struct radeon_device *rdev);
1279
extern void rv515_set_safe_registers(struct radeon_device *rdev);
1280
extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1281
extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1282
extern void rv515_clock_startup(struct radeon_device *rdev);
1283
extern void rv515_debugfs(struct radeon_device *rdev);
1284
extern int rv515_suspend(struct radeon_device *rdev);
1179 serge 1285
 
1221 serge 1286
/* rs400 */
1287
extern int rs400_gart_init(struct radeon_device *rdev);
1288
extern int rs400_gart_enable(struct radeon_device *rdev);
1289
extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1290
extern void rs400_gart_disable(struct radeon_device *rdev);
1291
extern void rs400_gart_fini(struct radeon_device *rdev);
1292
 
1293
/* rs600 */
1294
extern void rs600_set_safe_registers(struct radeon_device *rdev);
1295
extern int rs600_irq_set(struct radeon_device *rdev);
1296
extern void rs600_irq_disable(struct radeon_device *rdev);
1297
 
1179 serge 1298
/* rs690, rs740 */
1299
extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1300
					struct drm_display_mode *mode1,
1301
					struct drm_display_mode *mode2);
1302
 
1303
/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1430 serge 1304
extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1179 serge 1305
extern bool r600_card_posted(struct radeon_device *rdev);
1306
extern void r600_cp_stop(struct radeon_device *rdev);
1307
extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1308
extern int r600_cp_resume(struct radeon_device *rdev);
1404 serge 1309
extern void r600_cp_fini(struct radeon_device *rdev);
1179 serge 1310
extern int r600_count_pipe_bits(uint32_t val);
1311
extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1312
extern int r600_pcie_gart_init(struct radeon_device *rdev);
1313
extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1314
extern int r600_ib_test(struct radeon_device *rdev);
1315
extern int r600_ring_test(struct radeon_device *rdev);
1316
extern void r600_wb_fini(struct radeon_device *rdev);
1221 serge 1317
extern int r600_wb_enable(struct radeon_device *rdev);
1318
extern void r600_wb_disable(struct radeon_device *rdev);
1179 serge 1319
extern void r600_scratch_init(struct radeon_device *rdev);
1320
extern int r600_blit_init(struct radeon_device *rdev);
1321
extern void r600_blit_fini(struct radeon_device *rdev);
1321 serge 1322
extern int r600_init_microcode(struct radeon_device *rdev);
1179 serge 1323
extern int r600_gpu_reset(struct radeon_device *rdev);
1321 serge 1324
/* r600 irq */
1325
extern int r600_irq_init(struct radeon_device *rdev);
1326
extern void r600_irq_fini(struct radeon_device *rdev);
1327
extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1328
extern int r600_irq_set(struct radeon_device *rdev);
1403 serge 1329
extern void r600_irq_suspend(struct radeon_device *rdev);
1330
/* r600 audio */
1331
extern int r600_audio_init(struct radeon_device *rdev);
1332
extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1333
extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1334
extern void r600_audio_fini(struct radeon_device *rdev);
1335
extern void r600_hdmi_init(struct drm_encoder *encoder);
1336
extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
1337
extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1338
extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1339
extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
1340
					    int channels,
1341
					    int rate,
1342
					    int bps,
1343
					    uint8_t status_bits,
1344
					    uint8_t category_code);
1179 serge 1345
 
1430 serge 1346
/* evergreen */
1347
struct evergreen_mc_save {
1348
	u32 vga_control[6];
1349
	u32 vga_render_control;
1350
	u32 vga_hdp_control;
1351
	u32 crtc_control[6];
1352
};
1353
 
1321 serge 1354
#include "radeon_object.h"
1179 serge 1355
 
1117 serge 1356
#define DRM_UDELAY(d)           udelay(d)
1357
 
1358
resource_size_t
1359
drm_get_resource_start(struct drm_device *dev, unsigned int resource);
1360
resource_size_t
1361
drm_get_resource_len(struct drm_device *dev, unsigned int resource);
1362
 
1239 serge 1363
bool set_mode(struct drm_device *dev, struct drm_connector *connector,
1403 serge 1364
              videomode_t *mode, bool strict);
1117 serge 1365
 
1179 serge 1366
 
1117 serge 1367
#endif