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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #ifndef __RADEON_H__ |
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29 | #define __RADEON_H__ |
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30 | |||
31 | /* TODO: Here are things that needs to be done : |
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32 | * - surface allocator & initializer : (bit like scratch reg) should |
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33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
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34 | * related to surface |
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35 | * - WB : write back stuff (do it bit like scratch reg things) |
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36 | * - Vblank : look at Jesse's rework and what we should do |
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37 | * - r600/r700: gart & cp |
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38 | * - cs : clean cs ioctl use bitmap & things like that. |
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39 | * - power management stuff |
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40 | * - Barrier in gart code |
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41 | * - Unmappabled vram ? |
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42 | * - TESTING, TESTING, TESTING |
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43 | */ |
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44 | |||
1221 | serge | 45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various |
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47 | * reasons even thought we work hard to make it works on most |
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48 | * configurations. In order to still have a working userspace in such |
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49 | * situation the init path must succeed up to the memory controller |
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50 | * initialization point. Failure before this point are considered as |
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51 | * fatal error. Here is the init callchain : |
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52 | * radeon_device_init perform common structure, mutex initialization |
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53 | * asic_init setup the GPU memory layout and perform all |
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54 | * one time initialization (failure in this |
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55 | * function are considered fatal) |
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56 | * asic_startup setup the GPU acceleration, in order to |
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57 | * follow guideline the first thing this |
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58 | * function should do is setting the GPU |
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59 | * memory controller (only MC setup failure |
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60 | * are considered as fatal) |
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61 | */ |
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62 | |||
1321 | serge | 63 | #include |
1221 | serge | 64 | |
1321 | serge | 65 | #include |
66 | #include |
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1221 | serge | 67 | |
1321 | serge | 68 | #include |
69 | #include |
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70 | #include |
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71 | #include |
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1221 | serge | 72 | |
1117 | serge | 73 | |
1120 | serge | 74 | #include |
1117 | serge | 75 | |
1120 | serge | 76 | #include |
1123 | serge | 77 | #include "drm_edid.h" |
1179 | serge | 78 | |
79 | #include "radeon_family.h" |
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1117 | serge | 80 | #include "radeon_mode.h" |
81 | #include "radeon_reg.h" |
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82 | |||
83 | #include |
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84 | |||
1179 | serge | 85 | /* |
86 | * Modules parameters. |
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87 | */ |
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88 | extern int radeon_no_wb; |
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1123 | serge | 89 | extern int radeon_modeset; |
1117 | serge | 90 | extern int radeon_dynclks; |
1123 | serge | 91 | extern int radeon_r4xx_atom; |
1128 | serge | 92 | extern int radeon_agpmode; |
93 | extern int radeon_vram_limit; |
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1117 | serge | 94 | extern int radeon_gart_size; |
1128 | serge | 95 | extern int radeon_benchmarking; |
1179 | serge | 96 | extern int radeon_testing; |
1123 | serge | 97 | extern int radeon_connector_table; |
1179 | serge | 98 | extern int radeon_tv; |
1321 | serge | 99 | extern int radeon_new_pll; |
1403 | serge | 100 | extern int radeon_audio; |
1117 | serge | 101 | |
1233 | serge | 102 | typedef struct |
103 | { |
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104 | int width; |
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105 | int height; |
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106 | int bpp; |
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107 | int freq; |
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1321 | serge | 108 | }videomode_t; |
1179 | serge | 109 | |
110 | static inline uint8_t __raw_readb(const volatile void __iomem *addr) |
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111 | { |
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112 | return *(const volatile uint8_t __force *) addr; |
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113 | } |
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114 | |||
115 | static inline uint16_t __raw_readw(const volatile void __iomem *addr) |
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116 | { |
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117 | return *(const volatile uint16_t __force *) addr; |
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118 | } |
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119 | |||
120 | static inline uint32_t __raw_readl(const volatile void __iomem *addr) |
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121 | { |
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122 | return *(const volatile uint32_t __force *) addr; |
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123 | } |
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124 | |||
125 | #define readb __raw_readb |
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126 | #define readw __raw_readw |
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127 | #define readl __raw_readl |
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128 | |||
129 | |||
130 | |||
131 | static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr) |
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132 | { |
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133 | *(volatile uint8_t __force *) addr = b; |
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134 | } |
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135 | |||
136 | static inline void __raw_writew(uint16_t b, volatile void __iomem *addr) |
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137 | { |
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138 | *(volatile uint16_t __force *) addr = b; |
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139 | } |
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140 | |||
141 | static inline void __raw_writel(uint32_t b, volatile void __iomem *addr) |
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142 | { |
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143 | *(volatile uint32_t __force *) addr = b; |
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144 | } |
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145 | |||
146 | static inline void __raw_writeq(__u64 b, volatile void __iomem *addr) |
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147 | { |
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148 | *(volatile __u64 *)addr = b; |
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149 | } |
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150 | |||
151 | #define writeb __raw_writeb |
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152 | #define writew __raw_writew |
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153 | #define writel __raw_writel |
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154 | #define writeq __raw_writeq |
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155 | |||
156 | |||
1117 | serge | 157 | /* |
158 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
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159 | * symbol; |
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160 | */ |
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1120 | serge | 161 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
1428 | serge | 162 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
1120 | serge | 163 | #define RADEON_IB_POOL_SIZE 16 |
1117 | serge | 164 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
1120 | serge | 165 | #define RADEONFB_CONN_LIMIT 4 |
1179 | serge | 166 | #define RADEON_BIOS_NUM_SCRATCH 8 |
1117 | serge | 167 | |
168 | /* |
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169 | * Errata workarounds. |
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170 | */ |
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171 | enum radeon_pll_errata { |
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172 | CHIP_ERRATA_R300_CG = 0x00000001, |
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173 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
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174 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
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175 | }; |
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176 | |||
177 | |||
178 | struct radeon_device; |
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179 | |||
180 | |||
181 | /* |
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182 | * BIOS. |
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183 | */ |
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184 | bool radeon_get_bios(struct radeon_device *rdev); |
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185 | |||
1179 | serge | 186 | |
1117 | serge | 187 | /* |
1179 | serge | 188 | * Dummy page |
189 | */ |
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190 | struct radeon_dummy_page { |
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191 | struct page *page; |
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192 | dma_addr_t addr; |
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193 | }; |
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194 | int radeon_dummy_page_init(struct radeon_device *rdev); |
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195 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
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196 | |||
197 | |||
198 | /* |
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1117 | serge | 199 | * Clocks |
200 | */ |
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201 | struct radeon_clock { |
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202 | struct radeon_pll p1pll; |
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203 | struct radeon_pll p2pll; |
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204 | struct radeon_pll spll; |
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205 | struct radeon_pll mpll; |
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206 | /* 10 Khz units */ |
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207 | uint32_t default_mclk; |
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208 | uint32_t default_sclk; |
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209 | }; |
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210 | |||
1268 | serge | 211 | /* |
212 | * Power management |
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213 | */ |
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214 | int radeon_pm_init(struct radeon_device *rdev); |
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1179 | serge | 215 | |
1117 | serge | 216 | /* |
217 | * Fences. |
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218 | */ |
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219 | struct radeon_fence_driver { |
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220 | uint32_t scratch_reg; |
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1321 | serge | 221 | atomic_t seq; |
1117 | serge | 222 | uint32_t last_seq; |
223 | unsigned long count_timeout; |
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224 | // wait_queue_head_t queue; |
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1321 | serge | 225 | rwlock_t lock; |
1120 | serge | 226 | struct list_head created; |
227 | struct list_head emited; |
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228 | struct list_head signaled; |
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1403 | serge | 229 | bool initialized; |
1117 | serge | 230 | }; |
231 | |||
232 | struct radeon_fence { |
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233 | struct radeon_device *rdev; |
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1321 | serge | 234 | struct kref kref; |
1120 | serge | 235 | struct list_head list; |
1117 | serge | 236 | /* protected by radeon_fence.lock */ |
237 | uint32_t seq; |
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238 | unsigned long timeout; |
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239 | bool emited; |
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240 | bool signaled; |
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241 | }; |
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242 | |||
243 | int radeon_fence_driver_init(struct radeon_device *rdev); |
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244 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
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245 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); |
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246 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
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247 | void radeon_fence_process(struct radeon_device *rdev); |
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248 | bool radeon_fence_signaled(struct radeon_fence *fence); |
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249 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
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250 | int radeon_fence_wait_next(struct radeon_device *rdev); |
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251 | int radeon_fence_wait_last(struct radeon_device *rdev); |
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252 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
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253 | void radeon_fence_unref(struct radeon_fence **fence); |
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254 | |||
1179 | serge | 255 | /* |
256 | * Tiling registers |
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257 | */ |
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258 | struct radeon_surface_reg { |
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1321 | serge | 259 | struct radeon_bo *bo; |
1179 | serge | 260 | }; |
1117 | serge | 261 | |
1179 | serge | 262 | #define RADEON_GEM_MAX_SURFACES 8 |
263 | |||
1117 | serge | 264 | /* |
1321 | serge | 265 | * TTM. |
1117 | serge | 266 | */ |
1321 | serge | 267 | struct radeon_mman { |
268 | struct ttm_bo_global_ref bo_global_ref; |
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269 | struct ttm_global_reference mem_global_ref; |
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1403 | serge | 270 | struct ttm_bo_device bdev; |
1321 | serge | 271 | bool mem_global_referenced; |
1403 | serge | 272 | bool initialized; |
1321 | serge | 273 | }; |
1117 | serge | 274 | |
1321 | serge | 275 | struct radeon_bo { |
276 | /* Protected by gem.mutex */ |
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277 | struct list_head list; |
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278 | /* Protected by tbo.reserved */ |
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279 | u32 placements[3]; |
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280 | struct ttm_placement placement; |
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281 | struct ttm_buffer_object tbo; |
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282 | struct ttm_bo_kmap_obj kmap; |
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1404 | serge | 283 | unsigned pin_count; |
284 | void *kptr; |
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285 | u32 cpu_addr; |
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286 | u32 tiling_flags; |
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287 | u32 pitch; |
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288 | int surface_reg; |
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1321 | serge | 289 | /* Constant after initialization */ |
290 | struct radeon_device *rdev; |
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291 | struct drm_gem_object *gobj; |
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1404 | serge | 292 | u32 domain; |
1321 | serge | 293 | }; |
294 | |||
295 | struct radeon_bo_list { |
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1120 | serge | 296 | struct list_head list; |
1321 | serge | 297 | struct radeon_bo *bo; |
1117 | serge | 298 | uint64_t gpu_offset; |
299 | unsigned rdomain; |
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300 | unsigned wdomain; |
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1321 | serge | 301 | u32 tiling_flags; |
1117 | serge | 302 | }; |
303 | |||
1123 | serge | 304 | /* |
305 | * GEM objects. |
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306 | */ |
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307 | struct radeon_gem { |
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308 | struct list_head objects; |
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309 | }; |
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1117 | serge | 310 | |
1126 | serge | 311 | int radeon_gem_init(struct radeon_device *rdev); |
312 | void radeon_gem_fini(struct radeon_device *rdev); |
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313 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
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314 | int alignment, int initial_domain, |
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315 | bool discardable, bool kernel, |
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316 | struct drm_gem_object **obj); |
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317 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
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318 | uint64_t *gpu_addr); |
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319 | void radeon_gem_object_unpin(struct drm_gem_object *obj); |
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1117 | serge | 320 | |
321 | |||
322 | /* |
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323 | * GART structures, functions & helpers |
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324 | */ |
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325 | struct radeon_mc; |
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326 | |||
327 | struct radeon_gart_table_ram { |
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328 | volatile uint32_t *ptr; |
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329 | }; |
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330 | |||
331 | struct radeon_gart_table_vram { |
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1321 | serge | 332 | struct radeon_bo *robj; |
1117 | serge | 333 | volatile uint32_t *ptr; |
334 | }; |
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335 | |||
336 | union radeon_gart_table { |
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337 | struct radeon_gart_table_ram ram; |
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338 | struct radeon_gart_table_vram vram; |
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339 | }; |
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340 | |||
1268 | serge | 341 | #define RADEON_GPU_PAGE_SIZE 4096 |
342 | |||
1117 | serge | 343 | struct radeon_gart { |
344 | dma_addr_t table_addr; |
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345 | unsigned num_gpu_pages; |
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346 | unsigned num_cpu_pages; |
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347 | unsigned table_size; |
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348 | union radeon_gart_table table; |
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349 | struct page **pages; |
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350 | dma_addr_t *pages_addr; |
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351 | bool ready; |
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352 | }; |
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353 | |||
354 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
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355 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
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356 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
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357 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
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358 | int radeon_gart_init(struct radeon_device *rdev); |
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359 | void radeon_gart_fini(struct radeon_device *rdev); |
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360 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
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361 | int pages); |
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1120 | serge | 362 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
363 | int pages, u32_t *pagelist); |
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1117 | serge | 364 | |
365 | |||
366 | /* |
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367 | * GPU MC structures, functions & helpers |
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368 | */ |
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369 | struct radeon_mc { |
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370 | resource_size_t aper_size; |
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371 | resource_size_t aper_base; |
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372 | resource_size_t agp_base; |
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1179 | serge | 373 | /* for some chips with <= 32MB we need to lie |
374 | * about vram size near mc fb location */ |
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375 | u64 mc_vram_size; |
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376 | u64 gtt_location; |
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377 | u64 gtt_size; |
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378 | u64 gtt_start; |
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379 | u64 gtt_end; |
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380 | u64 vram_location; |
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381 | u64 vram_start; |
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382 | u64 vram_end; |
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1117 | serge | 383 | unsigned vram_width; |
1179 | serge | 384 | u64 real_vram_size; |
1117 | serge | 385 | int vram_mtrr; |
386 | bool vram_is_ddr; |
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1403 | serge | 387 | bool igp_sideport_enabled; |
1117 | serge | 388 | }; |
389 | |||
390 | int radeon_mc_setup(struct radeon_device *rdev); |
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1403 | serge | 391 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
392 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
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1117 | serge | 393 | |
394 | /* |
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395 | * GPU scratch registers structures, functions & helpers |
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396 | */ |
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397 | struct radeon_scratch { |
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398 | unsigned num_reg; |
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399 | bool free[32]; |
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400 | uint32_t reg[32]; |
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401 | }; |
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402 | |||
403 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
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404 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
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405 | |||
406 | |||
407 | /* |
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408 | * IRQS. |
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409 | */ |
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410 | struct radeon_irq { |
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411 | bool installed; |
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412 | bool sw_int; |
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413 | /* FIXME: use a define max crtc rather than hardcode it */ |
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414 | bool crtc_vblank_int[2]; |
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1321 | serge | 415 | /* FIXME: use defines for max hpd/dacs */ |
416 | bool hpd[6]; |
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417 | spinlock_t sw_lock; |
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418 | int sw_refcount; |
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1117 | serge | 419 | }; |
420 | |||
421 | int radeon_irq_kms_init(struct radeon_device *rdev); |
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422 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
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1321 | serge | 423 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); |
424 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); |
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1117 | serge | 425 | |
426 | /* |
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427 | * CP & ring. |
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428 | */ |
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429 | struct radeon_ib { |
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1403 | serge | 430 | struct list_head list; |
1428 | serge | 431 | unsigned idx; |
1403 | serge | 432 | uint64_t gpu_addr; |
1117 | serge | 433 | struct radeon_fence *fence; |
1403 | serge | 434 | uint32_t *ptr; |
435 | uint32_t length_dw; |
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1428 | serge | 436 | bool free; |
1117 | serge | 437 | }; |
438 | |||
1179 | serge | 439 | /* |
440 | * locking - |
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441 | * mutex protects scheduled_ibs, ready, alloc_bm |
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442 | */ |
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1117 | serge | 443 | struct radeon_ib_pool { |
1403 | serge | 444 | // struct mutex mutex; |
1321 | serge | 445 | struct radeon_bo *robj; |
1117 | serge | 446 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
1403 | serge | 447 | bool ready; |
1428 | serge | 448 | unsigned head_id; |
1117 | serge | 449 | }; |
450 | |||
451 | struct radeon_cp { |
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1321 | serge | 452 | struct radeon_bo *ring_obj; |
1117 | serge | 453 | volatile uint32_t *ring; |
1403 | serge | 454 | unsigned rptr; |
455 | unsigned wptr; |
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456 | unsigned wptr_old; |
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457 | unsigned ring_size; |
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458 | unsigned ring_free_dw; |
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459 | int count_dw; |
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460 | uint64_t gpu_addr; |
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461 | uint32_t align_mask; |
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462 | uint32_t ptr_mask; |
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1117 | serge | 463 | // struct mutex mutex; |
1403 | serge | 464 | bool ready; |
1117 | serge | 465 | }; |
466 | |||
1321 | serge | 467 | /* |
468 | * R6xx+ IH ring |
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469 | */ |
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470 | struct r600_ih { |
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471 | struct radeon_bo *ring_obj; |
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472 | volatile uint32_t *ring; |
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473 | unsigned rptr; |
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474 | unsigned wptr; |
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475 | unsigned wptr_old; |
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476 | unsigned ring_size; |
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477 | uint64_t gpu_addr; |
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478 | uint32_t ptr_mask; |
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479 | spinlock_t lock; |
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480 | bool enabled; |
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481 | }; |
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482 | |||
1179 | serge | 483 | struct r600_blit { |
1321 | serge | 484 | struct radeon_bo *shader_obj; |
1179 | serge | 485 | u64 shader_gpu_addr; |
486 | u32 vs_offset, ps_offset; |
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487 | u32 state_offset; |
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488 | u32 state_len; |
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489 | u32 vb_used, vb_total; |
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490 | struct radeon_ib *vb_ib; |
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491 | }; |
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492 | |||
1117 | serge | 493 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
494 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
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495 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
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496 | int radeon_ib_pool_init(struct radeon_device *rdev); |
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497 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
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498 | int radeon_ib_test(struct radeon_device *rdev); |
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499 | /* Ring access between begin & end cannot sleep */ |
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500 | void radeon_ring_free_size(struct radeon_device *rdev); |
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501 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
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502 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
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503 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
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504 | int radeon_ring_test(struct radeon_device *rdev); |
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505 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
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506 | void radeon_ring_fini(struct radeon_device *rdev); |
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507 | |||
508 | |||
509 | /* |
||
510 | * CS. |
||
511 | */ |
||
512 | struct radeon_cs_reloc { |
||
513 | // struct drm_gem_object *gobj; |
||
1321 | serge | 514 | struct radeon_bo *robj; |
515 | // struct radeon_bo_list lobj; |
||
1403 | serge | 516 | uint32_t handle; |
517 | uint32_t flags; |
||
1117 | serge | 518 | }; |
519 | |||
520 | struct radeon_cs_chunk { |
||
521 | uint32_t chunk_id; |
||
522 | uint32_t length_dw; |
||
1221 | serge | 523 | int kpage_idx[2]; |
524 | uint32_t *kpage[2]; |
||
1117 | serge | 525 | uint32_t *kdata; |
1221 | serge | 526 | void __user *user_ptr; |
527 | int last_copied_page; |
||
528 | int last_page_index; |
||
1117 | serge | 529 | }; |
530 | |||
531 | struct radeon_cs_parser { |
||
532 | struct radeon_device *rdev; |
||
533 | // struct drm_file *filp; |
||
534 | /* chunks */ |
||
535 | unsigned nchunks; |
||
536 | struct radeon_cs_chunk *chunks; |
||
537 | uint64_t *chunks_array; |
||
538 | /* IB */ |
||
539 | unsigned idx; |
||
540 | /* relocations */ |
||
541 | unsigned nrelocs; |
||
542 | struct radeon_cs_reloc *relocs; |
||
543 | struct radeon_cs_reloc **relocs_ptr; |
||
1120 | serge | 544 | struct list_head validated; |
1117 | serge | 545 | /* indices of various chunks */ |
546 | int chunk_ib_idx; |
||
547 | int chunk_relocs_idx; |
||
548 | struct radeon_ib *ib; |
||
549 | void *track; |
||
1179 | serge | 550 | unsigned family; |
1221 | serge | 551 | int parser_error; |
1117 | serge | 552 | }; |
553 | |||
1221 | serge | 554 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
555 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
||
556 | |||
557 | |||
558 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
||
559 | { |
||
560 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
||
561 | u32 pg_idx, pg_offset; |
||
562 | u32 idx_value = 0; |
||
563 | int new_page; |
||
564 | |||
565 | pg_idx = (idx * 4) / PAGE_SIZE; |
||
566 | pg_offset = (idx * 4) % PAGE_SIZE; |
||
567 | |||
568 | if (ibc->kpage_idx[0] == pg_idx) |
||
569 | return ibc->kpage[0][pg_offset/4]; |
||
570 | if (ibc->kpage_idx[1] == pg_idx) |
||
571 | return ibc->kpage[1][pg_offset/4]; |
||
572 | |||
573 | new_page = radeon_cs_update_pages(p, pg_idx); |
||
574 | if (new_page < 0) { |
||
575 | p->parser_error = new_page; |
||
576 | return 0; |
||
577 | } |
||
578 | |||
579 | idx_value = ibc->kpage[new_page][pg_offset/4]; |
||
580 | return idx_value; |
||
581 | } |
||
582 | |||
1117 | serge | 583 | struct radeon_cs_packet { |
584 | unsigned idx; |
||
585 | unsigned type; |
||
586 | unsigned reg; |
||
587 | unsigned opcode; |
||
588 | int count; |
||
589 | unsigned one_reg_wr; |
||
590 | }; |
||
591 | |||
592 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
||
593 | struct radeon_cs_packet *pkt, |
||
594 | unsigned idx, unsigned reg); |
||
595 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
||
596 | struct radeon_cs_packet *pkt); |
||
597 | |||
598 | |||
599 | /* |
||
600 | * AGP |
||
601 | */ |
||
602 | int radeon_agp_init(struct radeon_device *rdev); |
||
1321 | serge | 603 | void radeon_agp_resume(struct radeon_device *rdev); |
1117 | serge | 604 | void radeon_agp_fini(struct radeon_device *rdev); |
605 | |||
606 | |||
607 | /* |
||
608 | * Writeback |
||
609 | */ |
||
610 | struct radeon_wb { |
||
1321 | serge | 611 | struct radeon_bo *wb_obj; |
1117 | serge | 612 | volatile uint32_t *wb; |
613 | uint64_t gpu_addr; |
||
614 | }; |
||
615 | |||
1179 | serge | 616 | /** |
617 | * struct radeon_pm - power management datas |
||
618 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
||
619 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
||
620 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
||
621 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
||
622 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
||
623 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
||
624 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
||
625 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
||
626 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
||
627 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) |
||
628 | * @needed_bandwidth: current bandwidth needs |
||
629 | * |
||
630 | * It keeps track of various data needed to take powermanagement decision. |
||
631 | * Bandwith need is used to determine minimun clock of the GPU and memory. |
||
632 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
||
633 | * (type of memory, bus size, efficiency, ...) |
||
634 | */ |
||
635 | struct radeon_pm { |
||
636 | fixed20_12 max_bandwidth; |
||
637 | fixed20_12 igp_sideport_mclk; |
||
638 | fixed20_12 igp_system_mclk; |
||
639 | fixed20_12 igp_ht_link_clk; |
||
640 | fixed20_12 igp_ht_link_width; |
||
641 | fixed20_12 k8_bandwidth; |
||
642 | fixed20_12 sideport_bandwidth; |
||
643 | fixed20_12 ht_bandwidth; |
||
644 | fixed20_12 core_bandwidth; |
||
645 | fixed20_12 sclk; |
||
646 | fixed20_12 needed_bandwidth; |
||
647 | }; |
||
1117 | serge | 648 | |
649 | /* |
||
650 | * ASIC specific functions. |
||
651 | */ |
||
652 | struct radeon_asic { |
||
653 | int (*init)(struct radeon_device *rdev); |
||
1179 | serge | 654 | void (*fini)(struct radeon_device *rdev); |
655 | int (*resume)(struct radeon_device *rdev); |
||
656 | int (*suspend)(struct radeon_device *rdev); |
||
657 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
||
1117 | serge | 658 | int (*gpu_reset)(struct radeon_device *rdev); |
659 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
||
660 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
||
661 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
||
662 | void (*cp_fini)(struct radeon_device *rdev); |
||
663 | void (*cp_disable)(struct radeon_device *rdev); |
||
1179 | serge | 664 | void (*cp_commit)(struct radeon_device *rdev); |
1117 | serge | 665 | void (*ring_start)(struct radeon_device *rdev); |
1179 | serge | 666 | int (*ring_test)(struct radeon_device *rdev); |
667 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
||
1117 | serge | 668 | int (*irq_set)(struct radeon_device *rdev); |
669 | int (*irq_process)(struct radeon_device *rdev); |
||
1179 | serge | 670 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
1117 | serge | 671 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
672 | int (*cs_parse)(struct radeon_cs_parser *p); |
||
673 | int (*copy_blit)(struct radeon_device *rdev, |
||
674 | uint64_t src_offset, |
||
675 | uint64_t dst_offset, |
||
676 | unsigned num_pages, |
||
677 | struct radeon_fence *fence); |
||
678 | int (*copy_dma)(struct radeon_device *rdev, |
||
679 | uint64_t src_offset, |
||
680 | uint64_t dst_offset, |
||
681 | unsigned num_pages, |
||
682 | struct radeon_fence *fence); |
||
683 | int (*copy)(struct radeon_device *rdev, |
||
684 | uint64_t src_offset, |
||
685 | uint64_t dst_offset, |
||
686 | unsigned num_pages, |
||
687 | struct radeon_fence *fence); |
||
1268 | serge | 688 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1117 | serge | 689 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
1268 | serge | 690 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
1117 | serge | 691 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
692 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
||
693 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
||
1179 | serge | 694 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
695 | uint32_t tiling_flags, uint32_t pitch, |
||
696 | uint32_t offset, uint32_t obj_size); |
||
697 | int (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
||
698 | void (*bandwidth_update)(struct radeon_device *rdev); |
||
1321 | serge | 699 | void (*hpd_init)(struct radeon_device *rdev); |
700 | void (*hpd_fini)(struct radeon_device *rdev); |
||
701 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
||
702 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
||
1404 | serge | 703 | /* ioctl hw specific callback. Some hw might want to perform special |
704 | * operation on specific ioctl. For instance on wait idle some hw |
||
705 | * might want to perform and HDP flush through MMIO as it seems that |
||
706 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed |
||
707 | * through ring. |
||
708 | */ |
||
709 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
||
1117 | serge | 710 | }; |
711 | |||
1179 | serge | 712 | /* |
713 | * Asic structures |
||
714 | */ |
||
715 | struct r100_asic { |
||
716 | const unsigned *reg_safe_bm; |
||
717 | unsigned reg_safe_bm_size; |
||
1403 | serge | 718 | u32 hdp_cntl; |
1179 | serge | 719 | }; |
720 | |||
721 | struct r300_asic { |
||
722 | const unsigned *reg_safe_bm; |
||
723 | unsigned reg_safe_bm_size; |
||
1403 | serge | 724 | u32 resync_scratch; |
725 | u32 hdp_cntl; |
||
1179 | serge | 726 | }; |
727 | |||
728 | struct r600_asic { |
||
729 | unsigned max_pipes; |
||
730 | unsigned max_tile_pipes; |
||
731 | unsigned max_simds; |
||
732 | unsigned max_backends; |
||
733 | unsigned max_gprs; |
||
734 | unsigned max_threads; |
||
735 | unsigned max_stack_entries; |
||
736 | unsigned max_hw_contexts; |
||
737 | unsigned max_gs_threads; |
||
738 | unsigned sx_max_export_size; |
||
739 | unsigned sx_max_export_pos_size; |
||
740 | unsigned sx_max_export_smx_size; |
||
741 | unsigned sq_num_cf_insts; |
||
742 | }; |
||
743 | |||
744 | struct rv770_asic { |
||
745 | unsigned max_pipes; |
||
746 | unsigned max_tile_pipes; |
||
747 | unsigned max_simds; |
||
748 | unsigned max_backends; |
||
749 | unsigned max_gprs; |
||
750 | unsigned max_threads; |
||
751 | unsigned max_stack_entries; |
||
752 | unsigned max_hw_contexts; |
||
753 | unsigned max_gs_threads; |
||
754 | unsigned sx_max_export_size; |
||
755 | unsigned sx_max_export_pos_size; |
||
756 | unsigned sx_max_export_smx_size; |
||
757 | unsigned sq_num_cf_insts; |
||
758 | unsigned sx_num_of_sets; |
||
759 | unsigned sc_prim_fifo_size; |
||
760 | unsigned sc_hiz_tile_fifo_size; |
||
761 | unsigned sc_earlyz_tile_fifo_fize; |
||
762 | }; |
||
763 | |||
1117 | serge | 764 | union radeon_asic_config { |
765 | struct r300_asic r300; |
||
1179 | serge | 766 | struct r100_asic r100; |
767 | struct r600_asic r600; |
||
768 | struct rv770_asic rv770; |
||
1117 | serge | 769 | }; |
770 | |||
771 | |||
772 | /* |
||
1179 | serge | 773 | |
774 | |||
775 | |||
776 | |||
1117 | serge | 777 | /* |
778 | * Core structure, functions and helpers. |
||
779 | */ |
||
780 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
||
781 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
||
782 | |||
783 | struct radeon_device { |
||
1413 | serge | 784 | struct device *dev; |
1117 | serge | 785 | struct drm_device *ddev; |
786 | struct pci_dev *pdev; |
||
787 | /* ASIC */ |
||
788 | union radeon_asic_config config; |
||
789 | enum radeon_family family; |
||
790 | unsigned long flags; |
||
791 | int usec_timeout; |
||
792 | enum radeon_pll_errata pll_errata; |
||
793 | int num_gb_pipes; |
||
1413 | serge | 794 | int num_z_pipes; |
1117 | serge | 795 | int disp_priority; |
796 | /* BIOS */ |
||
797 | uint8_t *bios; |
||
798 | bool is_atom_bios; |
||
799 | uint16_t bios_header_start; |
||
1413 | serge | 800 | struct radeon_bo *stollen_vga_memory; |
1126 | serge | 801 | struct fb_info *fbdev_info; |
1413 | serge | 802 | struct radeon_bo *fbdev_rbo; |
1117 | serge | 803 | struct radeon_framebuffer *fbdev_rfb; |
804 | /* Register mmio */ |
||
805 | unsigned long rmmio_base; |
||
806 | unsigned long rmmio_size; |
||
807 | void *rmmio; |
||
1120 | serge | 808 | radeon_rreg_t mc_rreg; |
809 | radeon_wreg_t mc_wreg; |
||
810 | radeon_rreg_t pll_rreg; |
||
811 | radeon_wreg_t pll_wreg; |
||
1179 | serge | 812 | uint32_t pcie_reg_mask; |
1120 | serge | 813 | radeon_rreg_t pciep_rreg; |
814 | radeon_wreg_t pciep_wreg; |
||
815 | struct radeon_clock clock; |
||
1117 | serge | 816 | struct radeon_mc mc; |
817 | struct radeon_gart gart; |
||
818 | struct radeon_mode_info mode_info; |
||
819 | struct radeon_scratch scratch; |
||
1321 | serge | 820 | struct radeon_mman mman; |
1117 | serge | 821 | struct radeon_fence_driver fence_drv; |
1120 | serge | 822 | struct radeon_cp cp; |
1117 | serge | 823 | struct radeon_ib_pool ib_pool; |
824 | // struct radeon_irq irq; |
||
825 | struct radeon_asic *asic; |
||
1126 | serge | 826 | struct radeon_gem gem; |
1179 | serge | 827 | struct radeon_pm pm; |
828 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
||
1117 | serge | 829 | // struct mutex cs_mutex; |
830 | struct radeon_wb wb; |
||
1179 | serge | 831 | struct radeon_dummy_page dummy_page; |
1117 | serge | 832 | bool gpu_lockup; |
833 | bool shutdown; |
||
834 | bool suspend; |
||
1179 | serge | 835 | bool need_dma32; |
836 | bool accel_working; |
||
837 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
||
838 | const struct firmware *me_fw; /* all family ME firmware */ |
||
839 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
||
1403 | serge | 840 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
1179 | serge | 841 | struct r600_blit r600_blit; |
1268 | serge | 842 | int msi_enabled; /* msi enabled */ |
1403 | serge | 843 | |
844 | /* audio stuff */ |
||
845 | // struct timer_list audio_timer; |
||
846 | int audio_channels; |
||
847 | int audio_rate; |
||
848 | int audio_bits_per_sample; |
||
849 | uint8_t audio_status_bits; |
||
850 | uint8_t audio_category_code; |
||
1117 | serge | 851 | }; |
852 | |||
853 | int radeon_device_init(struct radeon_device *rdev, |
||
854 | struct drm_device *ddev, |
||
855 | struct pci_dev *pdev, |
||
856 | uint32_t flags); |
||
857 | void radeon_device_fini(struct radeon_device *rdev); |
||
858 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
||
859 | |||
1179 | serge | 860 | /* r600 blit */ |
861 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); |
||
862 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); |
||
863 | void r600_kms_blit_copy(struct radeon_device *rdev, |
||
864 | u64 src_gpu_addr, u64 dst_gpu_addr, |
||
865 | int size_bytes); |
||
1117 | serge | 866 | |
1179 | serge | 867 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
1117 | serge | 868 | { |
1403 | serge | 869 | if (reg < rdev->rmmio_size) |
1179 | serge | 870 | return readl(((void __iomem *)rdev->rmmio) + reg); |
871 | else { |
||
872 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
||
873 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
||
874 | } |
||
1117 | serge | 875 | } |
876 | |||
1179 | serge | 877 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
1117 | serge | 878 | { |
1403 | serge | 879 | if (reg < rdev->rmmio_size) |
1179 | serge | 880 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
881 | else { |
||
882 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
||
883 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
||
884 | } |
||
1117 | serge | 885 | } |
886 | |||
1321 | serge | 887 | /* |
888 | * Cast helper |
||
889 | */ |
||
890 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
||
1117 | serge | 891 | |
892 | /* |
||
893 | * Registers read & write functions. |
||
894 | */ |
||
895 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
||
896 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
||
1179 | serge | 897 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
898 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
||
1117 | serge | 899 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
900 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
||
901 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
||
902 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
||
903 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
||
904 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
||
1179 | serge | 905 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
906 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
||
1117 | serge | 907 | #define WREG32_P(reg, val, mask) \ |
908 | do { \ |
||
909 | uint32_t tmp_ = RREG32(reg); \ |
||
910 | tmp_ &= (mask); \ |
||
911 | tmp_ |= ((val) & ~(mask)); \ |
||
912 | WREG32(reg, tmp_); \ |
||
913 | } while (0) |
||
914 | #define WREG32_PLL_P(reg, val, mask) \ |
||
915 | do { \ |
||
916 | uint32_t tmp_ = RREG32_PLL(reg); \ |
||
917 | tmp_ &= (mask); \ |
||
918 | tmp_ |= ((val) & ~(mask)); \ |
||
919 | WREG32_PLL(reg, tmp_); \ |
||
920 | } while (0) |
||
921 | |||
1179 | serge | 922 | /* |
923 | * Indirect registers accessor |
||
924 | */ |
||
925 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
||
926 | { |
||
927 | uint32_t r; |
||
1117 | serge | 928 | |
1179 | serge | 929 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
930 | r = RREG32(RADEON_PCIE_DATA); |
||
931 | return r; |
||
932 | } |
||
933 | |||
934 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
||
935 | { |
||
936 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
||
937 | WREG32(RADEON_PCIE_DATA, (v)); |
||
938 | } |
||
939 | |||
940 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
||
941 | |||
942 | |||
1117 | serge | 943 | /* |
944 | * ASICs helpers. |
||
945 | */ |
||
1179 | serge | 946 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
947 | (rdev->pdev->device == 0x5969)) |
||
1117 | serge | 948 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
949 | (rdev->family == CHIP_RV200) || \ |
||
950 | (rdev->family == CHIP_RS100) || \ |
||
951 | (rdev->family == CHIP_RS200) || \ |
||
952 | (rdev->family == CHIP_RV250) || \ |
||
953 | (rdev->family == CHIP_RV280) || \ |
||
954 | (rdev->family == CHIP_RS300)) |
||
955 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
||
956 | (rdev->family == CHIP_RV350) || \ |
||
957 | (rdev->family == CHIP_R350) || \ |
||
958 | (rdev->family == CHIP_RV380) || \ |
||
959 | (rdev->family == CHIP_R420) || \ |
||
960 | (rdev->family == CHIP_R423) || \ |
||
961 | (rdev->family == CHIP_RV410) || \ |
||
962 | (rdev->family == CHIP_RS400) || \ |
||
963 | (rdev->family == CHIP_RS480)) |
||
964 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
||
965 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
||
966 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
||
967 | |||
968 | |||
969 | /* |
||
970 | * BIOS helpers. |
||
971 | */ |
||
972 | #define RBIOS8(i) (rdev->bios[i]) |
||
973 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
||
974 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
||
975 | |||
976 | int radeon_combios_init(struct radeon_device *rdev); |
||
977 | void radeon_combios_fini(struct radeon_device *rdev); |
||
978 | int radeon_atombios_init(struct radeon_device *rdev); |
||
979 | void radeon_atombios_fini(struct radeon_device *rdev); |
||
980 | |||
981 | |||
982 | /* |
||
983 | * RING helpers. |
||
984 | */ |
||
985 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
||
986 | { |
||
987 | #if DRM_DEBUG_CODE |
||
988 | if (rdev->cp.count_dw <= 0) { |
||
989 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
||
990 | } |
||
991 | #endif |
||
992 | rdev->cp.ring[rdev->cp.wptr++] = v; |
||
993 | rdev->cp.wptr &= rdev->cp.ptr_mask; |
||
994 | rdev->cp.count_dw--; |
||
995 | rdev->cp.ring_free_dw--; |
||
996 | } |
||
997 | |||
998 | |||
999 | /* |
||
1000 | * ASICs macro. |
||
1001 | */ |
||
1002 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
||
1179 | serge | 1003 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1004 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
||
1005 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
||
1117 | serge | 1006 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
1179 | serge | 1007 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
1117 | serge | 1008 | #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
1009 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
||
1010 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
||
1179 | serge | 1011 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
1117 | serge | 1012 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
1179 | serge | 1013 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
1014 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) |
||
1117 | serge | 1015 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
1016 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
||
1179 | serge | 1017 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
1117 | serge | 1018 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
1019 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
||
1020 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) |
||
1021 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
||
1268 | serge | 1022 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
1117 | serge | 1023 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
1268 | serge | 1024 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
1321 | serge | 1025 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
1117 | serge | 1026 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
1027 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
||
1179 | serge | 1028 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
1029 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) |
||
1030 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
||
1321 | serge | 1031 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
1032 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) |
||
1033 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) |
||
1034 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) |
||
1117 | serge | 1035 | |
1179 | serge | 1036 | /* Common functions */ |
1403 | serge | 1037 | /* AGP */ |
1038 | extern void radeon_agp_disable(struct radeon_device *rdev); |
||
1179 | serge | 1039 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
1040 | extern int radeon_modeset_init(struct radeon_device *rdev); |
||
1041 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
||
1042 | extern bool radeon_card_posted(struct radeon_device *rdev); |
||
1321 | serge | 1043 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
1179 | serge | 1044 | extern int radeon_clocks_init(struct radeon_device *rdev); |
1045 | extern void radeon_clocks_fini(struct radeon_device *rdev); |
||
1046 | extern void radeon_scratch_init(struct radeon_device *rdev); |
||
1047 | extern void radeon_surface_init(struct radeon_device *rdev); |
||
1048 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
||
1221 | serge | 1049 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
1050 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
||
1321 | serge | 1051 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
1403 | serge | 1052 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
1117 | serge | 1053 | |
1179 | serge | 1054 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
1055 | struct r100_mc_save { |
||
1056 | u32 GENMO_WT; |
||
1057 | u32 CRTC_EXT_CNTL; |
||
1058 | u32 CRTC_GEN_CNTL; |
||
1059 | u32 CRTC2_GEN_CNTL; |
||
1060 | u32 CUR_OFFSET; |
||
1061 | u32 CUR2_OFFSET; |
||
1062 | }; |
||
1063 | extern void r100_cp_disable(struct radeon_device *rdev); |
||
1064 | extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
||
1065 | extern void r100_cp_fini(struct radeon_device *rdev); |
||
1066 | extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
||
1067 | extern int r100_pci_gart_init(struct radeon_device *rdev); |
||
1068 | extern void r100_pci_gart_fini(struct radeon_device *rdev); |
||
1069 | extern int r100_pci_gart_enable(struct radeon_device *rdev); |
||
1070 | extern void r100_pci_gart_disable(struct radeon_device *rdev); |
||
1071 | extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
||
1072 | extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
||
1073 | extern int r100_gui_wait_for_idle(struct radeon_device *rdev); |
||
1074 | extern void r100_ib_fini(struct radeon_device *rdev); |
||
1075 | extern int r100_ib_init(struct radeon_device *rdev); |
||
1076 | extern void r100_irq_disable(struct radeon_device *rdev); |
||
1077 | extern int r100_irq_set(struct radeon_device *rdev); |
||
1078 | extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); |
||
1079 | extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); |
||
1080 | extern void r100_vram_init_sizes(struct radeon_device *rdev); |
||
1081 | extern void r100_wb_disable(struct radeon_device *rdev); |
||
1082 | extern void r100_wb_fini(struct radeon_device *rdev); |
||
1083 | extern int r100_wb_init(struct radeon_device *rdev); |
||
1221 | serge | 1084 | extern void r100_hdp_reset(struct radeon_device *rdev); |
1085 | extern int r100_rb2d_reset(struct radeon_device *rdev); |
||
1086 | extern int r100_cp_reset(struct radeon_device *rdev); |
||
1087 | extern void r100_vga_render_disable(struct radeon_device *rdev); |
||
1088 | extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
||
1089 | struct radeon_cs_packet *pkt, |
||
1321 | serge | 1090 | struct radeon_bo *robj); |
1221 | serge | 1091 | extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
1092 | struct radeon_cs_packet *pkt, |
||
1093 | const unsigned *auth, unsigned n, |
||
1094 | radeon_packet0_check_t check); |
||
1095 | extern int r100_cs_packet_parse(struct radeon_cs_parser *p, |
||
1096 | struct radeon_cs_packet *pkt, |
||
1097 | unsigned idx); |
||
1321 | serge | 1098 | extern void r100_enable_bm(struct radeon_device *rdev); |
1099 | extern void r100_set_common_regs(struct radeon_device *rdev); |
||
1179 | serge | 1100 | |
1221 | serge | 1101 | /* rv200,rv250,rv280 */ |
1102 | extern void r200_set_safe_registers(struct radeon_device *rdev); |
||
1103 | |||
1179 | serge | 1104 | /* r300,r350,rv350,rv370,rv380 */ |
1105 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
||
1106 | extern void r300_mc_program(struct radeon_device *rdev); |
||
1107 | extern void r300_vram_info(struct radeon_device *rdev); |
||
1221 | serge | 1108 | extern void r300_clock_startup(struct radeon_device *rdev); |
1109 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
||
1179 | serge | 1110 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
1111 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
||
1112 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
||
1113 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
||
1114 | |||
1115 | /* r420,r423,rv410 */ |
||
1221 | serge | 1116 | extern int r420_mc_init(struct radeon_device *rdev); |
1179 | serge | 1117 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
1118 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
||
1119 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
||
1221 | serge | 1120 | extern void r420_pipes_init(struct radeon_device *rdev); |
1179 | serge | 1121 | |
1122 | /* rv515 */ |
||
1221 | serge | 1123 | struct rv515_mc_save { |
1124 | u32 d1vga_control; |
||
1125 | u32 d2vga_control; |
||
1126 | u32 vga_render_control; |
||
1127 | u32 vga_hdp_control; |
||
1128 | u32 d1crtc_control; |
||
1129 | u32 d2crtc_control; |
||
1130 | }; |
||
1179 | serge | 1131 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
1221 | serge | 1132 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
1133 | extern void rv515_set_safe_registers(struct radeon_device *rdev); |
||
1134 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
||
1135 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); |
||
1136 | extern void rv515_clock_startup(struct radeon_device *rdev); |
||
1137 | extern void rv515_debugfs(struct radeon_device *rdev); |
||
1138 | extern int rv515_suspend(struct radeon_device *rdev); |
||
1179 | serge | 1139 | |
1221 | serge | 1140 | /* rs400 */ |
1141 | extern int rs400_gart_init(struct radeon_device *rdev); |
||
1142 | extern int rs400_gart_enable(struct radeon_device *rdev); |
||
1143 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); |
||
1144 | extern void rs400_gart_disable(struct radeon_device *rdev); |
||
1145 | extern void rs400_gart_fini(struct radeon_device *rdev); |
||
1146 | |||
1147 | /* rs600 */ |
||
1148 | extern void rs600_set_safe_registers(struct radeon_device *rdev); |
||
1149 | extern int rs600_irq_set(struct radeon_device *rdev); |
||
1150 | extern void rs600_irq_disable(struct radeon_device *rdev); |
||
1151 | |||
1179 | serge | 1152 | /* rs690, rs740 */ |
1153 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, |
||
1154 | struct drm_display_mode *mode1, |
||
1155 | struct drm_display_mode *mode2); |
||
1156 | |||
1157 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ |
||
1158 | extern bool r600_card_posted(struct radeon_device *rdev); |
||
1159 | extern void r600_cp_stop(struct radeon_device *rdev); |
||
1160 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
||
1161 | extern int r600_cp_resume(struct radeon_device *rdev); |
||
1404 | serge | 1162 | extern void r600_cp_fini(struct radeon_device *rdev); |
1179 | serge | 1163 | extern int r600_count_pipe_bits(uint32_t val); |
1164 | extern int r600_gart_clear_page(struct radeon_device *rdev, int i); |
||
1165 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
||
1166 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
||
1167 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
||
1168 | extern int r600_ib_test(struct radeon_device *rdev); |
||
1169 | extern int r600_ring_test(struct radeon_device *rdev); |
||
1170 | extern void r600_wb_fini(struct radeon_device *rdev); |
||
1221 | serge | 1171 | extern int r600_wb_enable(struct radeon_device *rdev); |
1172 | extern void r600_wb_disable(struct radeon_device *rdev); |
||
1179 | serge | 1173 | extern void r600_scratch_init(struct radeon_device *rdev); |
1174 | extern int r600_blit_init(struct radeon_device *rdev); |
||
1175 | extern void r600_blit_fini(struct radeon_device *rdev); |
||
1321 | serge | 1176 | extern int r600_init_microcode(struct radeon_device *rdev); |
1179 | serge | 1177 | extern int r600_gpu_reset(struct radeon_device *rdev); |
1321 | serge | 1178 | /* r600 irq */ |
1179 | extern int r600_irq_init(struct radeon_device *rdev); |
||
1180 | extern void r600_irq_fini(struct radeon_device *rdev); |
||
1181 | extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); |
||
1182 | extern int r600_irq_set(struct radeon_device *rdev); |
||
1403 | serge | 1183 | extern void r600_irq_suspend(struct radeon_device *rdev); |
1184 | /* r600 audio */ |
||
1185 | extern int r600_audio_init(struct radeon_device *rdev); |
||
1186 | extern int r600_audio_tmds_index(struct drm_encoder *encoder); |
||
1187 | extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); |
||
1188 | extern void r600_audio_fini(struct radeon_device *rdev); |
||
1189 | extern void r600_hdmi_init(struct drm_encoder *encoder); |
||
1190 | extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable); |
||
1191 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
||
1192 | extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
||
1193 | extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder, |
||
1194 | int channels, |
||
1195 | int rate, |
||
1196 | int bps, |
||
1197 | uint8_t status_bits, |
||
1198 | uint8_t category_code); |
||
1179 | serge | 1199 | |
1321 | serge | 1200 | #include "radeon_object.h" |
1179 | serge | 1201 | |
1117 | serge | 1202 | #define DRM_UDELAY(d) udelay(d) |
1203 | |||
1204 | resource_size_t |
||
1205 | drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
||
1206 | resource_size_t |
||
1207 | drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
||
1208 | |||
1239 | serge | 1209 | bool set_mode(struct drm_device *dev, struct drm_connector *connector, |
1403 | serge | 1210 | videomode_t *mode, bool strict); |
1117 | serge | 1211 | |
1179 | serge | 1212 | |
1117 | serge | 1213 | #endif=>><>><>><>><>>>>=> |