WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon.h

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28	#ifndef __RADEON_H__
		29	#define __RADEON_H__
		30
		31	//#include "radeon_object.h"
		32
		33	/* TODO: Here are things that needs to be done :
		34	* - surface allocator & initializer : (bit like scratch reg) should
		35	* initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
		36	* related to surface
		37	* - WB : write back stuff (do it bit like scratch reg things)
		38	* - Vblank : look at Jesse's rework and what we should do
		39	* - r600/r700: gart & cp
		40	* - cs : clean cs ioctl use bitmap & things like that.
		41	* - power management stuff
		42	* - Barrier in gart code
		43	* - Unmappabled vram ?
		44	* - TESTING, TESTING, TESTING
		45	*/
		46
1120	serge	47	#include
1179	serge	48	#include
1117	serge	49
1120	serge	50	#include
1117	serge	51
1120	serge	52	#include
1123	serge	53	#include "drm_edid.h"
1179	serge	54
		55	#include "radeon_family.h"
1117	serge	56	#include "radeon_mode.h"
		57	#include "radeon_reg.h"
		58
		59	#include
		60
1179	serge	61	/*
		62	* Modules parameters.
		63	*/
		64	extern int radeon_no_wb;
1123	serge	65	extern int radeon_modeset;
1117	serge	66	extern int radeon_dynclks;
1123	serge	67	extern int radeon_r4xx_atom;
1128	serge	68	extern int radeon_agpmode;
		69	extern int radeon_vram_limit;
1117	serge	70	extern int radeon_gart_size;
1128	serge	71	extern int radeon_benchmarking;
1179	serge	72	extern int radeon_testing;
1123	serge	73	extern int radeon_connector_table;
1179	serge	74	extern int radeon_tv;
1117	serge	75
1179	serge	76
		77	static inline uint8_t __raw_readb(const volatile void __iomem *addr)
		78	{
		79	return (const volatile uint8_t __force ) addr;
		80	}
		81
		82	static inline uint16_t __raw_readw(const volatile void __iomem *addr)
		83	{
		84	return (const volatile uint16_t __force ) addr;
		85	}
		86
		87	static inline uint32_t __raw_readl(const volatile void __iomem *addr)
		88	{
		89	return (const volatile uint32_t __force ) addr;
		90	}
		91
		92	#define readb __raw_readb
		93	#define readw __raw_readw
		94	#define readl __raw_readl
		95
		96
		97
		98	static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)
		99	{
		100	(volatile uint8_t __force ) addr = b;
		101	}
		102
		103	static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)
		104	{
		105	(volatile uint16_t __force ) addr = b;
		106	}
		107
		108	static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)
		109	{
		110	(volatile uint32_t __force ) addr = b;
		111	}
		112
		113	static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)
		114	{
		115	(volatile __u64 )addr = b;
		116	}
		117
		118	#define writeb __raw_writeb
		119	#define writew __raw_writew
		120	#define writel __raw_writel
		121	#define writeq __raw_writeq
		122
		123	//#define writeb(b,addr) (volatile uint8_t ) addr = (uint8_t)b
		124	//#define writew(b,addr) (volatile uint16_t) addr = (uint16_t)b
		125	//#define writel(b,addr) (volatile uint32_t) addr = (uint32_t)b
		126
		127
1117	serge	128	/*
		129	* Copy from radeon_drv.h so we don't have to include both and have conflicting
		130	* symbol;
		131	*/
1120	serge	132	#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
		133	#define RADEON_IB_POOL_SIZE 16
1117	serge	134	#define RADEON_DEBUGFS_MAX_NUM_FILES 32
1120	serge	135	#define RADEONFB_CONN_LIMIT 4
1179	serge	136	#define RADEON_BIOS_NUM_SCRATCH 8
1117	serge	137
		138	/*
		139	* Errata workarounds.
		140	*/
		141	enum radeon_pll_errata {
		142	CHIP_ERRATA_R300_CG = 0x00000001,
		143	CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
		144	CHIP_ERRATA_PLL_DELAY = 0x00000004
		145	};
		146
		147
		148	struct radeon_device;
		149
		150
		151	/*
		152	* BIOS.
		153	*/
		154	bool radeon_get_bios(struct radeon_device *rdev);
		155
1179	serge	156
1117	serge	157	/*
1179	serge	158	* Dummy page
		159	*/
		160	struct radeon_dummy_page {
		161	struct page *page;
		162	dma_addr_t addr;
		163	};
		164	int radeon_dummy_page_init(struct radeon_device *rdev);
		165	void radeon_dummy_page_fini(struct radeon_device *rdev);
		166
		167
		168	/*
1117	serge	169	* Clocks
		170	*/
		171	struct radeon_clock {
		172	struct radeon_pll p1pll;
		173	struct radeon_pll p2pll;
		174	struct radeon_pll spll;
		175	struct radeon_pll mpll;
		176	/* 10 Khz units */
		177	uint32_t default_mclk;
		178	uint32_t default_sclk;
		179	};
		180
1179	serge	181
1117	serge	182	/*
		183	* Fences.
		184	*/
		185	struct radeon_fence_driver {
		186	uint32_t scratch_reg;
		187	// atomic_t seq;
		188	uint32_t last_seq;
		189	unsigned long count_timeout;
		190	// wait_queue_head_t queue;
		191	// rwlock_t lock;
1120	serge	192	struct list_head created;
		193	struct list_head emited;
		194	struct list_head signaled;
1117	serge	195	};
		196
		197	struct radeon_fence {
		198	struct radeon_device *rdev;
		199	// struct kref kref;
1120	serge	200	struct list_head list;
1117	serge	201	/* protected by radeon_fence.lock */
		202	uint32_t seq;
		203	unsigned long timeout;
		204	bool emited;
		205	bool signaled;
		206	};
		207
		208	int radeon_fence_driver_init(struct radeon_device *rdev);
		209	void radeon_fence_driver_fini(struct radeon_device *rdev);
		210	int radeon_fence_create(struct radeon_device rdev, struct radeon_fence *fence);
		211	int radeon_fence_emit(struct radeon_device rdev, struct radeon_fence fence);
		212	void radeon_fence_process(struct radeon_device *rdev);
		213	bool radeon_fence_signaled(struct radeon_fence *fence);
		214	int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
		215	int radeon_fence_wait_next(struct radeon_device *rdev);
		216	int radeon_fence_wait_last(struct radeon_device *rdev);
		217	struct radeon_fence radeon_fence_ref(struct radeon_fence fence);
		218	void radeon_fence_unref(struct radeon_fence **fence);
		219
1179	serge	220	/*
		221	* Tiling registers
		222	*/
		223	struct radeon_surface_reg {
		224	struct radeon_object *robj;
		225	};
1117	serge	226
1179	serge	227	#define RADEON_GEM_MAX_SURFACES 8
		228
1117	serge	229	/*
		230	* Radeon buffer.
		231	*/
		232	struct radeon_object;
		233
		234	struct radeon_object_list {
1120	serge	235	struct list_head list;
1117	serge	236	struct radeon_object *robj;
		237	uint64_t gpu_offset;
		238	unsigned rdomain;
		239	unsigned wdomain;
1179	serge	240	uint32_t tiling_flags;
1117	serge	241	};
		242
1123	serge	243	int radeon_object_init(struct radeon_device *rdev);
		244	void radeon_object_fini(struct radeon_device *rdev);
		245	int radeon_object_create(struct radeon_device *rdev,
		246	struct drm_gem_object *gobj,
		247	unsigned long size,
		248	bool kernel,
		249	uint32_t domain,
		250	bool interruptible,
		251	struct radeon_object **robj_ptr);
1117	serge	252
		253
1123	serge	254	/*
		255	* GEM objects.
		256	*/
		257	struct radeon_gem {
		258	struct list_head objects;
		259	};
1117	serge	260
1126	serge	261	int radeon_gem_init(struct radeon_device *rdev);
		262	void radeon_gem_fini(struct radeon_device *rdev);
		263	int radeon_gem_object_create(struct radeon_device *rdev, int size,
		264	int alignment, int initial_domain,
		265	bool discardable, bool kernel,
		266	bool interruptible,
		267	struct drm_gem_object **obj);
		268	int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
		269	uint64_t *gpu_addr);
		270	void radeon_gem_object_unpin(struct drm_gem_object *obj);
1117	serge	271
		272
		273	/*
		274	* GART structures, functions & helpers
		275	*/
		276	struct radeon_mc;
		277
		278	struct radeon_gart_table_ram {
		279	volatile uint32_t *ptr;
		280	};
		281
		282	struct radeon_gart_table_vram {
		283	struct radeon_object *robj;
		284	volatile uint32_t *ptr;
		285	};
		286
		287	union radeon_gart_table {
		288	struct radeon_gart_table_ram ram;
		289	struct radeon_gart_table_vram vram;
		290	};
		291
		292	struct radeon_gart {
		293	dma_addr_t table_addr;
		294	unsigned num_gpu_pages;
		295	unsigned num_cpu_pages;
		296	unsigned table_size;
		297	union radeon_gart_table table;
		298	struct page **pages;
		299	dma_addr_t *pages_addr;
		300	bool ready;
		301	};
		302
		303	int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
		304	void radeon_gart_table_ram_free(struct radeon_device *rdev);
		305	int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
		306	void radeon_gart_table_vram_free(struct radeon_device *rdev);
		307	int radeon_gart_init(struct radeon_device *rdev);
		308	void radeon_gart_fini(struct radeon_device *rdev);
		309	void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
		310	int pages);
1120	serge	311	int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
		312	int pages, u32_t *pagelist);
1117	serge	313
		314
		315	/*
		316	* GPU MC structures, functions & helpers
		317	*/
		318	struct radeon_mc {
		319	resource_size_t aper_size;
		320	resource_size_t aper_base;
		321	resource_size_t agp_base;
1179	serge	322	/* for some chips with <= 32MB we need to lie
		323	* about vram size near mc fb location */
		324	u64 mc_vram_size;
		325	u64 gtt_location;
		326	u64 gtt_size;
		327	u64 gtt_start;
		328	u64 gtt_end;
		329	u64 vram_location;
		330	u64 vram_start;
		331	u64 vram_end;
1117	serge	332	unsigned vram_width;
1179	serge	333	u64 real_vram_size;
1117	serge	334	int vram_mtrr;
		335	bool vram_is_ddr;
		336	};
		337
		338	int radeon_mc_setup(struct radeon_device *rdev);
		339
		340
		341	/*
		342	* GPU scratch registers structures, functions & helpers
		343	*/
		344	struct radeon_scratch {
		345	unsigned num_reg;
		346	bool free[32];
		347	uint32_t reg[32];
		348	};
		349
		350	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg);
		351	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
		352
		353
		354	/*
		355	* IRQS.
		356	*/
		357	struct radeon_irq {
		358	bool installed;
		359	bool sw_int;
		360	/* FIXME: use a define max crtc rather than hardcode it */
		361	bool crtc_vblank_int[2];
		362	};
		363
		364	int radeon_irq_kms_init(struct radeon_device *rdev);
		365	void radeon_irq_kms_fini(struct radeon_device *rdev);
		366
		367
		368	/*
		369	* CP & ring.
		370	*/
		371	struct radeon_ib {
1120	serge	372	struct list_head list;
1117	serge	373	unsigned long idx;
		374	uint64_t gpu_addr;
		375	struct radeon_fence *fence;
		376	volatile uint32_t *ptr;
		377	uint32_t length_dw;
		378	};
		379
1179	serge	380	/*
		381	* locking -
		382	* mutex protects scheduled_ibs, ready, alloc_bm
		383	*/
1117	serge	384	struct radeon_ib_pool {
		385	// struct mutex mutex;
		386	struct radeon_object *robj;
1120	serge	387	struct list_head scheduled_ibs;
1117	serge	388	struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
		389	bool ready;
1120	serge	390	DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
1117	serge	391	};
		392
		393	struct radeon_cp {
		394	struct radeon_object *ring_obj;
		395	volatile uint32_t *ring;
		396	unsigned rptr;
		397	unsigned wptr;
		398	unsigned wptr_old;
		399	unsigned ring_size;
		400	unsigned ring_free_dw;
		401	int count_dw;
		402	uint64_t gpu_addr;
		403	uint32_t align_mask;
		404	uint32_t ptr_mask;
		405	// struct mutex mutex;
		406	bool ready;
		407	};
		408
1179	serge	409	struct r600_blit {
		410	struct radeon_object *shader_obj;
		411	u64 shader_gpu_addr;
		412	u32 vs_offset, ps_offset;
		413	u32 state_offset;
		414	u32 state_len;
		415	u32 vb_used, vb_total;
		416	struct radeon_ib *vb_ib;
		417	};
		418
1117	serge	419	int radeon_ib_get(struct radeon_device rdev, struct radeon_ib *ib);
		420	void radeon_ib_free(struct radeon_device rdev, struct radeon_ib *ib);
		421	int radeon_ib_schedule(struct radeon_device rdev, struct radeon_ib ib);
		422	int radeon_ib_pool_init(struct radeon_device *rdev);
		423	void radeon_ib_pool_fini(struct radeon_device *rdev);
		424	int radeon_ib_test(struct radeon_device *rdev);
		425	/* Ring access between begin & end cannot sleep */
		426	void radeon_ring_free_size(struct radeon_device *rdev);
		427	int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
		428	void radeon_ring_unlock_commit(struct radeon_device *rdev);
		429	void radeon_ring_unlock_undo(struct radeon_device *rdev);
		430	int radeon_ring_test(struct radeon_device *rdev);
		431	int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
		432	void radeon_ring_fini(struct radeon_device *rdev);
		433
		434
		435	/*
		436	* CS.
		437	*/
		438	struct radeon_cs_reloc {
		439	// struct drm_gem_object *gobj;
		440	struct radeon_object *robj;
1120	serge	441	struct radeon_object_list lobj;
1117	serge	442	uint32_t handle;
		443	uint32_t flags;
		444	};
		445
		446	struct radeon_cs_chunk {
		447	uint32_t chunk_id;
		448	uint32_t length_dw;
		449	uint32_t *kdata;
		450	};
		451
		452	struct radeon_cs_parser {
		453	struct radeon_device *rdev;
		454	// struct drm_file *filp;
		455	/* chunks */
		456	unsigned nchunks;
		457	struct radeon_cs_chunk *chunks;
		458	uint64_t *chunks_array;
		459	/* IB */
		460	unsigned idx;
		461	/* relocations */
		462	unsigned nrelocs;
		463	struct radeon_cs_reloc *relocs;
		464	struct radeon_cs_reloc **relocs_ptr;
1120	serge	465	struct list_head validated;
1117	serge	466	/* indices of various chunks */
		467	int chunk_ib_idx;
		468	int chunk_relocs_idx;
		469	struct radeon_ib *ib;
		470	void *track;
1179	serge	471	unsigned family;
1117	serge	472	};
		473
		474	struct radeon_cs_packet {
		475	unsigned idx;
		476	unsigned type;
		477	unsigned reg;
		478	unsigned opcode;
		479	int count;
		480	unsigned one_reg_wr;
		481	};
		482
		483	typedef int (radeon_packet0_check_t)(struct radeon_cs_parser p,
		484	struct radeon_cs_packet *pkt,
		485	unsigned idx, unsigned reg);
		486	typedef int (radeon_packet3_check_t)(struct radeon_cs_parser p,
		487	struct radeon_cs_packet *pkt);
		488
		489
		490	/*
		491	* AGP
		492	*/
		493	int radeon_agp_init(struct radeon_device *rdev);
		494	void radeon_agp_fini(struct radeon_device *rdev);
		495
		496
		497	/*
		498	* Writeback
		499	*/
		500	struct radeon_wb {
		501	struct radeon_object *wb_obj;
		502	volatile uint32_t *wb;
		503	uint64_t gpu_addr;
		504	};
		505
1179	serge	506	/**
		507	* struct radeon_pm - power management datas
		508	* @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
		509	* @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
		510	* @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
		511	* @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
		512	* @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
		513	* @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
		514	* @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
		515	* @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
		516	* @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
		517	* @sclk: GPU clock Mhz (core bandwith depends of this clock)
		518	* @needed_bandwidth: current bandwidth needs
		519	*
		520	* It keeps track of various data needed to take powermanagement decision.
		521	* Bandwith need is used to determine minimun clock of the GPU and memory.
		522	* Equation between gpu/memory clock and available bandwidth is hw dependent
		523	* (type of memory, bus size, efficiency, ...)
		524	*/
		525	struct radeon_pm {
		526	fixed20_12 max_bandwidth;
		527	fixed20_12 igp_sideport_mclk;
		528	fixed20_12 igp_system_mclk;
		529	fixed20_12 igp_ht_link_clk;
		530	fixed20_12 igp_ht_link_width;
		531	fixed20_12 k8_bandwidth;
		532	fixed20_12 sideport_bandwidth;
		533	fixed20_12 ht_bandwidth;
		534	fixed20_12 core_bandwidth;
		535	fixed20_12 sclk;
		536	fixed20_12 needed_bandwidth;
		537	};
1117	serge	538
		539	/*
		540	* ASIC specific functions.
		541	*/
		542	struct radeon_asic {
		543	int (init)(struct radeon_device rdev);
1179	serge	544	void (fini)(struct radeon_device rdev);
		545	int (resume)(struct radeon_device rdev);
		546	int (suspend)(struct radeon_device rdev);
1117	serge	547	void (errata)(struct radeon_device rdev);
		548	void (vram_info)(struct radeon_device rdev);
1179	serge	549	void (vga_set_state)(struct radeon_device rdev, bool state);
1117	serge	550	int (gpu_reset)(struct radeon_device rdev);
		551	int (mc_init)(struct radeon_device rdev);
		552	void (mc_fini)(struct radeon_device rdev);
		553	int (wb_init)(struct radeon_device rdev);
		554	void (wb_fini)(struct radeon_device rdev);
1179	serge	555	int (gart_init)(struct radeon_device rdev);
		556	void (gart_fini)(struct radeon_device rdev);
1117	serge	557	int (gart_enable)(struct radeon_device rdev);
		558	void (gart_disable)(struct radeon_device rdev);
		559	void (gart_tlb_flush)(struct radeon_device rdev);
		560	int (gart_set_page)(struct radeon_device rdev, int i, uint64_t addr);
		561	int (cp_init)(struct radeon_device rdev, unsigned ring_size);
		562	void (cp_fini)(struct radeon_device rdev);
		563	void (cp_disable)(struct radeon_device rdev);
1179	serge	564	void (cp_commit)(struct radeon_device rdev);
1117	serge	565	void (ring_start)(struct radeon_device rdev);
1179	serge	566	int (ring_test)(struct radeon_device rdev);
		567	void (ring_ib_execute)(struct radeon_device rdev, struct radeon_ib *ib);
		568	int (ib_test)(struct radeon_device rdev);
1117	serge	569	int (irq_set)(struct radeon_device rdev);
		570	int (irq_process)(struct radeon_device rdev);
1179	serge	571	u32 (get_vblank_counter)(struct radeon_device rdev, int crtc);
1117	serge	572	void (fence_ring_emit)(struct radeon_device rdev, struct radeon_fence *fence);
		573	int (cs_parse)(struct radeon_cs_parser p);
		574	int (copy_blit)(struct radeon_device rdev,
		575	uint64_t src_offset,
		576	uint64_t dst_offset,
		577	unsigned num_pages,
		578	struct radeon_fence *fence);
		579	int (copy_dma)(struct radeon_device rdev,
		580	uint64_t src_offset,
		581	uint64_t dst_offset,
		582	unsigned num_pages,
		583	struct radeon_fence *fence);
		584	int (copy)(struct radeon_device rdev,
		585	uint64_t src_offset,
		586	uint64_t dst_offset,
		587	unsigned num_pages,
		588	struct radeon_fence *fence);
		589	void (set_engine_clock)(struct radeon_device rdev, uint32_t eng_clock);
		590	void (set_memory_clock)(struct radeon_device rdev, uint32_t mem_clock);
		591	void (set_pcie_lanes)(struct radeon_device rdev, int lanes);
		592	void (set_clock_gating)(struct radeon_device rdev, int enable);
1179	serge	593	int (set_surface_reg)(struct radeon_device rdev, int reg,
		594	uint32_t tiling_flags, uint32_t pitch,
		595	uint32_t offset, uint32_t obj_size);
		596	int (clear_surface_reg)(struct radeon_device rdev, int reg);
		597	void (bandwidth_update)(struct radeon_device rdev);
1117	serge	598	};
		599
1179	serge	600	/*
		601	* Asic structures
		602	*/
		603	struct r100_asic {
		604	const unsigned *reg_safe_bm;
		605	unsigned reg_safe_bm_size;
		606	};
		607
		608	struct r300_asic {
		609	const unsigned *reg_safe_bm;
		610	unsigned reg_safe_bm_size;
		611	};
		612
		613	struct r600_asic {
		614	unsigned max_pipes;
		615	unsigned max_tile_pipes;
		616	unsigned max_simds;
		617	unsigned max_backends;
		618	unsigned max_gprs;
		619	unsigned max_threads;
		620	unsigned max_stack_entries;
		621	unsigned max_hw_contexts;
		622	unsigned max_gs_threads;
		623	unsigned sx_max_export_size;
		624	unsigned sx_max_export_pos_size;
		625	unsigned sx_max_export_smx_size;
		626	unsigned sq_num_cf_insts;
		627	};
		628
		629	struct rv770_asic {
		630	unsigned max_pipes;
		631	unsigned max_tile_pipes;
		632	unsigned max_simds;
		633	unsigned max_backends;
		634	unsigned max_gprs;
		635	unsigned max_threads;
		636	unsigned max_stack_entries;
		637	unsigned max_hw_contexts;
		638	unsigned max_gs_threads;
		639	unsigned sx_max_export_size;
		640	unsigned sx_max_export_pos_size;
		641	unsigned sx_max_export_smx_size;
		642	unsigned sq_num_cf_insts;
		643	unsigned sx_num_of_sets;
		644	unsigned sc_prim_fifo_size;
		645	unsigned sc_hiz_tile_fifo_size;
		646	unsigned sc_earlyz_tile_fifo_fize;
		647	};
		648
1117	serge	649	union radeon_asic_config {
		650	struct r300_asic r300;
1179	serge	651	struct r100_asic r100;
		652	struct r600_asic r600;
		653	struct rv770_asic rv770;
1117	serge	654	};
		655
		656
		657	/*
1179	serge	658
		659
		660
		661
1117	serge	662	/*
		663	* Core structure, functions and helpers.
		664	*/
		665	typedef uint32_t (radeon_rreg_t)(struct radeon_device, uint32_t);
		666	typedef void (radeon_wreg_t)(struct radeon_device, uint32_t, uint32_t);
		667
		668	struct radeon_device {
		669	struct drm_device *ddev;
		670	struct pci_dev *pdev;
		671	/* ASIC */
		672	union radeon_asic_config config;
		673	enum radeon_family family;
		674	unsigned long flags;
		675	int usec_timeout;
		676	enum radeon_pll_errata pll_errata;
		677	int num_gb_pipes;
1179	serge	678	int num_z_pipes;
1117	serge	679	int disp_priority;
		680	/* BIOS */
		681	uint8_t *bios;
		682	bool is_atom_bios;
		683	uint16_t bios_header_start;
		684
		685	// struct radeon_object *stollen_vga_memory;
1126	serge	686	struct fb_info *fbdev_info;
1117	serge	687	struct radeon_object *fbdev_robj;
		688	struct radeon_framebuffer *fbdev_rfb;
		689	/* Register mmio */
		690	unsigned long rmmio_base;
		691	unsigned long rmmio_size;
		692	void *rmmio;
1120	serge	693	radeon_rreg_t mc_rreg;
		694	radeon_wreg_t mc_wreg;
		695	radeon_rreg_t pll_rreg;
		696	radeon_wreg_t pll_wreg;
1179	serge	697	uint32_t pcie_reg_mask;
1120	serge	698	radeon_rreg_t pciep_rreg;
		699	radeon_wreg_t pciep_wreg;
		700	struct radeon_clock clock;
1117	serge	701	struct radeon_mc mc;
		702	struct radeon_gart gart;
		703	struct radeon_mode_info mode_info;
		704	struct radeon_scratch scratch;
1120	serge	705	// struct radeon_mman mman;
1117	serge	706	struct radeon_fence_driver fence_drv;
1120	serge	707	struct radeon_cp cp;
1117	serge	708	struct radeon_ib_pool ib_pool;
		709	// struct radeon_irq irq;
		710	struct radeon_asic *asic;
1126	serge	711	struct radeon_gem gem;
1179	serge	712	struct radeon_pm pm;
		713	uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1117	serge	714	// struct mutex cs_mutex;
		715	struct radeon_wb wb;
1179	serge	716	struct radeon_dummy_page dummy_page;
1117	serge	717	bool gpu_lockup;
		718	bool shutdown;
		719	bool suspend;
1179	serge	720	bool need_dma32;
		721	bool new_init_path;
		722	bool accel_working;
		723	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
		724	const struct firmware me_fw; / all family ME firmware */
		725	const struct firmware pfp_fw; / r6/700 PFP firmware */
		726	struct r600_blit r600_blit;
1117	serge	727	};
		728
		729	int radeon_device_init(struct radeon_device *rdev,
		730	struct drm_device *ddev,
		731	struct pci_dev *pdev,
		732	uint32_t flags);
		733	void radeon_device_fini(struct radeon_device *rdev);
		734	int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
		735
1179	serge	736	/* r600 blit */
		737	int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
		738	void r600_blit_done_copy(struct radeon_device rdev, struct radeon_fence fence);
		739	void r600_kms_blit_copy(struct radeon_device *rdev,
		740	u64 src_gpu_addr, u64 dst_gpu_addr,
		741	int size_bytes);
1117	serge	742
1179	serge	743	static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1117	serge	744	{
1179	serge	745	if (reg < 0x10000)
		746	return readl(((void __iomem *)rdev->rmmio) + reg);
		747	else {
		748	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		749	return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
		750	}
1117	serge	751	}
		752
1179	serge	753	static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1117	serge	754	{
1179	serge	755	if (reg < 0x10000)
		756	writel(v, ((void __iomem *)rdev->rmmio) + reg);
		757	else {
		758	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		759	writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
		760	}
1117	serge	761	}
		762
		763
		764	/*
		765	* Registers read & write functions.
		766	*/
		767	#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
		768	#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1179	serge	769	#define RREG32(reg) r100_mm_rreg(rdev, (reg))
		770	#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1117	serge	771	#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
		772	#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
		773	#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
		774	#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
		775	#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
		776	#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1179	serge	777	#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
		778	#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1117	serge	779	#define WREG32_P(reg, val, mask) \
		780	do { \
		781	uint32_t tmp_ = RREG32(reg); \
		782	tmp_ &= (mask); \
		783	tmp_ \|= ((val) & ~(mask)); \
		784	WREG32(reg, tmp_); \
		785	} while (0)
		786	#define WREG32_PLL_P(reg, val, mask) \
		787	do { \
		788	uint32_t tmp_ = RREG32_PLL(reg); \
		789	tmp_ &= (mask); \
		790	tmp_ \|= ((val) & ~(mask)); \
		791	WREG32_PLL(reg, tmp_); \
		792	} while (0)
		793
1179	serge	794	/*
		795	* Indirect registers accessor
		796	*/
		797	static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
		798	{
		799	uint32_t r;
1117	serge	800
1179	serge	801	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
		802	r = RREG32(RADEON_PCIE_DATA);
		803	return r;
		804	}
		805
		806	static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		807	{
		808	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
		809	WREG32(RADEON_PCIE_DATA, (v));
		810	}
		811
		812	void r100_pll_errata_after_index(struct radeon_device *rdev);
		813
		814
		815
		816
		817
		818
		819
		820
		821
1117	serge	822	#define radeon_PCI_IDS \
		823	{0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_IS_MOBILITY}, \
		824	{0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		825	{0x1002, 0x3154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		826	{0x1002, 0x3E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_NEW_MEMMAP}, \
		827	{0x1002, 0x3E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_NEW_MEMMAP}, \
		828	{0x1002, 0x4136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100\|RADEON_IS_IGP}, \
		829	{0x1002, 0x4137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200\|RADEON_IS_IGP}, \
		830	{0x1002, 0x4144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
		831	{0x1002, 0x4145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
		832	{0x1002, 0x4146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
		833	{0x1002, 0x4147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
		834	{0x1002, 0x4148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
		835	{0x1002, 0x4149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
		836	{0x1002, 0x414A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
		837	{0x1002, 0x414B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
		838	{0x1002, 0x4150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
		839	{0x1002, 0x4151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
		840	{0x1002, 0x4152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
		841	{0x1002, 0x4153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
		842	{0x1002, 0x4154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
		843	{0x1002, 0x4155, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
		844	{0x1002, 0x4156, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
		845	{0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200\|RADEON_IS_IGP}, \
		846	{0x1002, 0x4242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
		847	{0x1002, 0x4243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
		848	{0x1002, 0x4336, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100\|RADEON_IS_IGP\|RADEON_IS_MOBILITY}, \
		849	{0x1002, 0x4337, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200\|RADEON_IS_IGP\|RADEON_IS_MOBILITY}, \
		850	{0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200\|RADEON_IS_IGP\|RADEON_IS_MOBILITY}, \
		851	{0x1002, 0x4966, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \
		852	{0x1002, 0x4967, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \
		853	{0x1002, 0x4A48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		854	{0x1002, 0x4A49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		855	{0x1002, 0x4A4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		856	{0x1002, 0x4A4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		857	{0x1002, 0x4A4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		858	{0x1002, 0x4A4D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		859	{0x1002, 0x4A4E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		860	{0x1002, 0x4A4F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		861	{0x1002, 0x4A50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		862	{0x1002, 0x4A54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		863	{0x1002, 0x4B49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		864	{0x1002, 0x4B4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		865	{0x1002, 0x4B4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		866	{0x1002, 0x4B4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		867	{0x1002, 0x4C57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200\|RADEON_IS_MOBILITY}, \
		868	{0x1002, 0x4C58, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200\|RADEON_IS_MOBILITY}, \
		869	{0x1002, 0x4C59, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100\|RADEON_IS_MOBILITY}, \
		870	{0x1002, 0x4C5A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100\|RADEON_IS_MOBILITY}, \
		871	{0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250\|RADEON_IS_MOBILITY}, \
		872	{0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250\|RADEON_IS_MOBILITY}, \
		873	{0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250\|RADEON_IS_MOBILITY}, \
		874	{0x1002, 0x4E44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
		875	{0x1002, 0x4E45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
		876	{0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
		877	{0x1002, 0x4E47, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
		878	{0x1002, 0x4E48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
		879	{0x1002, 0x4E49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
		880	{0x1002, 0x4E4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
		881	{0x1002, 0x4E4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
		882	{0x1002, 0x4E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350\|RADEON_IS_MOBILITY}, \
		883	{0x1002, 0x4E51, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350\|RADEON_IS_MOBILITY}, \
		884	{0x1002, 0x4E52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350\|RADEON_IS_MOBILITY}, \
		885	{0x1002, 0x4E53, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350\|RADEON_IS_MOBILITY}, \
		886	{0x1002, 0x4E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350\|RADEON_IS_MOBILITY}, \
		887	{0x1002, 0x4E56, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350\|RADEON_IS_MOBILITY}, \
		888	{0x1002, 0x5144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100\|RADEON_SINGLE_CRTC}, \
		889	{0x1002, 0x5145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100\|RADEON_SINGLE_CRTC}, \
		890	{0x1002, 0x5146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100\|RADEON_SINGLE_CRTC}, \
		891	{0x1002, 0x5147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100\|RADEON_SINGLE_CRTC}, \
		892	{0x1002, 0x5148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
		893	{0x1002, 0x514C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
		894	{0x1002, 0x514D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
		895	{0x1002, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \
		896	{0x1002, 0x5158, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \
		897	{0x1002, 0x5159, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
		898	{0x1002, 0x515A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
		899	{0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
		900	{0x1002, 0x5460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_IS_MOBILITY}, \
		901	{0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_IS_MOBILITY}, \
		902	{0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_IS_MOBILITY}, \
		903	{0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_NEW_MEMMAP}, \
		904	{0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		905	{0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		906	{0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		907	{0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		908	{0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		909	{0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		910	{0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		911	{0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		912	{0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		913	{0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		914	{0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		915	{0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		916	{0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		917	{0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		918	{0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		919	{0x1002, 0x5652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		920	{0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		921	{0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300\|RADEON_IS_IGP}, \
		922	{0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300\|RADEON_IS_IGP\|RADEON_IS_MOBILITY}, \
		923	{0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480\|RADEON_IS_IGP\|RADEON_IS_MOBILITY\|RADEON_IS_IGPGART}, \
		924	{0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480\|RADEON_IS_IGP\|RADEON_IS_MOBILITY\|RADEON_IS_IGPGART}, \
		925	{0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480\|RADEON_IS_IGP\|RADEON_IS_MOBILITY\|RADEON_IS_IGPGART}, \
		926	{0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480\|RADEON_IS_IGP\|RADEON_IS_MOBILITY\|RADEON_IS_IGPGART}, \
		927	{0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
		928	{0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
		929	{0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
		930	{0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
		931	{0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
		932	{0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
		933	{0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400\|RADEON_IS_IGP\|RADEON_IS_IGPGART}, \
		934	{0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400\|RADEON_IS_IGP\|RADEON_IS_MOBILITY\|RADEON_IS_IGPGART}, \
		935	{0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400\|RADEON_IS_IGP\|RADEON_IS_IGPGART}, \
		936	{0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400\|RADEON_IS_IGP\|RADEON_IS_MOBILITY\|RADEON_IS_IGPGART}, \
		937	{0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_NEW_MEMMAP}, \
		938	{0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_NEW_MEMMAP}, \
		939	{0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_NEW_MEMMAP}, \
		940	{0x1002, 0x5b64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_NEW_MEMMAP}, \
		941	{0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_NEW_MEMMAP}, \
		942	{0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280\|RADEON_IS_MOBILITY}, \
		943	{0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280\|RADEON_IS_MOBILITY}, \
		944	{0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		945	{0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		946	{0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		947	{0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		948	{0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		949	{0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		950	{0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		951	{0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		952	{0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		953	{0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		954	{0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \
		955	{0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \
		956	{0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \
		957	{0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \
		958	{0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \
		959	{0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \
		960	{0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		961	{0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		962	{0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		963	{0x1002, 0x7103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		964	{0x1002, 0x7104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		965	{0x1002, 0x7105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		966	{0x1002, 0x7106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		967	{0x1002, 0x7108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		968	{0x1002, 0x7109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		969	{0x1002, 0x710A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		970	{0x1002, 0x710B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		971	{0x1002, 0x710C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		972	{0x1002, 0x710E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		973	{0x1002, 0x710F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		974	{0x1002, 0x7140, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		975	{0x1002, 0x7141, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		976	{0x1002, 0x7142, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		977	{0x1002, 0x7143, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		978	{0x1002, 0x7144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		979	{0x1002, 0x7145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		980	{0x1002, 0x7146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		981	{0x1002, 0x7147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		982	{0x1002, 0x7149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		983	{0x1002, 0x714A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		984	{0x1002, 0x714B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		985	{0x1002, 0x714C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		986	{0x1002, 0x714D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		987	{0x1002, 0x714E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		988	{0x1002, 0x714F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		989	{0x1002, 0x7151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		990	{0x1002, 0x7152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		991	{0x1002, 0x7153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		992	{0x1002, 0x715E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		993	{0x1002, 0x715F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		994	{0x1002, 0x7180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		995	{0x1002, 0x7181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		996	{0x1002, 0x7183, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		997	{0x1002, 0x7186, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		998	{0x1002, 0x7187, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		999	{0x1002, 0x7188, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1000	{0x1002, 0x718A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1001	{0x1002, 0x718B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1002	{0x1002, 0x718C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1003	{0x1002, 0x718D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1004	{0x1002, 0x718F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		1005	{0x1002, 0x7193, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		1006	{0x1002, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1007	{0x1002, 0x719B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		1008	{0x1002, 0x719F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		1009	{0x1002, 0x71C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		1010	{0x1002, 0x71C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		1011	{0x1002, 0x71C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		1012	{0x1002, 0x71C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		1013	{0x1002, 0x71C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1014	{0x1002, 0x71C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1015	{0x1002, 0x71C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		1016	{0x1002, 0x71C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		1017	{0x1002, 0x71CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		1018	{0x1002, 0x71CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		1019	{0x1002, 0x71D2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		1020	{0x1002, 0x71D4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1021	{0x1002, 0x71D5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1022	{0x1002, 0x71D6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1023	{0x1002, 0x71DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		1024	{0x1002, 0x71DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1025	{0x1002, 0x7200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		1026	{0x1002, 0x7210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1027	{0x1002, 0x7211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1028	{0x1002, 0x7240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		1029	{0x1002, 0x7243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		1030	{0x1002, 0x7244, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		1031	{0x1002, 0x7245, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		1032	{0x1002, 0x7246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		1033	{0x1002, 0x7247, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		1034	{0x1002, 0x7248, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		1035	{0x1002, 0x7249, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		1036	{0x1002, 0x724A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		1037	{0x1002, 0x724B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		1038	{0x1002, 0x724C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		1039	{0x1002, 0x724D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		1040	{0x1002, 0x724E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		1041	{0x1002, 0x724F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		1042	{0x1002, 0x7280, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570\|RADEON_NEW_MEMMAP}, \
		1043	{0x1002, 0x7281, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560\|RADEON_NEW_MEMMAP}, \
		1044	{0x1002, 0x7283, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560\|RADEON_NEW_MEMMAP}, \
		1045	{0x1002, 0x7284, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1046	{0x1002, 0x7287, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560\|RADEON_NEW_MEMMAP}, \
		1047	{0x1002, 0x7288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570\|RADEON_NEW_MEMMAP}, \
		1048	{0x1002, 0x7289, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570\|RADEON_NEW_MEMMAP}, \
		1049	{0x1002, 0x728B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570\|RADEON_NEW_MEMMAP}, \
		1050	{0x1002, 0x728C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570\|RADEON_NEW_MEMMAP}, \
		1051	{0x1002, 0x7290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560\|RADEON_NEW_MEMMAP}, \
		1052	{0x1002, 0x7291, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560\|RADEON_NEW_MEMMAP}, \
		1053	{0x1002, 0x7293, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560\|RADEON_NEW_MEMMAP}, \
		1054	{0x1002, 0x7297, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560\|RADEON_NEW_MEMMAP}, \
		1055	{0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP}, \
		1056	{0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300\|RADEON_IS_IGP\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1057	{0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP\|RADEON_IS_IGPGART}, \
		1058	{0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP\|RADEON_IS_IGPGART}, \
		1059	{0x1002, 0x793f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP}, \
		1060	{0x1002, 0x7941, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP}, \
		1061	{0x1002, 0x7942, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP}, \
		1062	{0x1002, 0x796c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP\|RADEON_IS_IGPGART}, \
		1063	{0x1002, 0x796d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP\|RADEON_IS_IGPGART}, \
		1064	{0x1002, 0x796e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP\|RADEON_IS_IGPGART}, \
		1065	{0x1002, 0x796f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP\|RADEON_IS_IGPGART}, \
		1066	{0x1002, 0x9400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600\|RADEON_NEW_MEMMAP}, \
		1067	{0x1002, 0x9401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600\|RADEON_NEW_MEMMAP}, \
		1068	{0x1002, 0x9402, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600\|RADEON_NEW_MEMMAP}, \
		1069	{0x1002, 0x9403, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600\|RADEON_NEW_MEMMAP}, \
		1070	{0x1002, 0x9405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600\|RADEON_NEW_MEMMAP}, \
		1071	{0x1002, 0x940A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600\|RADEON_NEW_MEMMAP}, \
		1072	{0x1002, 0x940B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600\|RADEON_NEW_MEMMAP}, \
		1073	{0x1002, 0x940F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600\|RADEON_NEW_MEMMAP}, \
		1074	{0x1002, 0x9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		1075	{0x1002, 0x9441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		1076	{0x1002, 0x9442, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		1077	{0x1002, 0x9444, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		1078	{0x1002, 0x9446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		1079	{0x1002, 0x944A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1080	{0x1002, 0x944B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1081	{0x1002, 0x944C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		1082	{0x1002, 0x944E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		1083	{0x1002, 0x9450, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		1084	{0x1002, 0x9452, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		1085	{0x1002, 0x9456, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		1086	{0x1002, 0x945A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1087	{0x1002, 0x945B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1088	{0x1002, 0x9460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		1089	{0x1002, 0x9462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		1090	{0x1002, 0x946A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1091	{0x1002, 0x946B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1092	{0x1002, 0x947A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1093	{0x1002, 0x947B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1094	{0x1002, 0x9480, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1095	{0x1002, 0x9487, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_NEW_MEMMAP}, \
		1096	{0x1002, 0x9488, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1097	{0x1002, 0x9489, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1098	{0x1002, 0x948F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_NEW_MEMMAP}, \
		1099	{0x1002, 0x9490, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_NEW_MEMMAP}, \
		1100	{0x1002, 0x9491, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1101	{0x1002, 0x9498, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_NEW_MEMMAP}, \
		1102	{0x1002, 0x949C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_NEW_MEMMAP}, \
		1103	{0x1002, 0x949E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_NEW_MEMMAP}, \
		1104	{0x1002, 0x949F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_NEW_MEMMAP}, \
		1105	{0x1002, 0x94C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		1106	{0x1002, 0x94C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		1107	{0x1002, 0x94C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		1108	{0x1002, 0x94C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		1109	{0x1002, 0x94C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		1110	{0x1002, 0x94C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		1111	{0x1002, 0x94C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		1112	{0x1002, 0x94C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1113	{0x1002, 0x94C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1114	{0x1002, 0x94CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1115	{0x1002, 0x94CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		1116	{0x1002, 0x94CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		1117	{0x1002, 0x9500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		1118	{0x1002, 0x9501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		1119	{0x1002, 0x9504, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1120	{0x1002, 0x9505, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		1121	{0x1002, 0x9506, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1122	{0x1002, 0x9507, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		1123	{0x1002, 0x9508, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1124	{0x1002, 0x9509, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1125	{0x1002, 0x950F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		1126	{0x1002, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		1127	{0x1002, 0x9515, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		1128	{0x1002, 0x9517, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		1129	{0x1002, 0x9519, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		1130	{0x1002, 0x9540, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710\|RADEON_NEW_MEMMAP}, \
		1131	{0x1002, 0x9541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710\|RADEON_NEW_MEMMAP}, \
		1132	{0x1002, 0x9542, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710\|RADEON_NEW_MEMMAP}, \
		1133	{0x1002, 0x954E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710\|RADEON_NEW_MEMMAP}, \
		1134	{0x1002, 0x954F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710\|RADEON_NEW_MEMMAP}, \
		1135	{0x1002, 0x9552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1136	{0x1002, 0x9553, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1137	{0x1002, 0x9555, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1138	{0x1002, 0x9580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		1139	{0x1002, 0x9581, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1140	{0x1002, 0x9583, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1141	{0x1002, 0x9586, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		1142	{0x1002, 0x9587, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		1143	{0x1002, 0x9588, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		1144	{0x1002, 0x9589, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		1145	{0x1002, 0x958A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		1146	{0x1002, 0x958B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1147	{0x1002, 0x958C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		1148	{0x1002, 0x958D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		1149	{0x1002, 0x958E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		1150	{0x1002, 0x958F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1151	{0x1002, 0x9590, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_NEW_MEMMAP}, \
		1152	{0x1002, 0x9591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1153	{0x1002, 0x9593, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1154	{0x1002, 0x9595, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1155	{0x1002, 0x9596, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_NEW_MEMMAP}, \
		1156	{0x1002, 0x9597, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_NEW_MEMMAP}, \
		1157	{0x1002, 0x9598, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_NEW_MEMMAP}, \
		1158	{0x1002, 0x9599, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_NEW_MEMMAP}, \
		1159	{0x1002, 0x959B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1160	{0x1002, 0x95C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		1161	{0x1002, 0x95C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		1162	{0x1002, 0x95C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		1163	{0x1002, 0x95C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		1164	{0x1002, 0x95C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		1165	{0x1002, 0x95C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1166	{0x1002, 0x95C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1167	{0x1002, 0x95CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		1168	{0x1002, 0x95CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		1169	{0x1002, 0x95CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		1170	{0x1002, 0x95CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		1171	{0x1002, 0x9610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780\|RADEON_NEW_MEMMAP\|RADEON_IS_IGP}, \
		1172	{0x1002, 0x9611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780\|RADEON_NEW_MEMMAP\|RADEON_IS_IGP}, \
		1173	{0x1002, 0x9612, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780\|RADEON_NEW_MEMMAP\|RADEON_IS_IGP}, \
		1174	{0x1002, 0x9613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780\|RADEON_NEW_MEMMAP\|RADEON_IS_IGP}, \
		1175	{0x1002, 0x9614, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780\|RADEON_NEW_MEMMAP\|RADEON_IS_IGP}, \
		1176	{0x1002, 0x9615, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780\|RADEON_NEW_MEMMAP\|RADEON_IS_IGP}, \
		1177	{0x1002, 0x9616, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780\|RADEON_NEW_MEMMAP\|RADEON_IS_IGP}, \
		1178	{0, 0, 0}
		1179
		1180
		1181	enum chipset_type {
		1182	NOT_SUPPORTED,
		1183	SUPPORTED,
		1184	};
		1185
		1186	struct agp_version {
		1187	u16_t major;
		1188	u16_t minor;
		1189	};
		1190
		1191	struct agp_bridge_data;
		1192
		1193	struct agp_kern_info {
		1194	struct agp_version version;
		1195	struct pci_dev *device;
		1196	enum chipset_type chipset;
		1197	unsigned long mode;
		1198	unsigned long aper_base;
		1199	size_t aper_size;
		1200	int max_memory; /* In pages */
		1201	int current_memory;
		1202	bool cant_use_aperture;
		1203	unsigned long page_mask;
		1204	// struct vm_operations_struct *vm_ops;
		1205	};
		1206
		1207
		1208	/**
		1209	* AGP data.
		1210	*
		1211	* \sa drm_agp_init() and drm_device::agp.
		1212	*/
		1213	struct drm_agp_head {
		1214	struct agp_kern_info agp_info; /*< AGP device information /
		1215	// struct list_head memory;
		1216	unsigned long mode; /*< AGP mode /
		1217	struct agp_bridge_data *bridge;
		1218	int enabled; /*< whether the AGP bus as been enabled /
		1219	int acquired; /*< whether the AGP device has been acquired /
		1220	unsigned long base;
		1221	int agp_mtrr;
		1222	int cant_use_aperture;
		1223	unsigned long page_mask;
		1224	};
		1225
		1226
		1227	#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
		1228
		1229
		1230	/*
		1231	* ASICs helpers.
		1232	*/
1179	serge	1233	#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) \|\| \
		1234	(rdev->pdev->device == 0x5969))
1117	serge	1235	#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) \|\| \
		1236	(rdev->family == CHIP_RV200) \|\| \
		1237	(rdev->family == CHIP_RS100) \|\| \
		1238	(rdev->family == CHIP_RS200) \|\| \
		1239	(rdev->family == CHIP_RV250) \|\| \
		1240	(rdev->family == CHIP_RV280) \|\| \
		1241	(rdev->family == CHIP_RS300))
		1242	#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) \|\| \
		1243	(rdev->family == CHIP_RV350) \|\| \
		1244	(rdev->family == CHIP_R350) \|\| \
		1245	(rdev->family == CHIP_RV380) \|\| \
		1246	(rdev->family == CHIP_R420) \|\| \
		1247	(rdev->family == CHIP_R423) \|\| \
		1248	(rdev->family == CHIP_RV410) \|\| \
		1249	(rdev->family == CHIP_RS400) \|\| \
		1250	(rdev->family == CHIP_RS480))
		1251	#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
		1252	#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
		1253	#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
		1254
		1255
		1256	/*
		1257	* BIOS helpers.
		1258	*/
		1259	#define RBIOS8(i) (rdev->bios[i])
		1260	#define RBIOS16(i) (RBIOS8(i) \| (RBIOS8((i)+1) << 8))
		1261	#define RBIOS32(i) ((RBIOS16(i)) \| (RBIOS16((i)+2) << 16))
		1262
		1263	int radeon_combios_init(struct radeon_device *rdev);
		1264	void radeon_combios_fini(struct radeon_device *rdev);
		1265	int radeon_atombios_init(struct radeon_device *rdev);
		1266	void radeon_atombios_fini(struct radeon_device *rdev);
		1267
		1268
		1269	/*
		1270	* RING helpers.
		1271	*/
		1272	#define CP_PACKET0 0x00000000
		1273	#define PACKET0_BASE_INDEX_SHIFT 0
		1274	#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
		1275	#define PACKET0_COUNT_SHIFT 16
		1276	#define PACKET0_COUNT_MASK (0x3fff << 16)
		1277	#define CP_PACKET1 0x40000000
		1278	#define CP_PACKET2 0x80000000
		1279	#define PACKET2_PAD_SHIFT 0
		1280	#define PACKET2_PAD_MASK (0x3fffffff << 0)
		1281	#define CP_PACKET3 0xC0000000
		1282	#define PACKET3_IT_OPCODE_SHIFT 8
		1283	#define PACKET3_IT_OPCODE_MASK (0xff << 8)
		1284	#define PACKET3_COUNT_SHIFT 16
		1285	#define PACKET3_COUNT_MASK (0x3fff << 16)
		1286	/* PACKET3 op code */
		1287	#define PACKET3_NOP 0x10
		1288	#define PACKET3_3D_DRAW_VBUF 0x28
		1289	#define PACKET3_3D_DRAW_IMMD 0x29
		1290	#define PACKET3_3D_DRAW_INDX 0x2A
		1291	#define PACKET3_3D_LOAD_VBPNTR 0x2F
		1292	#define PACKET3_INDX_BUFFER 0x33
		1293	#define PACKET3_3D_DRAW_VBUF_2 0x34
		1294	#define PACKET3_3D_DRAW_IMMD_2 0x35
		1295	#define PACKET3_3D_DRAW_INDX_2 0x36
		1296	#define PACKET3_BITBLT_MULTI 0x9B
		1297
		1298	#define PACKET0(reg, n) (CP_PACKET0 \| \
		1299	REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) \| \
		1300	REG_SET(PACKET0_COUNT, (n)))
		1301	#define PACKET2(v) (CP_PACKET2 \| REG_SET(PACKET2_PAD, (v)))
		1302	#define PACKET3(op, n) (CP_PACKET3 \| \
		1303	REG_SET(PACKET3_IT_OPCODE, (op)) \| \
		1304	REG_SET(PACKET3_COUNT, (n)))
		1305
		1306	#define PACKET_TYPE0 0
		1307	#define PACKET_TYPE1 1
		1308	#define PACKET_TYPE2 2
		1309	#define PACKET_TYPE3 3
		1310
		1311	#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
		1312	#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
		1313	#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
		1314	#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
		1315	#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
		1316
		1317	static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
		1318	{
		1319	#if DRM_DEBUG_CODE
		1320	if (rdev->cp.count_dw <= 0) {
		1321	DRM_ERROR("radeon: writting more dword to ring than expected !\n");
		1322	}
		1323	#endif
		1324	rdev->cp.ring[rdev->cp.wptr++] = v;
		1325	rdev->cp.wptr &= rdev->cp.ptr_mask;
		1326	rdev->cp.count_dw--;
		1327	rdev->cp.ring_free_dw--;
		1328	}
		1329
		1330
		1331	/*
		1332	* ASICs macro.
		1333	*/
		1334	#define radeon_init(rdev) (rdev)->asic->init((rdev))
1179	serge	1335	#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
		1336	#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
		1337	#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1117	serge	1338	#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
		1339	#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
		1340	#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
1179	serge	1341	#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1117	serge	1342	#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
		1343	#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
		1344	#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
		1345	#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
		1346	#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
1179	serge	1347	#define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev))
		1348	#define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev))
1117	serge	1349	#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
		1350	#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
		1351	#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
		1352	#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
		1353	#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
		1354	#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
		1355	#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
1179	serge	1356	#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1117	serge	1357	#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1179	serge	1358	#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
		1359	#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
		1360	#define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev))
1117	serge	1361	#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
		1362	#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1179	serge	1363	#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1117	serge	1364	#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
		1365	#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
		1366	#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
		1367	#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
		1368	#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
		1369	#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
		1370	#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
		1371	#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1179	serge	1372	#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
		1373	#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
		1374	#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1117	serge	1375
1179	serge	1376	/* Common functions */
		1377	extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
		1378	extern int radeon_modeset_init(struct radeon_device *rdev);
		1379	extern void radeon_modeset_fini(struct radeon_device *rdev);
		1380	extern bool radeon_card_posted(struct radeon_device *rdev);
		1381	extern int radeon_clocks_init(struct radeon_device *rdev);
		1382	extern void radeon_clocks_fini(struct radeon_device *rdev);
		1383	extern void radeon_scratch_init(struct radeon_device *rdev);
		1384	extern void radeon_surface_init(struct radeon_device *rdev);
		1385	extern int radeon_cs_parser_init(struct radeon_cs_parser p, void data);
1117	serge	1386
1179	serge	1387	/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
		1388	struct r100_mc_save {
		1389	u32 GENMO_WT;
		1390	u32 CRTC_EXT_CNTL;
		1391	u32 CRTC_GEN_CNTL;
		1392	u32 CRTC2_GEN_CNTL;
		1393	u32 CUR_OFFSET;
		1394	u32 CUR2_OFFSET;
		1395	};
		1396	extern void r100_cp_disable(struct radeon_device *rdev);
		1397	extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
		1398	extern void r100_cp_fini(struct radeon_device *rdev);
		1399	extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
		1400	extern int r100_pci_gart_init(struct radeon_device *rdev);
		1401	extern void r100_pci_gart_fini(struct radeon_device *rdev);
		1402	extern int r100_pci_gart_enable(struct radeon_device *rdev);
		1403	extern void r100_pci_gart_disable(struct radeon_device *rdev);
		1404	extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
		1405	extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
		1406	extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
		1407	extern void r100_ib_fini(struct radeon_device *rdev);
		1408	extern int r100_ib_init(struct radeon_device *rdev);
		1409	extern void r100_irq_disable(struct radeon_device *rdev);
		1410	extern int r100_irq_set(struct radeon_device *rdev);
		1411	extern void r100_mc_stop(struct radeon_device rdev, struct r100_mc_save save);
		1412	extern void r100_mc_resume(struct radeon_device rdev, struct r100_mc_save save);
		1413	extern void r100_vram_init_sizes(struct radeon_device *rdev);
		1414	extern void r100_wb_disable(struct radeon_device *rdev);
		1415	extern void r100_wb_fini(struct radeon_device *rdev);
		1416	extern int r100_wb_init(struct radeon_device *rdev);
		1417
		1418	/* r300,r350,rv350,rv370,rv380 */
		1419	extern void r300_set_reg_safe(struct radeon_device *rdev);
		1420	extern void r300_mc_program(struct radeon_device *rdev);
		1421	extern void r300_vram_info(struct radeon_device *rdev);
		1422	extern int rv370_pcie_gart_init(struct radeon_device *rdev);
		1423	extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
		1424	extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
		1425	extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
		1426
		1427	/* r420,r423,rv410 */
		1428	extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
		1429	extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
		1430	extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
		1431
		1432	/* rv515 */
		1433	extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
		1434
		1435	/* rs690, rs740 */
		1436	extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
		1437	struct drm_display_mode *mode1,
		1438	struct drm_display_mode *mode2);
		1439
		1440	/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
		1441	extern bool r600_card_posted(struct radeon_device *rdev);
		1442	extern void r600_cp_stop(struct radeon_device *rdev);
		1443	extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
		1444	extern int r600_cp_resume(struct radeon_device *rdev);
		1445	extern int r600_count_pipe_bits(uint32_t val);
		1446	extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
		1447	extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
		1448	extern int r600_pcie_gart_init(struct radeon_device *rdev);
		1449	extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
		1450	extern int r600_ib_test(struct radeon_device *rdev);
		1451	extern int r600_ring_test(struct radeon_device *rdev);
		1452	extern int r600_wb_init(struct radeon_device *rdev);
		1453	extern void r600_wb_fini(struct radeon_device *rdev);
		1454	extern void r600_scratch_init(struct radeon_device *rdev);
		1455	extern int r600_blit_init(struct radeon_device *rdev);
		1456	extern void r600_blit_fini(struct radeon_device *rdev);
		1457	extern int r600_cp_init_microcode(struct radeon_device *rdev);
		1458	extern int r600_gpu_reset(struct radeon_device *rdev);
		1459
		1460
		1461
		1462
		1463
		1464
		1465
		1466
		1467
1117	serge	1468	#define DRM_UDELAY(d) udelay(d)
		1469
		1470	resource_size_t
		1471	drm_get_resource_start(struct drm_device *dev, unsigned int resource);
		1472	resource_size_t
		1473	drm_get_resource_len(struct drm_device *dev, unsigned int resource);
		1474
1128	serge	1475	bool set_mode(struct drm_device *dev, int width, int height);
1117	serge	1476
1179	serge	1477
		1478
1117	serge	1479	#endif

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(root)/drivers/video/drm/radeon/radeon.h – Rev 1179