WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon.h

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28	#ifndef __RADEON_H__
		29	#define __RADEON_H__
		30
		31	//#include "radeon_object.h"
		32
		33	/* TODO: Here are things that needs to be done :
		34	* - surface allocator & initializer : (bit like scratch reg) should
		35	* initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
		36	* related to surface
		37	* - WB : write back stuff (do it bit like scratch reg things)
		38	* - Vblank : look at Jesse's rework and what we should do
		39	* - r600/r700: gart & cp
		40	* - cs : clean cs ioctl use bitmap & things like that.
		41	* - power management stuff
		42	* - Barrier in gart code
		43	* - Unmappabled vram ?
		44	* - TESTING, TESTING, TESTING
		45	*/
		46
1120	serge	47	#include
		48	#include
1117	serge	49
1120	serge	50	#include
1117	serge	51
1120	serge	52	#include
1123	serge	53	#include "drm_edid.h"
1117	serge	54	#include "radeon_mode.h"
		55	#include "radeon_reg.h"
		56	#include "r300.h"
		57
		58	#include
		59
1123	serge	60	extern int radeon_modeset;
1117	serge	61	extern int radeon_dynclks;
1123	serge	62	extern int radeon_r4xx_atom;
1117	serge	63	extern int radeon_gart_size;
1123	serge	64	extern int radeon_connector_table;
1117	serge	65
		66	/*
		67	* Copy from radeon_drv.h so we don't have to include both and have conflicting
		68	* symbol;
		69	*/
1120	serge	70	#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
		71	#define RADEON_IB_POOL_SIZE 16
1117	serge	72	#define RADEON_DEBUGFS_MAX_NUM_FILES 32
1120	serge	73	#define RADEONFB_CONN_LIMIT 4
1117	serge	74
		75	enum radeon_family {
		76	CHIP_R100,
		77	CHIP_RV100,
		78	CHIP_RS100,
		79	CHIP_RV200,
		80	CHIP_RS200,
		81	CHIP_R200,
		82	CHIP_RV250,
		83	CHIP_RS300,
		84	CHIP_RV280,
		85	CHIP_R300,
		86	CHIP_R350,
		87	CHIP_RV350,
		88	CHIP_RV380,
		89	CHIP_R420,
		90	CHIP_R423,
		91	CHIP_RV410,
		92	CHIP_RS400,
		93	CHIP_RS480,
		94	CHIP_RS600,
		95	CHIP_RS690,
		96	CHIP_RS740,
		97	CHIP_RV515,
		98	CHIP_R520,
		99	CHIP_RV530,
		100	CHIP_RV560,
		101	CHIP_RV570,
		102	CHIP_R580,
		103	CHIP_R600,
		104	CHIP_RV610,
		105	CHIP_RV630,
		106	CHIP_RV620,
		107	CHIP_RV635,
		108	CHIP_RV670,
		109	CHIP_RS780,
		110	CHIP_RV770,
		111	CHIP_RV730,
		112	CHIP_RV710,
		113	CHIP_LAST,
		114	};
		115
		116	enum radeon_chip_flags {
		117	RADEON_FAMILY_MASK = 0x0000ffffUL,
		118	RADEON_FLAGS_MASK = 0xffff0000UL,
		119	RADEON_IS_MOBILITY = 0x00010000UL,
		120	RADEON_IS_IGP = 0x00020000UL,
		121	RADEON_SINGLE_CRTC = 0x00040000UL,
		122	RADEON_IS_AGP = 0x00080000UL,
		123	RADEON_HAS_HIERZ = 0x00100000UL,
		124	RADEON_IS_PCIE = 0x00200000UL,
		125	RADEON_NEW_MEMMAP = 0x00400000UL,
		126	RADEON_IS_PCI = 0x00800000UL,
		127	RADEON_IS_IGPGART = 0x01000000UL,
		128	};
		129
		130
		131	/*
		132	* Errata workarounds.
		133	*/
		134	enum radeon_pll_errata {
		135	CHIP_ERRATA_R300_CG = 0x00000001,
		136	CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
		137	CHIP_ERRATA_PLL_DELAY = 0x00000004
		138	};
		139
		140
		141	struct radeon_device;
		142
		143
		144	/*
		145	* BIOS.
		146	*/
		147	bool radeon_get_bios(struct radeon_device *rdev);
		148
		149	/*
		150	* Clocks
		151	*/
		152
		153	struct radeon_clock {
		154	struct radeon_pll p1pll;
		155	struct radeon_pll p2pll;
		156	struct radeon_pll spll;
		157	struct radeon_pll mpll;
		158	/* 10 Khz units */
		159	uint32_t default_mclk;
		160	uint32_t default_sclk;
		161	};
		162
		163	/*
		164	* Fences.
		165	*/
		166	struct radeon_fence_driver {
		167	uint32_t scratch_reg;
		168	// atomic_t seq;
		169	uint32_t last_seq;
		170	unsigned long count_timeout;
		171	// wait_queue_head_t queue;
		172	// rwlock_t lock;
1120	serge	173	struct list_head created;
		174	struct list_head emited;
		175	struct list_head signaled;
1117	serge	176	};
		177
		178	struct radeon_fence {
		179	struct radeon_device *rdev;
		180	// struct kref kref;
1120	serge	181	struct list_head list;
1117	serge	182	/* protected by radeon_fence.lock */
		183	uint32_t seq;
		184	unsigned long timeout;
		185	bool emited;
		186	bool signaled;
		187	};
		188
		189	int radeon_fence_driver_init(struct radeon_device *rdev);
		190	void radeon_fence_driver_fini(struct radeon_device *rdev);
		191	int radeon_fence_create(struct radeon_device rdev, struct radeon_fence *fence);
		192	int radeon_fence_emit(struct radeon_device rdev, struct radeon_fence fence);
		193	void radeon_fence_process(struct radeon_device *rdev);
		194	bool radeon_fence_signaled(struct radeon_fence *fence);
		195	int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
		196	int radeon_fence_wait_next(struct radeon_device *rdev);
		197	int radeon_fence_wait_last(struct radeon_device *rdev);
		198	struct radeon_fence radeon_fence_ref(struct radeon_fence fence);
		199	void radeon_fence_unref(struct radeon_fence **fence);
		200
		201
		202	/*
		203	* Radeon buffer.
		204	*/
		205	struct radeon_object;
		206
		207	struct radeon_object_list {
1120	serge	208	struct list_head list;
1117	serge	209	struct radeon_object *robj;
		210	uint64_t gpu_offset;
		211	unsigned rdomain;
		212	unsigned wdomain;
		213	};
		214
1123	serge	215	int radeon_object_init(struct radeon_device *rdev);
		216	void radeon_object_fini(struct radeon_device *rdev);
		217	int radeon_object_create(struct radeon_device *rdev,
		218	struct drm_gem_object *gobj,
		219	unsigned long size,
		220	bool kernel,
		221	uint32_t domain,
		222	bool interruptible,
		223	struct radeon_object **robj_ptr);
1117	serge	224
		225
1123	serge	226	/*
		227	* GEM objects.
		228	*/
		229	struct radeon_gem {
		230	struct list_head objects;
		231	};
1117	serge	232
1126	serge	233	int radeon_gem_init(struct radeon_device *rdev);
		234	void radeon_gem_fini(struct radeon_device *rdev);
		235	int radeon_gem_object_create(struct radeon_device *rdev, int size,
		236	int alignment, int initial_domain,
		237	bool discardable, bool kernel,
		238	bool interruptible,
		239	struct drm_gem_object **obj);
		240	int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
		241	uint64_t *gpu_addr);
		242	void radeon_gem_object_unpin(struct drm_gem_object *obj);
1117	serge	243
		244
		245	/*
		246	* GART structures, functions & helpers
		247	*/
		248	struct radeon_mc;
		249
		250	struct radeon_gart_table_ram {
		251	volatile uint32_t *ptr;
		252	};
		253
		254	struct radeon_gart_table_vram {
		255	struct radeon_object *robj;
		256	volatile uint32_t *ptr;
		257	};
		258
		259	union radeon_gart_table {
		260	struct radeon_gart_table_ram ram;
		261	struct radeon_gart_table_vram vram;
		262	};
		263
		264	struct radeon_gart {
		265	dma_addr_t table_addr;
		266	unsigned num_gpu_pages;
		267	unsigned num_cpu_pages;
		268	unsigned table_size;
		269	union radeon_gart_table table;
		270	struct page **pages;
		271	dma_addr_t *pages_addr;
		272	bool ready;
		273	};
		274
		275	int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
		276	void radeon_gart_table_ram_free(struct radeon_device *rdev);
		277	int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
		278	void radeon_gart_table_vram_free(struct radeon_device *rdev);
		279	int radeon_gart_init(struct radeon_device *rdev);
		280	void radeon_gart_fini(struct radeon_device *rdev);
		281	void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
		282	int pages);
1120	serge	283	int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
		284	int pages, u32_t *pagelist);
1117	serge	285
		286
		287	/*
		288	* GPU MC structures, functions & helpers
		289	*/
		290	struct radeon_mc {
		291	resource_size_t aper_size;
		292	resource_size_t aper_base;
		293	resource_size_t agp_base;
		294	unsigned gtt_location;
		295	unsigned gtt_size;
		296	unsigned vram_location;
		297	unsigned vram_size;
		298	unsigned vram_width;
		299	int vram_mtrr;
		300	bool vram_is_ddr;
		301	};
		302
		303	int radeon_mc_setup(struct radeon_device *rdev);
		304
		305
		306	/*
		307	* GPU scratch registers structures, functions & helpers
		308	*/
		309	struct radeon_scratch {
		310	unsigned num_reg;
		311	bool free[32];
		312	uint32_t reg[32];
		313	};
		314
		315	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg);
		316	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
		317
		318
		319	/*
		320	* IRQS.
		321	*/
		322	struct radeon_irq {
		323	bool installed;
		324	bool sw_int;
		325	/* FIXME: use a define max crtc rather than hardcode it */
		326	bool crtc_vblank_int[2];
		327	};
		328
		329	int radeon_irq_kms_init(struct radeon_device *rdev);
		330	void radeon_irq_kms_fini(struct radeon_device *rdev);
		331
		332
		333	/*
		334	* CP & ring.
		335	*/
		336	struct radeon_ib {
1120	serge	337	struct list_head list;
1117	serge	338	unsigned long idx;
		339	uint64_t gpu_addr;
		340	struct radeon_fence *fence;
		341	volatile uint32_t *ptr;
		342	uint32_t length_dw;
		343	};
		344
		345	struct radeon_ib_pool {
		346	// struct mutex mutex;
		347	struct radeon_object *robj;
1120	serge	348	struct list_head scheduled_ibs;
1117	serge	349	struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
		350	bool ready;
1120	serge	351	DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
1117	serge	352	};
		353
		354	struct radeon_cp {
		355	struct radeon_object *ring_obj;
		356	volatile uint32_t *ring;
		357	unsigned rptr;
		358	unsigned wptr;
		359	unsigned wptr_old;
		360	unsigned ring_size;
		361	unsigned ring_free_dw;
		362	int count_dw;
		363	uint64_t gpu_addr;
		364	uint32_t align_mask;
		365	uint32_t ptr_mask;
		366	// struct mutex mutex;
		367	bool ready;
		368	};
		369
		370	int radeon_ib_get(struct radeon_device rdev, struct radeon_ib *ib);
		371	void radeon_ib_free(struct radeon_device rdev, struct radeon_ib *ib);
		372	int radeon_ib_schedule(struct radeon_device rdev, struct radeon_ib ib);
		373	int radeon_ib_pool_init(struct radeon_device *rdev);
		374	void radeon_ib_pool_fini(struct radeon_device *rdev);
		375	int radeon_ib_test(struct radeon_device *rdev);
		376	/* Ring access between begin & end cannot sleep */
		377	void radeon_ring_free_size(struct radeon_device *rdev);
		378	int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
		379	void radeon_ring_unlock_commit(struct radeon_device *rdev);
		380	void radeon_ring_unlock_undo(struct radeon_device *rdev);
		381	int radeon_ring_test(struct radeon_device *rdev);
		382	int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
		383	void radeon_ring_fini(struct radeon_device *rdev);
		384
		385
		386	/*
		387	* CS.
		388	*/
		389	struct radeon_cs_reloc {
		390	// struct drm_gem_object *gobj;
		391	struct radeon_object *robj;
1120	serge	392	struct radeon_object_list lobj;
1117	serge	393	uint32_t handle;
		394	uint32_t flags;
		395	};
		396
		397	struct radeon_cs_chunk {
		398	uint32_t chunk_id;
		399	uint32_t length_dw;
		400	uint32_t *kdata;
		401	};
		402
		403	struct radeon_cs_parser {
		404	struct radeon_device *rdev;
		405	// struct drm_file *filp;
		406	/* chunks */
		407	unsigned nchunks;
		408	struct radeon_cs_chunk *chunks;
		409	uint64_t *chunks_array;
		410	/* IB */
		411	unsigned idx;
		412	/* relocations */
		413	unsigned nrelocs;
		414	struct radeon_cs_reloc *relocs;
		415	struct radeon_cs_reloc **relocs_ptr;
1120	serge	416	struct list_head validated;
1117	serge	417	/* indices of various chunks */
		418	int chunk_ib_idx;
		419	int chunk_relocs_idx;
		420	struct radeon_ib *ib;
		421	void *track;
		422	};
		423
		424	struct radeon_cs_packet {
		425	unsigned idx;
		426	unsigned type;
		427	unsigned reg;
		428	unsigned opcode;
		429	int count;
		430	unsigned one_reg_wr;
		431	};
		432
		433	typedef int (radeon_packet0_check_t)(struct radeon_cs_parser p,
		434	struct radeon_cs_packet *pkt,
		435	unsigned idx, unsigned reg);
		436	typedef int (radeon_packet3_check_t)(struct radeon_cs_parser p,
		437	struct radeon_cs_packet *pkt);
		438
		439
		440	/*
		441	* AGP
		442	*/
		443	int radeon_agp_init(struct radeon_device *rdev);
		444	void radeon_agp_fini(struct radeon_device *rdev);
		445
		446
		447	/*
		448	* Writeback
		449	*/
		450	struct radeon_wb {
		451	struct radeon_object *wb_obj;
		452	volatile uint32_t *wb;
		453	uint64_t gpu_addr;
		454	};
		455
		456
		457	/*
		458	* ASIC specific functions.
		459	*/
		460	struct radeon_asic {
		461	int (init)(struct radeon_device rdev);
		462	void (errata)(struct radeon_device rdev);
		463	void (vram_info)(struct radeon_device rdev);
		464	int (gpu_reset)(struct radeon_device rdev);
		465	int (mc_init)(struct radeon_device rdev);
		466	void (mc_fini)(struct radeon_device rdev);
		467	int (wb_init)(struct radeon_device rdev);
		468	void (wb_fini)(struct radeon_device rdev);
		469	int (gart_enable)(struct radeon_device rdev);
		470	void (gart_disable)(struct radeon_device rdev);
		471	void (gart_tlb_flush)(struct radeon_device rdev);
		472	int (gart_set_page)(struct radeon_device rdev, int i, uint64_t addr);
		473	int (cp_init)(struct radeon_device rdev, unsigned ring_size);
		474	void (cp_fini)(struct radeon_device rdev);
		475	void (cp_disable)(struct radeon_device rdev);
		476	void (ring_start)(struct radeon_device rdev);
		477	int (irq_set)(struct radeon_device rdev);
		478	int (irq_process)(struct radeon_device rdev);
		479	void (fence_ring_emit)(struct radeon_device rdev, struct radeon_fence *fence);
		480	int (cs_parse)(struct radeon_cs_parser p);
		481	int (copy_blit)(struct radeon_device rdev,
		482	uint64_t src_offset,
		483	uint64_t dst_offset,
		484	unsigned num_pages,
		485	struct radeon_fence *fence);
		486	int (copy_dma)(struct radeon_device rdev,
		487	uint64_t src_offset,
		488	uint64_t dst_offset,
		489	unsigned num_pages,
		490	struct radeon_fence *fence);
		491	int (copy)(struct radeon_device rdev,
		492	uint64_t src_offset,
		493	uint64_t dst_offset,
		494	unsigned num_pages,
		495	struct radeon_fence *fence);
		496	void (set_engine_clock)(struct radeon_device rdev, uint32_t eng_clock);
		497	void (set_memory_clock)(struct radeon_device rdev, uint32_t mem_clock);
		498	void (set_pcie_lanes)(struct radeon_device rdev, int lanes);
		499	void (set_clock_gating)(struct radeon_device rdev, int enable);
		500	};
		501
		502	union radeon_asic_config {
		503	struct r300_asic r300;
		504	};
		505
		506
		507	/*
		508	/*
		509	* Core structure, functions and helpers.
		510	*/
		511	typedef uint32_t (radeon_rreg_t)(struct radeon_device, uint32_t);
		512	typedef void (radeon_wreg_t)(struct radeon_device, uint32_t, uint32_t);
		513
		514	struct radeon_device {
		515	struct drm_device *ddev;
		516	struct pci_dev *pdev;
		517	/* ASIC */
		518	union radeon_asic_config config;
		519	enum radeon_family family;
		520	unsigned long flags;
		521	int usec_timeout;
		522	enum radeon_pll_errata pll_errata;
		523	int num_gb_pipes;
		524	int disp_priority;
		525	/* BIOS */
		526	uint8_t *bios;
		527	bool is_atom_bios;
		528	uint16_t bios_header_start;
		529
		530	// struct radeon_object *stollen_vga_memory;
1126	serge	531	struct fb_info *fbdev_info;
1117	serge	532	struct radeon_object *fbdev_robj;
		533	struct radeon_framebuffer *fbdev_rfb;
		534
		535	/* Register mmio */
		536	unsigned long rmmio_base;
		537	unsigned long rmmio_size;
		538	void *rmmio;
		539
1120	serge	540	radeon_rreg_t mm_rreg;
		541	radeon_wreg_t mm_wreg;
		542	radeon_rreg_t mc_rreg;
		543	radeon_wreg_t mc_wreg;
		544	radeon_rreg_t pll_rreg;
		545	radeon_wreg_t pll_wreg;
		546	radeon_rreg_t pcie_rreg;
		547	radeon_wreg_t pcie_wreg;
		548	radeon_rreg_t pciep_rreg;
		549	radeon_wreg_t pciep_wreg;
		550	struct radeon_clock clock;
1117	serge	551	struct radeon_mc mc;
		552	struct radeon_gart gart;
		553	struct radeon_mode_info mode_info;
		554	struct radeon_scratch scratch;
1120	serge	555	// struct radeon_mman mman;
1117	serge	556	struct radeon_fence_driver fence_drv;
1120	serge	557	struct radeon_cp cp;
1117	serge	558	struct radeon_ib_pool ib_pool;
		559	// struct radeon_irq irq;
		560	struct radeon_asic *asic;
1126	serge	561	struct radeon_gem gem;
1117	serge	562	// struct mutex cs_mutex;
		563	struct radeon_wb wb;
		564	bool gpu_lockup;
		565	bool shutdown;
		566	bool suspend;
		567	};
		568
		569	int radeon_device_init(struct radeon_device *rdev,
		570	struct drm_device *ddev,
		571	struct pci_dev *pdev,
		572	uint32_t flags);
		573	void radeon_device_fini(struct radeon_device *rdev);
		574	int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
		575
		576	#define __iomem
		577	#define __force
		578
		579
		580
		581	static inline uint8_t __raw_readb(const volatile void __iomem *addr)
		582	{
		583	return (const volatile uint8_t __force ) addr;
		584	}
		585
		586	static inline uint16_t __raw_readw(const volatile void __iomem *addr)
		587	{
		588	return (const volatile uint16_t __force ) addr;
		589	}
		590
		591	static inline uint32_t __raw_readl(const volatile void __iomem *addr)
		592	{
		593	return (const volatile uint32_t __force ) addr;
		594	}
		595
		596	#define readb __raw_readb
		597	#define readw __raw_readw
		598	#define readl __raw_readl
		599
		600
		601
		602	static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)
		603	{
		604	(volatile uint8_t __force ) addr = b;
		605	}
		606
		607	static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)
		608	{
		609	(volatile uint16_t __force ) addr = b;
		610	}
		611
		612	static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)
		613	{
		614	(volatile uint32_t __force ) addr = b;
		615	}
		616
		617	#define writeb __raw_writeb
		618	#define writew __raw_writew
		619	#define writel __raw_writel
		620
		621	//#define writeb(b,addr) (volatile uint8_t ) addr = (uint8_t)b
		622	//#define writew(b,addr) (volatile uint16_t) addr = (uint16_t)b
		623	//#define writel(b,addr) (volatile uint32_t) addr = (uint32_t)b
		624
		625
		626
		627	/*
		628	* Registers read & write functions.
		629	*/
		630	#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
		631	#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
		632	#define RREG32(reg) rdev->mm_rreg(rdev, (reg))
		633	#define WREG32(reg, v) rdev->mm_wreg(rdev, (reg), (v))
		634	#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
		635	#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
		636	#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
		637	#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
		638	#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
		639	#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
		640	#define RREG32_PCIE(reg) rdev->pcie_rreg(rdev, (reg))
		641	#define WREG32_PCIE(reg, v) rdev->pcie_wreg(rdev, (reg), (v))
		642	#define WREG32_P(reg, val, mask) \
		643	do { \
		644	uint32_t tmp_ = RREG32(reg); \
		645	tmp_ &= (mask); \
		646	tmp_ \|= ((val) & ~(mask)); \
		647	WREG32(reg, tmp_); \
		648	} while (0)
		649	#define WREG32_PLL_P(reg, val, mask) \
		650	do { \
		651	uint32_t tmp_ = RREG32_PLL(reg); \
		652	tmp_ &= (mask); \
		653	tmp_ \|= ((val) & ~(mask)); \
		654	WREG32_PLL(reg, tmp_); \
		655	} while (0)
		656
		657
		658	#define radeon_PCI_IDS \
		659	{0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_IS_MOBILITY}, \
		660	{0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		661	{0x1002, 0x3154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		662	{0x1002, 0x3E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_NEW_MEMMAP}, \
		663	{0x1002, 0x3E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_NEW_MEMMAP}, \
		664	{0x1002, 0x4136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100\|RADEON_IS_IGP}, \
		665	{0x1002, 0x4137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200\|RADEON_IS_IGP}, \
		666	{0x1002, 0x4144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
		667	{0x1002, 0x4145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
		668	{0x1002, 0x4146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
		669	{0x1002, 0x4147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
		670	{0x1002, 0x4148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
		671	{0x1002, 0x4149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
		672	{0x1002, 0x414A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
		673	{0x1002, 0x414B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
		674	{0x1002, 0x4150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
		675	{0x1002, 0x4151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
		676	{0x1002, 0x4152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
		677	{0x1002, 0x4153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
		678	{0x1002, 0x4154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
		679	{0x1002, 0x4155, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
		680	{0x1002, 0x4156, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
		681	{0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200\|RADEON_IS_IGP}, \
		682	{0x1002, 0x4242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
		683	{0x1002, 0x4243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
		684	{0x1002, 0x4336, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100\|RADEON_IS_IGP\|RADEON_IS_MOBILITY}, \
		685	{0x1002, 0x4337, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200\|RADEON_IS_IGP\|RADEON_IS_MOBILITY}, \
		686	{0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200\|RADEON_IS_IGP\|RADEON_IS_MOBILITY}, \
		687	{0x1002, 0x4966, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \
		688	{0x1002, 0x4967, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \
		689	{0x1002, 0x4A48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		690	{0x1002, 0x4A49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		691	{0x1002, 0x4A4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		692	{0x1002, 0x4A4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		693	{0x1002, 0x4A4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		694	{0x1002, 0x4A4D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		695	{0x1002, 0x4A4E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		696	{0x1002, 0x4A4F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		697	{0x1002, 0x4A50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		698	{0x1002, 0x4A54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		699	{0x1002, 0x4B49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		700	{0x1002, 0x4B4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		701	{0x1002, 0x4B4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		702	{0x1002, 0x4B4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420\|RADEON_NEW_MEMMAP}, \
		703	{0x1002, 0x4C57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200\|RADEON_IS_MOBILITY}, \
		704	{0x1002, 0x4C58, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200\|RADEON_IS_MOBILITY}, \
		705	{0x1002, 0x4C59, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100\|RADEON_IS_MOBILITY}, \
		706	{0x1002, 0x4C5A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100\|RADEON_IS_MOBILITY}, \
		707	{0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250\|RADEON_IS_MOBILITY}, \
		708	{0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250\|RADEON_IS_MOBILITY}, \
		709	{0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250\|RADEON_IS_MOBILITY}, \
		710	{0x1002, 0x4E44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
		711	{0x1002, 0x4E45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
		712	{0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
		713	{0x1002, 0x4E47, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
		714	{0x1002, 0x4E48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
		715	{0x1002, 0x4E49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
		716	{0x1002, 0x4E4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
		717	{0x1002, 0x4E4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
		718	{0x1002, 0x4E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350\|RADEON_IS_MOBILITY}, \
		719	{0x1002, 0x4E51, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350\|RADEON_IS_MOBILITY}, \
		720	{0x1002, 0x4E52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350\|RADEON_IS_MOBILITY}, \
		721	{0x1002, 0x4E53, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350\|RADEON_IS_MOBILITY}, \
		722	{0x1002, 0x4E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350\|RADEON_IS_MOBILITY}, \
		723	{0x1002, 0x4E56, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350\|RADEON_IS_MOBILITY}, \
		724	{0x1002, 0x5144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100\|RADEON_SINGLE_CRTC}, \
		725	{0x1002, 0x5145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100\|RADEON_SINGLE_CRTC}, \
		726	{0x1002, 0x5146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100\|RADEON_SINGLE_CRTC}, \
		727	{0x1002, 0x5147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100\|RADEON_SINGLE_CRTC}, \
		728	{0x1002, 0x5148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
		729	{0x1002, 0x514C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
		730	{0x1002, 0x514D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
		731	{0x1002, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \
		732	{0x1002, 0x5158, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \
		733	{0x1002, 0x5159, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
		734	{0x1002, 0x515A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
		735	{0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
		736	{0x1002, 0x5460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_IS_MOBILITY}, \
		737	{0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_IS_MOBILITY}, \
		738	{0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_IS_MOBILITY}, \
		739	{0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_NEW_MEMMAP}, \
		740	{0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		741	{0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		742	{0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		743	{0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		744	{0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		745	{0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		746	{0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		747	{0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		748	{0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		749	{0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		750	{0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		751	{0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		752	{0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		753	{0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		754	{0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		755	{0x1002, 0x5652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		756	{0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		757	{0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300\|RADEON_IS_IGP}, \
		758	{0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300\|RADEON_IS_IGP\|RADEON_IS_MOBILITY}, \
		759	{0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480\|RADEON_IS_IGP\|RADEON_IS_MOBILITY\|RADEON_IS_IGPGART}, \
		760	{0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480\|RADEON_IS_IGP\|RADEON_IS_MOBILITY\|RADEON_IS_IGPGART}, \
		761	{0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480\|RADEON_IS_IGP\|RADEON_IS_MOBILITY\|RADEON_IS_IGPGART}, \
		762	{0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480\|RADEON_IS_IGP\|RADEON_IS_MOBILITY\|RADEON_IS_IGPGART}, \
		763	{0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
		764	{0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
		765	{0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
		766	{0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
		767	{0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
		768	{0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
		769	{0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400\|RADEON_IS_IGP\|RADEON_IS_IGPGART}, \
		770	{0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400\|RADEON_IS_IGP\|RADEON_IS_MOBILITY\|RADEON_IS_IGPGART}, \
		771	{0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400\|RADEON_IS_IGP\|RADEON_IS_IGPGART}, \
		772	{0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400\|RADEON_IS_IGP\|RADEON_IS_MOBILITY\|RADEON_IS_IGPGART}, \
		773	{0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_NEW_MEMMAP}, \
		774	{0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_NEW_MEMMAP}, \
		775	{0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_NEW_MEMMAP}, \
		776	{0x1002, 0x5b64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_NEW_MEMMAP}, \
		777	{0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380\|RADEON_NEW_MEMMAP}, \
		778	{0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280\|RADEON_IS_MOBILITY}, \
		779	{0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280\|RADEON_IS_MOBILITY}, \
		780	{0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		781	{0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		782	{0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		783	{0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		784	{0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		785	{0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		786	{0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		787	{0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		788	{0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		789	{0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423\|RADEON_NEW_MEMMAP}, \
		790	{0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \
		791	{0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \
		792	{0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \
		793	{0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \
		794	{0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \
		795	{0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \
		796	{0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		797	{0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		798	{0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		799	{0x1002, 0x7103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		800	{0x1002, 0x7104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		801	{0x1002, 0x7105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		802	{0x1002, 0x7106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		803	{0x1002, 0x7108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		804	{0x1002, 0x7109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		805	{0x1002, 0x710A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		806	{0x1002, 0x710B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		807	{0x1002, 0x710C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		808	{0x1002, 0x710E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		809	{0x1002, 0x710F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
		810	{0x1002, 0x7140, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		811	{0x1002, 0x7141, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		812	{0x1002, 0x7142, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		813	{0x1002, 0x7143, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		814	{0x1002, 0x7144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		815	{0x1002, 0x7145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		816	{0x1002, 0x7146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		817	{0x1002, 0x7147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		818	{0x1002, 0x7149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		819	{0x1002, 0x714A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		820	{0x1002, 0x714B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		821	{0x1002, 0x714C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		822	{0x1002, 0x714D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		823	{0x1002, 0x714E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		824	{0x1002, 0x714F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		825	{0x1002, 0x7151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		826	{0x1002, 0x7152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		827	{0x1002, 0x7153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		828	{0x1002, 0x715E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		829	{0x1002, 0x715F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		830	{0x1002, 0x7180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		831	{0x1002, 0x7181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		832	{0x1002, 0x7183, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		833	{0x1002, 0x7186, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		834	{0x1002, 0x7187, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		835	{0x1002, 0x7188, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		836	{0x1002, 0x718A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		837	{0x1002, 0x718B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		838	{0x1002, 0x718C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		839	{0x1002, 0x718D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		840	{0x1002, 0x718F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		841	{0x1002, 0x7193, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		842	{0x1002, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		843	{0x1002, 0x719B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		844	{0x1002, 0x719F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		845	{0x1002, 0x71C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		846	{0x1002, 0x71C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		847	{0x1002, 0x71C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		848	{0x1002, 0x71C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		849	{0x1002, 0x71C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		850	{0x1002, 0x71C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		851	{0x1002, 0x71C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		852	{0x1002, 0x71C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		853	{0x1002, 0x71CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		854	{0x1002, 0x71CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		855	{0x1002, 0x71D2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		856	{0x1002, 0x71D4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		857	{0x1002, 0x71D5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		858	{0x1002, 0x71D6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		859	{0x1002, 0x71DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_NEW_MEMMAP}, \
		860	{0x1002, 0x71DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		861	{0x1002, 0x7200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_NEW_MEMMAP}, \
		862	{0x1002, 0x7210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		863	{0x1002, 0x7211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		864	{0x1002, 0x7240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		865	{0x1002, 0x7243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		866	{0x1002, 0x7244, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		867	{0x1002, 0x7245, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		868	{0x1002, 0x7246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		869	{0x1002, 0x7247, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		870	{0x1002, 0x7248, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		871	{0x1002, 0x7249, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		872	{0x1002, 0x724A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		873	{0x1002, 0x724B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		874	{0x1002, 0x724C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		875	{0x1002, 0x724D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		876	{0x1002, 0x724E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		877	{0x1002, 0x724F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_NEW_MEMMAP}, \
		878	{0x1002, 0x7280, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570\|RADEON_NEW_MEMMAP}, \
		879	{0x1002, 0x7281, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560\|RADEON_NEW_MEMMAP}, \
		880	{0x1002, 0x7283, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560\|RADEON_NEW_MEMMAP}, \
		881	{0x1002, 0x7284, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		882	{0x1002, 0x7287, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560\|RADEON_NEW_MEMMAP}, \
		883	{0x1002, 0x7288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570\|RADEON_NEW_MEMMAP}, \
		884	{0x1002, 0x7289, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570\|RADEON_NEW_MEMMAP}, \
		885	{0x1002, 0x728B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570\|RADEON_NEW_MEMMAP}, \
		886	{0x1002, 0x728C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570\|RADEON_NEW_MEMMAP}, \
		887	{0x1002, 0x7290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560\|RADEON_NEW_MEMMAP}, \
		888	{0x1002, 0x7291, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560\|RADEON_NEW_MEMMAP}, \
		889	{0x1002, 0x7293, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560\|RADEON_NEW_MEMMAP}, \
		890	{0x1002, 0x7297, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560\|RADEON_NEW_MEMMAP}, \
		891	{0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP}, \
		892	{0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300\|RADEON_IS_IGP\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		893	{0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP\|RADEON_IS_IGPGART}, \
		894	{0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP\|RADEON_IS_IGPGART}, \
		895	{0x1002, 0x793f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP}, \
		896	{0x1002, 0x7941, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP}, \
		897	{0x1002, 0x7942, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP}, \
		898	{0x1002, 0x796c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP\|RADEON_IS_IGPGART}, \
		899	{0x1002, 0x796d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP\|RADEON_IS_IGPGART}, \
		900	{0x1002, 0x796e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP\|RADEON_IS_IGPGART}, \
		901	{0x1002, 0x796f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740\|RADEON_IS_IGP\|RADEON_NEW_MEMMAP\|RADEON_IS_IGPGART}, \
		902	{0x1002, 0x9400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600\|RADEON_NEW_MEMMAP}, \
		903	{0x1002, 0x9401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600\|RADEON_NEW_MEMMAP}, \
		904	{0x1002, 0x9402, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600\|RADEON_NEW_MEMMAP}, \
		905	{0x1002, 0x9403, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600\|RADEON_NEW_MEMMAP}, \
		906	{0x1002, 0x9405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600\|RADEON_NEW_MEMMAP}, \
		907	{0x1002, 0x940A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600\|RADEON_NEW_MEMMAP}, \
		908	{0x1002, 0x940B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600\|RADEON_NEW_MEMMAP}, \
		909	{0x1002, 0x940F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600\|RADEON_NEW_MEMMAP}, \
		910	{0x1002, 0x9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		911	{0x1002, 0x9441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		912	{0x1002, 0x9442, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		913	{0x1002, 0x9444, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		914	{0x1002, 0x9446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		915	{0x1002, 0x944A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		916	{0x1002, 0x944B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		917	{0x1002, 0x944C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		918	{0x1002, 0x944E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		919	{0x1002, 0x9450, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		920	{0x1002, 0x9452, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		921	{0x1002, 0x9456, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		922	{0x1002, 0x945A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		923	{0x1002, 0x945B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		924	{0x1002, 0x9460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		925	{0x1002, 0x9462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_NEW_MEMMAP}, \
		926	{0x1002, 0x946A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		927	{0x1002, 0x946B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		928	{0x1002, 0x947A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		929	{0x1002, 0x947B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		930	{0x1002, 0x9480, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		931	{0x1002, 0x9487, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_NEW_MEMMAP}, \
		932	{0x1002, 0x9488, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		933	{0x1002, 0x9489, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		934	{0x1002, 0x948F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_NEW_MEMMAP}, \
		935	{0x1002, 0x9490, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_NEW_MEMMAP}, \
		936	{0x1002, 0x9491, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		937	{0x1002, 0x9498, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_NEW_MEMMAP}, \
		938	{0x1002, 0x949C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_NEW_MEMMAP}, \
		939	{0x1002, 0x949E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_NEW_MEMMAP}, \
		940	{0x1002, 0x949F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730\|RADEON_NEW_MEMMAP}, \
		941	{0x1002, 0x94C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		942	{0x1002, 0x94C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		943	{0x1002, 0x94C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		944	{0x1002, 0x94C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		945	{0x1002, 0x94C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		946	{0x1002, 0x94C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		947	{0x1002, 0x94C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		948	{0x1002, 0x94C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		949	{0x1002, 0x94C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		950	{0x1002, 0x94CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		951	{0x1002, 0x94CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		952	{0x1002, 0x94CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610\|RADEON_NEW_MEMMAP}, \
		953	{0x1002, 0x9500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		954	{0x1002, 0x9501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		955	{0x1002, 0x9504, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		956	{0x1002, 0x9505, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		957	{0x1002, 0x9506, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		958	{0x1002, 0x9507, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		959	{0x1002, 0x9508, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		960	{0x1002, 0x9509, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		961	{0x1002, 0x950F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		962	{0x1002, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		963	{0x1002, 0x9515, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		964	{0x1002, 0x9517, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		965	{0x1002, 0x9519, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670\|RADEON_NEW_MEMMAP}, \
		966	{0x1002, 0x9540, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710\|RADEON_NEW_MEMMAP}, \
		967	{0x1002, 0x9541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710\|RADEON_NEW_MEMMAP}, \
		968	{0x1002, 0x9542, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710\|RADEON_NEW_MEMMAP}, \
		969	{0x1002, 0x954E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710\|RADEON_NEW_MEMMAP}, \
		970	{0x1002, 0x954F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710\|RADEON_NEW_MEMMAP}, \
		971	{0x1002, 0x9552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		972	{0x1002, 0x9553, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		973	{0x1002, 0x9555, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		974	{0x1002, 0x9580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		975	{0x1002, 0x9581, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		976	{0x1002, 0x9583, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		977	{0x1002, 0x9586, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		978	{0x1002, 0x9587, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		979	{0x1002, 0x9588, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		980	{0x1002, 0x9589, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		981	{0x1002, 0x958A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		982	{0x1002, 0x958B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		983	{0x1002, 0x958C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		984	{0x1002, 0x958D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		985	{0x1002, 0x958E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_NEW_MEMMAP}, \
		986	{0x1002, 0x958F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		987	{0x1002, 0x9590, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_NEW_MEMMAP}, \
		988	{0x1002, 0x9591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		989	{0x1002, 0x9593, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		990	{0x1002, 0x9595, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		991	{0x1002, 0x9596, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_NEW_MEMMAP}, \
		992	{0x1002, 0x9597, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_NEW_MEMMAP}, \
		993	{0x1002, 0x9598, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_NEW_MEMMAP}, \
		994	{0x1002, 0x9599, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_NEW_MEMMAP}, \
		995	{0x1002, 0x959B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		996	{0x1002, 0x95C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		997	{0x1002, 0x95C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		998	{0x1002, 0x95C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		999	{0x1002, 0x95C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		1000	{0x1002, 0x95C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		1001	{0x1002, 0x95C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1002	{0x1002, 0x95C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		1003	{0x1002, 0x95CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		1004	{0x1002, 0x95CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		1005	{0x1002, 0x95CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		1006	{0x1002, 0x95CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620\|RADEON_NEW_MEMMAP}, \
		1007	{0x1002, 0x9610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780\|RADEON_NEW_MEMMAP\|RADEON_IS_IGP}, \
		1008	{0x1002, 0x9611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780\|RADEON_NEW_MEMMAP\|RADEON_IS_IGP}, \
		1009	{0x1002, 0x9612, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780\|RADEON_NEW_MEMMAP\|RADEON_IS_IGP}, \
		1010	{0x1002, 0x9613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780\|RADEON_NEW_MEMMAP\|RADEON_IS_IGP}, \
		1011	{0x1002, 0x9614, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780\|RADEON_NEW_MEMMAP\|RADEON_IS_IGP}, \
		1012	{0x1002, 0x9615, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780\|RADEON_NEW_MEMMAP\|RADEON_IS_IGP}, \
		1013	{0x1002, 0x9616, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780\|RADEON_NEW_MEMMAP\|RADEON_IS_IGP}, \
		1014	{0, 0, 0}
		1015
		1016
		1017	enum chipset_type {
		1018	NOT_SUPPORTED,
		1019	SUPPORTED,
		1020	};
		1021
		1022	struct agp_version {
		1023	u16_t major;
		1024	u16_t minor;
		1025	};
		1026
		1027	struct agp_bridge_data;
		1028
		1029	struct agp_kern_info {
		1030	struct agp_version version;
		1031	struct pci_dev *device;
		1032	enum chipset_type chipset;
		1033	unsigned long mode;
		1034	unsigned long aper_base;
		1035	size_t aper_size;
		1036	int max_memory; /* In pages */
		1037	int current_memory;
		1038	bool cant_use_aperture;
		1039	unsigned long page_mask;
		1040	// struct vm_operations_struct *vm_ops;
		1041	};
		1042
		1043
		1044	/**
		1045	* AGP data.
		1046	*
		1047	* \sa drm_agp_init() and drm_device::agp.
		1048	*/
		1049	struct drm_agp_head {
		1050	struct agp_kern_info agp_info; /*< AGP device information /
		1051	// struct list_head memory;
		1052	unsigned long mode; /*< AGP mode /
		1053	struct agp_bridge_data *bridge;
		1054	int enabled; /*< whether the AGP bus as been enabled /
		1055	int acquired; /*< whether the AGP device has been acquired /
		1056	unsigned long base;
		1057	int agp_mtrr;
		1058	int cant_use_aperture;
		1059	unsigned long page_mask;
		1060	};
		1061
		1062
		1063	#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
		1064
		1065
		1066	/*
		1067	* ASICs helpers.
		1068	*/
		1069	#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) \|\| \
		1070	(rdev->family == CHIP_RV200) \|\| \
		1071	(rdev->family == CHIP_RS100) \|\| \
		1072	(rdev->family == CHIP_RS200) \|\| \
		1073	(rdev->family == CHIP_RV250) \|\| \
		1074	(rdev->family == CHIP_RV280) \|\| \
		1075	(rdev->family == CHIP_RS300))
		1076	#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) \|\| \
		1077	(rdev->family == CHIP_RV350) \|\| \
		1078	(rdev->family == CHIP_R350) \|\| \
		1079	(rdev->family == CHIP_RV380) \|\| \
		1080	(rdev->family == CHIP_R420) \|\| \
		1081	(rdev->family == CHIP_R423) \|\| \
		1082	(rdev->family == CHIP_RV410) \|\| \
		1083	(rdev->family == CHIP_RS400) \|\| \
		1084	(rdev->family == CHIP_RS480))
		1085	#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
		1086	#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
		1087	#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
		1088
		1089
		1090	/*
		1091	* BIOS helpers.
		1092	*/
		1093	#define RBIOS8(i) (rdev->bios[i])
		1094	#define RBIOS16(i) (RBIOS8(i) \| (RBIOS8((i)+1) << 8))
		1095	#define RBIOS32(i) ((RBIOS16(i)) \| (RBIOS16((i)+2) << 16))
		1096
		1097	int radeon_combios_init(struct radeon_device *rdev);
		1098	void radeon_combios_fini(struct radeon_device *rdev);
		1099	int radeon_atombios_init(struct radeon_device *rdev);
		1100	void radeon_atombios_fini(struct radeon_device *rdev);
		1101
		1102
		1103	/*
		1104	* RING helpers.
		1105	*/
		1106	#define CP_PACKET0 0x00000000
		1107	#define PACKET0_BASE_INDEX_SHIFT 0
		1108	#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
		1109	#define PACKET0_COUNT_SHIFT 16
		1110	#define PACKET0_COUNT_MASK (0x3fff << 16)
		1111	#define CP_PACKET1 0x40000000
		1112	#define CP_PACKET2 0x80000000
		1113	#define PACKET2_PAD_SHIFT 0
		1114	#define PACKET2_PAD_MASK (0x3fffffff << 0)
		1115	#define CP_PACKET3 0xC0000000
		1116	#define PACKET3_IT_OPCODE_SHIFT 8
		1117	#define PACKET3_IT_OPCODE_MASK (0xff << 8)
		1118	#define PACKET3_COUNT_SHIFT 16
		1119	#define PACKET3_COUNT_MASK (0x3fff << 16)
		1120	/* PACKET3 op code */
		1121	#define PACKET3_NOP 0x10
		1122	#define PACKET3_3D_DRAW_VBUF 0x28
		1123	#define PACKET3_3D_DRAW_IMMD 0x29
		1124	#define PACKET3_3D_DRAW_INDX 0x2A
		1125	#define PACKET3_3D_LOAD_VBPNTR 0x2F
		1126	#define PACKET3_INDX_BUFFER 0x33
		1127	#define PACKET3_3D_DRAW_VBUF_2 0x34
		1128	#define PACKET3_3D_DRAW_IMMD_2 0x35
		1129	#define PACKET3_3D_DRAW_INDX_2 0x36
		1130	#define PACKET3_BITBLT_MULTI 0x9B
		1131
		1132	#define PACKET0(reg, n) (CP_PACKET0 \| \
		1133	REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) \| \
		1134	REG_SET(PACKET0_COUNT, (n)))
		1135	#define PACKET2(v) (CP_PACKET2 \| REG_SET(PACKET2_PAD, (v)))
		1136	#define PACKET3(op, n) (CP_PACKET3 \| \
		1137	REG_SET(PACKET3_IT_OPCODE, (op)) \| \
		1138	REG_SET(PACKET3_COUNT, (n)))
		1139
		1140	#define PACKET_TYPE0 0
		1141	#define PACKET_TYPE1 1
		1142	#define PACKET_TYPE2 2
		1143	#define PACKET_TYPE3 3
		1144
		1145	#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
		1146	#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
		1147	#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
		1148	#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
		1149	#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
		1150
		1151	static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
		1152	{
		1153	#if DRM_DEBUG_CODE
		1154	if (rdev->cp.count_dw <= 0) {
		1155	DRM_ERROR("radeon: writting more dword to ring than expected !\n");
		1156	}
		1157	#endif
		1158	rdev->cp.ring[rdev->cp.wptr++] = v;
		1159	rdev->cp.wptr &= rdev->cp.ptr_mask;
		1160	rdev->cp.count_dw--;
		1161	rdev->cp.ring_free_dw--;
		1162	}
		1163
		1164
		1165	/*
		1166	* ASICs macro.
		1167	*/
		1168	#define radeon_init(rdev) (rdev)->asic->init((rdev))
		1169	#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
		1170	#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
		1171	#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
		1172	#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
		1173	#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
		1174	#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
		1175	#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
		1176	#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
		1177	#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
		1178	#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
		1179	#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
		1180	#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
		1181	#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
		1182	#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
		1183	#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
		1184	#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
		1185	#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
		1186	#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
		1187	#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
		1188	#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
		1189	#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
		1190	#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
		1191	#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
		1192	#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
		1193	#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
		1194	#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
		1195
		1196
		1197	#define DRM_UDELAY(d) udelay(d)
		1198
		1199	resource_size_t
		1200	drm_get_resource_start(struct drm_device *dev, unsigned int resource);
		1201	resource_size_t
		1202	drm_get_resource_len(struct drm_device *dev, unsigned int resource);
		1203
		1204
		1205	#endif

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon.h @ 2175 – Rev 1126