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1221 | serge | 1 | /* |
2 | * Copyright 2009 Advanced Micro Devices, Inc. |
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3 | * Copyright 2009 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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25 | * Jerome Glisse |
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26 | */ |
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27 | #ifndef R600D_H |
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28 | #define R600D_H |
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29 | |||
30 | #define CP_PACKET2 0x80000000 |
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31 | #define PACKET2_PAD_SHIFT 0 |
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32 | #define PACKET2_PAD_MASK (0x3fffffff << 0) |
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33 | |||
34 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) |
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35 | |||
36 | #define R6XX_MAX_SH_GPRS 256 |
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37 | #define R6XX_MAX_TEMP_GPRS 16 |
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38 | #define R6XX_MAX_SH_THREADS 256 |
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39 | #define R6XX_MAX_SH_STACK_ENTRIES 4096 |
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40 | #define R6XX_MAX_BACKENDS 8 |
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41 | #define R6XX_MAX_BACKENDS_MASK 0xff |
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42 | #define R6XX_MAX_SIMDS 8 |
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43 | #define R6XX_MAX_SIMDS_MASK 0xff |
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44 | #define R6XX_MAX_PIPES 8 |
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45 | #define R6XX_MAX_PIPES_MASK 0xff |
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46 | |||
47 | /* PTE flags */ |
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48 | #define PTE_VALID (1 << 0) |
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49 | #define PTE_SYSTEM (1 << 1) |
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50 | #define PTE_SNOOPED (1 << 2) |
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51 | #define PTE_READABLE (1 << 5) |
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52 | #define PTE_WRITEABLE (1 << 6) |
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53 | |||
1963 | serge | 54 | /* tiling bits */ |
55 | #define ARRAY_LINEAR_GENERAL 0x00000000 |
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56 | #define ARRAY_LINEAR_ALIGNED 0x00000001 |
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57 | #define ARRAY_1D_TILED_THIN1 0x00000002 |
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58 | #define ARRAY_2D_TILED_THIN1 0x00000004 |
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59 | |||
1221 | serge | 60 | /* Registers */ |
61 | #define ARB_POP 0x2418 |
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62 | #define ENABLE_TC128 (1 << 30) |
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63 | #define ARB_GDEC_RD_CNTL 0x246C |
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64 | |||
65 | #define CC_GC_SHADER_PIPE_CONFIG 0x8950 |
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66 | #define CC_RB_BACKEND_DISABLE 0x98F4 |
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67 | #define BACKEND_DISABLE(x) ((x) << 16) |
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68 | |||
2997 | Serge | 69 | #define R_028808_CB_COLOR_CONTROL 0x28808 |
70 | #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) |
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71 | #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) |
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72 | #define C_028808_SPECIAL_OP 0xFFFFFF8F |
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73 | #define V_028808_SPECIAL_NORMAL 0x00 |
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74 | #define V_028808_SPECIAL_DISABLE 0x01 |
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75 | #define V_028808_SPECIAL_RESOLVE_BOX 0x07 |
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76 | |||
1221 | serge | 77 | #define CB_COLOR0_BASE 0x28040 |
78 | #define CB_COLOR1_BASE 0x28044 |
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79 | #define CB_COLOR2_BASE 0x28048 |
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80 | #define CB_COLOR3_BASE 0x2804C |
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81 | #define CB_COLOR4_BASE 0x28050 |
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82 | #define CB_COLOR5_BASE 0x28054 |
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83 | #define CB_COLOR6_BASE 0x28058 |
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84 | #define CB_COLOR7_BASE 0x2805C |
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85 | #define CB_COLOR7_FRAG 0x280FC |
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86 | |||
87 | #define CB_COLOR0_SIZE 0x28060 |
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88 | #define CB_COLOR0_VIEW 0x28080 |
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2997 | Serge | 89 | #define R_028080_CB_COLOR0_VIEW 0x028080 |
90 | #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) |
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91 | #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) |
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92 | #define C_028080_SLICE_START 0xFFFFF800 |
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93 | #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) |
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94 | #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) |
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95 | #define C_028080_SLICE_MAX 0xFF001FFF |
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96 | #define R_028084_CB_COLOR1_VIEW 0x028084 |
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97 | #define R_028088_CB_COLOR2_VIEW 0x028088 |
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98 | #define R_02808C_CB_COLOR3_VIEW 0x02808C |
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99 | #define R_028090_CB_COLOR4_VIEW 0x028090 |
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100 | #define R_028094_CB_COLOR5_VIEW 0x028094 |
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101 | #define R_028098_CB_COLOR6_VIEW 0x028098 |
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102 | #define R_02809C_CB_COLOR7_VIEW 0x02809C |
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103 | #define R_028100_CB_COLOR0_MASK 0x028100 |
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104 | #define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) |
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105 | #define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) |
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106 | #define C_028100_CMASK_BLOCK_MAX 0xFFFFF000 |
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107 | #define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) |
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108 | #define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF) |
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109 | #define C_028100_FMASK_TILE_MAX 0x00000FFF |
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110 | #define R_028104_CB_COLOR1_MASK 0x028104 |
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111 | #define R_028108_CB_COLOR2_MASK 0x028108 |
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112 | #define R_02810C_CB_COLOR3_MASK 0x02810C |
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113 | #define R_028110_CB_COLOR4_MASK 0x028110 |
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114 | #define R_028114_CB_COLOR5_MASK 0x028114 |
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115 | #define R_028118_CB_COLOR6_MASK 0x028118 |
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116 | #define R_02811C_CB_COLOR7_MASK 0x02811C |
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1221 | serge | 117 | #define CB_COLOR0_INFO 0x280a0 |
2997 | Serge | 118 | # define CB_FORMAT(x) ((x) << 2) |
119 | # define CB_ARRAY_MODE(x) ((x) << 8) |
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120 | # define CB_SOURCE_FORMAT(x) ((x) << 27) |
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121 | # define CB_SF_EXPORT_FULL 0 |
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122 | # define CB_SF_EXPORT_NORM 1 |
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1221 | serge | 123 | #define CB_COLOR0_TILE 0x280c0 |
124 | #define CB_COLOR0_FRAG 0x280e0 |
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125 | #define CB_COLOR0_MASK 0x28100 |
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126 | |||
1963 | serge | 127 | #define SQ_ALU_CONST_CACHE_PS_0 0x28940 |
128 | #define SQ_ALU_CONST_CACHE_PS_1 0x28944 |
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129 | #define SQ_ALU_CONST_CACHE_PS_2 0x28948 |
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130 | #define SQ_ALU_CONST_CACHE_PS_3 0x2894c |
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131 | #define SQ_ALU_CONST_CACHE_PS_4 0x28950 |
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132 | #define SQ_ALU_CONST_CACHE_PS_5 0x28954 |
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133 | #define SQ_ALU_CONST_CACHE_PS_6 0x28958 |
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134 | #define SQ_ALU_CONST_CACHE_PS_7 0x2895c |
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135 | #define SQ_ALU_CONST_CACHE_PS_8 0x28960 |
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136 | #define SQ_ALU_CONST_CACHE_PS_9 0x28964 |
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137 | #define SQ_ALU_CONST_CACHE_PS_10 0x28968 |
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138 | #define SQ_ALU_CONST_CACHE_PS_11 0x2896c |
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139 | #define SQ_ALU_CONST_CACHE_PS_12 0x28970 |
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140 | #define SQ_ALU_CONST_CACHE_PS_13 0x28974 |
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141 | #define SQ_ALU_CONST_CACHE_PS_14 0x28978 |
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142 | #define SQ_ALU_CONST_CACHE_PS_15 0x2897c |
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143 | #define SQ_ALU_CONST_CACHE_VS_0 0x28980 |
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144 | #define SQ_ALU_CONST_CACHE_VS_1 0x28984 |
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145 | #define SQ_ALU_CONST_CACHE_VS_2 0x28988 |
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146 | #define SQ_ALU_CONST_CACHE_VS_3 0x2898c |
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147 | #define SQ_ALU_CONST_CACHE_VS_4 0x28990 |
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148 | #define SQ_ALU_CONST_CACHE_VS_5 0x28994 |
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149 | #define SQ_ALU_CONST_CACHE_VS_6 0x28998 |
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150 | #define SQ_ALU_CONST_CACHE_VS_7 0x2899c |
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151 | #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 |
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152 | #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 |
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153 | #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 |
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154 | #define SQ_ALU_CONST_CACHE_VS_11 0x289ac |
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155 | #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 |
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156 | #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 |
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157 | #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 |
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158 | #define SQ_ALU_CONST_CACHE_VS_15 0x289bc |
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159 | #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 |
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160 | #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 |
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161 | #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 |
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162 | #define SQ_ALU_CONST_CACHE_GS_3 0x289cc |
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163 | #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 |
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164 | #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 |
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165 | #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 |
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166 | #define SQ_ALU_CONST_CACHE_GS_7 0x289dc |
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167 | #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 |
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168 | #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 |
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169 | #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 |
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170 | #define SQ_ALU_CONST_CACHE_GS_11 0x289ec |
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171 | #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 |
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172 | #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 |
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173 | #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 |
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174 | #define SQ_ALU_CONST_CACHE_GS_15 0x289fc |
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175 | |||
1221 | serge | 176 | #define CONFIG_MEMSIZE 0x5428 |
177 | #define CONFIG_CNTL 0x5424 |
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2997 | Serge | 178 | #define CP_STALLED_STAT1 0x8674 |
179 | #define CP_STALLED_STAT2 0x8678 |
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180 | #define CP_BUSY_STAT 0x867C |
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1221 | serge | 181 | #define CP_STAT 0x8680 |
182 | #define CP_COHER_BASE 0x85F8 |
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183 | #define CP_DEBUG 0xC1FC |
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184 | #define R_0086D8_CP_ME_CNTL 0x86D8 |
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185 | #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) |
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186 | #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) |
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187 | #define CP_ME_RAM_DATA 0xC160 |
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188 | #define CP_ME_RAM_RADDR 0xC158 |
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189 | #define CP_ME_RAM_WADDR 0xC15C |
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190 | #define CP_MEQ_THRESHOLDS 0x8764 |
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191 | #define MEQ_END(x) ((x) << 16) |
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192 | #define ROQ_END(x) ((x) << 24) |
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193 | #define CP_PERFMON_CNTL 0x87FC |
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194 | #define CP_PFP_UCODE_ADDR 0xC150 |
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195 | #define CP_PFP_UCODE_DATA 0xC154 |
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196 | #define CP_QUEUE_THRESHOLDS 0x8760 |
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197 | #define ROQ_IB1_START(x) ((x) << 0) |
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198 | #define ROQ_IB2_START(x) ((x) << 8) |
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199 | #define CP_RB_BASE 0xC100 |
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200 | #define CP_RB_CNTL 0xC104 |
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1963 | serge | 201 | #define RB_BUFSZ(x) ((x) << 0) |
202 | #define RB_BLKSZ(x) ((x) << 8) |
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203 | #define RB_NO_UPDATE (1 << 27) |
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204 | #define RB_RPTR_WR_ENA (1 << 31) |
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1221 | serge | 205 | #define BUF_SWAP_32BIT (2 << 16) |
206 | #define CP_RB_RPTR 0x8700 |
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207 | #define CP_RB_RPTR_ADDR 0xC10C |
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1963 | serge | 208 | #define RB_RPTR_SWAP(x) ((x) << 0) |
1221 | serge | 209 | #define CP_RB_RPTR_ADDR_HI 0xC110 |
210 | #define CP_RB_RPTR_WR 0xC108 |
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211 | #define CP_RB_WPTR 0xC114 |
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212 | #define CP_RB_WPTR_ADDR 0xC118 |
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213 | #define CP_RB_WPTR_ADDR_HI 0xC11C |
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214 | #define CP_RB_WPTR_DELAY 0x8704 |
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215 | #define CP_ROQ_IB1_STAT 0x8784 |
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216 | #define CP_ROQ_IB2_STAT 0x8788 |
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217 | #define CP_SEM_WAIT_TIMER 0x85BC |
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218 | |||
219 | #define DB_DEBUG 0x9830 |
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220 | #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) |
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221 | #define DB_DEPTH_BASE 0x2800C |
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1268 | serge | 222 | #define DB_HTILE_DATA_BASE 0x28014 |
2997 | Serge | 223 | #define DB_HTILE_SURFACE 0x28D24 |
224 | #define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0) |
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225 | #define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1) |
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226 | #define C_028D24_HTILE_WIDTH 0xFFFFFFFE |
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227 | #define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1) |
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228 | #define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) |
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229 | #define C_028D24_HTILE_HEIGHT 0xFFFFFFFD |
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230 | #define G_028D24_LINEAR(x) (((x) >> 2) & 0x1) |
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1221 | serge | 231 | #define DB_WATERMARKS 0x9838 |
232 | #define DEPTH_FREE(x) ((x) << 0) |
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233 | #define DEPTH_FLUSH(x) ((x) << 5) |
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234 | #define DEPTH_PENDING_FREE(x) ((x) << 15) |
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235 | #define DEPTH_CACHELINE_FREE(x) ((x) << 20) |
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236 | |||
237 | #define DCP_TILING_CONFIG 0x6CA0 |
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238 | #define PIPE_TILING(x) ((x) << 1) |
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239 | #define BANK_TILING(x) ((x) << 4) |
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240 | #define GROUP_SIZE(x) ((x) << 6) |
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241 | #define ROW_TILING(x) ((x) << 8) |
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242 | #define BANK_SWAPS(x) ((x) << 11) |
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243 | #define SAMPLE_SPLIT(x) ((x) << 14) |
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244 | #define BACKEND_MAP(x) ((x) << 16) |
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245 | |||
246 | #define GB_TILING_CONFIG 0x98F0 |
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2997 | Serge | 247 | #define PIPE_TILING__SHIFT 1 |
248 | #define PIPE_TILING__MASK 0x0000000e |
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1221 | serge | 249 | |
250 | #define GC_USER_SHADER_PIPE_CONFIG 0x8954 |
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251 | #define INACTIVE_QD_PIPES(x) ((x) << 8) |
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252 | #define INACTIVE_QD_PIPES_MASK 0x0000FF00 |
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253 | #define INACTIVE_SIMDS(x) ((x) << 16) |
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254 | #define INACTIVE_SIMDS_MASK 0x00FF0000 |
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255 | |||
256 | #define SQ_CONFIG 0x8c00 |
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257 | # define VC_ENABLE (1 << 0) |
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258 | # define EXPORT_SRC_C (1 << 1) |
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259 | # define DX9_CONSTS (1 << 2) |
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260 | # define ALU_INST_PREFER_VECTOR (1 << 3) |
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261 | # define DX10_CLAMP (1 << 4) |
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262 | # define CLAUSE_SEQ_PRIO(x) ((x) << 8) |
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263 | # define PS_PRIO(x) ((x) << 24) |
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264 | # define VS_PRIO(x) ((x) << 26) |
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265 | # define GS_PRIO(x) ((x) << 28) |
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266 | # define ES_PRIO(x) ((x) << 30) |
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267 | #define SQ_GPR_RESOURCE_MGMT_1 0x8c04 |
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268 | # define NUM_PS_GPRS(x) ((x) << 0) |
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269 | # define NUM_VS_GPRS(x) ((x) << 16) |
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270 | # define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) |
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271 | #define SQ_GPR_RESOURCE_MGMT_2 0x8c08 |
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272 | # define NUM_GS_GPRS(x) ((x) << 0) |
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273 | # define NUM_ES_GPRS(x) ((x) << 16) |
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274 | #define SQ_THREAD_RESOURCE_MGMT 0x8c0c |
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275 | # define NUM_PS_THREADS(x) ((x) << 0) |
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276 | # define NUM_VS_THREADS(x) ((x) << 8) |
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277 | # define NUM_GS_THREADS(x) ((x) << 16) |
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278 | # define NUM_ES_THREADS(x) ((x) << 24) |
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279 | #define SQ_STACK_RESOURCE_MGMT_1 0x8c10 |
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280 | # define NUM_PS_STACK_ENTRIES(x) ((x) << 0) |
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281 | # define NUM_VS_STACK_ENTRIES(x) ((x) << 16) |
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282 | #define SQ_STACK_RESOURCE_MGMT_2 0x8c14 |
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283 | # define NUM_GS_STACK_ENTRIES(x) ((x) << 0) |
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284 | # define NUM_ES_STACK_ENTRIES(x) ((x) << 16) |
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1268 | serge | 285 | #define SQ_ESGS_RING_BASE 0x8c40 |
286 | #define SQ_GSVS_RING_BASE 0x8c48 |
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287 | #define SQ_ESTMP_RING_BASE 0x8c50 |
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288 | #define SQ_GSTMP_RING_BASE 0x8c58 |
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289 | #define SQ_VSTMP_RING_BASE 0x8c60 |
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290 | #define SQ_PSTMP_RING_BASE 0x8c68 |
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291 | #define SQ_FBUF_RING_BASE 0x8c70 |
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292 | #define SQ_REDUC_RING_BASE 0x8c78 |
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1221 | serge | 293 | |
294 | #define GRBM_CNTL 0x8000 |
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295 | # define GRBM_READ_TIMEOUT(x) ((x) << 0) |
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296 | #define GRBM_STATUS 0x8010 |
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297 | #define CMDFIFO_AVAIL_MASK 0x0000001F |
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298 | #define GUI_ACTIVE (1<<31) |
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299 | #define GRBM_STATUS2 0x8014 |
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300 | #define GRBM_SOFT_RESET 0x8020 |
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301 | #define SOFT_RESET_CP (1<<0) |
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302 | |||
1963 | serge | 303 | #define CG_THERMAL_STATUS 0x7F4 |
304 | #define ASIC_T(x) ((x) << 0) |
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305 | #define ASIC_T_MASK 0x1FF |
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306 | #define ASIC_T_SHIFT 0 |
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307 | |||
1221 | serge | 308 | #define HDP_HOST_PATH_CNTL 0x2C00 |
309 | #define HDP_NONSURFACE_BASE 0x2C04 |
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310 | #define HDP_NONSURFACE_INFO 0x2C08 |
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311 | #define HDP_NONSURFACE_SIZE 0x2C0C |
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312 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
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313 | #define HDP_TILING_CONFIG 0x2F3C |
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1963 | serge | 314 | #define HDP_DEBUG1 0x2F34 |
1221 | serge | 315 | |
316 | #define MC_VM_AGP_TOP 0x2184 |
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317 | #define MC_VM_AGP_BOT 0x2188 |
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318 | #define MC_VM_AGP_BASE 0x218C |
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319 | #define MC_VM_FB_LOCATION 0x2180 |
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320 | #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C |
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321 | #define ENABLE_L1_TLB (1 << 0) |
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322 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) |
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323 | #define ENABLE_L1_STRICT_ORDERING (1 << 2) |
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324 | #define SYSTEM_ACCESS_MODE_MASK 0x000000C0 |
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325 | #define SYSTEM_ACCESS_MODE_SHIFT 6 |
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326 | #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) |
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327 | #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) |
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328 | #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) |
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329 | #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) |
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330 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) |
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331 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) |
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332 | #define ENABLE_SEMAPHORE_MODE (1 << 10) |
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333 | #define ENABLE_WAIT_L2_QUERY (1 << 11) |
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334 | #define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) |
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335 | #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 |
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336 | #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 |
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337 | #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) |
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338 | #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 |
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339 | #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 |
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340 | #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 |
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341 | #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC |
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342 | #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 |
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343 | #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 |
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344 | #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C |
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345 | #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 |
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346 | #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 |
||
347 | #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 |
||
348 | #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 |
||
349 | #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 |
||
350 | #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C |
||
351 | #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 |
||
352 | #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 |
||
353 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 |
||
354 | #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF |
||
355 | #define LOGICAL_PAGE_NUMBER_SHIFT 0 |
||
356 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 |
||
357 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 |
||
358 | |||
359 | #define PA_CL_ENHANCE 0x8A14 |
||
360 | #define CLIP_VTX_REORDER_ENA (1 << 0) |
||
361 | #define NUM_CLIP_SEQ(x) ((x) << 1) |
||
362 | #define PA_SC_AA_CONFIG 0x28C04 |
||
363 | #define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 |
||
364 | #define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 |
||
365 | #define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 |
||
366 | #define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C |
||
367 | #define S0_X(x) ((x) << 0) |
||
368 | #define S0_Y(x) ((x) << 4) |
||
369 | #define S1_X(x) ((x) << 8) |
||
370 | #define S1_Y(x) ((x) << 12) |
||
371 | #define S2_X(x) ((x) << 16) |
||
372 | #define S2_Y(x) ((x) << 20) |
||
373 | #define S3_X(x) ((x) << 24) |
||
374 | #define S3_Y(x) ((x) << 28) |
||
375 | #define S4_X(x) ((x) << 0) |
||
376 | #define S4_Y(x) ((x) << 4) |
||
377 | #define S5_X(x) ((x) << 8) |
||
378 | #define S5_Y(x) ((x) << 12) |
||
379 | #define S6_X(x) ((x) << 16) |
||
380 | #define S6_Y(x) ((x) << 20) |
||
381 | #define S7_X(x) ((x) << 24) |
||
382 | #define S7_Y(x) ((x) << 28) |
||
383 | #define PA_SC_CLIPRECT_RULE 0x2820c |
||
384 | #define PA_SC_ENHANCE 0x8BF0 |
||
385 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) |
||
386 | #define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) |
||
387 | #define PA_SC_LINE_STIPPLE 0x28A0C |
||
388 | #define PA_SC_LINE_STIPPLE_STATE 0x8B10 |
||
389 | #define PA_SC_MODE_CNTL 0x28A4C |
||
390 | #define PA_SC_MULTI_CHIP_CNTL 0x8B20 |
||
391 | |||
392 | #define PA_SC_SCREEN_SCISSOR_TL 0x28030 |
||
393 | #define PA_SC_GENERIC_SCISSOR_TL 0x28240 |
||
394 | #define PA_SC_WINDOW_SCISSOR_TL 0x28204 |
||
395 | |||
396 | #define PCIE_PORT_INDEX 0x0038 |
||
397 | #define PCIE_PORT_DATA 0x003C |
||
398 | |||
1268 | serge | 399 | #define CHMAP 0x2004 |
400 | #define NOOFCHAN_SHIFT 12 |
||
401 | #define NOOFCHAN_MASK 0x00003000 |
||
402 | |||
1221 | serge | 403 | #define RAMCFG 0x2408 |
404 | #define NOOFBANK_SHIFT 0 |
||
405 | #define NOOFBANK_MASK 0x00000001 |
||
406 | #define NOOFRANK_SHIFT 1 |
||
407 | #define NOOFRANK_MASK 0x00000002 |
||
408 | #define NOOFROWS_SHIFT 2 |
||
409 | #define NOOFROWS_MASK 0x0000001C |
||
410 | #define NOOFCOLS_SHIFT 5 |
||
411 | #define NOOFCOLS_MASK 0x00000060 |
||
412 | #define CHANSIZE_SHIFT 7 |
||
413 | #define CHANSIZE_MASK 0x00000080 |
||
414 | #define BURSTLENGTH_SHIFT 8 |
||
415 | #define BURSTLENGTH_MASK 0x00000100 |
||
416 | #define CHANSIZE_OVERRIDE (1 << 10) |
||
417 | |||
418 | #define SCRATCH_REG0 0x8500 |
||
419 | #define SCRATCH_REG1 0x8504 |
||
420 | #define SCRATCH_REG2 0x8508 |
||
421 | #define SCRATCH_REG3 0x850C |
||
422 | #define SCRATCH_REG4 0x8510 |
||
423 | #define SCRATCH_REG5 0x8514 |
||
424 | #define SCRATCH_REG6 0x8518 |
||
425 | #define SCRATCH_REG7 0x851C |
||
426 | #define SCRATCH_UMSK 0x8540 |
||
427 | #define SCRATCH_ADDR 0x8544 |
||
428 | |||
429 | #define SPI_CONFIG_CNTL 0x9100 |
||
430 | #define GPR_WRITE_PRIORITY(x) ((x) << 0) |
||
431 | #define DISABLE_INTERP_1 (1 << 5) |
||
432 | #define SPI_CONFIG_CNTL_1 0x913C |
||
433 | #define VTX_DONE_DELAY(x) ((x) << 0) |
||
434 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) |
||
435 | #define SPI_INPUT_Z 0x286D8 |
||
436 | #define SPI_PS_IN_CONTROL_0 0x286CC |
||
437 | #define NUM_INTERP(x) ((x)<<0) |
||
438 | #define POSITION_ENA (1<<8) |
||
439 | #define POSITION_CENTROID (1<<9) |
||
440 | #define POSITION_ADDR(x) ((x)<<10) |
||
441 | #define PARAM_GEN(x) ((x)<<15) |
||
442 | #define PARAM_GEN_ADDR(x) ((x)<<19) |
||
443 | #define BARYC_SAMPLE_CNTL(x) ((x)<<26) |
||
444 | #define PERSP_GRADIENT_ENA (1<<28) |
||
445 | #define LINEAR_GRADIENT_ENA (1<<29) |
||
446 | #define POSITION_SAMPLE (1<<30) |
||
447 | #define BARYC_AT_SAMPLE_ENA (1<<31) |
||
448 | #define SPI_PS_IN_CONTROL_1 0x286D0 |
||
449 | #define GEN_INDEX_PIX (1<<0) |
||
450 | #define GEN_INDEX_PIX_ADDR(x) ((x)<<1) |
||
451 | #define FRONT_FACE_ENA (1<<8) |
||
452 | #define FRONT_FACE_CHAN(x) ((x)<<9) |
||
453 | #define FRONT_FACE_ALL_BITS (1<<11) |
||
454 | #define FRONT_FACE_ADDR(x) ((x)<<12) |
||
455 | #define FOG_ADDR(x) ((x)<<17) |
||
456 | #define FIXED_PT_POSITION_ENA (1<<24) |
||
457 | #define FIXED_PT_POSITION_ADDR(x) ((x)<<25) |
||
458 | |||
459 | #define SQ_MS_FIFO_SIZES 0x8CF0 |
||
460 | #define CACHE_FIFO_SIZE(x) ((x) << 0) |
||
461 | #define FETCH_FIFO_HIWATER(x) ((x) << 8) |
||
462 | #define DONE_FIFO_HIWATER(x) ((x) << 16) |
||
463 | #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) |
||
464 | #define SQ_PGM_START_ES 0x28880 |
||
465 | #define SQ_PGM_START_FS 0x28894 |
||
466 | #define SQ_PGM_START_GS 0x2886C |
||
467 | #define SQ_PGM_START_PS 0x28840 |
||
468 | #define SQ_PGM_RESOURCES_PS 0x28850 |
||
469 | #define SQ_PGM_EXPORTS_PS 0x28854 |
||
470 | #define SQ_PGM_CF_OFFSET_PS 0x288cc |
||
471 | #define SQ_PGM_START_VS 0x28858 |
||
472 | #define SQ_PGM_RESOURCES_VS 0x28868 |
||
473 | #define SQ_PGM_CF_OFFSET_VS 0x288d0 |
||
2997 | Serge | 474 | |
475 | #define SQ_VTX_CONSTANT_WORD0_0 0x30000 |
||
476 | #define SQ_VTX_CONSTANT_WORD1_0 0x30004 |
||
477 | #define SQ_VTX_CONSTANT_WORD2_0 0x30008 |
||
478 | # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) |
||
479 | # define SQ_VTXC_STRIDE(x) ((x) << 8) |
||
480 | # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) |
||
481 | # define SQ_ENDIAN_NONE 0 |
||
482 | # define SQ_ENDIAN_8IN16 1 |
||
483 | # define SQ_ENDIAN_8IN32 2 |
||
484 | #define SQ_VTX_CONSTANT_WORD3_0 0x3000c |
||
1221 | serge | 485 | #define SQ_VTX_CONSTANT_WORD6_0 0x38018 |
486 | #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) |
||
487 | #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) |
||
488 | #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 |
||
489 | #define SQ_TEX_VTX_INVALID_BUFFER 0x1 |
||
490 | #define SQ_TEX_VTX_VALID_TEXTURE 0x2 |
||
491 | #define SQ_TEX_VTX_VALID_BUFFER 0x3 |
||
492 | |||
493 | |||
494 | #define SX_MISC 0x28350 |
||
1268 | serge | 495 | #define SX_MEMORY_EXPORT_BASE 0x9010 |
1221 | serge | 496 | #define SX_DEBUG_1 0x9054 |
497 | #define SMX_EVENT_RELEASE (1 << 0) |
||
498 | #define ENABLE_NEW_SMX_ADDRESS (1 << 16) |
||
499 | |||
500 | #define TA_CNTL_AUX 0x9508 |
||
501 | #define DISABLE_CUBE_WRAP (1 << 0) |
||
502 | #define DISABLE_CUBE_ANISO (1 << 1) |
||
503 | #define SYNC_GRADIENT (1 << 24) |
||
504 | #define SYNC_WALKER (1 << 25) |
||
505 | #define SYNC_ALIGNER (1 << 26) |
||
506 | #define BILINEAR_PRECISION_6_BIT (0 << 31) |
||
507 | #define BILINEAR_PRECISION_8_BIT (1 << 31) |
||
508 | |||
509 | #define TC_CNTL 0x9608 |
||
510 | #define TC_L2_SIZE(x) ((x)<<5) |
||
511 | #define L2_DISABLE_LATE_HIT (1<<9) |
||
512 | |||
2997 | Serge | 513 | #define VC_ENHANCE 0x9714 |
1221 | serge | 514 | |
515 | #define VGT_CACHE_INVALIDATION 0x88C4 |
||
516 | #define CACHE_INVALIDATION(x) ((x)<<0) |
||
517 | #define VC_ONLY 0 |
||
518 | #define TC_ONLY 1 |
||
519 | #define VC_AND_TC 2 |
||
520 | #define VGT_DMA_BASE 0x287E8 |
||
521 | #define VGT_DMA_BASE_HI 0x287E4 |
||
522 | #define VGT_ES_PER_GS 0x88CC |
||
523 | #define VGT_GS_PER_ES 0x88C8 |
||
524 | #define VGT_GS_PER_VS 0x88E8 |
||
525 | #define VGT_GS_VERTEX_REUSE 0x88D4 |
||
526 | #define VGT_PRIMITIVE_TYPE 0x8958 |
||
527 | #define VGT_NUM_INSTANCES 0x8974 |
||
528 | #define VGT_OUT_DEALLOC_CNTL 0x28C5C |
||
529 | #define DEALLOC_DIST_MASK 0x0000007F |
||
530 | #define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 |
||
531 | #define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 |
||
532 | #define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 |
||
533 | #define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c |
||
534 | #define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 |
||
535 | #define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 |
||
536 | #define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c |
||
537 | #define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 |
||
538 | #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 |
||
539 | #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 |
||
540 | #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 |
||
541 | #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 |
||
542 | #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC |
||
543 | #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC |
||
544 | #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC |
||
545 | #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C |
||
2997 | Serge | 546 | #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 |
547 | #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 |
||
548 | #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 |
||
549 | #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 |
||
550 | |||
1221 | serge | 551 | #define VGT_STRMOUT_EN 0x28AB0 |
552 | #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 |
||
553 | #define VTX_REUSE_DEPTH_MASK 0x000000FF |
||
554 | #define VGT_EVENT_INITIATOR 0x28a90 |
||
1963 | serge | 555 | # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) |
1221 | serge | 556 | # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) |
557 | |||
558 | #define VM_CONTEXT0_CNTL 0x1410 |
||
559 | #define ENABLE_CONTEXT (1 << 0) |
||
560 | #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) |
||
561 | #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) |
||
562 | #define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 |
||
563 | #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 |
||
564 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 |
||
565 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 |
||
566 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 |
||
567 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 |
||
568 | #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 |
||
569 | #define REQUEST_TYPE(x) (((x) & 0xf) << 0) |
||
570 | #define RESPONSE_TYPE_MASK 0x000000F0 |
||
571 | #define RESPONSE_TYPE_SHIFT 4 |
||
572 | #define VM_L2_CNTL 0x1400 |
||
573 | #define ENABLE_L2_CACHE (1 << 0) |
||
574 | #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) |
||
575 | #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) |
||
576 | #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) |
||
577 | #define VM_L2_CNTL2 0x1404 |
||
578 | #define INVALIDATE_ALL_L1_TLBS (1 << 0) |
||
579 | #define INVALIDATE_L2_CACHE (1 << 1) |
||
580 | #define VM_L2_CNTL3 0x1408 |
||
581 | #define BANK_SELECT_0(x) (((x) & 0x1f) << 0) |
||
582 | #define BANK_SELECT_1(x) (((x) & 0x1f) << 5) |
||
583 | #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) |
||
584 | #define VM_L2_STATUS 0x140C |
||
585 | #define L2_BUSY (1 << 0) |
||
586 | |||
587 | #define WAIT_UNTIL 0x8040 |
||
588 | #define WAIT_2D_IDLE_bit (1 << 14) |
||
589 | #define WAIT_3D_IDLE_bit (1 << 15) |
||
590 | #define WAIT_2D_IDLECLEAN_bit (1 << 16) |
||
591 | #define WAIT_3D_IDLECLEAN_bit (1 << 17) |
||
592 | |||
1321 | serge | 593 | #define IH_RB_CNTL 0x3e00 |
594 | # define IH_RB_ENABLE (1 << 0) |
||
595 | # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ |
||
596 | # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) |
||
597 | # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) |
||
598 | # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ |
||
599 | # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) |
||
600 | # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) |
||
601 | #define IH_RB_BASE 0x3e04 |
||
602 | #define IH_RB_RPTR 0x3e08 |
||
603 | #define IH_RB_WPTR 0x3e0c |
||
604 | # define RB_OVERFLOW (1 << 0) |
||
605 | # define WPTR_OFFSET_MASK 0x3fffc |
||
606 | #define IH_RB_WPTR_ADDR_HI 0x3e10 |
||
607 | #define IH_RB_WPTR_ADDR_LO 0x3e14 |
||
608 | #define IH_CNTL 0x3e18 |
||
609 | # define ENABLE_INTR (1 << 0) |
||
2004 | serge | 610 | # define IH_MC_SWAP(x) ((x) << 1) |
1321 | serge | 611 | # define IH_MC_SWAP_NONE 0 |
612 | # define IH_MC_SWAP_16BIT 1 |
||
613 | # define IH_MC_SWAP_32BIT 2 |
||
614 | # define IH_MC_SWAP_64BIT 3 |
||
615 | # define RPTR_REARM (1 << 4) |
||
616 | # define MC_WRREQ_CREDIT(x) ((x) << 15) |
||
617 | # define MC_WR_CLEAN_CNT(x) ((x) << 20) |
||
1221 | serge | 618 | |
1321 | serge | 619 | #define RLC_CNTL 0x3f00 |
620 | # define RLC_ENABLE (1 << 0) |
||
621 | #define RLC_HB_BASE 0x3f10 |
||
622 | #define RLC_HB_CNTL 0x3f0c |
||
623 | #define RLC_HB_RPTR 0x3f20 |
||
624 | #define RLC_HB_WPTR 0x3f1c |
||
625 | #define RLC_HB_WPTR_LSB_ADDR 0x3f14 |
||
626 | #define RLC_HB_WPTR_MSB_ADDR 0x3f18 |
||
2997 | Serge | 627 | #define RLC_GPU_CLOCK_COUNT_LSB 0x3f38 |
628 | #define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c |
||
629 | #define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40 |
||
1321 | serge | 630 | #define RLC_MC_CNTL 0x3f44 |
631 | #define RLC_UCODE_CNTL 0x3f48 |
||
632 | #define RLC_UCODE_ADDR 0x3f2c |
||
633 | #define RLC_UCODE_DATA 0x3f30 |
||
1221 | serge | 634 | |
2997 | Serge | 635 | /* new for TN */ |
636 | #define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10 |
||
637 | #define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 |
||
638 | |||
1321 | serge | 639 | #define SRBM_SOFT_RESET 0xe60 |
640 | # define SOFT_RESET_RLC (1 << 13) |
||
641 | |||
642 | #define CP_INT_CNTL 0xc124 |
||
643 | # define CNTX_BUSY_INT_ENABLE (1 << 19) |
||
644 | # define CNTX_EMPTY_INT_ENABLE (1 << 20) |
||
645 | # define SCRATCH_INT_ENABLE (1 << 25) |
||
646 | # define TIME_STAMP_INT_ENABLE (1 << 26) |
||
647 | # define IB2_INT_ENABLE (1 << 29) |
||
648 | # define IB1_INT_ENABLE (1 << 30) |
||
649 | # define RB_INT_ENABLE (1 << 31) |
||
650 | #define CP_INT_STATUS 0xc128 |
||
651 | # define SCRATCH_INT_STAT (1 << 25) |
||
652 | # define TIME_STAMP_INT_STAT (1 << 26) |
||
653 | # define IB2_INT_STAT (1 << 29) |
||
654 | # define IB1_INT_STAT (1 << 30) |
||
655 | # define RB_INT_STAT (1 << 31) |
||
656 | |||
657 | #define GRBM_INT_CNTL 0x8060 |
||
658 | # define RDERR_INT_ENABLE (1 << 0) |
||
659 | # define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1) |
||
660 | # define GUI_IDLE_INT_ENABLE (1 << 19) |
||
661 | |||
662 | #define INTERRUPT_CNTL 0x5468 |
||
663 | # define IH_DUMMY_RD_OVERRIDE (1 << 0) |
||
664 | # define IH_DUMMY_RD_EN (1 << 1) |
||
665 | # define IH_REQ_NONSNOOP_EN (1 << 3) |
||
666 | # define GEN_IH_INT_EN (1 << 8) |
||
667 | #define INTERRUPT_CNTL2 0x546c |
||
668 | |||
669 | #define D1MODE_VBLANK_STATUS 0x6534 |
||
670 | #define D2MODE_VBLANK_STATUS 0x6d34 |
||
671 | # define DxMODE_VBLANK_OCCURRED (1 << 0) |
||
672 | # define DxMODE_VBLANK_ACK (1 << 4) |
||
673 | # define DxMODE_VBLANK_STAT (1 << 12) |
||
674 | # define DxMODE_VBLANK_INTERRUPT (1 << 16) |
||
675 | # define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17) |
||
676 | #define D1MODE_VLINE_STATUS 0x653c |
||
677 | #define D2MODE_VLINE_STATUS 0x6d3c |
||
678 | # define DxMODE_VLINE_OCCURRED (1 << 0) |
||
679 | # define DxMODE_VLINE_ACK (1 << 4) |
||
680 | # define DxMODE_VLINE_STAT (1 << 12) |
||
681 | # define DxMODE_VLINE_INTERRUPT (1 << 16) |
||
682 | # define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17) |
||
683 | #define DxMODE_INT_MASK 0x6540 |
||
684 | # define D1MODE_VBLANK_INT_MASK (1 << 0) |
||
685 | # define D1MODE_VLINE_INT_MASK (1 << 4) |
||
686 | # define D2MODE_VBLANK_INT_MASK (1 << 8) |
||
687 | # define D2MODE_VLINE_INT_MASK (1 << 12) |
||
688 | #define DCE3_DISP_INTERRUPT_STATUS 0x7ddc |
||
689 | # define DC_HPD1_INTERRUPT (1 << 18) |
||
690 | # define DC_HPD2_INTERRUPT (1 << 19) |
||
691 | #define DISP_INTERRUPT_STATUS 0x7edc |
||
692 | # define LB_D1_VLINE_INTERRUPT (1 << 2) |
||
693 | # define LB_D2_VLINE_INTERRUPT (1 << 3) |
||
694 | # define LB_D1_VBLANK_INTERRUPT (1 << 4) |
||
695 | # define LB_D2_VBLANK_INTERRUPT (1 << 5) |
||
696 | # define DACA_AUTODETECT_INTERRUPT (1 << 16) |
||
697 | # define DACB_AUTODETECT_INTERRUPT (1 << 17) |
||
698 | # define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18) |
||
699 | # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) |
||
700 | # define DC_I2C_SW_DONE_INTERRUPT (1 << 20) |
||
701 | # define DC_I2C_HW_DONE_INTERRUPT (1 << 21) |
||
702 | #define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8 |
||
703 | #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 |
||
704 | # define DC_HPD4_INTERRUPT (1 << 14) |
||
705 | # define DC_HPD4_RX_INTERRUPT (1 << 15) |
||
706 | # define DC_HPD3_INTERRUPT (1 << 28) |
||
707 | # define DC_HPD1_RX_INTERRUPT (1 << 29) |
||
708 | # define DC_HPD2_RX_INTERRUPT (1 << 30) |
||
709 | #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec |
||
710 | # define DC_HPD3_RX_INTERRUPT (1 << 0) |
||
711 | # define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1) |
||
712 | # define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2) |
||
713 | # define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3) |
||
714 | # define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4) |
||
715 | # define AUX1_SW_DONE_INTERRUPT (1 << 5) |
||
716 | # define AUX1_LS_DONE_INTERRUPT (1 << 6) |
||
717 | # define AUX2_SW_DONE_INTERRUPT (1 << 7) |
||
718 | # define AUX2_LS_DONE_INTERRUPT (1 << 8) |
||
719 | # define AUX3_SW_DONE_INTERRUPT (1 << 9) |
||
720 | # define AUX3_LS_DONE_INTERRUPT (1 << 10) |
||
721 | # define AUX4_SW_DONE_INTERRUPT (1 << 11) |
||
722 | # define AUX4_LS_DONE_INTERRUPT (1 << 12) |
||
723 | # define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13) |
||
724 | # define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14) |
||
725 | /* DCE 3.2 */ |
||
726 | # define AUX5_SW_DONE_INTERRUPT (1 << 15) |
||
727 | # define AUX5_LS_DONE_INTERRUPT (1 << 16) |
||
728 | # define AUX6_SW_DONE_INTERRUPT (1 << 17) |
||
729 | # define AUX6_LS_DONE_INTERRUPT (1 << 18) |
||
730 | # define DC_HPD5_INTERRUPT (1 << 19) |
||
731 | # define DC_HPD5_RX_INTERRUPT (1 << 20) |
||
732 | # define DC_HPD6_INTERRUPT (1 << 21) |
||
733 | # define DC_HPD6_RX_INTERRUPT (1 << 22) |
||
734 | |||
735 | #define DACA_AUTO_DETECT_CONTROL 0x7828 |
||
736 | #define DACB_AUTO_DETECT_CONTROL 0x7a28 |
||
737 | #define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028 |
||
738 | #define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128 |
||
739 | # define DACx_AUTODETECT_MODE(x) ((x) << 0) |
||
740 | # define DACx_AUTODETECT_MODE_NONE 0 |
||
741 | # define DACx_AUTODETECT_MODE_CONNECT 1 |
||
742 | # define DACx_AUTODETECT_MODE_DISCONNECT 2 |
||
743 | # define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8) |
||
744 | /* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */ |
||
745 | # define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16) |
||
746 | |||
747 | #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 |
||
748 | #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 |
||
749 | #define DACA_AUTODETECT_INT_CONTROL 0x7838 |
||
750 | #define DACB_AUTODETECT_INT_CONTROL 0x7a38 |
||
751 | # define DACx_AUTODETECT_ACK (1 << 0) |
||
752 | # define DACx_AUTODETECT_INT_ENABLE (1 << 16) |
||
753 | |||
754 | #define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00 |
||
755 | #define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10 |
||
756 | #define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24 |
||
757 | # define DC_HOT_PLUG_DETECTx_EN (1 << 0) |
||
758 | |||
759 | #define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04 |
||
760 | #define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14 |
||
761 | #define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28 |
||
762 | # define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0) |
||
763 | # define DC_HOT_PLUG_DETECTx_SENSE (1 << 1) |
||
764 | |||
765 | /* DCE 3.0 */ |
||
766 | #define DC_HPD1_INT_STATUS 0x7d00 |
||
767 | #define DC_HPD2_INT_STATUS 0x7d0c |
||
768 | #define DC_HPD3_INT_STATUS 0x7d18 |
||
769 | #define DC_HPD4_INT_STATUS 0x7d24 |
||
770 | /* DCE 3.2 */ |
||
771 | #define DC_HPD5_INT_STATUS 0x7dc0 |
||
772 | #define DC_HPD6_INT_STATUS 0x7df4 |
||
773 | # define DC_HPDx_INT_STATUS (1 << 0) |
||
774 | # define DC_HPDx_SENSE (1 << 1) |
||
775 | # define DC_HPDx_RX_INT_STATUS (1 << 8) |
||
776 | |||
777 | #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 |
||
778 | #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 |
||
779 | #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c |
||
780 | # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) |
||
781 | # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) |
||
782 | # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) |
||
783 | /* DCE 3.0 */ |
||
784 | #define DC_HPD1_INT_CONTROL 0x7d04 |
||
785 | #define DC_HPD2_INT_CONTROL 0x7d10 |
||
786 | #define DC_HPD3_INT_CONTROL 0x7d1c |
||
787 | #define DC_HPD4_INT_CONTROL 0x7d28 |
||
788 | /* DCE 3.2 */ |
||
789 | #define DC_HPD5_INT_CONTROL 0x7dc4 |
||
790 | #define DC_HPD6_INT_CONTROL 0x7df8 |
||
791 | # define DC_HPDx_INT_ACK (1 << 0) |
||
792 | # define DC_HPDx_INT_POLARITY (1 << 8) |
||
793 | # define DC_HPDx_INT_EN (1 << 16) |
||
794 | # define DC_HPDx_RX_INT_ACK (1 << 20) |
||
795 | # define DC_HPDx_RX_INT_EN (1 << 24) |
||
796 | |||
797 | /* DCE 3.0 */ |
||
798 | #define DC_HPD1_CONTROL 0x7d08 |
||
799 | #define DC_HPD2_CONTROL 0x7d14 |
||
800 | #define DC_HPD3_CONTROL 0x7d20 |
||
801 | #define DC_HPD4_CONTROL 0x7d2c |
||
802 | /* DCE 3.2 */ |
||
803 | #define DC_HPD5_CONTROL 0x7dc8 |
||
804 | #define DC_HPD6_CONTROL 0x7dfc |
||
805 | # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) |
||
806 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) |
||
807 | /* DCE 3.2 */ |
||
808 | # define DC_HPDx_EN (1 << 28) |
||
809 | |||
1963 | serge | 810 | #define D1GRPH_INTERRUPT_STATUS 0x6158 |
811 | #define D2GRPH_INTERRUPT_STATUS 0x6958 |
||
812 | # define DxGRPH_PFLIP_INT_OCCURRED (1 << 0) |
||
813 | # define DxGRPH_PFLIP_INT_CLEAR (1 << 8) |
||
814 | #define D1GRPH_INTERRUPT_CONTROL 0x615c |
||
815 | #define D2GRPH_INTERRUPT_CONTROL 0x695c |
||
816 | # define DxGRPH_PFLIP_INT_MASK (1 << 0) |
||
817 | # define DxGRPH_PFLIP_INT_TYPE (1 << 8) |
||
818 | |||
819 | /* PCIE link stuff */ |
||
820 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ |
||
821 | # define LC_POINT_7_PLUS_EN (1 << 6) |
||
822 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ |
||
823 | # define LC_LINK_WIDTH_SHIFT 0 |
||
824 | # define LC_LINK_WIDTH_MASK 0x7 |
||
825 | # define LC_LINK_WIDTH_X0 0 |
||
826 | # define LC_LINK_WIDTH_X1 1 |
||
827 | # define LC_LINK_WIDTH_X2 2 |
||
828 | # define LC_LINK_WIDTH_X4 3 |
||
829 | # define LC_LINK_WIDTH_X8 4 |
||
830 | # define LC_LINK_WIDTH_X16 6 |
||
831 | # define LC_LINK_WIDTH_RD_SHIFT 4 |
||
832 | # define LC_LINK_WIDTH_RD_MASK 0x70 |
||
833 | # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) |
||
834 | # define LC_RECONFIG_NOW (1 << 8) |
||
835 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) |
||
836 | # define LC_RENEGOTIATE_EN (1 << 10) |
||
837 | # define LC_SHORT_RECONFIG_EN (1 << 11) |
||
838 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) |
||
839 | # define LC_UPCONFIGURE_DIS (1 << 13) |
||
840 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ |
||
841 | # define LC_GEN2_EN_STRAP (1 << 0) |
||
842 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) |
||
843 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) |
||
844 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) |
||
845 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) |
||
846 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 |
||
847 | # define LC_CURRENT_DATA_RATE (1 << 11) |
||
848 | # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) |
||
849 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) |
||
850 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) |
||
851 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) |
||
852 | #define MM_CFGREGS_CNTL 0x544c |
||
853 | # define MM_WR_TO_CFG_EN (1 << 3) |
||
854 | #define LINK_CNTL2 0x88 /* F0 */ |
||
855 | # define TARGET_LINK_SPEED_MASK (0xf << 0) |
||
856 | # define SELECTABLE_DEEMPHASIS (1 << 6) |
||
857 | |||
2997 | Serge | 858 | /* Audio clocks */ |
859 | #define DCCG_AUDIO_DTO0_PHASE 0x0514 |
||
860 | #define DCCG_AUDIO_DTO0_MODULE 0x0518 |
||
861 | #define DCCG_AUDIO_DTO0_LOAD 0x051c |
||
862 | # define DTO_LOAD (1 << 31) |
||
863 | #define DCCG_AUDIO_DTO0_CNTL 0x0520 |
||
864 | |||
865 | #define DCCG_AUDIO_DTO1_PHASE 0x0524 |
||
866 | #define DCCG_AUDIO_DTO1_MODULE 0x0528 |
||
867 | #define DCCG_AUDIO_DTO1_LOAD 0x052c |
||
868 | #define DCCG_AUDIO_DTO1_CNTL 0x0530 |
||
869 | |||
870 | #define DCCG_AUDIO_DTO_SELECT 0x0534 |
||
871 | |||
872 | /* digital blocks */ |
||
873 | #define TMDSA_CNTL 0x7880 |
||
874 | # define TMDSA_HDMI_EN (1 << 2) |
||
875 | #define LVTMA_CNTL 0x7a80 |
||
876 | # define LVTMA_HDMI_EN (1 << 2) |
||
877 | #define DDIA_CNTL 0x7200 |
||
878 | # define DDIA_HDMI_EN (1 << 2) |
||
879 | #define DIG0_CNTL 0x75a0 |
||
880 | # define DIG_MODE(x) (((x) & 7) << 8) |
||
881 | # define DIG_MODE_DP 0 |
||
882 | # define DIG_MODE_LVDS 1 |
||
883 | # define DIG_MODE_TMDS_DVI 2 |
||
884 | # define DIG_MODE_TMDS_HDMI 3 |
||
885 | # define DIG_MODE_SDVO 4 |
||
886 | #define DIG1_CNTL 0x79a0 |
||
887 | |||
888 | /* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one |
||
889 | * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly |
||
890 | * different due to the new DIG blocks, but also have 2 instances. |
||
891 | * DCE 3.0 HDMI blocks are part of each DIG encoder. |
||
892 | */ |
||
893 | |||
894 | /* rs6xx/rs740/r6xx/dce3 */ |
||
895 | #define HDMI0_CONTROL 0x7400 |
||
896 | /* rs6xx/rs740/r6xx */ |
||
897 | # define HDMI0_ENABLE (1 << 0) |
||
898 | # define HDMI0_STREAM(x) (((x) & 3) << 2) |
||
899 | # define HDMI0_STREAM_TMDSA 0 |
||
900 | # define HDMI0_STREAM_LVTMA 1 |
||
901 | # define HDMI0_STREAM_DVOA 2 |
||
902 | # define HDMI0_STREAM_DDIA 3 |
||
903 | /* rs6xx/r6xx/dce3 */ |
||
904 | # define HDMI0_ERROR_ACK (1 << 8) |
||
905 | # define HDMI0_ERROR_MASK (1 << 9) |
||
906 | #define HDMI0_STATUS 0x7404 |
||
907 | # define HDMI0_ACTIVE_AVMUTE (1 << 0) |
||
908 | # define HDMI0_AUDIO_ENABLE (1 << 4) |
||
909 | # define HDMI0_AZ_FORMAT_WTRIG (1 << 28) |
||
910 | # define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29) |
||
911 | #define HDMI0_AUDIO_PACKET_CONTROL 0x7408 |
||
912 | # define HDMI0_AUDIO_SAMPLE_SEND (1 << 0) |
||
913 | # define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4) |
||
914 | # define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8) |
||
915 | # define HDMI0_AUDIO_TEST_EN (1 << 12) |
||
916 | # define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) |
||
917 | # define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24) |
||
918 | # define HDMI0_60958_CS_UPDATE (1 << 26) |
||
919 | # define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28) |
||
920 | # define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29) |
||
921 | #define HDMI0_AUDIO_CRC_CONTROL 0x740c |
||
922 | # define HDMI0_AUDIO_CRC_EN (1 << 0) |
||
923 | #define HDMI0_VBI_PACKET_CONTROL 0x7410 |
||
924 | # define HDMI0_NULL_SEND (1 << 0) |
||
925 | # define HDMI0_GC_SEND (1 << 4) |
||
926 | # define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ |
||
927 | #define HDMI0_INFOFRAME_CONTROL0 0x7414 |
||
928 | # define HDMI0_AVI_INFO_SEND (1 << 0) |
||
929 | # define HDMI0_AVI_INFO_CONT (1 << 1) |
||
930 | # define HDMI0_AUDIO_INFO_SEND (1 << 4) |
||
931 | # define HDMI0_AUDIO_INFO_CONT (1 << 5) |
||
932 | # define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */ |
||
933 | # define HDMI0_AUDIO_INFO_UPDATE (1 << 7) |
||
934 | # define HDMI0_MPEG_INFO_SEND (1 << 8) |
||
935 | # define HDMI0_MPEG_INFO_CONT (1 << 9) |
||
936 | # define HDMI0_MPEG_INFO_UPDATE (1 << 10) |
||
937 | #define HDMI0_INFOFRAME_CONTROL1 0x7418 |
||
938 | # define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) |
||
939 | # define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) |
||
940 | # define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) |
||
941 | #define HDMI0_GENERIC_PACKET_CONTROL 0x741c |
||
942 | # define HDMI0_GENERIC0_SEND (1 << 0) |
||
943 | # define HDMI0_GENERIC0_CONT (1 << 1) |
||
944 | # define HDMI0_GENERIC0_UPDATE (1 << 2) |
||
945 | # define HDMI0_GENERIC1_SEND (1 << 4) |
||
946 | # define HDMI0_GENERIC1_CONT (1 << 5) |
||
947 | # define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16) |
||
948 | # define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24) |
||
949 | #define HDMI0_GC 0x7428 |
||
950 | # define HDMI0_GC_AVMUTE (1 << 0) |
||
951 | #define HDMI0_AVI_INFO0 0x7454 |
||
952 | # define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) |
||
953 | # define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8) |
||
954 | # define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10) |
||
955 | # define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12) |
||
956 | # define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13) |
||
957 | # define HDMI0_AVI_INFO_Y_RGB 0 |
||
958 | # define HDMI0_AVI_INFO_Y_YCBCR422 1 |
||
959 | # define HDMI0_AVI_INFO_Y_YCBCR444 2 |
||
960 | # define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) |
||
961 | # define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16) |
||
962 | # define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20) |
||
963 | # define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22) |
||
964 | # define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) |
||
965 | # define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24) |
||
966 | # define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) |
||
967 | #define HDMI0_AVI_INFO1 0x7458 |
||
968 | # define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ |
||
969 | # define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ |
||
970 | # define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) |
||
971 | #define HDMI0_AVI_INFO2 0x745c |
||
972 | # define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) |
||
973 | # define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) |
||
974 | #define HDMI0_AVI_INFO3 0x7460 |
||
975 | # define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) |
||
976 | # define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24) |
||
977 | #define HDMI0_MPEG_INFO0 0x7464 |
||
978 | # define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) |
||
979 | # define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) |
||
980 | # define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) |
||
981 | # define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) |
||
982 | #define HDMI0_MPEG_INFO1 0x7468 |
||
983 | # define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) |
||
984 | # define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8) |
||
985 | # define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12) |
||
986 | #define HDMI0_GENERIC0_HDR 0x746c |
||
987 | #define HDMI0_GENERIC0_0 0x7470 |
||
988 | #define HDMI0_GENERIC0_1 0x7474 |
||
989 | #define HDMI0_GENERIC0_2 0x7478 |
||
990 | #define HDMI0_GENERIC0_3 0x747c |
||
991 | #define HDMI0_GENERIC0_4 0x7480 |
||
992 | #define HDMI0_GENERIC0_5 0x7484 |
||
993 | #define HDMI0_GENERIC0_6 0x7488 |
||
994 | #define HDMI0_GENERIC1_HDR 0x748c |
||
995 | #define HDMI0_GENERIC1_0 0x7490 |
||
996 | #define HDMI0_GENERIC1_1 0x7494 |
||
997 | #define HDMI0_GENERIC1_2 0x7498 |
||
998 | #define HDMI0_GENERIC1_3 0x749c |
||
999 | #define HDMI0_GENERIC1_4 0x74a0 |
||
1000 | #define HDMI0_GENERIC1_5 0x74a4 |
||
1001 | #define HDMI0_GENERIC1_6 0x74a8 |
||
1002 | #define HDMI0_ACR_32_0 0x74ac |
||
1003 | # define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12) |
||
1004 | #define HDMI0_ACR_32_1 0x74b0 |
||
1005 | # define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0) |
||
1006 | #define HDMI0_ACR_44_0 0x74b4 |
||
1007 | # define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12) |
||
1008 | #define HDMI0_ACR_44_1 0x74b8 |
||
1009 | # define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0) |
||
1010 | #define HDMI0_ACR_48_0 0x74bc |
||
1011 | # define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12) |
||
1012 | #define HDMI0_ACR_48_1 0x74c0 |
||
1013 | # define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0) |
||
1014 | #define HDMI0_ACR_STATUS_0 0x74c4 |
||
1015 | #define HDMI0_ACR_STATUS_1 0x74c8 |
||
1016 | #define HDMI0_AUDIO_INFO0 0x74cc |
||
1017 | # define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) |
||
1018 | # define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8) |
||
1019 | #define HDMI0_AUDIO_INFO1 0x74d0 |
||
1020 | # define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) |
||
1021 | # define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) |
||
1022 | # define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) |
||
1023 | # define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) |
||
1024 | #define HDMI0_60958_0 0x74d4 |
||
1025 | # define HDMI0_60958_CS_A(x) (((x) & 1) << 0) |
||
1026 | # define HDMI0_60958_CS_B(x) (((x) & 1) << 1) |
||
1027 | # define HDMI0_60958_CS_C(x) (((x) & 1) << 2) |
||
1028 | # define HDMI0_60958_CS_D(x) (((x) & 3) << 3) |
||
1029 | # define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6) |
||
1030 | # define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) |
||
1031 | # define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) |
||
1032 | # define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) |
||
1033 | # define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) |
||
1034 | # define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) |
||
1035 | #define HDMI0_60958_1 0x74d8 |
||
1036 | # define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) |
||
1037 | # define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) |
||
1038 | # define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16) |
||
1039 | # define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18) |
||
1040 | # define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) |
||
1041 | #define HDMI0_ACR_PACKET_CONTROL 0x74dc |
||
1042 | # define HDMI0_ACR_SEND (1 << 0) |
||
1043 | # define HDMI0_ACR_CONT (1 << 1) |
||
1044 | # define HDMI0_ACR_SELECT(x) (((x) & 3) << 4) |
||
1045 | # define HDMI0_ACR_HW 0 |
||
1046 | # define HDMI0_ACR_32 1 |
||
1047 | # define HDMI0_ACR_44 2 |
||
1048 | # define HDMI0_ACR_48 3 |
||
1049 | # define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ |
||
1050 | # define HDMI0_ACR_AUTO_SEND (1 << 12) |
||
1051 | #define HDMI0_RAMP_CONTROL0 0x74e0 |
||
1052 | # define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) |
||
1053 | #define HDMI0_RAMP_CONTROL1 0x74e4 |
||
1054 | # define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) |
||
1055 | #define HDMI0_RAMP_CONTROL2 0x74e8 |
||
1056 | # define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) |
||
1057 | #define HDMI0_RAMP_CONTROL3 0x74ec |
||
1058 | # define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) |
||
1059 | /* HDMI0_60958_2 is r7xx only */ |
||
1060 | #define HDMI0_60958_2 0x74f0 |
||
1061 | # define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) |
||
1062 | # define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) |
||
1063 | # define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) |
||
1064 | # define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) |
||
1065 | # define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) |
||
1066 | # define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) |
||
1067 | /* r6xx only; second instance starts at 0x7700 */ |
||
1068 | #define HDMI1_CONTROL 0x7700 |
||
1069 | #define HDMI1_STATUS 0x7704 |
||
1070 | #define HDMI1_AUDIO_PACKET_CONTROL 0x7708 |
||
1071 | /* DCE3; second instance starts at 0x7800 NOT 0x7700 */ |
||
1072 | #define DCE3_HDMI1_CONTROL 0x7800 |
||
1073 | #define DCE3_HDMI1_STATUS 0x7804 |
||
1074 | #define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808 |
||
1075 | /* DCE3.2 (for interrupts) */ |
||
1076 | #define AFMT_STATUS 0x7600 |
||
1077 | # define AFMT_AUDIO_ENABLE (1 << 4) |
||
1078 | # define AFMT_AZ_FORMAT_WTRIG (1 << 28) |
||
1079 | # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) |
||
1080 | # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) |
||
1081 | #define AFMT_AUDIO_PACKET_CONTROL 0x7604 |
||
1082 | # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) |
||
1083 | # define AFMT_AUDIO_TEST_EN (1 << 12) |
||
1084 | # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) |
||
1085 | # define AFMT_60958_CS_UPDATE (1 << 26) |
||
1086 | # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) |
||
1087 | # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) |
||
1088 | # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) |
||
1089 | # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) |
||
1090 | |||
1221 | serge | 1091 | /* |
1092 | * PM4 |
||
1093 | */ |
||
1094 | #define PACKET_TYPE0 0 |
||
1095 | #define PACKET_TYPE1 1 |
||
1096 | #define PACKET_TYPE2 2 |
||
1097 | #define PACKET_TYPE3 3 |
||
1098 | |||
1099 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) |
||
1100 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) |
||
1101 | #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) |
||
1102 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
||
1103 | #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ |
||
1104 | (((reg) >> 2) & 0xFFFF) | \ |
||
1105 | ((n) & 0x3FFF) << 16) |
||
1106 | #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ |
||
1107 | (((op) & 0xFF) << 8) | \ |
||
1108 | ((n) & 0x3FFF) << 16) |
||
1109 | |||
1110 | /* Packet 3 types */ |
||
1111 | #define PACKET3_NOP 0x10 |
||
1112 | #define PACKET3_INDIRECT_BUFFER_END 0x17 |
||
1113 | #define PACKET3_SET_PREDICATION 0x20 |
||
1114 | #define PACKET3_REG_RMW 0x21 |
||
1115 | #define PACKET3_COND_EXEC 0x22 |
||
1116 | #define PACKET3_PRED_EXEC 0x23 |
||
1117 | #define PACKET3_START_3D_CMDBUF 0x24 |
||
1118 | #define PACKET3_DRAW_INDEX_2 0x27 |
||
1119 | #define PACKET3_CONTEXT_CONTROL 0x28 |
||
1120 | #define PACKET3_DRAW_INDEX_IMMD_BE 0x29 |
||
1121 | #define PACKET3_INDEX_TYPE 0x2A |
||
1122 | #define PACKET3_DRAW_INDEX 0x2B |
||
1123 | #define PACKET3_DRAW_INDEX_AUTO 0x2D |
||
1124 | #define PACKET3_DRAW_INDEX_IMMD 0x2E |
||
1125 | #define PACKET3_NUM_INSTANCES 0x2F |
||
1126 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 |
||
1127 | #define PACKET3_INDIRECT_BUFFER_MP 0x38 |
||
1128 | #define PACKET3_MEM_SEMAPHORE 0x39 |
||
2997 | Serge | 1129 | # define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) |
1130 | # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) |
||
1131 | # define PACKET3_SEM_SEL_WAIT (0x7 << 29) |
||
1221 | serge | 1132 | #define PACKET3_MPEG_INDEX 0x3A |
2997 | Serge | 1133 | #define PACKET3_COPY_DW 0x3B |
1221 | serge | 1134 | #define PACKET3_WAIT_REG_MEM 0x3C |
1135 | #define PACKET3_MEM_WRITE 0x3D |
||
1136 | #define PACKET3_INDIRECT_BUFFER 0x32 |
||
1137 | #define PACKET3_SURFACE_SYNC 0x43 |
||
1138 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
||
1139 | # define PACKET3_TC_ACTION_ENA (1 << 23) |
||
1140 | # define PACKET3_VC_ACTION_ENA (1 << 24) |
||
1141 | # define PACKET3_CB_ACTION_ENA (1 << 25) |
||
1142 | # define PACKET3_DB_ACTION_ENA (1 << 26) |
||
1143 | # define PACKET3_SH_ACTION_ENA (1 << 27) |
||
1144 | # define PACKET3_SMX_ACTION_ENA (1 << 28) |
||
1145 | #define PACKET3_ME_INITIALIZE 0x44 |
||
1146 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) |
||
1147 | #define PACKET3_COND_WRITE 0x45 |
||
1148 | #define PACKET3_EVENT_WRITE 0x46 |
||
1963 | serge | 1149 | #define EVENT_TYPE(x) ((x) << 0) |
1150 | #define EVENT_INDEX(x) ((x) << 8) |
||
1151 | /* 0 - any non-TS event |
||
1152 | * 1 - ZPASS_DONE |
||
1153 | * 2 - SAMPLE_PIPELINESTAT |
||
1154 | * 3 - SAMPLE_STREAMOUTSTAT* |
||
1155 | * 4 - *S_PARTIAL_FLUSH |
||
1156 | * 5 - TS events |
||
1157 | */ |
||
1221 | serge | 1158 | #define PACKET3_EVENT_WRITE_EOP 0x47 |
1963 | serge | 1159 | #define DATA_SEL(x) ((x) << 29) |
1160 | /* 0 - discard |
||
1161 | * 1 - send low 32bit data |
||
1162 | * 2 - send 64bit data |
||
1163 | * 3 - send 64bit counter value |
||
1164 | */ |
||
1165 | #define INT_SEL(x) ((x) << 24) |
||
1166 | /* 0 - none |
||
1167 | * 1 - interrupt only (DATA_SEL = 0) |
||
1168 | * 2 - interrupt when data write is confirmed |
||
1169 | */ |
||
1221 | serge | 1170 | #define PACKET3_ONE_REG_WRITE 0x57 |
1171 | #define PACKET3_SET_CONFIG_REG 0x68 |
||
1172 | #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 |
||
1173 | #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 |
||
1174 | #define PACKET3_SET_CONTEXT_REG 0x69 |
||
1175 | #define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 |
||
1176 | #define PACKET3_SET_CONTEXT_REG_END 0x00029000 |
||
1177 | #define PACKET3_SET_ALU_CONST 0x6A |
||
1178 | #define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 |
||
1179 | #define PACKET3_SET_ALU_CONST_END 0x00032000 |
||
1180 | #define PACKET3_SET_BOOL_CONST 0x6B |
||
1181 | #define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 |
||
1182 | #define PACKET3_SET_BOOL_CONST_END 0x00040000 |
||
1183 | #define PACKET3_SET_LOOP_CONST 0x6C |
||
1184 | #define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 |
||
1185 | #define PACKET3_SET_LOOP_CONST_END 0x0003e380 |
||
1186 | #define PACKET3_SET_RESOURCE 0x6D |
||
1187 | #define PACKET3_SET_RESOURCE_OFFSET 0x00038000 |
||
1188 | #define PACKET3_SET_RESOURCE_END 0x0003c000 |
||
1189 | #define PACKET3_SET_SAMPLER 0x6E |
||
1190 | #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 |
||
1191 | #define PACKET3_SET_SAMPLER_END 0x0003cff0 |
||
1192 | #define PACKET3_SET_CTL_CONST 0x6F |
||
1193 | #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 |
||
1194 | #define PACKET3_SET_CTL_CONST_END 0x0003e200 |
||
2997 | Serge | 1195 | #define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */ |
1221 | serge | 1196 | #define PACKET3_SURFACE_BASE_UPDATE 0x73 |
1197 | |||
1198 | |||
1199 | #define R_008020_GRBM_SOFT_RESET 0x8020 |
||
1200 | #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) |
||
1201 | #define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) |
||
1202 | #define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) |
||
1203 | #define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) |
||
1204 | #define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) |
||
1205 | #define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) |
||
1206 | #define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) |
||
1207 | #define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) |
||
1208 | #define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) |
||
1209 | #define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) |
||
1210 | #define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) |
||
1211 | #define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) |
||
1212 | #define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) |
||
1213 | #define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) |
||
1214 | #define R_008010_GRBM_STATUS 0x8010 |
||
1215 | #define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) |
||
1216 | #define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) |
||
1217 | #define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) |
||
1218 | #define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) |
||
1219 | #define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) |
||
1220 | #define S_008010_VC_BUSY(x) (((x) & 1) << 11) |
||
1221 | #define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) |
||
1222 | #define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) |
||
1223 | #define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) |
||
1224 | #define S_008010_VGT_BUSY(x) (((x) & 1) << 17) |
||
1225 | #define S_008010_TA03_BUSY(x) (((x) & 1) << 18) |
||
1226 | #define S_008010_TC_BUSY(x) (((x) & 1) << 19) |
||
1227 | #define S_008010_SX_BUSY(x) (((x) & 1) << 20) |
||
1228 | #define S_008010_SH_BUSY(x) (((x) & 1) << 21) |
||
1229 | #define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) |
||
1230 | #define S_008010_SMX_BUSY(x) (((x) & 1) << 23) |
||
1231 | #define S_008010_SC_BUSY(x) (((x) & 1) << 24) |
||
1232 | #define S_008010_PA_BUSY(x) (((x) & 1) << 25) |
||
1233 | #define S_008010_DB03_BUSY(x) (((x) & 1) << 26) |
||
1234 | #define S_008010_CR_BUSY(x) (((x) & 1) << 27) |
||
1235 | #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) |
||
1236 | #define S_008010_CP_BUSY(x) (((x) & 1) << 29) |
||
1237 | #define S_008010_CB03_BUSY(x) (((x) & 1) << 30) |
||
1238 | #define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) |
||
1239 | #define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) |
||
1240 | #define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) |
||
1241 | #define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) |
||
1242 | #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) |
||
1243 | #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) |
||
1244 | #define G_008010_VC_BUSY(x) (((x) >> 11) & 1) |
||
1245 | #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) |
||
1246 | #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) |
||
1247 | #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) |
||
1248 | #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) |
||
1249 | #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) |
||
1250 | #define G_008010_TC_BUSY(x) (((x) >> 19) & 1) |
||
1251 | #define G_008010_SX_BUSY(x) (((x) >> 20) & 1) |
||
1252 | #define G_008010_SH_BUSY(x) (((x) >> 21) & 1) |
||
1253 | #define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) |
||
1254 | #define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) |
||
1255 | #define G_008010_SC_BUSY(x) (((x) >> 24) & 1) |
||
1256 | #define G_008010_PA_BUSY(x) (((x) >> 25) & 1) |
||
1257 | #define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) |
||
1258 | #define G_008010_CR_BUSY(x) (((x) >> 27) & 1) |
||
1259 | #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) |
||
1260 | #define G_008010_CP_BUSY(x) (((x) >> 29) & 1) |
||
1261 | #define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) |
||
1262 | #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) |
||
1263 | #define R_008014_GRBM_STATUS2 0x8014 |
||
1264 | #define S_008014_CR_CLEAN(x) (((x) & 1) << 0) |
||
1265 | #define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) |
||
1266 | #define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) |
||
1267 | #define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) |
||
1268 | #define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) |
||
1269 | #define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) |
||
1270 | #define S_008014_TA0_BUSY(x) (((x) & 1) << 12) |
||
1271 | #define S_008014_TA1_BUSY(x) (((x) & 1) << 13) |
||
1272 | #define S_008014_TA2_BUSY(x) (((x) & 1) << 14) |
||
1273 | #define S_008014_TA3_BUSY(x) (((x) & 1) << 15) |
||
1274 | #define S_008014_DB0_BUSY(x) (((x) & 1) << 16) |
||
1275 | #define S_008014_DB1_BUSY(x) (((x) & 1) << 17) |
||
1276 | #define S_008014_DB2_BUSY(x) (((x) & 1) << 18) |
||
1277 | #define S_008014_DB3_BUSY(x) (((x) & 1) << 19) |
||
1278 | #define S_008014_CB0_BUSY(x) (((x) & 1) << 20) |
||
1279 | #define S_008014_CB1_BUSY(x) (((x) & 1) << 21) |
||
1280 | #define S_008014_CB2_BUSY(x) (((x) & 1) << 22) |
||
1281 | #define S_008014_CB3_BUSY(x) (((x) & 1) << 23) |
||
1282 | #define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) |
||
1283 | #define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) |
||
1284 | #define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) |
||
1285 | #define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) |
||
1286 | #define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) |
||
1287 | #define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) |
||
1288 | #define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) |
||
1289 | #define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) |
||
1290 | #define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) |
||
1291 | #define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) |
||
1292 | #define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) |
||
1293 | #define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) |
||
1294 | #define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) |
||
1295 | #define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) |
||
1296 | #define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) |
||
1297 | #define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) |
||
1298 | #define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) |
||
1299 | #define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) |
||
1300 | #define R_000E50_SRBM_STATUS 0x0E50 |
||
1301 | #define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) |
||
1302 | #define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) |
||
1303 | #define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) |
||
1304 | #define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) |
||
1305 | #define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) |
||
1306 | #define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) |
||
1307 | #define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) |
||
1308 | #define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) |
||
1309 | #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) |
||
1310 | #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) |
||
1311 | #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) |
||
1312 | #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) |
||
1313 | #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) |
||
1314 | #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) |
||
1315 | #define R_000E60_SRBM_SOFT_RESET 0x0E60 |
||
1316 | #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) |
||
1317 | #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) |
||
1318 | #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) |
||
1319 | #define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) |
||
1320 | #define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) |
||
1321 | #define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) |
||
1322 | #define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) |
||
1323 | #define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) |
||
1324 | #define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) |
||
1325 | #define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) |
||
1326 | #define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) |
||
1327 | #define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) |
||
1328 | #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) |
||
1329 | #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) |
||
1330 | |||
1321 | serge | 1331 | #define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 |
1403 | serge | 1332 | |
1430 | serge | 1333 | #define R_028C04_PA_SC_AA_CONFIG 0x028C04 |
1334 | #define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0) |
||
1335 | #define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3) |
||
1336 | #define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC |
||
1337 | #define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) |
||
1338 | #define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) |
||
1339 | #define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF |
||
1340 | #define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13) |
||
1341 | #define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) |
||
1342 | #define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF |
||
1403 | serge | 1343 | #define R_0280E0_CB_COLOR0_FRAG 0x0280E0 |
1344 | #define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) |
||
1345 | #define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) |
||
1346 | #define C_0280E0_BASE_256B 0x00000000 |
||
1347 | #define R_0280E4_CB_COLOR1_FRAG 0x0280E4 |
||
1348 | #define R_0280E8_CB_COLOR2_FRAG 0x0280E8 |
||
1349 | #define R_0280EC_CB_COLOR3_FRAG 0x0280EC |
||
1350 | #define R_0280F0_CB_COLOR4_FRAG 0x0280F0 |
||
1351 | #define R_0280F4_CB_COLOR5_FRAG 0x0280F4 |
||
1352 | #define R_0280F8_CB_COLOR6_FRAG 0x0280F8 |
||
1353 | #define R_0280FC_CB_COLOR7_FRAG 0x0280FC |
||
1354 | #define R_0280C0_CB_COLOR0_TILE 0x0280C0 |
||
1355 | #define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) |
||
1356 | #define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) |
||
1357 | #define C_0280C0_BASE_256B 0x00000000 |
||
1358 | #define R_0280C4_CB_COLOR1_TILE 0x0280C4 |
||
1359 | #define R_0280C8_CB_COLOR2_TILE 0x0280C8 |
||
1360 | #define R_0280CC_CB_COLOR3_TILE 0x0280CC |
||
1361 | #define R_0280D0_CB_COLOR4_TILE 0x0280D0 |
||
1362 | #define R_0280D4_CB_COLOR5_TILE 0x0280D4 |
||
1363 | #define R_0280D8_CB_COLOR6_TILE 0x0280D8 |
||
1364 | #define R_0280DC_CB_COLOR7_TILE 0x0280DC |
||
1430 | serge | 1365 | #define R_0280A0_CB_COLOR0_INFO 0x0280A0 |
1366 | #define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) |
||
1367 | #define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) |
||
1368 | #define C_0280A0_ENDIAN 0xFFFFFFFC |
||
1369 | #define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) |
||
1370 | #define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) |
||
1371 | #define C_0280A0_FORMAT 0xFFFFFF03 |
||
1372 | #define V_0280A0_COLOR_INVALID 0x00000000 |
||
1373 | #define V_0280A0_COLOR_8 0x00000001 |
||
1374 | #define V_0280A0_COLOR_4_4 0x00000002 |
||
1375 | #define V_0280A0_COLOR_3_3_2 0x00000003 |
||
1376 | #define V_0280A0_COLOR_16 0x00000005 |
||
1377 | #define V_0280A0_COLOR_16_FLOAT 0x00000006 |
||
1378 | #define V_0280A0_COLOR_8_8 0x00000007 |
||
1379 | #define V_0280A0_COLOR_5_6_5 0x00000008 |
||
1380 | #define V_0280A0_COLOR_6_5_5 0x00000009 |
||
1381 | #define V_0280A0_COLOR_1_5_5_5 0x0000000A |
||
1382 | #define V_0280A0_COLOR_4_4_4_4 0x0000000B |
||
1383 | #define V_0280A0_COLOR_5_5_5_1 0x0000000C |
||
1384 | #define V_0280A0_COLOR_32 0x0000000D |
||
1385 | #define V_0280A0_COLOR_32_FLOAT 0x0000000E |
||
1386 | #define V_0280A0_COLOR_16_16 0x0000000F |
||
1387 | #define V_0280A0_COLOR_16_16_FLOAT 0x00000010 |
||
1388 | #define V_0280A0_COLOR_8_24 0x00000011 |
||
1389 | #define V_0280A0_COLOR_8_24_FLOAT 0x00000012 |
||
1390 | #define V_0280A0_COLOR_24_8 0x00000013 |
||
1391 | #define V_0280A0_COLOR_24_8_FLOAT 0x00000014 |
||
1392 | #define V_0280A0_COLOR_10_11_11 0x00000015 |
||
1393 | #define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 |
||
1394 | #define V_0280A0_COLOR_11_11_10 0x00000017 |
||
1395 | #define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 |
||
1396 | #define V_0280A0_COLOR_2_10_10_10 0x00000019 |
||
1397 | #define V_0280A0_COLOR_8_8_8_8 0x0000001A |
||
1398 | #define V_0280A0_COLOR_10_10_10_2 0x0000001B |
||
1399 | #define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C |
||
1400 | #define V_0280A0_COLOR_32_32 0x0000001D |
||
1401 | #define V_0280A0_COLOR_32_32_FLOAT 0x0000001E |
||
1402 | #define V_0280A0_COLOR_16_16_16_16 0x0000001F |
||
1403 | #define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 |
||
1404 | #define V_0280A0_COLOR_32_32_32_32 0x00000022 |
||
1405 | #define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 |
||
1406 | #define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) |
||
1407 | #define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) |
||
1408 | #define C_0280A0_ARRAY_MODE 0xFFFFF0FF |
||
1409 | #define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 |
||
1410 | #define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 |
||
1411 | #define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 |
||
1412 | #define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 |
||
1413 | #define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) |
||
1414 | #define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) |
||
1415 | #define C_0280A0_NUMBER_TYPE 0xFFFF8FFF |
||
1416 | #define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) |
||
1417 | #define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) |
||
1418 | #define C_0280A0_READ_SIZE 0xFFFF7FFF |
||
1419 | #define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) |
||
1420 | #define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) |
||
1421 | #define C_0280A0_COMP_SWAP 0xFFFCFFFF |
||
1422 | #define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) |
||
1423 | #define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) |
||
1424 | #define C_0280A0_TILE_MODE 0xFFF3FFFF |
||
2997 | Serge | 1425 | #define V_0280A0_TILE_DISABLE 0 |
1426 | #define V_0280A0_CLEAR_ENABLE 1 |
||
1427 | #define V_0280A0_FRAG_ENABLE 2 |
||
1430 | serge | 1428 | #define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) |
1429 | #define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) |
||
1430 | #define C_0280A0_BLEND_CLAMP 0xFFEFFFFF |
||
1431 | #define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) |
||
1432 | #define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) |
||
1433 | #define C_0280A0_CLEAR_COLOR 0xFFDFFFFF |
||
1434 | #define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) |
||
1435 | #define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) |
||
1436 | #define C_0280A0_BLEND_BYPASS 0xFFBFFFFF |
||
1437 | #define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) |
||
1438 | #define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) |
||
1439 | #define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF |
||
1440 | #define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) |
||
1441 | #define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) |
||
1442 | #define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF |
||
1443 | #define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) |
||
1444 | #define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) |
||
1445 | #define C_0280A0_ROUND_MODE 0xFDFFFFFF |
||
1446 | #define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) |
||
1447 | #define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) |
||
1448 | #define C_0280A0_TILE_COMPACT 0xFBFFFFFF |
||
1449 | #define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) |
||
1450 | #define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) |
||
1451 | #define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF |
||
1452 | #define R_0280A4_CB_COLOR1_INFO 0x0280A4 |
||
1453 | #define R_0280A8_CB_COLOR2_INFO 0x0280A8 |
||
1454 | #define R_0280AC_CB_COLOR3_INFO 0x0280AC |
||
1455 | #define R_0280B0_CB_COLOR4_INFO 0x0280B0 |
||
1456 | #define R_0280B4_CB_COLOR5_INFO 0x0280B4 |
||
1457 | #define R_0280B8_CB_COLOR6_INFO 0x0280B8 |
||
1458 | #define R_0280BC_CB_COLOR7_INFO 0x0280BC |
||
1459 | #define R_028060_CB_COLOR0_SIZE 0x028060 |
||
1460 | #define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) |
||
1461 | #define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) |
||
1462 | #define C_028060_PITCH_TILE_MAX 0xFFFFFC00 |
||
1463 | #define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) |
||
1464 | #define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) |
||
1465 | #define C_028060_SLICE_TILE_MAX 0xC00003FF |
||
1466 | #define R_028064_CB_COLOR1_SIZE 0x028064 |
||
1467 | #define R_028068_CB_COLOR2_SIZE 0x028068 |
||
1468 | #define R_02806C_CB_COLOR3_SIZE 0x02806C |
||
1469 | #define R_028070_CB_COLOR4_SIZE 0x028070 |
||
1470 | #define R_028074_CB_COLOR5_SIZE 0x028074 |
||
1471 | #define R_028078_CB_COLOR6_SIZE 0x028078 |
||
1472 | #define R_02807C_CB_COLOR7_SIZE 0x02807C |
||
1473 | #define R_028238_CB_TARGET_MASK 0x028238 |
||
1474 | #define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0) |
||
1475 | #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF) |
||
1476 | #define C_028238_TARGET0_ENABLE 0xFFFFFFF0 |
||
1477 | #define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4) |
||
1478 | #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF) |
||
1479 | #define C_028238_TARGET1_ENABLE 0xFFFFFF0F |
||
1480 | #define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8) |
||
1481 | #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF) |
||
1482 | #define C_028238_TARGET2_ENABLE 0xFFFFF0FF |
||
1483 | #define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12) |
||
1484 | #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF) |
||
1485 | #define C_028238_TARGET3_ENABLE 0xFFFF0FFF |
||
1486 | #define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16) |
||
1487 | #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF) |
||
1488 | #define C_028238_TARGET4_ENABLE 0xFFF0FFFF |
||
1489 | #define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20) |
||
1490 | #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF) |
||
1491 | #define C_028238_TARGET5_ENABLE 0xFF0FFFFF |
||
1492 | #define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24) |
||
1493 | #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF) |
||
1494 | #define C_028238_TARGET6_ENABLE 0xF0FFFFFF |
||
1495 | #define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28) |
||
1496 | #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF) |
||
1497 | #define C_028238_TARGET7_ENABLE 0x0FFFFFFF |
||
1498 | #define R_02823C_CB_SHADER_MASK 0x02823C |
||
1499 | #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0) |
||
1500 | #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF) |
||
1501 | #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 |
||
1502 | #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4) |
||
1503 | #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF) |
||
1504 | #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F |
||
1505 | #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8) |
||
1506 | #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF) |
||
1507 | #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF |
||
1508 | #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12) |
||
1509 | #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF) |
||
1510 | #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF |
||
1511 | #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16) |
||
1512 | #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF) |
||
1513 | #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF |
||
1514 | #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20) |
||
1515 | #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF) |
||
1516 | #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF |
||
1517 | #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24) |
||
1518 | #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF) |
||
1519 | #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF |
||
1520 | #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28) |
||
1521 | #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF) |
||
1522 | #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF |
||
1523 | #define R_028AB0_VGT_STRMOUT_EN 0x028AB0 |
||
1524 | #define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) |
||
1525 | #define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) |
||
1526 | #define C_028AB0_STREAMOUT 0xFFFFFFFE |
||
1527 | #define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 |
||
1528 | #define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) |
||
1529 | #define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) |
||
1530 | #define C_028B20_BUFFER_0_EN 0xFFFFFFFE |
||
1531 | #define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) |
||
1532 | #define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) |
||
1533 | #define C_028B20_BUFFER_1_EN 0xFFFFFFFD |
||
1534 | #define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) |
||
1535 | #define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) |
||
1536 | #define C_028B20_BUFFER_2_EN 0xFFFFFFFB |
||
1537 | #define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) |
||
1538 | #define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) |
||
1539 | #define C_028B20_BUFFER_3_EN 0xFFFFFFF7 |
||
1540 | #define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
1541 | #define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
1542 | #define C_028B20_SIZE 0x00000000 |
||
1543 | #define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000 |
||
1544 | #define S_038000_DIM(x) (((x) & 0x7) << 0) |
||
1545 | #define G_038000_DIM(x) (((x) >> 0) & 0x7) |
||
1546 | #define C_038000_DIM 0xFFFFFFF8 |
||
1547 | #define V_038000_SQ_TEX_DIM_1D 0x00000000 |
||
1548 | #define V_038000_SQ_TEX_DIM_2D 0x00000001 |
||
1549 | #define V_038000_SQ_TEX_DIM_3D 0x00000002 |
||
1550 | #define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003 |
||
1551 | #define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004 |
||
1552 | #define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005 |
||
1553 | #define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006 |
||
1554 | #define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 |
||
1555 | #define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) |
||
1556 | #define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) |
||
1557 | #define C_038000_TILE_MODE 0xFFFFFF87 |
||
1963 | serge | 1558 | #define V_038000_ARRAY_LINEAR_GENERAL 0x00000000 |
1559 | #define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001 |
||
1560 | #define V_038000_ARRAY_1D_TILED_THIN1 0x00000002 |
||
1561 | #define V_038000_ARRAY_2D_TILED_THIN1 0x00000004 |
||
1430 | serge | 1562 | #define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) |
1563 | #define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) |
||
1564 | #define C_038000_TILE_TYPE 0xFFFFFF7F |
||
1565 | #define S_038000_PITCH(x) (((x) & 0x7FF) << 8) |
||
1566 | #define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) |
||
1567 | #define C_038000_PITCH 0xFFF800FF |
||
1568 | #define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19) |
||
1569 | #define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF) |
||
1570 | #define C_038000_TEX_WIDTH 0x0007FFFF |
||
1571 | #define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004 |
||
1572 | #define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0) |
||
1573 | #define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF) |
||
1574 | #define C_038004_TEX_HEIGHT 0xFFFFE000 |
||
1575 | #define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13) |
||
1576 | #define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF) |
||
1577 | #define C_038004_TEX_DEPTH 0xFC001FFF |
||
1578 | #define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26) |
||
1579 | #define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F) |
||
1580 | #define C_038004_DATA_FORMAT 0x03FFFFFF |
||
1581 | #define V_038004_COLOR_INVALID 0x00000000 |
||
1582 | #define V_038004_COLOR_8 0x00000001 |
||
1583 | #define V_038004_COLOR_4_4 0x00000002 |
||
1584 | #define V_038004_COLOR_3_3_2 0x00000003 |
||
1585 | #define V_038004_COLOR_16 0x00000005 |
||
1586 | #define V_038004_COLOR_16_FLOAT 0x00000006 |
||
1587 | #define V_038004_COLOR_8_8 0x00000007 |
||
1588 | #define V_038004_COLOR_5_6_5 0x00000008 |
||
1589 | #define V_038004_COLOR_6_5_5 0x00000009 |
||
1590 | #define V_038004_COLOR_1_5_5_5 0x0000000A |
||
1591 | #define V_038004_COLOR_4_4_4_4 0x0000000B |
||
1592 | #define V_038004_COLOR_5_5_5_1 0x0000000C |
||
1593 | #define V_038004_COLOR_32 0x0000000D |
||
1594 | #define V_038004_COLOR_32_FLOAT 0x0000000E |
||
1595 | #define V_038004_COLOR_16_16 0x0000000F |
||
1596 | #define V_038004_COLOR_16_16_FLOAT 0x00000010 |
||
1597 | #define V_038004_COLOR_8_24 0x00000011 |
||
1598 | #define V_038004_COLOR_8_24_FLOAT 0x00000012 |
||
1599 | #define V_038004_COLOR_24_8 0x00000013 |
||
1600 | #define V_038004_COLOR_24_8_FLOAT 0x00000014 |
||
1601 | #define V_038004_COLOR_10_11_11 0x00000015 |
||
1602 | #define V_038004_COLOR_10_11_11_FLOAT 0x00000016 |
||
1603 | #define V_038004_COLOR_11_11_10 0x00000017 |
||
1604 | #define V_038004_COLOR_11_11_10_FLOAT 0x00000018 |
||
1605 | #define V_038004_COLOR_2_10_10_10 0x00000019 |
||
1606 | #define V_038004_COLOR_8_8_8_8 0x0000001A |
||
1607 | #define V_038004_COLOR_10_10_10_2 0x0000001B |
||
1608 | #define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C |
||
1609 | #define V_038004_COLOR_32_32 0x0000001D |
||
1610 | #define V_038004_COLOR_32_32_FLOAT 0x0000001E |
||
1611 | #define V_038004_COLOR_16_16_16_16 0x0000001F |
||
1612 | #define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020 |
||
1613 | #define V_038004_COLOR_32_32_32_32 0x00000022 |
||
1614 | #define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023 |
||
1615 | #define V_038004_FMT_1 0x00000025 |
||
1616 | #define V_038004_FMT_GB_GR 0x00000027 |
||
1617 | #define V_038004_FMT_BG_RG 0x00000028 |
||
1618 | #define V_038004_FMT_32_AS_8 0x00000029 |
||
1619 | #define V_038004_FMT_32_AS_8_8 0x0000002A |
||
1620 | #define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B |
||
1621 | #define V_038004_FMT_8_8_8 0x0000002C |
||
1622 | #define V_038004_FMT_16_16_16 0x0000002D |
||
1623 | #define V_038004_FMT_16_16_16_FLOAT 0x0000002E |
||
1624 | #define V_038004_FMT_32_32_32 0x0000002F |
||
1625 | #define V_038004_FMT_32_32_32_FLOAT 0x00000030 |
||
1963 | serge | 1626 | #define V_038004_FMT_BC1 0x00000031 |
1627 | #define V_038004_FMT_BC2 0x00000032 |
||
1628 | #define V_038004_FMT_BC3 0x00000033 |
||
1629 | #define V_038004_FMT_BC4 0x00000034 |
||
1630 | #define V_038004_FMT_BC5 0x00000035 |
||
1631 | #define V_038004_FMT_BC6 0x00000036 |
||
1632 | #define V_038004_FMT_BC7 0x00000037 |
||
1633 | #define V_038004_FMT_32_AS_32_32_32_32 0x00000038 |
||
1430 | serge | 1634 | #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 |
1635 | #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) |
||
1636 | #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) |
||
1637 | #define C_038010_FORMAT_COMP_X 0xFFFFFFFC |
||
1638 | #define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) |
||
1639 | #define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) |
||
1640 | #define C_038010_FORMAT_COMP_Y 0xFFFFFFF3 |
||
1641 | #define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) |
||
1642 | #define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) |
||
1643 | #define C_038010_FORMAT_COMP_Z 0xFFFFFFCF |
||
1644 | #define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) |
||
1645 | #define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) |
||
1646 | #define C_038010_FORMAT_COMP_W 0xFFFFFF3F |
||
1647 | #define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) |
||
1648 | #define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) |
||
1649 | #define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF |
||
1650 | #define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) |
||
1651 | #define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) |
||
1652 | #define C_038010_SRF_MODE_ALL 0xFFFFFBFF |
||
1653 | #define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) |
||
1654 | #define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) |
||
1655 | #define C_038010_FORCE_DEGAMMA 0xFFFFF7FF |
||
1656 | #define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) |
||
1657 | #define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) |
||
1658 | #define C_038010_ENDIAN_SWAP 0xFFFFCFFF |
||
1659 | #define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14) |
||
1660 | #define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) |
||
1661 | #define C_038010_REQUEST_SIZE 0xFFFF3FFF |
||
1662 | #define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16) |
||
1663 | #define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7) |
||
1664 | #define C_038010_DST_SEL_X 0xFFF8FFFF |
||
1665 | #define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19) |
||
1666 | #define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7) |
||
1667 | #define C_038010_DST_SEL_Y 0xFFC7FFFF |
||
1668 | #define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22) |
||
1669 | #define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) |
||
1670 | #define C_038010_DST_SEL_Z 0xFE3FFFFF |
||
1671 | #define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) |
||
1672 | #define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) |
||
1673 | #define C_038010_DST_SEL_W 0xF1FFFFFF |
||
2997 | Serge | 1674 | # define SQ_SEL_X 0 |
1675 | # define SQ_SEL_Y 1 |
||
1676 | # define SQ_SEL_Z 2 |
||
1677 | # define SQ_SEL_W 3 |
||
1678 | # define SQ_SEL_0 4 |
||
1679 | # define SQ_SEL_1 5 |
||
1430 | serge | 1680 | #define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) |
1681 | #define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) |
||
1682 | #define C_038010_BASE_LEVEL 0x0FFFFFFF |
||
1683 | #define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 |
||
1684 | #define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) |
||
1685 | #define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF) |
||
1686 | #define C_038014_LAST_LEVEL 0xFFFFFFF0 |
||
1687 | #define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) |
||
1688 | #define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) |
||
1689 | #define C_038014_BASE_ARRAY 0xFFFE000F |
||
1690 | #define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) |
||
1691 | #define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) |
||
1692 | #define C_038014_LAST_ARRAY 0xC001FFFF |
||
1693 | #define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8 |
||
1694 | #define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
1695 | #define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
1696 | #define C_0288A8_ITEMSIZE 0xFFFF8000 |
||
1697 | #define R_008C44_SQ_ESGS_RING_SIZE 0x008C44 |
||
1698 | #define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
1699 | #define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
1700 | #define C_008C44_MEM_SIZE 0x00000000 |
||
1701 | #define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0 |
||
1702 | #define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
1703 | #define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
1704 | #define C_0288B0_ITEMSIZE 0xFFFF8000 |
||
1705 | #define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54 |
||
1706 | #define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
1707 | #define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
1708 | #define C_008C54_MEM_SIZE 0x00000000 |
||
1709 | #define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0 |
||
1710 | #define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
1711 | #define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
1712 | #define C_0288C0_ITEMSIZE 0xFFFF8000 |
||
1713 | #define R_008C74_SQ_FBUF_RING_SIZE 0x008C74 |
||
1714 | #define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
1715 | #define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
1716 | #define C_008C74_MEM_SIZE 0x00000000 |
||
1717 | #define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4 |
||
1718 | #define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
1719 | #define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
1720 | #define C_0288B4_ITEMSIZE 0xFFFF8000 |
||
1721 | #define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C |
||
1722 | #define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
1723 | #define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
1724 | #define C_008C5C_MEM_SIZE 0x00000000 |
||
1725 | #define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC |
||
1726 | #define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
1727 | #define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
1728 | #define C_0288AC_ITEMSIZE 0xFFFF8000 |
||
1729 | #define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C |
||
1730 | #define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
1731 | #define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
1732 | #define C_008C4C_MEM_SIZE 0x00000000 |
||
1733 | #define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC |
||
1734 | #define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
1735 | #define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
1736 | #define C_0288BC_ITEMSIZE 0xFFFF8000 |
||
1737 | #define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C |
||
1738 | #define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
1739 | #define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
1740 | #define C_008C6C_MEM_SIZE 0x00000000 |
||
1741 | #define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4 |
||
1742 | #define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
1743 | #define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
1744 | #define C_0288C4_ITEMSIZE 0xFFFF8000 |
||
1745 | #define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C |
||
1746 | #define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
1747 | #define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
1748 | #define C_008C7C_MEM_SIZE 0x00000000 |
||
1749 | #define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8 |
||
1750 | #define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
1751 | #define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
1752 | #define C_0288B8_ITEMSIZE 0xFFFF8000 |
||
1753 | #define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64 |
||
1754 | #define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
1755 | #define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
1756 | #define C_008C64_MEM_SIZE 0x00000000 |
||
1757 | #define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 |
||
1758 | #define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
1759 | #define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
1760 | #define C_0288C8_ITEMSIZE 0xFFFF8000 |
||
1761 | #define R_028010_DB_DEPTH_INFO 0x028010 |
||
1762 | #define S_028010_FORMAT(x) (((x) & 0x7) << 0) |
||
1763 | #define G_028010_FORMAT(x) (((x) >> 0) & 0x7) |
||
1764 | #define C_028010_FORMAT 0xFFFFFFF8 |
||
1765 | #define V_028010_DEPTH_INVALID 0x00000000 |
||
1766 | #define V_028010_DEPTH_16 0x00000001 |
||
1767 | #define V_028010_DEPTH_X8_24 0x00000002 |
||
1768 | #define V_028010_DEPTH_8_24 0x00000003 |
||
1769 | #define V_028010_DEPTH_X8_24_FLOAT 0x00000004 |
||
1770 | #define V_028010_DEPTH_8_24_FLOAT 0x00000005 |
||
1771 | #define V_028010_DEPTH_32_FLOAT 0x00000006 |
||
1772 | #define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 |
||
1773 | #define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) |
||
1774 | #define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) |
||
1775 | #define C_028010_READ_SIZE 0xFFFFFFF7 |
||
1776 | #define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) |
||
1777 | #define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) |
||
1778 | #define C_028010_ARRAY_MODE 0xFFF87FFF |
||
1963 | serge | 1779 | #define V_028010_ARRAY_1D_TILED_THIN1 0x00000002 |
1780 | #define V_028010_ARRAY_2D_TILED_THIN1 0x00000004 |
||
1430 | serge | 1781 | #define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) |
1782 | #define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) |
||
1783 | #define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF |
||
1784 | #define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) |
||
1785 | #define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) |
||
1786 | #define C_028010_TILE_COMPACT 0xFBFFFFFF |
||
1787 | #define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) |
||
1788 | #define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) |
||
1789 | #define C_028010_ZRANGE_PRECISION 0x7FFFFFFF |
||
1790 | #define R_028000_DB_DEPTH_SIZE 0x028000 |
||
1791 | #define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) |
||
1792 | #define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) |
||
1793 | #define C_028000_PITCH_TILE_MAX 0xFFFFFC00 |
||
1794 | #define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) |
||
1795 | #define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) |
||
1796 | #define C_028000_SLICE_TILE_MAX 0xC00003FF |
||
1797 | #define R_028004_DB_DEPTH_VIEW 0x028004 |
||
1798 | #define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) |
||
1799 | #define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) |
||
1800 | #define C_028004_SLICE_START 0xFFFFF800 |
||
1801 | #define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) |
||
1802 | #define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) |
||
1803 | #define C_028004_SLICE_MAX 0xFF001FFF |
||
1804 | #define R_028800_DB_DEPTH_CONTROL 0x028800 |
||
1805 | #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) |
||
1806 | #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) |
||
1807 | #define C_028800_STENCIL_ENABLE 0xFFFFFFFE |
||
1808 | #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) |
||
1809 | #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) |
||
1810 | #define C_028800_Z_ENABLE 0xFFFFFFFD |
||
1811 | #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) |
||
1812 | #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) |
||
1813 | #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB |
||
1814 | #define S_028800_ZFUNC(x) (((x) & 0x7) << 4) |
||
1815 | #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) |
||
1816 | #define C_028800_ZFUNC 0xFFFFFF8F |
||
1817 | #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) |
||
1818 | #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) |
||
1819 | #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F |
||
1820 | #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) |
||
1821 | #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) |
||
1822 | #define C_028800_STENCILFUNC 0xFFFFF8FF |
||
1823 | #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) |
||
1824 | #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) |
||
1825 | #define C_028800_STENCILFAIL 0xFFFFC7FF |
||
1826 | #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) |
||
1827 | #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) |
||
1828 | #define C_028800_STENCILZPASS 0xFFFE3FFF |
||
1829 | #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) |
||
1830 | #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) |
||
1831 | #define C_028800_STENCILZFAIL 0xFFF1FFFF |
||
1832 | #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) |
||
1833 | #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) |
||
1834 | #define C_028800_STENCILFUNC_BF 0xFF8FFFFF |
||
1835 | #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) |
||
1836 | #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) |
||
1837 | #define C_028800_STENCILFAIL_BF 0xFC7FFFFF |
||
1838 | #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) |
||
1839 | #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) |
||
1840 | #define C_028800_STENCILZPASS_BF 0xE3FFFFFF |
||
1841 | #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) |
||
1842 | #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) |
||
1843 | #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF |
||
1403 | serge | 1844 | |
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