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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1221 | serge | 1 | /* |
| 2 | * Copyright 2009 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2009 Red Hat Inc. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the "Software"), |
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| 7 | * to deal in the Software without restriction, including without limitation |
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 10 | * Software is furnished to do so, subject to the following conditions: |
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| 11 | * |
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| 12 | * The above copyright notice and this permission notice shall be included in |
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| 13 | * all copies or substantial portions of the Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | * |
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| 23 | * Authors: Dave Airlie |
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| 24 | * Alex Deucher |
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| 25 | * Jerome Glisse |
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| 26 | */ |
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| 27 | #ifndef R600D_H |
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| 28 | #define R600D_H |
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| 29 | |||
| 30 | #define CP_PACKET2 0x80000000 |
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| 31 | #define PACKET2_PAD_SHIFT 0 |
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| 32 | #define PACKET2_PAD_MASK (0x3fffffff << 0) |
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| 33 | |||
| 34 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) |
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| 35 | |||
| 36 | #define R6XX_MAX_SH_GPRS 256 |
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| 37 | #define R6XX_MAX_TEMP_GPRS 16 |
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| 38 | #define R6XX_MAX_SH_THREADS 256 |
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| 39 | #define R6XX_MAX_SH_STACK_ENTRIES 4096 |
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| 40 | #define R6XX_MAX_BACKENDS 8 |
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| 41 | #define R6XX_MAX_BACKENDS_MASK 0xff |
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| 42 | #define R6XX_MAX_SIMDS 8 |
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| 43 | #define R6XX_MAX_SIMDS_MASK 0xff |
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| 44 | #define R6XX_MAX_PIPES 8 |
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| 45 | #define R6XX_MAX_PIPES_MASK 0xff |
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| 46 | |||
| 47 | /* PTE flags */ |
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| 48 | #define PTE_VALID (1 << 0) |
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| 49 | #define PTE_SYSTEM (1 << 1) |
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| 50 | #define PTE_SNOOPED (1 << 2) |
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| 51 | #define PTE_READABLE (1 << 5) |
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| 52 | #define PTE_WRITEABLE (1 << 6) |
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| 53 | |||
| 1963 | serge | 54 | /* tiling bits */ |
| 55 | #define ARRAY_LINEAR_GENERAL 0x00000000 |
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| 56 | #define ARRAY_LINEAR_ALIGNED 0x00000001 |
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| 57 | #define ARRAY_1D_TILED_THIN1 0x00000002 |
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| 58 | #define ARRAY_2D_TILED_THIN1 0x00000004 |
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| 59 | |||
| 1221 | serge | 60 | /* Registers */ |
| 61 | #define ARB_POP 0x2418 |
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| 62 | #define ENABLE_TC128 (1 << 30) |
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| 63 | #define ARB_GDEC_RD_CNTL 0x246C |
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| 64 | |||
| 65 | #define CC_GC_SHADER_PIPE_CONFIG 0x8950 |
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| 66 | #define CC_RB_BACKEND_DISABLE 0x98F4 |
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| 67 | #define BACKEND_DISABLE(x) ((x) << 16) |
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| 68 | |||
| 69 | #define CB_COLOR0_BASE 0x28040 |
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| 70 | #define CB_COLOR1_BASE 0x28044 |
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| 71 | #define CB_COLOR2_BASE 0x28048 |
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| 72 | #define CB_COLOR3_BASE 0x2804C |
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| 73 | #define CB_COLOR4_BASE 0x28050 |
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| 74 | #define CB_COLOR5_BASE 0x28054 |
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| 75 | #define CB_COLOR6_BASE 0x28058 |
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| 76 | #define CB_COLOR7_BASE 0x2805C |
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| 77 | #define CB_COLOR7_FRAG 0x280FC |
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| 78 | |||
| 79 | #define CB_COLOR0_SIZE 0x28060 |
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| 80 | #define CB_COLOR0_VIEW 0x28080 |
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| 81 | #define CB_COLOR0_INFO 0x280a0 |
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| 82 | #define CB_COLOR0_TILE 0x280c0 |
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| 83 | #define CB_COLOR0_FRAG 0x280e0 |
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| 84 | #define CB_COLOR0_MASK 0x28100 |
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| 85 | |||
| 1963 | serge | 86 | #define SQ_ALU_CONST_CACHE_PS_0 0x28940 |
| 87 | #define SQ_ALU_CONST_CACHE_PS_1 0x28944 |
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| 88 | #define SQ_ALU_CONST_CACHE_PS_2 0x28948 |
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| 89 | #define SQ_ALU_CONST_CACHE_PS_3 0x2894c |
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| 90 | #define SQ_ALU_CONST_CACHE_PS_4 0x28950 |
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| 91 | #define SQ_ALU_CONST_CACHE_PS_5 0x28954 |
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| 92 | #define SQ_ALU_CONST_CACHE_PS_6 0x28958 |
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| 93 | #define SQ_ALU_CONST_CACHE_PS_7 0x2895c |
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| 94 | #define SQ_ALU_CONST_CACHE_PS_8 0x28960 |
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| 95 | #define SQ_ALU_CONST_CACHE_PS_9 0x28964 |
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| 96 | #define SQ_ALU_CONST_CACHE_PS_10 0x28968 |
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| 97 | #define SQ_ALU_CONST_CACHE_PS_11 0x2896c |
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| 98 | #define SQ_ALU_CONST_CACHE_PS_12 0x28970 |
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| 99 | #define SQ_ALU_CONST_CACHE_PS_13 0x28974 |
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| 100 | #define SQ_ALU_CONST_CACHE_PS_14 0x28978 |
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| 101 | #define SQ_ALU_CONST_CACHE_PS_15 0x2897c |
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| 102 | #define SQ_ALU_CONST_CACHE_VS_0 0x28980 |
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| 103 | #define SQ_ALU_CONST_CACHE_VS_1 0x28984 |
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| 104 | #define SQ_ALU_CONST_CACHE_VS_2 0x28988 |
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| 105 | #define SQ_ALU_CONST_CACHE_VS_3 0x2898c |
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| 106 | #define SQ_ALU_CONST_CACHE_VS_4 0x28990 |
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| 107 | #define SQ_ALU_CONST_CACHE_VS_5 0x28994 |
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| 108 | #define SQ_ALU_CONST_CACHE_VS_6 0x28998 |
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| 109 | #define SQ_ALU_CONST_CACHE_VS_7 0x2899c |
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| 110 | #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 |
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| 111 | #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 |
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| 112 | #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 |
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| 113 | #define SQ_ALU_CONST_CACHE_VS_11 0x289ac |
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| 114 | #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 |
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| 115 | #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 |
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| 116 | #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 |
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| 117 | #define SQ_ALU_CONST_CACHE_VS_15 0x289bc |
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| 118 | #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 |
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| 119 | #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 |
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| 120 | #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 |
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| 121 | #define SQ_ALU_CONST_CACHE_GS_3 0x289cc |
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| 122 | #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 |
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| 123 | #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 |
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| 124 | #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 |
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| 125 | #define SQ_ALU_CONST_CACHE_GS_7 0x289dc |
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| 126 | #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 |
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| 127 | #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 |
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| 128 | #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 |
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| 129 | #define SQ_ALU_CONST_CACHE_GS_11 0x289ec |
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| 130 | #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 |
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| 131 | #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 |
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| 132 | #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 |
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| 133 | #define SQ_ALU_CONST_CACHE_GS_15 0x289fc |
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| 134 | |||
| 1221 | serge | 135 | #define CONFIG_MEMSIZE 0x5428 |
| 136 | #define CONFIG_CNTL 0x5424 |
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| 137 | #define CP_STAT 0x8680 |
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| 138 | #define CP_COHER_BASE 0x85F8 |
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| 139 | #define CP_DEBUG 0xC1FC |
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| 140 | #define R_0086D8_CP_ME_CNTL 0x86D8 |
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| 141 | #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) |
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| 142 | #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) |
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| 143 | #define CP_ME_RAM_DATA 0xC160 |
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| 144 | #define CP_ME_RAM_RADDR 0xC158 |
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| 145 | #define CP_ME_RAM_WADDR 0xC15C |
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| 146 | #define CP_MEQ_THRESHOLDS 0x8764 |
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| 147 | #define MEQ_END(x) ((x) << 16) |
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| 148 | #define ROQ_END(x) ((x) << 24) |
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| 149 | #define CP_PERFMON_CNTL 0x87FC |
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| 150 | #define CP_PFP_UCODE_ADDR 0xC150 |
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| 151 | #define CP_PFP_UCODE_DATA 0xC154 |
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| 152 | #define CP_QUEUE_THRESHOLDS 0x8760 |
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| 153 | #define ROQ_IB1_START(x) ((x) << 0) |
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| 154 | #define ROQ_IB2_START(x) ((x) << 8) |
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| 155 | #define CP_RB_BASE 0xC100 |
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| 156 | #define CP_RB_CNTL 0xC104 |
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| 1963 | serge | 157 | #define RB_BUFSZ(x) ((x) << 0) |
| 158 | #define RB_BLKSZ(x) ((x) << 8) |
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| 159 | #define RB_NO_UPDATE (1 << 27) |
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| 160 | #define RB_RPTR_WR_ENA (1 << 31) |
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| 1221 | serge | 161 | #define BUF_SWAP_32BIT (2 << 16) |
| 162 | #define CP_RB_RPTR 0x8700 |
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| 163 | #define CP_RB_RPTR_ADDR 0xC10C |
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| 1963 | serge | 164 | #define RB_RPTR_SWAP(x) ((x) << 0) |
| 1221 | serge | 165 | #define CP_RB_RPTR_ADDR_HI 0xC110 |
| 166 | #define CP_RB_RPTR_WR 0xC108 |
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| 167 | #define CP_RB_WPTR 0xC114 |
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| 168 | #define CP_RB_WPTR_ADDR 0xC118 |
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| 169 | #define CP_RB_WPTR_ADDR_HI 0xC11C |
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| 170 | #define CP_RB_WPTR_DELAY 0x8704 |
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| 171 | #define CP_ROQ_IB1_STAT 0x8784 |
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| 172 | #define CP_ROQ_IB2_STAT 0x8788 |
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| 173 | #define CP_SEM_WAIT_TIMER 0x85BC |
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| 174 | |||
| 175 | #define DB_DEBUG 0x9830 |
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| 176 | #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) |
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| 177 | #define DB_DEPTH_BASE 0x2800C |
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| 1268 | serge | 178 | #define DB_HTILE_DATA_BASE 0x28014 |
| 1221 | serge | 179 | #define DB_WATERMARKS 0x9838 |
| 180 | #define DEPTH_FREE(x) ((x) << 0) |
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| 181 | #define DEPTH_FLUSH(x) ((x) << 5) |
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| 182 | #define DEPTH_PENDING_FREE(x) ((x) << 15) |
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| 183 | #define DEPTH_CACHELINE_FREE(x) ((x) << 20) |
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| 184 | |||
| 185 | #define DCP_TILING_CONFIG 0x6CA0 |
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| 186 | #define PIPE_TILING(x) ((x) << 1) |
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| 187 | #define BANK_TILING(x) ((x) << 4) |
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| 188 | #define GROUP_SIZE(x) ((x) << 6) |
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| 189 | #define ROW_TILING(x) ((x) << 8) |
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| 190 | #define BANK_SWAPS(x) ((x) << 11) |
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| 191 | #define SAMPLE_SPLIT(x) ((x) << 14) |
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| 192 | #define BACKEND_MAP(x) ((x) << 16) |
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| 193 | |||
| 194 | #define GB_TILING_CONFIG 0x98F0 |
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| 195 | |||
| 196 | #define GC_USER_SHADER_PIPE_CONFIG 0x8954 |
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| 197 | #define INACTIVE_QD_PIPES(x) ((x) << 8) |
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| 198 | #define INACTIVE_QD_PIPES_MASK 0x0000FF00 |
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| 199 | #define INACTIVE_SIMDS(x) ((x) << 16) |
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| 200 | #define INACTIVE_SIMDS_MASK 0x00FF0000 |
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| 201 | |||
| 202 | #define SQ_CONFIG 0x8c00 |
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| 203 | # define VC_ENABLE (1 << 0) |
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| 204 | # define EXPORT_SRC_C (1 << 1) |
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| 205 | # define DX9_CONSTS (1 << 2) |
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| 206 | # define ALU_INST_PREFER_VECTOR (1 << 3) |
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| 207 | # define DX10_CLAMP (1 << 4) |
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| 208 | # define CLAUSE_SEQ_PRIO(x) ((x) << 8) |
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| 209 | # define PS_PRIO(x) ((x) << 24) |
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| 210 | # define VS_PRIO(x) ((x) << 26) |
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| 211 | # define GS_PRIO(x) ((x) << 28) |
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| 212 | # define ES_PRIO(x) ((x) << 30) |
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| 213 | #define SQ_GPR_RESOURCE_MGMT_1 0x8c04 |
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| 214 | # define NUM_PS_GPRS(x) ((x) << 0) |
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| 215 | # define NUM_VS_GPRS(x) ((x) << 16) |
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| 216 | # define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) |
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| 217 | #define SQ_GPR_RESOURCE_MGMT_2 0x8c08 |
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| 218 | # define NUM_GS_GPRS(x) ((x) << 0) |
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| 219 | # define NUM_ES_GPRS(x) ((x) << 16) |
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| 220 | #define SQ_THREAD_RESOURCE_MGMT 0x8c0c |
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| 221 | # define NUM_PS_THREADS(x) ((x) << 0) |
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| 222 | # define NUM_VS_THREADS(x) ((x) << 8) |
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| 223 | # define NUM_GS_THREADS(x) ((x) << 16) |
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| 224 | # define NUM_ES_THREADS(x) ((x) << 24) |
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| 225 | #define SQ_STACK_RESOURCE_MGMT_1 0x8c10 |
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| 226 | # define NUM_PS_STACK_ENTRIES(x) ((x) << 0) |
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| 227 | # define NUM_VS_STACK_ENTRIES(x) ((x) << 16) |
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| 228 | #define SQ_STACK_RESOURCE_MGMT_2 0x8c14 |
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| 229 | # define NUM_GS_STACK_ENTRIES(x) ((x) << 0) |
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| 230 | # define NUM_ES_STACK_ENTRIES(x) ((x) << 16) |
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| 1268 | serge | 231 | #define SQ_ESGS_RING_BASE 0x8c40 |
| 232 | #define SQ_GSVS_RING_BASE 0x8c48 |
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| 233 | #define SQ_ESTMP_RING_BASE 0x8c50 |
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| 234 | #define SQ_GSTMP_RING_BASE 0x8c58 |
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| 235 | #define SQ_VSTMP_RING_BASE 0x8c60 |
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| 236 | #define SQ_PSTMP_RING_BASE 0x8c68 |
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| 237 | #define SQ_FBUF_RING_BASE 0x8c70 |
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| 238 | #define SQ_REDUC_RING_BASE 0x8c78 |
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| 1221 | serge | 239 | |
| 240 | #define GRBM_CNTL 0x8000 |
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| 241 | # define GRBM_READ_TIMEOUT(x) ((x) << 0) |
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| 242 | #define GRBM_STATUS 0x8010 |
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| 243 | #define CMDFIFO_AVAIL_MASK 0x0000001F |
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| 244 | #define GUI_ACTIVE (1<<31) |
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| 245 | #define GRBM_STATUS2 0x8014 |
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| 246 | #define GRBM_SOFT_RESET 0x8020 |
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| 247 | #define SOFT_RESET_CP (1<<0) |
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| 248 | |||
| 1963 | serge | 249 | #define CG_THERMAL_STATUS 0x7F4 |
| 250 | #define ASIC_T(x) ((x) << 0) |
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| 251 | #define ASIC_T_MASK 0x1FF |
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| 252 | #define ASIC_T_SHIFT 0 |
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| 253 | |||
| 1221 | serge | 254 | #define HDP_HOST_PATH_CNTL 0x2C00 |
| 255 | #define HDP_NONSURFACE_BASE 0x2C04 |
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| 256 | #define HDP_NONSURFACE_INFO 0x2C08 |
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| 257 | #define HDP_NONSURFACE_SIZE 0x2C0C |
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| 258 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
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| 259 | #define HDP_TILING_CONFIG 0x2F3C |
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| 1963 | serge | 260 | #define HDP_DEBUG1 0x2F34 |
| 1221 | serge | 261 | |
| 262 | #define MC_VM_AGP_TOP 0x2184 |
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| 263 | #define MC_VM_AGP_BOT 0x2188 |
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| 264 | #define MC_VM_AGP_BASE 0x218C |
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| 265 | #define MC_VM_FB_LOCATION 0x2180 |
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| 266 | #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C |
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| 267 | #define ENABLE_L1_TLB (1 << 0) |
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| 268 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) |
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| 269 | #define ENABLE_L1_STRICT_ORDERING (1 << 2) |
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| 270 | #define SYSTEM_ACCESS_MODE_MASK 0x000000C0 |
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| 271 | #define SYSTEM_ACCESS_MODE_SHIFT 6 |
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| 272 | #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) |
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| 273 | #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) |
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| 274 | #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) |
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| 275 | #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) |
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| 276 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) |
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| 277 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) |
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| 278 | #define ENABLE_SEMAPHORE_MODE (1 << 10) |
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| 279 | #define ENABLE_WAIT_L2_QUERY (1 << 11) |
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| 280 | #define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) |
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| 281 | #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 |
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| 282 | #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 |
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| 283 | #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) |
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| 284 | #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 |
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| 285 | #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 |
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| 286 | #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 |
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| 287 | #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC |
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| 288 | #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 |
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| 289 | #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 |
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| 290 | #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C |
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| 291 | #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 |
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| 292 | #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 |
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| 293 | #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 |
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| 294 | #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 |
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| 295 | #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 |
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| 296 | #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C |
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| 297 | #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 |
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| 298 | #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 |
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| 299 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 |
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| 300 | #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF |
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| 301 | #define LOGICAL_PAGE_NUMBER_SHIFT 0 |
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| 302 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 |
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| 303 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 |
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| 304 | |||
| 305 | #define PA_CL_ENHANCE 0x8A14 |
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| 306 | #define CLIP_VTX_REORDER_ENA (1 << 0) |
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| 307 | #define NUM_CLIP_SEQ(x) ((x) << 1) |
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| 308 | #define PA_SC_AA_CONFIG 0x28C04 |
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| 309 | #define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 |
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| 310 | #define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 |
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| 311 | #define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 |
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| 312 | #define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C |
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| 313 | #define S0_X(x) ((x) << 0) |
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| 314 | #define S0_Y(x) ((x) << 4) |
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| 315 | #define S1_X(x) ((x) << 8) |
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| 316 | #define S1_Y(x) ((x) << 12) |
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| 317 | #define S2_X(x) ((x) << 16) |
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| 318 | #define S2_Y(x) ((x) << 20) |
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| 319 | #define S3_X(x) ((x) << 24) |
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| 320 | #define S3_Y(x) ((x) << 28) |
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| 321 | #define S4_X(x) ((x) << 0) |
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| 322 | #define S4_Y(x) ((x) << 4) |
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| 323 | #define S5_X(x) ((x) << 8) |
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| 324 | #define S5_Y(x) ((x) << 12) |
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| 325 | #define S6_X(x) ((x) << 16) |
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| 326 | #define S6_Y(x) ((x) << 20) |
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| 327 | #define S7_X(x) ((x) << 24) |
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| 328 | #define S7_Y(x) ((x) << 28) |
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| 329 | #define PA_SC_CLIPRECT_RULE 0x2820c |
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| 330 | #define PA_SC_ENHANCE 0x8BF0 |
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| 331 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) |
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| 332 | #define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) |
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| 333 | #define PA_SC_LINE_STIPPLE 0x28A0C |
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| 334 | #define PA_SC_LINE_STIPPLE_STATE 0x8B10 |
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| 335 | #define PA_SC_MODE_CNTL 0x28A4C |
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| 336 | #define PA_SC_MULTI_CHIP_CNTL 0x8B20 |
||
| 337 | |||
| 338 | #define PA_SC_SCREEN_SCISSOR_TL 0x28030 |
||
| 339 | #define PA_SC_GENERIC_SCISSOR_TL 0x28240 |
||
| 340 | #define PA_SC_WINDOW_SCISSOR_TL 0x28204 |
||
| 341 | |||
| 342 | #define PCIE_PORT_INDEX 0x0038 |
||
| 343 | #define PCIE_PORT_DATA 0x003C |
||
| 344 | |||
| 1268 | serge | 345 | #define CHMAP 0x2004 |
| 346 | #define NOOFCHAN_SHIFT 12 |
||
| 347 | #define NOOFCHAN_MASK 0x00003000 |
||
| 348 | |||
| 1221 | serge | 349 | #define RAMCFG 0x2408 |
| 350 | #define NOOFBANK_SHIFT 0 |
||
| 351 | #define NOOFBANK_MASK 0x00000001 |
||
| 352 | #define NOOFRANK_SHIFT 1 |
||
| 353 | #define NOOFRANK_MASK 0x00000002 |
||
| 354 | #define NOOFROWS_SHIFT 2 |
||
| 355 | #define NOOFROWS_MASK 0x0000001C |
||
| 356 | #define NOOFCOLS_SHIFT 5 |
||
| 357 | #define NOOFCOLS_MASK 0x00000060 |
||
| 358 | #define CHANSIZE_SHIFT 7 |
||
| 359 | #define CHANSIZE_MASK 0x00000080 |
||
| 360 | #define BURSTLENGTH_SHIFT 8 |
||
| 361 | #define BURSTLENGTH_MASK 0x00000100 |
||
| 362 | #define CHANSIZE_OVERRIDE (1 << 10) |
||
| 363 | |||
| 364 | #define SCRATCH_REG0 0x8500 |
||
| 365 | #define SCRATCH_REG1 0x8504 |
||
| 366 | #define SCRATCH_REG2 0x8508 |
||
| 367 | #define SCRATCH_REG3 0x850C |
||
| 368 | #define SCRATCH_REG4 0x8510 |
||
| 369 | #define SCRATCH_REG5 0x8514 |
||
| 370 | #define SCRATCH_REG6 0x8518 |
||
| 371 | #define SCRATCH_REG7 0x851C |
||
| 372 | #define SCRATCH_UMSK 0x8540 |
||
| 373 | #define SCRATCH_ADDR 0x8544 |
||
| 374 | |||
| 375 | #define SPI_CONFIG_CNTL 0x9100 |
||
| 376 | #define GPR_WRITE_PRIORITY(x) ((x) << 0) |
||
| 377 | #define DISABLE_INTERP_1 (1 << 5) |
||
| 378 | #define SPI_CONFIG_CNTL_1 0x913C |
||
| 379 | #define VTX_DONE_DELAY(x) ((x) << 0) |
||
| 380 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) |
||
| 381 | #define SPI_INPUT_Z 0x286D8 |
||
| 382 | #define SPI_PS_IN_CONTROL_0 0x286CC |
||
| 383 | #define NUM_INTERP(x) ((x)<<0) |
||
| 384 | #define POSITION_ENA (1<<8) |
||
| 385 | #define POSITION_CENTROID (1<<9) |
||
| 386 | #define POSITION_ADDR(x) ((x)<<10) |
||
| 387 | #define PARAM_GEN(x) ((x)<<15) |
||
| 388 | #define PARAM_GEN_ADDR(x) ((x)<<19) |
||
| 389 | #define BARYC_SAMPLE_CNTL(x) ((x)<<26) |
||
| 390 | #define PERSP_GRADIENT_ENA (1<<28) |
||
| 391 | #define LINEAR_GRADIENT_ENA (1<<29) |
||
| 392 | #define POSITION_SAMPLE (1<<30) |
||
| 393 | #define BARYC_AT_SAMPLE_ENA (1<<31) |
||
| 394 | #define SPI_PS_IN_CONTROL_1 0x286D0 |
||
| 395 | #define GEN_INDEX_PIX (1<<0) |
||
| 396 | #define GEN_INDEX_PIX_ADDR(x) ((x)<<1) |
||
| 397 | #define FRONT_FACE_ENA (1<<8) |
||
| 398 | #define FRONT_FACE_CHAN(x) ((x)<<9) |
||
| 399 | #define FRONT_FACE_ALL_BITS (1<<11) |
||
| 400 | #define FRONT_FACE_ADDR(x) ((x)<<12) |
||
| 401 | #define FOG_ADDR(x) ((x)<<17) |
||
| 402 | #define FIXED_PT_POSITION_ENA (1<<24) |
||
| 403 | #define FIXED_PT_POSITION_ADDR(x) ((x)<<25) |
||
| 404 | |||
| 405 | #define SQ_MS_FIFO_SIZES 0x8CF0 |
||
| 406 | #define CACHE_FIFO_SIZE(x) ((x) << 0) |
||
| 407 | #define FETCH_FIFO_HIWATER(x) ((x) << 8) |
||
| 408 | #define DONE_FIFO_HIWATER(x) ((x) << 16) |
||
| 409 | #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) |
||
| 410 | #define SQ_PGM_START_ES 0x28880 |
||
| 411 | #define SQ_PGM_START_FS 0x28894 |
||
| 412 | #define SQ_PGM_START_GS 0x2886C |
||
| 413 | #define SQ_PGM_START_PS 0x28840 |
||
| 414 | #define SQ_PGM_RESOURCES_PS 0x28850 |
||
| 415 | #define SQ_PGM_EXPORTS_PS 0x28854 |
||
| 416 | #define SQ_PGM_CF_OFFSET_PS 0x288cc |
||
| 417 | #define SQ_PGM_START_VS 0x28858 |
||
| 418 | #define SQ_PGM_RESOURCES_VS 0x28868 |
||
| 419 | #define SQ_PGM_CF_OFFSET_VS 0x288d0 |
||
| 420 | #define SQ_VTX_CONSTANT_WORD6_0 0x38018 |
||
| 421 | #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) |
||
| 422 | #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) |
||
| 423 | #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 |
||
| 424 | #define SQ_TEX_VTX_INVALID_BUFFER 0x1 |
||
| 425 | #define SQ_TEX_VTX_VALID_TEXTURE 0x2 |
||
| 426 | #define SQ_TEX_VTX_VALID_BUFFER 0x3 |
||
| 427 | |||
| 428 | |||
| 429 | #define SX_MISC 0x28350 |
||
| 1268 | serge | 430 | #define SX_MEMORY_EXPORT_BASE 0x9010 |
| 1221 | serge | 431 | #define SX_DEBUG_1 0x9054 |
| 432 | #define SMX_EVENT_RELEASE (1 << 0) |
||
| 433 | #define ENABLE_NEW_SMX_ADDRESS (1 << 16) |
||
| 434 | |||
| 435 | #define TA_CNTL_AUX 0x9508 |
||
| 436 | #define DISABLE_CUBE_WRAP (1 << 0) |
||
| 437 | #define DISABLE_CUBE_ANISO (1 << 1) |
||
| 438 | #define SYNC_GRADIENT (1 << 24) |
||
| 439 | #define SYNC_WALKER (1 << 25) |
||
| 440 | #define SYNC_ALIGNER (1 << 26) |
||
| 441 | #define BILINEAR_PRECISION_6_BIT (0 << 31) |
||
| 442 | #define BILINEAR_PRECISION_8_BIT (1 << 31) |
||
| 443 | |||
| 444 | #define TC_CNTL 0x9608 |
||
| 445 | #define TC_L2_SIZE(x) ((x)<<5) |
||
| 446 | #define L2_DISABLE_LATE_HIT (1<<9) |
||
| 447 | |||
| 448 | |||
| 449 | #define VGT_CACHE_INVALIDATION 0x88C4 |
||
| 450 | #define CACHE_INVALIDATION(x) ((x)<<0) |
||
| 451 | #define VC_ONLY 0 |
||
| 452 | #define TC_ONLY 1 |
||
| 453 | #define VC_AND_TC 2 |
||
| 454 | #define VGT_DMA_BASE 0x287E8 |
||
| 455 | #define VGT_DMA_BASE_HI 0x287E4 |
||
| 456 | #define VGT_ES_PER_GS 0x88CC |
||
| 457 | #define VGT_GS_PER_ES 0x88C8 |
||
| 458 | #define VGT_GS_PER_VS 0x88E8 |
||
| 459 | #define VGT_GS_VERTEX_REUSE 0x88D4 |
||
| 460 | #define VGT_PRIMITIVE_TYPE 0x8958 |
||
| 461 | #define VGT_NUM_INSTANCES 0x8974 |
||
| 462 | #define VGT_OUT_DEALLOC_CNTL 0x28C5C |
||
| 463 | #define DEALLOC_DIST_MASK 0x0000007F |
||
| 464 | #define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 |
||
| 465 | #define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 |
||
| 466 | #define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 |
||
| 467 | #define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c |
||
| 468 | #define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 |
||
| 469 | #define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 |
||
| 470 | #define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c |
||
| 471 | #define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 |
||
| 472 | #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 |
||
| 473 | #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 |
||
| 474 | #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 |
||
| 475 | #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 |
||
| 476 | #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC |
||
| 477 | #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC |
||
| 478 | #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC |
||
| 479 | #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C |
||
| 480 | #define VGT_STRMOUT_EN 0x28AB0 |
||
| 481 | #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 |
||
| 482 | #define VTX_REUSE_DEPTH_MASK 0x000000FF |
||
| 483 | #define VGT_EVENT_INITIATOR 0x28a90 |
||
| 1963 | serge | 484 | # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) |
| 1221 | serge | 485 | # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) |
| 486 | |||
| 487 | #define VM_CONTEXT0_CNTL 0x1410 |
||
| 488 | #define ENABLE_CONTEXT (1 << 0) |
||
| 489 | #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) |
||
| 490 | #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) |
||
| 491 | #define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 |
||
| 492 | #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 |
||
| 493 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 |
||
| 494 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 |
||
| 495 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 |
||
| 496 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 |
||
| 497 | #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 |
||
| 498 | #define REQUEST_TYPE(x) (((x) & 0xf) << 0) |
||
| 499 | #define RESPONSE_TYPE_MASK 0x000000F0 |
||
| 500 | #define RESPONSE_TYPE_SHIFT 4 |
||
| 501 | #define VM_L2_CNTL 0x1400 |
||
| 502 | #define ENABLE_L2_CACHE (1 << 0) |
||
| 503 | #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) |
||
| 504 | #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) |
||
| 505 | #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) |
||
| 506 | #define VM_L2_CNTL2 0x1404 |
||
| 507 | #define INVALIDATE_ALL_L1_TLBS (1 << 0) |
||
| 508 | #define INVALIDATE_L2_CACHE (1 << 1) |
||
| 509 | #define VM_L2_CNTL3 0x1408 |
||
| 510 | #define BANK_SELECT_0(x) (((x) & 0x1f) << 0) |
||
| 511 | #define BANK_SELECT_1(x) (((x) & 0x1f) << 5) |
||
| 512 | #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) |
||
| 513 | #define VM_L2_STATUS 0x140C |
||
| 514 | #define L2_BUSY (1 << 0) |
||
| 515 | |||
| 516 | #define WAIT_UNTIL 0x8040 |
||
| 517 | #define WAIT_2D_IDLE_bit (1 << 14) |
||
| 518 | #define WAIT_3D_IDLE_bit (1 << 15) |
||
| 519 | #define WAIT_2D_IDLECLEAN_bit (1 << 16) |
||
| 520 | #define WAIT_3D_IDLECLEAN_bit (1 << 17) |
||
| 521 | |||
| 1321 | serge | 522 | #define IH_RB_CNTL 0x3e00 |
| 523 | # define IH_RB_ENABLE (1 << 0) |
||
| 524 | # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ |
||
| 525 | # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) |
||
| 526 | # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) |
||
| 527 | # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ |
||
| 528 | # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) |
||
| 529 | # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) |
||
| 530 | #define IH_RB_BASE 0x3e04 |
||
| 531 | #define IH_RB_RPTR 0x3e08 |
||
| 532 | #define IH_RB_WPTR 0x3e0c |
||
| 533 | # define RB_OVERFLOW (1 << 0) |
||
| 534 | # define WPTR_OFFSET_MASK 0x3fffc |
||
| 535 | #define IH_RB_WPTR_ADDR_HI 0x3e10 |
||
| 536 | #define IH_RB_WPTR_ADDR_LO 0x3e14 |
||
| 537 | #define IH_CNTL 0x3e18 |
||
| 538 | # define ENABLE_INTR (1 << 0) |
||
| 539 | # define IH_MC_SWAP(x) ((x) << 2) |
||
| 540 | # define IH_MC_SWAP_NONE 0 |
||
| 541 | # define IH_MC_SWAP_16BIT 1 |
||
| 542 | # define IH_MC_SWAP_32BIT 2 |
||
| 543 | # define IH_MC_SWAP_64BIT 3 |
||
| 544 | # define RPTR_REARM (1 << 4) |
||
| 545 | # define MC_WRREQ_CREDIT(x) ((x) << 15) |
||
| 546 | # define MC_WR_CLEAN_CNT(x) ((x) << 20) |
||
| 1221 | serge | 547 | |
| 1321 | serge | 548 | #define RLC_CNTL 0x3f00 |
| 549 | # define RLC_ENABLE (1 << 0) |
||
| 550 | #define RLC_HB_BASE 0x3f10 |
||
| 551 | #define RLC_HB_CNTL 0x3f0c |
||
| 552 | #define RLC_HB_RPTR 0x3f20 |
||
| 553 | #define RLC_HB_WPTR 0x3f1c |
||
| 554 | #define RLC_HB_WPTR_LSB_ADDR 0x3f14 |
||
| 555 | #define RLC_HB_WPTR_MSB_ADDR 0x3f18 |
||
| 556 | #define RLC_MC_CNTL 0x3f44 |
||
| 557 | #define RLC_UCODE_CNTL 0x3f48 |
||
| 558 | #define RLC_UCODE_ADDR 0x3f2c |
||
| 559 | #define RLC_UCODE_DATA 0x3f30 |
||
| 1221 | serge | 560 | |
| 1321 | serge | 561 | #define SRBM_SOFT_RESET 0xe60 |
| 562 | # define SOFT_RESET_RLC (1 << 13) |
||
| 563 | |||
| 564 | #define CP_INT_CNTL 0xc124 |
||
| 565 | # define CNTX_BUSY_INT_ENABLE (1 << 19) |
||
| 566 | # define CNTX_EMPTY_INT_ENABLE (1 << 20) |
||
| 567 | # define SCRATCH_INT_ENABLE (1 << 25) |
||
| 568 | # define TIME_STAMP_INT_ENABLE (1 << 26) |
||
| 569 | # define IB2_INT_ENABLE (1 << 29) |
||
| 570 | # define IB1_INT_ENABLE (1 << 30) |
||
| 571 | # define RB_INT_ENABLE (1 << 31) |
||
| 572 | #define CP_INT_STATUS 0xc128 |
||
| 573 | # define SCRATCH_INT_STAT (1 << 25) |
||
| 574 | # define TIME_STAMP_INT_STAT (1 << 26) |
||
| 575 | # define IB2_INT_STAT (1 << 29) |
||
| 576 | # define IB1_INT_STAT (1 << 30) |
||
| 577 | # define RB_INT_STAT (1 << 31) |
||
| 578 | |||
| 579 | #define GRBM_INT_CNTL 0x8060 |
||
| 580 | # define RDERR_INT_ENABLE (1 << 0) |
||
| 581 | # define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1) |
||
| 582 | # define GUI_IDLE_INT_ENABLE (1 << 19) |
||
| 583 | |||
| 584 | #define INTERRUPT_CNTL 0x5468 |
||
| 585 | # define IH_DUMMY_RD_OVERRIDE (1 << 0) |
||
| 586 | # define IH_DUMMY_RD_EN (1 << 1) |
||
| 587 | # define IH_REQ_NONSNOOP_EN (1 << 3) |
||
| 588 | # define GEN_IH_INT_EN (1 << 8) |
||
| 589 | #define INTERRUPT_CNTL2 0x546c |
||
| 590 | |||
| 591 | #define D1MODE_VBLANK_STATUS 0x6534 |
||
| 592 | #define D2MODE_VBLANK_STATUS 0x6d34 |
||
| 593 | # define DxMODE_VBLANK_OCCURRED (1 << 0) |
||
| 594 | # define DxMODE_VBLANK_ACK (1 << 4) |
||
| 595 | # define DxMODE_VBLANK_STAT (1 << 12) |
||
| 596 | # define DxMODE_VBLANK_INTERRUPT (1 << 16) |
||
| 597 | # define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17) |
||
| 598 | #define D1MODE_VLINE_STATUS 0x653c |
||
| 599 | #define D2MODE_VLINE_STATUS 0x6d3c |
||
| 600 | # define DxMODE_VLINE_OCCURRED (1 << 0) |
||
| 601 | # define DxMODE_VLINE_ACK (1 << 4) |
||
| 602 | # define DxMODE_VLINE_STAT (1 << 12) |
||
| 603 | # define DxMODE_VLINE_INTERRUPT (1 << 16) |
||
| 604 | # define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17) |
||
| 605 | #define DxMODE_INT_MASK 0x6540 |
||
| 606 | # define D1MODE_VBLANK_INT_MASK (1 << 0) |
||
| 607 | # define D1MODE_VLINE_INT_MASK (1 << 4) |
||
| 608 | # define D2MODE_VBLANK_INT_MASK (1 << 8) |
||
| 609 | # define D2MODE_VLINE_INT_MASK (1 << 12) |
||
| 610 | #define DCE3_DISP_INTERRUPT_STATUS 0x7ddc |
||
| 611 | # define DC_HPD1_INTERRUPT (1 << 18) |
||
| 612 | # define DC_HPD2_INTERRUPT (1 << 19) |
||
| 613 | #define DISP_INTERRUPT_STATUS 0x7edc |
||
| 614 | # define LB_D1_VLINE_INTERRUPT (1 << 2) |
||
| 615 | # define LB_D2_VLINE_INTERRUPT (1 << 3) |
||
| 616 | # define LB_D1_VBLANK_INTERRUPT (1 << 4) |
||
| 617 | # define LB_D2_VBLANK_INTERRUPT (1 << 5) |
||
| 618 | # define DACA_AUTODETECT_INTERRUPT (1 << 16) |
||
| 619 | # define DACB_AUTODETECT_INTERRUPT (1 << 17) |
||
| 620 | # define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18) |
||
| 621 | # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) |
||
| 622 | # define DC_I2C_SW_DONE_INTERRUPT (1 << 20) |
||
| 623 | # define DC_I2C_HW_DONE_INTERRUPT (1 << 21) |
||
| 624 | #define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8 |
||
| 625 | #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 |
||
| 626 | # define DC_HPD4_INTERRUPT (1 << 14) |
||
| 627 | # define DC_HPD4_RX_INTERRUPT (1 << 15) |
||
| 628 | # define DC_HPD3_INTERRUPT (1 << 28) |
||
| 629 | # define DC_HPD1_RX_INTERRUPT (1 << 29) |
||
| 630 | # define DC_HPD2_RX_INTERRUPT (1 << 30) |
||
| 631 | #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec |
||
| 632 | # define DC_HPD3_RX_INTERRUPT (1 << 0) |
||
| 633 | # define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1) |
||
| 634 | # define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2) |
||
| 635 | # define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3) |
||
| 636 | # define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4) |
||
| 637 | # define AUX1_SW_DONE_INTERRUPT (1 << 5) |
||
| 638 | # define AUX1_LS_DONE_INTERRUPT (1 << 6) |
||
| 639 | # define AUX2_SW_DONE_INTERRUPT (1 << 7) |
||
| 640 | # define AUX2_LS_DONE_INTERRUPT (1 << 8) |
||
| 641 | # define AUX3_SW_DONE_INTERRUPT (1 << 9) |
||
| 642 | # define AUX3_LS_DONE_INTERRUPT (1 << 10) |
||
| 643 | # define AUX4_SW_DONE_INTERRUPT (1 << 11) |
||
| 644 | # define AUX4_LS_DONE_INTERRUPT (1 << 12) |
||
| 645 | # define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13) |
||
| 646 | # define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14) |
||
| 647 | /* DCE 3.2 */ |
||
| 648 | # define AUX5_SW_DONE_INTERRUPT (1 << 15) |
||
| 649 | # define AUX5_LS_DONE_INTERRUPT (1 << 16) |
||
| 650 | # define AUX6_SW_DONE_INTERRUPT (1 << 17) |
||
| 651 | # define AUX6_LS_DONE_INTERRUPT (1 << 18) |
||
| 652 | # define DC_HPD5_INTERRUPT (1 << 19) |
||
| 653 | # define DC_HPD5_RX_INTERRUPT (1 << 20) |
||
| 654 | # define DC_HPD6_INTERRUPT (1 << 21) |
||
| 655 | # define DC_HPD6_RX_INTERRUPT (1 << 22) |
||
| 656 | |||
| 657 | #define DACA_AUTO_DETECT_CONTROL 0x7828 |
||
| 658 | #define DACB_AUTO_DETECT_CONTROL 0x7a28 |
||
| 659 | #define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028 |
||
| 660 | #define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128 |
||
| 661 | # define DACx_AUTODETECT_MODE(x) ((x) << 0) |
||
| 662 | # define DACx_AUTODETECT_MODE_NONE 0 |
||
| 663 | # define DACx_AUTODETECT_MODE_CONNECT 1 |
||
| 664 | # define DACx_AUTODETECT_MODE_DISCONNECT 2 |
||
| 665 | # define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8) |
||
| 666 | /* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */ |
||
| 667 | # define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16) |
||
| 668 | |||
| 669 | #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 |
||
| 670 | #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 |
||
| 671 | #define DACA_AUTODETECT_INT_CONTROL 0x7838 |
||
| 672 | #define DACB_AUTODETECT_INT_CONTROL 0x7a38 |
||
| 673 | # define DACx_AUTODETECT_ACK (1 << 0) |
||
| 674 | # define DACx_AUTODETECT_INT_ENABLE (1 << 16) |
||
| 675 | |||
| 676 | #define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00 |
||
| 677 | #define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10 |
||
| 678 | #define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24 |
||
| 679 | # define DC_HOT_PLUG_DETECTx_EN (1 << 0) |
||
| 680 | |||
| 681 | #define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04 |
||
| 682 | #define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14 |
||
| 683 | #define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28 |
||
| 684 | # define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0) |
||
| 685 | # define DC_HOT_PLUG_DETECTx_SENSE (1 << 1) |
||
| 686 | |||
| 687 | /* DCE 3.0 */ |
||
| 688 | #define DC_HPD1_INT_STATUS 0x7d00 |
||
| 689 | #define DC_HPD2_INT_STATUS 0x7d0c |
||
| 690 | #define DC_HPD3_INT_STATUS 0x7d18 |
||
| 691 | #define DC_HPD4_INT_STATUS 0x7d24 |
||
| 692 | /* DCE 3.2 */ |
||
| 693 | #define DC_HPD5_INT_STATUS 0x7dc0 |
||
| 694 | #define DC_HPD6_INT_STATUS 0x7df4 |
||
| 695 | # define DC_HPDx_INT_STATUS (1 << 0) |
||
| 696 | # define DC_HPDx_SENSE (1 << 1) |
||
| 697 | # define DC_HPDx_RX_INT_STATUS (1 << 8) |
||
| 698 | |||
| 699 | #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 |
||
| 700 | #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 |
||
| 701 | #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c |
||
| 702 | # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) |
||
| 703 | # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) |
||
| 704 | # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) |
||
| 705 | /* DCE 3.0 */ |
||
| 706 | #define DC_HPD1_INT_CONTROL 0x7d04 |
||
| 707 | #define DC_HPD2_INT_CONTROL 0x7d10 |
||
| 708 | #define DC_HPD3_INT_CONTROL 0x7d1c |
||
| 709 | #define DC_HPD4_INT_CONTROL 0x7d28 |
||
| 710 | /* DCE 3.2 */ |
||
| 711 | #define DC_HPD5_INT_CONTROL 0x7dc4 |
||
| 712 | #define DC_HPD6_INT_CONTROL 0x7df8 |
||
| 713 | # define DC_HPDx_INT_ACK (1 << 0) |
||
| 714 | # define DC_HPDx_INT_POLARITY (1 << 8) |
||
| 715 | # define DC_HPDx_INT_EN (1 << 16) |
||
| 716 | # define DC_HPDx_RX_INT_ACK (1 << 20) |
||
| 717 | # define DC_HPDx_RX_INT_EN (1 << 24) |
||
| 718 | |||
| 719 | /* DCE 3.0 */ |
||
| 720 | #define DC_HPD1_CONTROL 0x7d08 |
||
| 721 | #define DC_HPD2_CONTROL 0x7d14 |
||
| 722 | #define DC_HPD3_CONTROL 0x7d20 |
||
| 723 | #define DC_HPD4_CONTROL 0x7d2c |
||
| 724 | /* DCE 3.2 */ |
||
| 725 | #define DC_HPD5_CONTROL 0x7dc8 |
||
| 726 | #define DC_HPD6_CONTROL 0x7dfc |
||
| 727 | # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) |
||
| 728 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) |
||
| 729 | /* DCE 3.2 */ |
||
| 730 | # define DC_HPDx_EN (1 << 28) |
||
| 731 | |||
| 1963 | serge | 732 | #define D1GRPH_INTERRUPT_STATUS 0x6158 |
| 733 | #define D2GRPH_INTERRUPT_STATUS 0x6958 |
||
| 734 | # define DxGRPH_PFLIP_INT_OCCURRED (1 << 0) |
||
| 735 | # define DxGRPH_PFLIP_INT_CLEAR (1 << 8) |
||
| 736 | #define D1GRPH_INTERRUPT_CONTROL 0x615c |
||
| 737 | #define D2GRPH_INTERRUPT_CONTROL 0x695c |
||
| 738 | # define DxGRPH_PFLIP_INT_MASK (1 << 0) |
||
| 739 | # define DxGRPH_PFLIP_INT_TYPE (1 << 8) |
||
| 740 | |||
| 741 | /* PCIE link stuff */ |
||
| 742 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ |
||
| 743 | # define LC_POINT_7_PLUS_EN (1 << 6) |
||
| 744 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ |
||
| 745 | # define LC_LINK_WIDTH_SHIFT 0 |
||
| 746 | # define LC_LINK_WIDTH_MASK 0x7 |
||
| 747 | # define LC_LINK_WIDTH_X0 0 |
||
| 748 | # define LC_LINK_WIDTH_X1 1 |
||
| 749 | # define LC_LINK_WIDTH_X2 2 |
||
| 750 | # define LC_LINK_WIDTH_X4 3 |
||
| 751 | # define LC_LINK_WIDTH_X8 4 |
||
| 752 | # define LC_LINK_WIDTH_X16 6 |
||
| 753 | # define LC_LINK_WIDTH_RD_SHIFT 4 |
||
| 754 | # define LC_LINK_WIDTH_RD_MASK 0x70 |
||
| 755 | # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) |
||
| 756 | # define LC_RECONFIG_NOW (1 << 8) |
||
| 757 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) |
||
| 758 | # define LC_RENEGOTIATE_EN (1 << 10) |
||
| 759 | # define LC_SHORT_RECONFIG_EN (1 << 11) |
||
| 760 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) |
||
| 761 | # define LC_UPCONFIGURE_DIS (1 << 13) |
||
| 762 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ |
||
| 763 | # define LC_GEN2_EN_STRAP (1 << 0) |
||
| 764 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) |
||
| 765 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) |
||
| 766 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) |
||
| 767 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) |
||
| 768 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 |
||
| 769 | # define LC_CURRENT_DATA_RATE (1 << 11) |
||
| 770 | # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) |
||
| 771 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) |
||
| 772 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) |
||
| 773 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) |
||
| 774 | #define MM_CFGREGS_CNTL 0x544c |
||
| 775 | # define MM_WR_TO_CFG_EN (1 << 3) |
||
| 776 | #define LINK_CNTL2 0x88 /* F0 */ |
||
| 777 | # define TARGET_LINK_SPEED_MASK (0xf << 0) |
||
| 778 | # define SELECTABLE_DEEMPHASIS (1 << 6) |
||
| 779 | |||
| 1221 | serge | 780 | /* |
| 781 | * PM4 |
||
| 782 | */ |
||
| 783 | #define PACKET_TYPE0 0 |
||
| 784 | #define PACKET_TYPE1 1 |
||
| 785 | #define PACKET_TYPE2 2 |
||
| 786 | #define PACKET_TYPE3 3 |
||
| 787 | |||
| 788 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) |
||
| 789 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) |
||
| 790 | #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) |
||
| 791 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
||
| 792 | #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ |
||
| 793 | (((reg) >> 2) & 0xFFFF) | \ |
||
| 794 | ((n) & 0x3FFF) << 16) |
||
| 795 | #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ |
||
| 796 | (((op) & 0xFF) << 8) | \ |
||
| 797 | ((n) & 0x3FFF) << 16) |
||
| 798 | |||
| 799 | /* Packet 3 types */ |
||
| 800 | #define PACKET3_NOP 0x10 |
||
| 801 | #define PACKET3_INDIRECT_BUFFER_END 0x17 |
||
| 802 | #define PACKET3_SET_PREDICATION 0x20 |
||
| 803 | #define PACKET3_REG_RMW 0x21 |
||
| 804 | #define PACKET3_COND_EXEC 0x22 |
||
| 805 | #define PACKET3_PRED_EXEC 0x23 |
||
| 806 | #define PACKET3_START_3D_CMDBUF 0x24 |
||
| 807 | #define PACKET3_DRAW_INDEX_2 0x27 |
||
| 808 | #define PACKET3_CONTEXT_CONTROL 0x28 |
||
| 809 | #define PACKET3_DRAW_INDEX_IMMD_BE 0x29 |
||
| 810 | #define PACKET3_INDEX_TYPE 0x2A |
||
| 811 | #define PACKET3_DRAW_INDEX 0x2B |
||
| 812 | #define PACKET3_DRAW_INDEX_AUTO 0x2D |
||
| 813 | #define PACKET3_DRAW_INDEX_IMMD 0x2E |
||
| 814 | #define PACKET3_NUM_INSTANCES 0x2F |
||
| 815 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 |
||
| 816 | #define PACKET3_INDIRECT_BUFFER_MP 0x38 |
||
| 817 | #define PACKET3_MEM_SEMAPHORE 0x39 |
||
| 818 | #define PACKET3_MPEG_INDEX 0x3A |
||
| 819 | #define PACKET3_WAIT_REG_MEM 0x3C |
||
| 820 | #define PACKET3_MEM_WRITE 0x3D |
||
| 821 | #define PACKET3_INDIRECT_BUFFER 0x32 |
||
| 822 | #define PACKET3_SURFACE_SYNC 0x43 |
||
| 823 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
||
| 824 | # define PACKET3_TC_ACTION_ENA (1 << 23) |
||
| 825 | # define PACKET3_VC_ACTION_ENA (1 << 24) |
||
| 826 | # define PACKET3_CB_ACTION_ENA (1 << 25) |
||
| 827 | # define PACKET3_DB_ACTION_ENA (1 << 26) |
||
| 828 | # define PACKET3_SH_ACTION_ENA (1 << 27) |
||
| 829 | # define PACKET3_SMX_ACTION_ENA (1 << 28) |
||
| 830 | #define PACKET3_ME_INITIALIZE 0x44 |
||
| 831 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) |
||
| 832 | #define PACKET3_COND_WRITE 0x45 |
||
| 833 | #define PACKET3_EVENT_WRITE 0x46 |
||
| 1963 | serge | 834 | #define EVENT_TYPE(x) ((x) << 0) |
| 835 | #define EVENT_INDEX(x) ((x) << 8) |
||
| 836 | /* 0 - any non-TS event |
||
| 837 | * 1 - ZPASS_DONE |
||
| 838 | * 2 - SAMPLE_PIPELINESTAT |
||
| 839 | * 3 - SAMPLE_STREAMOUTSTAT* |
||
| 840 | * 4 - *S_PARTIAL_FLUSH |
||
| 841 | * 5 - TS events |
||
| 842 | */ |
||
| 1221 | serge | 843 | #define PACKET3_EVENT_WRITE_EOP 0x47 |
| 1963 | serge | 844 | #define DATA_SEL(x) ((x) << 29) |
| 845 | /* 0 - discard |
||
| 846 | * 1 - send low 32bit data |
||
| 847 | * 2 - send 64bit data |
||
| 848 | * 3 - send 64bit counter value |
||
| 849 | */ |
||
| 850 | #define INT_SEL(x) ((x) << 24) |
||
| 851 | /* 0 - none |
||
| 852 | * 1 - interrupt only (DATA_SEL = 0) |
||
| 853 | * 2 - interrupt when data write is confirmed |
||
| 854 | */ |
||
| 1221 | serge | 855 | #define PACKET3_ONE_REG_WRITE 0x57 |
| 856 | #define PACKET3_SET_CONFIG_REG 0x68 |
||
| 857 | #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 |
||
| 858 | #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 |
||
| 859 | #define PACKET3_SET_CONTEXT_REG 0x69 |
||
| 860 | #define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 |
||
| 861 | #define PACKET3_SET_CONTEXT_REG_END 0x00029000 |
||
| 862 | #define PACKET3_SET_ALU_CONST 0x6A |
||
| 863 | #define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 |
||
| 864 | #define PACKET3_SET_ALU_CONST_END 0x00032000 |
||
| 865 | #define PACKET3_SET_BOOL_CONST 0x6B |
||
| 866 | #define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 |
||
| 867 | #define PACKET3_SET_BOOL_CONST_END 0x00040000 |
||
| 868 | #define PACKET3_SET_LOOP_CONST 0x6C |
||
| 869 | #define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 |
||
| 870 | #define PACKET3_SET_LOOP_CONST_END 0x0003e380 |
||
| 871 | #define PACKET3_SET_RESOURCE 0x6D |
||
| 872 | #define PACKET3_SET_RESOURCE_OFFSET 0x00038000 |
||
| 873 | #define PACKET3_SET_RESOURCE_END 0x0003c000 |
||
| 874 | #define PACKET3_SET_SAMPLER 0x6E |
||
| 875 | #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 |
||
| 876 | #define PACKET3_SET_SAMPLER_END 0x0003cff0 |
||
| 877 | #define PACKET3_SET_CTL_CONST 0x6F |
||
| 878 | #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 |
||
| 879 | #define PACKET3_SET_CTL_CONST_END 0x0003e200 |
||
| 880 | #define PACKET3_SURFACE_BASE_UPDATE 0x73 |
||
| 881 | |||
| 882 | |||
| 883 | #define R_008020_GRBM_SOFT_RESET 0x8020 |
||
| 884 | #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) |
||
| 885 | #define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) |
||
| 886 | #define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) |
||
| 887 | #define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) |
||
| 888 | #define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) |
||
| 889 | #define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) |
||
| 890 | #define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) |
||
| 891 | #define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) |
||
| 892 | #define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) |
||
| 893 | #define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) |
||
| 894 | #define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) |
||
| 895 | #define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) |
||
| 896 | #define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) |
||
| 897 | #define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) |
||
| 898 | #define R_008010_GRBM_STATUS 0x8010 |
||
| 899 | #define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) |
||
| 900 | #define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) |
||
| 901 | #define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) |
||
| 902 | #define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) |
||
| 903 | #define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) |
||
| 904 | #define S_008010_VC_BUSY(x) (((x) & 1) << 11) |
||
| 905 | #define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) |
||
| 906 | #define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) |
||
| 907 | #define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) |
||
| 908 | #define S_008010_VGT_BUSY(x) (((x) & 1) << 17) |
||
| 909 | #define S_008010_TA03_BUSY(x) (((x) & 1) << 18) |
||
| 910 | #define S_008010_TC_BUSY(x) (((x) & 1) << 19) |
||
| 911 | #define S_008010_SX_BUSY(x) (((x) & 1) << 20) |
||
| 912 | #define S_008010_SH_BUSY(x) (((x) & 1) << 21) |
||
| 913 | #define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) |
||
| 914 | #define S_008010_SMX_BUSY(x) (((x) & 1) << 23) |
||
| 915 | #define S_008010_SC_BUSY(x) (((x) & 1) << 24) |
||
| 916 | #define S_008010_PA_BUSY(x) (((x) & 1) << 25) |
||
| 917 | #define S_008010_DB03_BUSY(x) (((x) & 1) << 26) |
||
| 918 | #define S_008010_CR_BUSY(x) (((x) & 1) << 27) |
||
| 919 | #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) |
||
| 920 | #define S_008010_CP_BUSY(x) (((x) & 1) << 29) |
||
| 921 | #define S_008010_CB03_BUSY(x) (((x) & 1) << 30) |
||
| 922 | #define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) |
||
| 923 | #define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) |
||
| 924 | #define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) |
||
| 925 | #define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) |
||
| 926 | #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) |
||
| 927 | #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) |
||
| 928 | #define G_008010_VC_BUSY(x) (((x) >> 11) & 1) |
||
| 929 | #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) |
||
| 930 | #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) |
||
| 931 | #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) |
||
| 932 | #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) |
||
| 933 | #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) |
||
| 934 | #define G_008010_TC_BUSY(x) (((x) >> 19) & 1) |
||
| 935 | #define G_008010_SX_BUSY(x) (((x) >> 20) & 1) |
||
| 936 | #define G_008010_SH_BUSY(x) (((x) >> 21) & 1) |
||
| 937 | #define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) |
||
| 938 | #define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) |
||
| 939 | #define G_008010_SC_BUSY(x) (((x) >> 24) & 1) |
||
| 940 | #define G_008010_PA_BUSY(x) (((x) >> 25) & 1) |
||
| 941 | #define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) |
||
| 942 | #define G_008010_CR_BUSY(x) (((x) >> 27) & 1) |
||
| 943 | #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) |
||
| 944 | #define G_008010_CP_BUSY(x) (((x) >> 29) & 1) |
||
| 945 | #define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) |
||
| 946 | #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) |
||
| 947 | #define R_008014_GRBM_STATUS2 0x8014 |
||
| 948 | #define S_008014_CR_CLEAN(x) (((x) & 1) << 0) |
||
| 949 | #define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) |
||
| 950 | #define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) |
||
| 951 | #define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) |
||
| 952 | #define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) |
||
| 953 | #define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) |
||
| 954 | #define S_008014_TA0_BUSY(x) (((x) & 1) << 12) |
||
| 955 | #define S_008014_TA1_BUSY(x) (((x) & 1) << 13) |
||
| 956 | #define S_008014_TA2_BUSY(x) (((x) & 1) << 14) |
||
| 957 | #define S_008014_TA3_BUSY(x) (((x) & 1) << 15) |
||
| 958 | #define S_008014_DB0_BUSY(x) (((x) & 1) << 16) |
||
| 959 | #define S_008014_DB1_BUSY(x) (((x) & 1) << 17) |
||
| 960 | #define S_008014_DB2_BUSY(x) (((x) & 1) << 18) |
||
| 961 | #define S_008014_DB3_BUSY(x) (((x) & 1) << 19) |
||
| 962 | #define S_008014_CB0_BUSY(x) (((x) & 1) << 20) |
||
| 963 | #define S_008014_CB1_BUSY(x) (((x) & 1) << 21) |
||
| 964 | #define S_008014_CB2_BUSY(x) (((x) & 1) << 22) |
||
| 965 | #define S_008014_CB3_BUSY(x) (((x) & 1) << 23) |
||
| 966 | #define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) |
||
| 967 | #define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) |
||
| 968 | #define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) |
||
| 969 | #define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) |
||
| 970 | #define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) |
||
| 971 | #define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) |
||
| 972 | #define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) |
||
| 973 | #define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) |
||
| 974 | #define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) |
||
| 975 | #define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) |
||
| 976 | #define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) |
||
| 977 | #define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) |
||
| 978 | #define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) |
||
| 979 | #define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) |
||
| 980 | #define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) |
||
| 981 | #define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) |
||
| 982 | #define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) |
||
| 983 | #define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) |
||
| 984 | #define R_000E50_SRBM_STATUS 0x0E50 |
||
| 985 | #define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) |
||
| 986 | #define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) |
||
| 987 | #define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) |
||
| 988 | #define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) |
||
| 989 | #define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) |
||
| 990 | #define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) |
||
| 991 | #define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) |
||
| 992 | #define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) |
||
| 993 | #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) |
||
| 994 | #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) |
||
| 995 | #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) |
||
| 996 | #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) |
||
| 997 | #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) |
||
| 998 | #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) |
||
| 999 | #define R_000E60_SRBM_SOFT_RESET 0x0E60 |
||
| 1000 | #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) |
||
| 1001 | #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) |
||
| 1002 | #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) |
||
| 1003 | #define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) |
||
| 1004 | #define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) |
||
| 1005 | #define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) |
||
| 1006 | #define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) |
||
| 1007 | #define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) |
||
| 1008 | #define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) |
||
| 1009 | #define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) |
||
| 1010 | #define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) |
||
| 1011 | #define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) |
||
| 1012 | #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) |
||
| 1013 | #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) |
||
| 1014 | |||
| 1321 | serge | 1015 | #define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 |
| 1403 | serge | 1016 | |
| 1430 | serge | 1017 | #define R_028C04_PA_SC_AA_CONFIG 0x028C04 |
| 1018 | #define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0) |
||
| 1019 | #define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3) |
||
| 1020 | #define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC |
||
| 1021 | #define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) |
||
| 1022 | #define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) |
||
| 1023 | #define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF |
||
| 1024 | #define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13) |
||
| 1025 | #define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) |
||
| 1026 | #define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF |
||
| 1403 | serge | 1027 | #define R_0280E0_CB_COLOR0_FRAG 0x0280E0 |
| 1028 | #define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 1029 | #define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 1030 | #define C_0280E0_BASE_256B 0x00000000 |
||
| 1031 | #define R_0280E4_CB_COLOR1_FRAG 0x0280E4 |
||
| 1032 | #define R_0280E8_CB_COLOR2_FRAG 0x0280E8 |
||
| 1033 | #define R_0280EC_CB_COLOR3_FRAG 0x0280EC |
||
| 1034 | #define R_0280F0_CB_COLOR4_FRAG 0x0280F0 |
||
| 1035 | #define R_0280F4_CB_COLOR5_FRAG 0x0280F4 |
||
| 1036 | #define R_0280F8_CB_COLOR6_FRAG 0x0280F8 |
||
| 1037 | #define R_0280FC_CB_COLOR7_FRAG 0x0280FC |
||
| 1038 | #define R_0280C0_CB_COLOR0_TILE 0x0280C0 |
||
| 1039 | #define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 1040 | #define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 1041 | #define C_0280C0_BASE_256B 0x00000000 |
||
| 1042 | #define R_0280C4_CB_COLOR1_TILE 0x0280C4 |
||
| 1043 | #define R_0280C8_CB_COLOR2_TILE 0x0280C8 |
||
| 1044 | #define R_0280CC_CB_COLOR3_TILE 0x0280CC |
||
| 1045 | #define R_0280D0_CB_COLOR4_TILE 0x0280D0 |
||
| 1046 | #define R_0280D4_CB_COLOR5_TILE 0x0280D4 |
||
| 1047 | #define R_0280D8_CB_COLOR6_TILE 0x0280D8 |
||
| 1048 | #define R_0280DC_CB_COLOR7_TILE 0x0280DC |
||
| 1430 | serge | 1049 | #define R_0280A0_CB_COLOR0_INFO 0x0280A0 |
| 1050 | #define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) |
||
| 1051 | #define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) |
||
| 1052 | #define C_0280A0_ENDIAN 0xFFFFFFFC |
||
| 1053 | #define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) |
||
| 1054 | #define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) |
||
| 1055 | #define C_0280A0_FORMAT 0xFFFFFF03 |
||
| 1056 | #define V_0280A0_COLOR_INVALID 0x00000000 |
||
| 1057 | #define V_0280A0_COLOR_8 0x00000001 |
||
| 1058 | #define V_0280A0_COLOR_4_4 0x00000002 |
||
| 1059 | #define V_0280A0_COLOR_3_3_2 0x00000003 |
||
| 1060 | #define V_0280A0_COLOR_16 0x00000005 |
||
| 1061 | #define V_0280A0_COLOR_16_FLOAT 0x00000006 |
||
| 1062 | #define V_0280A0_COLOR_8_8 0x00000007 |
||
| 1063 | #define V_0280A0_COLOR_5_6_5 0x00000008 |
||
| 1064 | #define V_0280A0_COLOR_6_5_5 0x00000009 |
||
| 1065 | #define V_0280A0_COLOR_1_5_5_5 0x0000000A |
||
| 1066 | #define V_0280A0_COLOR_4_4_4_4 0x0000000B |
||
| 1067 | #define V_0280A0_COLOR_5_5_5_1 0x0000000C |
||
| 1068 | #define V_0280A0_COLOR_32 0x0000000D |
||
| 1069 | #define V_0280A0_COLOR_32_FLOAT 0x0000000E |
||
| 1070 | #define V_0280A0_COLOR_16_16 0x0000000F |
||
| 1071 | #define V_0280A0_COLOR_16_16_FLOAT 0x00000010 |
||
| 1072 | #define V_0280A0_COLOR_8_24 0x00000011 |
||
| 1073 | #define V_0280A0_COLOR_8_24_FLOAT 0x00000012 |
||
| 1074 | #define V_0280A0_COLOR_24_8 0x00000013 |
||
| 1075 | #define V_0280A0_COLOR_24_8_FLOAT 0x00000014 |
||
| 1076 | #define V_0280A0_COLOR_10_11_11 0x00000015 |
||
| 1077 | #define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 |
||
| 1078 | #define V_0280A0_COLOR_11_11_10 0x00000017 |
||
| 1079 | #define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 |
||
| 1080 | #define V_0280A0_COLOR_2_10_10_10 0x00000019 |
||
| 1081 | #define V_0280A0_COLOR_8_8_8_8 0x0000001A |
||
| 1082 | #define V_0280A0_COLOR_10_10_10_2 0x0000001B |
||
| 1083 | #define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C |
||
| 1084 | #define V_0280A0_COLOR_32_32 0x0000001D |
||
| 1085 | #define V_0280A0_COLOR_32_32_FLOAT 0x0000001E |
||
| 1086 | #define V_0280A0_COLOR_16_16_16_16 0x0000001F |
||
| 1087 | #define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 |
||
| 1088 | #define V_0280A0_COLOR_32_32_32_32 0x00000022 |
||
| 1089 | #define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 |
||
| 1090 | #define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) |
||
| 1091 | #define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) |
||
| 1092 | #define C_0280A0_ARRAY_MODE 0xFFFFF0FF |
||
| 1093 | #define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 |
||
| 1094 | #define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 |
||
| 1095 | #define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 |
||
| 1096 | #define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 |
||
| 1097 | #define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) |
||
| 1098 | #define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) |
||
| 1099 | #define C_0280A0_NUMBER_TYPE 0xFFFF8FFF |
||
| 1100 | #define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) |
||
| 1101 | #define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) |
||
| 1102 | #define C_0280A0_READ_SIZE 0xFFFF7FFF |
||
| 1103 | #define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) |
||
| 1104 | #define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) |
||
| 1105 | #define C_0280A0_COMP_SWAP 0xFFFCFFFF |
||
| 1106 | #define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) |
||
| 1107 | #define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) |
||
| 1108 | #define C_0280A0_TILE_MODE 0xFFF3FFFF |
||
| 1109 | #define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) |
||
| 1110 | #define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) |
||
| 1111 | #define C_0280A0_BLEND_CLAMP 0xFFEFFFFF |
||
| 1112 | #define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) |
||
| 1113 | #define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) |
||
| 1114 | #define C_0280A0_CLEAR_COLOR 0xFFDFFFFF |
||
| 1115 | #define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) |
||
| 1116 | #define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) |
||
| 1117 | #define C_0280A0_BLEND_BYPASS 0xFFBFFFFF |
||
| 1118 | #define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) |
||
| 1119 | #define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) |
||
| 1120 | #define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF |
||
| 1121 | #define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) |
||
| 1122 | #define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) |
||
| 1123 | #define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF |
||
| 1124 | #define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) |
||
| 1125 | #define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) |
||
| 1126 | #define C_0280A0_ROUND_MODE 0xFDFFFFFF |
||
| 1127 | #define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) |
||
| 1128 | #define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) |
||
| 1129 | #define C_0280A0_TILE_COMPACT 0xFBFFFFFF |
||
| 1130 | #define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) |
||
| 1131 | #define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) |
||
| 1132 | #define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF |
||
| 1133 | #define R_0280A4_CB_COLOR1_INFO 0x0280A4 |
||
| 1134 | #define R_0280A8_CB_COLOR2_INFO 0x0280A8 |
||
| 1135 | #define R_0280AC_CB_COLOR3_INFO 0x0280AC |
||
| 1136 | #define R_0280B0_CB_COLOR4_INFO 0x0280B0 |
||
| 1137 | #define R_0280B4_CB_COLOR5_INFO 0x0280B4 |
||
| 1138 | #define R_0280B8_CB_COLOR6_INFO 0x0280B8 |
||
| 1139 | #define R_0280BC_CB_COLOR7_INFO 0x0280BC |
||
| 1140 | #define R_028060_CB_COLOR0_SIZE 0x028060 |
||
| 1141 | #define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) |
||
| 1142 | #define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) |
||
| 1143 | #define C_028060_PITCH_TILE_MAX 0xFFFFFC00 |
||
| 1144 | #define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) |
||
| 1145 | #define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) |
||
| 1146 | #define C_028060_SLICE_TILE_MAX 0xC00003FF |
||
| 1147 | #define R_028064_CB_COLOR1_SIZE 0x028064 |
||
| 1148 | #define R_028068_CB_COLOR2_SIZE 0x028068 |
||
| 1149 | #define R_02806C_CB_COLOR3_SIZE 0x02806C |
||
| 1150 | #define R_028070_CB_COLOR4_SIZE 0x028070 |
||
| 1151 | #define R_028074_CB_COLOR5_SIZE 0x028074 |
||
| 1152 | #define R_028078_CB_COLOR6_SIZE 0x028078 |
||
| 1153 | #define R_02807C_CB_COLOR7_SIZE 0x02807C |
||
| 1154 | #define R_028238_CB_TARGET_MASK 0x028238 |
||
| 1155 | #define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0) |
||
| 1156 | #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF) |
||
| 1157 | #define C_028238_TARGET0_ENABLE 0xFFFFFFF0 |
||
| 1158 | #define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4) |
||
| 1159 | #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF) |
||
| 1160 | #define C_028238_TARGET1_ENABLE 0xFFFFFF0F |
||
| 1161 | #define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8) |
||
| 1162 | #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF) |
||
| 1163 | #define C_028238_TARGET2_ENABLE 0xFFFFF0FF |
||
| 1164 | #define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12) |
||
| 1165 | #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF) |
||
| 1166 | #define C_028238_TARGET3_ENABLE 0xFFFF0FFF |
||
| 1167 | #define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16) |
||
| 1168 | #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF) |
||
| 1169 | #define C_028238_TARGET4_ENABLE 0xFFF0FFFF |
||
| 1170 | #define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20) |
||
| 1171 | #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF) |
||
| 1172 | #define C_028238_TARGET5_ENABLE 0xFF0FFFFF |
||
| 1173 | #define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24) |
||
| 1174 | #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF) |
||
| 1175 | #define C_028238_TARGET6_ENABLE 0xF0FFFFFF |
||
| 1176 | #define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28) |
||
| 1177 | #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF) |
||
| 1178 | #define C_028238_TARGET7_ENABLE 0x0FFFFFFF |
||
| 1179 | #define R_02823C_CB_SHADER_MASK 0x02823C |
||
| 1180 | #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0) |
||
| 1181 | #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF) |
||
| 1182 | #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 |
||
| 1183 | #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4) |
||
| 1184 | #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF) |
||
| 1185 | #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F |
||
| 1186 | #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8) |
||
| 1187 | #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF) |
||
| 1188 | #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF |
||
| 1189 | #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12) |
||
| 1190 | #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF) |
||
| 1191 | #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF |
||
| 1192 | #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16) |
||
| 1193 | #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF) |
||
| 1194 | #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF |
||
| 1195 | #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20) |
||
| 1196 | #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF) |
||
| 1197 | #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF |
||
| 1198 | #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24) |
||
| 1199 | #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF) |
||
| 1200 | #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF |
||
| 1201 | #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28) |
||
| 1202 | #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF) |
||
| 1203 | #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF |
||
| 1204 | #define R_028AB0_VGT_STRMOUT_EN 0x028AB0 |
||
| 1205 | #define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) |
||
| 1206 | #define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) |
||
| 1207 | #define C_028AB0_STREAMOUT 0xFFFFFFFE |
||
| 1208 | #define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 |
||
| 1209 | #define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) |
||
| 1210 | #define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) |
||
| 1211 | #define C_028B20_BUFFER_0_EN 0xFFFFFFFE |
||
| 1212 | #define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) |
||
| 1213 | #define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) |
||
| 1214 | #define C_028B20_BUFFER_1_EN 0xFFFFFFFD |
||
| 1215 | #define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) |
||
| 1216 | #define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) |
||
| 1217 | #define C_028B20_BUFFER_2_EN 0xFFFFFFFB |
||
| 1218 | #define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) |
||
| 1219 | #define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) |
||
| 1220 | #define C_028B20_BUFFER_3_EN 0xFFFFFFF7 |
||
| 1221 | #define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 1222 | #define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 1223 | #define C_028B20_SIZE 0x00000000 |
||
| 1224 | #define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000 |
||
| 1225 | #define S_038000_DIM(x) (((x) & 0x7) << 0) |
||
| 1226 | #define G_038000_DIM(x) (((x) >> 0) & 0x7) |
||
| 1227 | #define C_038000_DIM 0xFFFFFFF8 |
||
| 1228 | #define V_038000_SQ_TEX_DIM_1D 0x00000000 |
||
| 1229 | #define V_038000_SQ_TEX_DIM_2D 0x00000001 |
||
| 1230 | #define V_038000_SQ_TEX_DIM_3D 0x00000002 |
||
| 1231 | #define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003 |
||
| 1232 | #define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004 |
||
| 1233 | #define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005 |
||
| 1234 | #define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006 |
||
| 1235 | #define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 |
||
| 1236 | #define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) |
||
| 1237 | #define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) |
||
| 1238 | #define C_038000_TILE_MODE 0xFFFFFF87 |
||
| 1963 | serge | 1239 | #define V_038000_ARRAY_LINEAR_GENERAL 0x00000000 |
| 1240 | #define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001 |
||
| 1241 | #define V_038000_ARRAY_1D_TILED_THIN1 0x00000002 |
||
| 1242 | #define V_038000_ARRAY_2D_TILED_THIN1 0x00000004 |
||
| 1430 | serge | 1243 | #define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) |
| 1244 | #define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) |
||
| 1245 | #define C_038000_TILE_TYPE 0xFFFFFF7F |
||
| 1246 | #define S_038000_PITCH(x) (((x) & 0x7FF) << 8) |
||
| 1247 | #define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) |
||
| 1248 | #define C_038000_PITCH 0xFFF800FF |
||
| 1249 | #define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19) |
||
| 1250 | #define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF) |
||
| 1251 | #define C_038000_TEX_WIDTH 0x0007FFFF |
||
| 1252 | #define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004 |
||
| 1253 | #define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0) |
||
| 1254 | #define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF) |
||
| 1255 | #define C_038004_TEX_HEIGHT 0xFFFFE000 |
||
| 1256 | #define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13) |
||
| 1257 | #define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF) |
||
| 1258 | #define C_038004_TEX_DEPTH 0xFC001FFF |
||
| 1259 | #define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26) |
||
| 1260 | #define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F) |
||
| 1261 | #define C_038004_DATA_FORMAT 0x03FFFFFF |
||
| 1262 | #define V_038004_COLOR_INVALID 0x00000000 |
||
| 1263 | #define V_038004_COLOR_8 0x00000001 |
||
| 1264 | #define V_038004_COLOR_4_4 0x00000002 |
||
| 1265 | #define V_038004_COLOR_3_3_2 0x00000003 |
||
| 1266 | #define V_038004_COLOR_16 0x00000005 |
||
| 1267 | #define V_038004_COLOR_16_FLOAT 0x00000006 |
||
| 1268 | #define V_038004_COLOR_8_8 0x00000007 |
||
| 1269 | #define V_038004_COLOR_5_6_5 0x00000008 |
||
| 1270 | #define V_038004_COLOR_6_5_5 0x00000009 |
||
| 1271 | #define V_038004_COLOR_1_5_5_5 0x0000000A |
||
| 1272 | #define V_038004_COLOR_4_4_4_4 0x0000000B |
||
| 1273 | #define V_038004_COLOR_5_5_5_1 0x0000000C |
||
| 1274 | #define V_038004_COLOR_32 0x0000000D |
||
| 1275 | #define V_038004_COLOR_32_FLOAT 0x0000000E |
||
| 1276 | #define V_038004_COLOR_16_16 0x0000000F |
||
| 1277 | #define V_038004_COLOR_16_16_FLOAT 0x00000010 |
||
| 1278 | #define V_038004_COLOR_8_24 0x00000011 |
||
| 1279 | #define V_038004_COLOR_8_24_FLOAT 0x00000012 |
||
| 1280 | #define V_038004_COLOR_24_8 0x00000013 |
||
| 1281 | #define V_038004_COLOR_24_8_FLOAT 0x00000014 |
||
| 1282 | #define V_038004_COLOR_10_11_11 0x00000015 |
||
| 1283 | #define V_038004_COLOR_10_11_11_FLOAT 0x00000016 |
||
| 1284 | #define V_038004_COLOR_11_11_10 0x00000017 |
||
| 1285 | #define V_038004_COLOR_11_11_10_FLOAT 0x00000018 |
||
| 1286 | #define V_038004_COLOR_2_10_10_10 0x00000019 |
||
| 1287 | #define V_038004_COLOR_8_8_8_8 0x0000001A |
||
| 1288 | #define V_038004_COLOR_10_10_10_2 0x0000001B |
||
| 1289 | #define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C |
||
| 1290 | #define V_038004_COLOR_32_32 0x0000001D |
||
| 1291 | #define V_038004_COLOR_32_32_FLOAT 0x0000001E |
||
| 1292 | #define V_038004_COLOR_16_16_16_16 0x0000001F |
||
| 1293 | #define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020 |
||
| 1294 | #define V_038004_COLOR_32_32_32_32 0x00000022 |
||
| 1295 | #define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023 |
||
| 1296 | #define V_038004_FMT_1 0x00000025 |
||
| 1297 | #define V_038004_FMT_GB_GR 0x00000027 |
||
| 1298 | #define V_038004_FMT_BG_RG 0x00000028 |
||
| 1299 | #define V_038004_FMT_32_AS_8 0x00000029 |
||
| 1300 | #define V_038004_FMT_32_AS_8_8 0x0000002A |
||
| 1301 | #define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B |
||
| 1302 | #define V_038004_FMT_8_8_8 0x0000002C |
||
| 1303 | #define V_038004_FMT_16_16_16 0x0000002D |
||
| 1304 | #define V_038004_FMT_16_16_16_FLOAT 0x0000002E |
||
| 1305 | #define V_038004_FMT_32_32_32 0x0000002F |
||
| 1306 | #define V_038004_FMT_32_32_32_FLOAT 0x00000030 |
||
| 1963 | serge | 1307 | #define V_038004_FMT_BC1 0x00000031 |
| 1308 | #define V_038004_FMT_BC2 0x00000032 |
||
| 1309 | #define V_038004_FMT_BC3 0x00000033 |
||
| 1310 | #define V_038004_FMT_BC4 0x00000034 |
||
| 1311 | #define V_038004_FMT_BC5 0x00000035 |
||
| 1312 | #define V_038004_FMT_BC6 0x00000036 |
||
| 1313 | #define V_038004_FMT_BC7 0x00000037 |
||
| 1314 | #define V_038004_FMT_32_AS_32_32_32_32 0x00000038 |
||
| 1430 | serge | 1315 | #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 |
| 1316 | #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) |
||
| 1317 | #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) |
||
| 1318 | #define C_038010_FORMAT_COMP_X 0xFFFFFFFC |
||
| 1319 | #define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) |
||
| 1320 | #define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) |
||
| 1321 | #define C_038010_FORMAT_COMP_Y 0xFFFFFFF3 |
||
| 1322 | #define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) |
||
| 1323 | #define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) |
||
| 1324 | #define C_038010_FORMAT_COMP_Z 0xFFFFFFCF |
||
| 1325 | #define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) |
||
| 1326 | #define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) |
||
| 1327 | #define C_038010_FORMAT_COMP_W 0xFFFFFF3F |
||
| 1328 | #define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) |
||
| 1329 | #define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) |
||
| 1330 | #define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF |
||
| 1331 | #define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) |
||
| 1332 | #define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) |
||
| 1333 | #define C_038010_SRF_MODE_ALL 0xFFFFFBFF |
||
| 1334 | #define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) |
||
| 1335 | #define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) |
||
| 1336 | #define C_038010_FORCE_DEGAMMA 0xFFFFF7FF |
||
| 1337 | #define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) |
||
| 1338 | #define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) |
||
| 1339 | #define C_038010_ENDIAN_SWAP 0xFFFFCFFF |
||
| 1340 | #define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14) |
||
| 1341 | #define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) |
||
| 1342 | #define C_038010_REQUEST_SIZE 0xFFFF3FFF |
||
| 1343 | #define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16) |
||
| 1344 | #define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7) |
||
| 1345 | #define C_038010_DST_SEL_X 0xFFF8FFFF |
||
| 1346 | #define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19) |
||
| 1347 | #define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7) |
||
| 1348 | #define C_038010_DST_SEL_Y 0xFFC7FFFF |
||
| 1349 | #define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22) |
||
| 1350 | #define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) |
||
| 1351 | #define C_038010_DST_SEL_Z 0xFE3FFFFF |
||
| 1352 | #define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) |
||
| 1353 | #define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) |
||
| 1354 | #define C_038010_DST_SEL_W 0xF1FFFFFF |
||
| 1355 | #define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) |
||
| 1356 | #define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) |
||
| 1357 | #define C_038010_BASE_LEVEL 0x0FFFFFFF |
||
| 1358 | #define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 |
||
| 1359 | #define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) |
||
| 1360 | #define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF) |
||
| 1361 | #define C_038014_LAST_LEVEL 0xFFFFFFF0 |
||
| 1362 | #define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) |
||
| 1363 | #define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) |
||
| 1364 | #define C_038014_BASE_ARRAY 0xFFFE000F |
||
| 1365 | #define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) |
||
| 1366 | #define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) |
||
| 1367 | #define C_038014_LAST_ARRAY 0xC001FFFF |
||
| 1368 | #define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8 |
||
| 1369 | #define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
| 1370 | #define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
| 1371 | #define C_0288A8_ITEMSIZE 0xFFFF8000 |
||
| 1372 | #define R_008C44_SQ_ESGS_RING_SIZE 0x008C44 |
||
| 1373 | #define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 1374 | #define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 1375 | #define C_008C44_MEM_SIZE 0x00000000 |
||
| 1376 | #define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0 |
||
| 1377 | #define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
| 1378 | #define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
| 1379 | #define C_0288B0_ITEMSIZE 0xFFFF8000 |
||
| 1380 | #define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54 |
||
| 1381 | #define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 1382 | #define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 1383 | #define C_008C54_MEM_SIZE 0x00000000 |
||
| 1384 | #define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0 |
||
| 1385 | #define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
| 1386 | #define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
| 1387 | #define C_0288C0_ITEMSIZE 0xFFFF8000 |
||
| 1388 | #define R_008C74_SQ_FBUF_RING_SIZE 0x008C74 |
||
| 1389 | #define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 1390 | #define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 1391 | #define C_008C74_MEM_SIZE 0x00000000 |
||
| 1392 | #define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4 |
||
| 1393 | #define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
| 1394 | #define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
| 1395 | #define C_0288B4_ITEMSIZE 0xFFFF8000 |
||
| 1396 | #define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C |
||
| 1397 | #define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 1398 | #define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 1399 | #define C_008C5C_MEM_SIZE 0x00000000 |
||
| 1400 | #define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC |
||
| 1401 | #define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
| 1402 | #define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
| 1403 | #define C_0288AC_ITEMSIZE 0xFFFF8000 |
||
| 1404 | #define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C |
||
| 1405 | #define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 1406 | #define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 1407 | #define C_008C4C_MEM_SIZE 0x00000000 |
||
| 1408 | #define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC |
||
| 1409 | #define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
| 1410 | #define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
| 1411 | #define C_0288BC_ITEMSIZE 0xFFFF8000 |
||
| 1412 | #define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C |
||
| 1413 | #define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 1414 | #define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 1415 | #define C_008C6C_MEM_SIZE 0x00000000 |
||
| 1416 | #define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4 |
||
| 1417 | #define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
| 1418 | #define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
| 1419 | #define C_0288C4_ITEMSIZE 0xFFFF8000 |
||
| 1420 | #define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C |
||
| 1421 | #define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 1422 | #define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 1423 | #define C_008C7C_MEM_SIZE 0x00000000 |
||
| 1424 | #define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8 |
||
| 1425 | #define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
| 1426 | #define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
| 1427 | #define C_0288B8_ITEMSIZE 0xFFFF8000 |
||
| 1428 | #define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64 |
||
| 1429 | #define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) |
||
| 1430 | #define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
||
| 1431 | #define C_008C64_MEM_SIZE 0x00000000 |
||
| 1432 | #define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 |
||
| 1433 | #define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) |
||
| 1434 | #define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) |
||
| 1435 | #define C_0288C8_ITEMSIZE 0xFFFF8000 |
||
| 1436 | #define R_028010_DB_DEPTH_INFO 0x028010 |
||
| 1437 | #define S_028010_FORMAT(x) (((x) & 0x7) << 0) |
||
| 1438 | #define G_028010_FORMAT(x) (((x) >> 0) & 0x7) |
||
| 1439 | #define C_028010_FORMAT 0xFFFFFFF8 |
||
| 1440 | #define V_028010_DEPTH_INVALID 0x00000000 |
||
| 1441 | #define V_028010_DEPTH_16 0x00000001 |
||
| 1442 | #define V_028010_DEPTH_X8_24 0x00000002 |
||
| 1443 | #define V_028010_DEPTH_8_24 0x00000003 |
||
| 1444 | #define V_028010_DEPTH_X8_24_FLOAT 0x00000004 |
||
| 1445 | #define V_028010_DEPTH_8_24_FLOAT 0x00000005 |
||
| 1446 | #define V_028010_DEPTH_32_FLOAT 0x00000006 |
||
| 1447 | #define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 |
||
| 1448 | #define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) |
||
| 1449 | #define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) |
||
| 1450 | #define C_028010_READ_SIZE 0xFFFFFFF7 |
||
| 1451 | #define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) |
||
| 1452 | #define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) |
||
| 1453 | #define C_028010_ARRAY_MODE 0xFFF87FFF |
||
| 1963 | serge | 1454 | #define V_028010_ARRAY_1D_TILED_THIN1 0x00000002 |
| 1455 | #define V_028010_ARRAY_2D_TILED_THIN1 0x00000004 |
||
| 1430 | serge | 1456 | #define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) |
| 1457 | #define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) |
||
| 1458 | #define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF |
||
| 1459 | #define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) |
||
| 1460 | #define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) |
||
| 1461 | #define C_028010_TILE_COMPACT 0xFBFFFFFF |
||
| 1462 | #define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) |
||
| 1463 | #define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) |
||
| 1464 | #define C_028010_ZRANGE_PRECISION 0x7FFFFFFF |
||
| 1465 | #define R_028000_DB_DEPTH_SIZE 0x028000 |
||
| 1466 | #define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) |
||
| 1467 | #define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) |
||
| 1468 | #define C_028000_PITCH_TILE_MAX 0xFFFFFC00 |
||
| 1469 | #define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) |
||
| 1470 | #define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) |
||
| 1471 | #define C_028000_SLICE_TILE_MAX 0xC00003FF |
||
| 1472 | #define R_028004_DB_DEPTH_VIEW 0x028004 |
||
| 1473 | #define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) |
||
| 1474 | #define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) |
||
| 1475 | #define C_028004_SLICE_START 0xFFFFF800 |
||
| 1476 | #define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) |
||
| 1477 | #define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) |
||
| 1478 | #define C_028004_SLICE_MAX 0xFF001FFF |
||
| 1479 | #define R_028800_DB_DEPTH_CONTROL 0x028800 |
||
| 1480 | #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) |
||
| 1481 | #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) |
||
| 1482 | #define C_028800_STENCIL_ENABLE 0xFFFFFFFE |
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| 1483 | #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) |
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| 1484 | #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) |
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| 1485 | #define C_028800_Z_ENABLE 0xFFFFFFFD |
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| 1486 | #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) |
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| 1487 | #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) |
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| 1488 | #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB |
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| 1489 | #define S_028800_ZFUNC(x) (((x) & 0x7) << 4) |
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| 1490 | #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) |
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| 1491 | #define C_028800_ZFUNC 0xFFFFFF8F |
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| 1492 | #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) |
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| 1493 | #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) |
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| 1494 | #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F |
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| 1495 | #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) |
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| 1496 | #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) |
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| 1497 | #define C_028800_STENCILFUNC 0xFFFFF8FF |
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| 1498 | #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) |
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| 1499 | #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) |
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| 1500 | #define C_028800_STENCILFAIL 0xFFFFC7FF |
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| 1501 | #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) |
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| 1502 | #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) |
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| 1503 | #define C_028800_STENCILZPASS 0xFFFE3FFF |
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| 1504 | #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) |
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| 1505 | #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) |
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| 1506 | #define C_028800_STENCILZFAIL 0xFFF1FFFF |
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| 1507 | #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) |
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| 1508 | #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) |
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| 1509 | #define C_028800_STENCILFUNC_BF 0xFF8FFFFF |
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| 1510 | #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) |
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| 1511 | #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) |
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| 1512 | #define C_028800_STENCILFAIL_BF 0xFC7FFFFF |
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| 1513 | #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) |
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| 1514 | #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) |
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| 1515 | #define C_028800_STENCILZPASS_BF 0xE3FFFFFF |
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| 1516 | #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) |
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| 1517 | #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) |
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| 1518 | #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF |
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| 1403 | serge | 1519 | |
| 1221 | serge | 1520 | #endif |