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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2176 | serge | 1 | /* |
| 2 | * RadeonHD R6xx, R7xx DRI driver |
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| 3 | * |
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| 4 | * Copyright (C) 2008-2009 Alexander Deucher |
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| 5 | * Copyright (C) 2008-2009 Matthias Hopf |
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| 6 | * |
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| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 8 | * copy of this software and associated documentation files (the "Software"), |
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| 9 | * to deal in the Software without restriction, including without limitation |
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| 10 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 11 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 12 | * Software is furnished to do so, subject to the following conditions: |
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| 13 | * |
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| 14 | * The above copyright notice and this permission notice shall be included |
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| 15 | * in all copies or substantial portions of the Software. |
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| 16 | * |
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| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 20 | * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 21 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 22 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | */ |
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| 24 | |||
| 25 | /* |
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| 26 | * Shader macros |
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| 27 | */ |
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| 28 | |||
| 29 | #ifndef __SHADER_H__ |
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| 30 | #define __SHADER_H__ |
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| 31 | |||
| 32 | //#include "radeon.h" |
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| 33 | |||
| 34 | /* Restrictions of ALU instructions |
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| 35 | * order of scalar ops is always x,y,z,w,t(rans), last to be indicated by last==1. |
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| 36 | * max of 3 different src GPRs per instr. |
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| 37 | * max of 4 different cfile constant components per instr. |
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| 38 | * max of 2 (different) constants (any type) for t. |
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| 39 | * bank swizzle (see below). |
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| 40 | * GPR write stalls read of same register. Auto-replaced by PV/PS, NOP needed if registers are relative to |
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| 41 | * different indices (gpr,loop,nothing). |
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| 42 | * may use constant registers or constant cache, but not both. |
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| 43 | */ |
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| 44 | |||
| 45 | /* Bank_swizzle: (pp. 297ff) |
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| 46 | * Only one of each x,y,z,w GPR component can be loaded per cycle (3 cycles per instr, called 0-2). |
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| 47 | * per scalar instruction bank_swizzle can select which cycle each operand comes from. e.g.: |
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| 48 | * SRC0 SRC1 SRC2 SWIZZLE cycle0 cycle1 cycle2 |
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| 49 | * 1.x 2.x 012 1.x 2.x - |
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| 50 | * 3.x 1.y 201 1.y - 3.x |
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| 51 | * 2.x 1.y 102 (1.y) (2.x) - |
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| 52 | * If data is read in a cycle, multiple scalar instructions can reference it. |
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| 53 | * Special case: square() - i.e. same component in src0+src1 doesn't need read port -> ignores swizzle for src1. |
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| 54 | * No restrictions for constants or PV/PS. |
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| 55 | * t can load multiple components in a single cycle slot, but has to share cycles with xyzw. |
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| 56 | * t with single constant may not load GPRs or PV/PS in cycle 0 (carefull with ALU_TRANS_210). |
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| 57 | * t with two constants may only load GPRs or PV/PS in cycle 2. |
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| 58 | */ |
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| 59 | |||
| 60 | |||
| 61 | /* Oder of instructions: All CF, All ALU, All Tex/Vtx fetches */ |
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| 62 | |||
| 63 | |||
| 64 | // CF insts |
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| 65 | // addr |
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| 66 | #define ADDR(x) (x) |
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| 67 | // pc |
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| 68 | #define POP_COUNT(x) (x) |
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| 69 | // const |
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| 70 | #define CF_CONST(x) (x) |
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| 71 | // cond |
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| 72 | #define COND(x) (x) // SQ_COND_* |
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| 73 | // count |
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| 74 | #define I_COUNT(x) ((x) ? ((x) - 1) : 0) |
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| 75 | //r7xx |
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| 76 | #define COUNT_3(x) (x) |
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| 77 | // call count |
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| 78 | #define CALL_COUNT(x) (x) |
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| 79 | // eop |
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| 80 | #define END_OF_PROGRAM(x) (x) |
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| 81 | // vpm |
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| 82 | #define VALID_PIXEL_MODE(x) (x) |
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| 83 | // cf inst |
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| 84 | #define CF_INST(x) (x) // SQ_CF_INST_* |
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| 85 | |||
| 86 | // wqm |
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| 87 | #define WHOLE_QUAD_MODE(x) (x) |
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| 88 | // barrier |
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| 89 | #define BARRIER(x) (x) |
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| 90 | //kb0 |
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| 91 | #define KCACHE_BANK0(x) (x) |
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| 92 | //kb1 |
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| 93 | #define KCACHE_BANK1(x) (x) |
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| 94 | // km0/1 |
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| 95 | #define KCACHE_MODE0(x) (x) |
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| 96 | #define KCACHE_MODE1(x) (x) // SQ_CF_KCACHE_* |
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| 97 | // |
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| 98 | #define KCACHE_ADDR0(x) (x) |
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| 99 | #define KCACHE_ADDR1(x) (x) |
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| 100 | // uw |
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| 101 | #define USES_WATERFALL(x) (x) |
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| 102 | |||
| 103 | #define ARRAY_BASE(x) (x) |
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| 104 | // export pixel |
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| 105 | #define CF_PIXEL_MRT0 0 |
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| 106 | #define CF_PIXEL_MRT1 1 |
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| 107 | #define CF_PIXEL_MRT2 2 |
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| 108 | #define CF_PIXEL_MRT3 3 |
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| 109 | #define CF_PIXEL_MRT4 4 |
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| 110 | #define CF_PIXEL_MRT5 5 |
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| 111 | #define CF_PIXEL_MRT6 6 |
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| 112 | #define CF_PIXEL_MRT7 7 |
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| 113 | // *_FOG: r6xx only |
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| 114 | #define CF_PIXEL_MRT0_FOG 16 |
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| 115 | #define CF_PIXEL_MRT1_FOG 17 |
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| 116 | #define CF_PIXEL_MRT2_FOG 18 |
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| 117 | #define CF_PIXEL_MRT3_FOG 19 |
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| 118 | #define CF_PIXEL_MRT4_FOG 20 |
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| 119 | #define CF_PIXEL_MRT5_FOG 21 |
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| 120 | #define CF_PIXEL_MRT6_FOG 22 |
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| 121 | #define CF_PIXEL_MRT7_FOG 23 |
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| 122 | #define CF_PIXEL_Z 61 |
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| 123 | // export pos |
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| 124 | #define CF_POS0 60 |
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| 125 | #define CF_POS1 61 |
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| 126 | #define CF_POS2 62 |
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| 127 | #define CF_POS3 63 |
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| 128 | // export param |
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| 129 | // 0...31 |
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| 130 | #define TYPE(x) (x) // SQ_EXPORT_* |
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| 131 | #if 0 |
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| 132 | // type export |
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| 133 | #define SQ_EXPORT_PIXEL 0 |
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| 134 | #define SQ_EXPORT_POS 1 |
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| 135 | #define SQ_EXPORT_PARAM 2 |
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| 136 | // reserved 3 |
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| 137 | // type mem |
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| 138 | #define SQ_EXPORT_WRITE 0 |
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| 139 | #define SQ_EXPORT_WRITE_IND 1 |
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| 140 | #define SQ_EXPORT_WRITE_ACK 2 |
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| 141 | #define SQ_EXPORT_WRITE_IND_ACK 3 |
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| 142 | #endif |
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| 143 | |||
| 144 | #define RW_GPR(x) (x) |
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| 145 | #define RW_REL(x) (x) |
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| 146 | #define ABSOLUTE 0 |
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| 147 | #define RELATIVE 1 |
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| 148 | #define INDEX_GPR(x) (x) |
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| 149 | #define ELEM_SIZE(x) (x ? (x - 1) : 0) |
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| 150 | #define COMP_MASK(x) (x) |
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| 151 | #define R6xx_ELEM_LOOP(x) (x) |
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| 152 | #define BURST_COUNT(x) (x ? (x - 1) : 0) |
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| 153 | |||
| 154 | // swiz |
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| 155 | #define SRC_SEL_X(x) (x) // SQ_SEL_* each |
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| 156 | #define SRC_SEL_Y(x) (x) |
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| 157 | #define SRC_SEL_Z(x) (x) |
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| 158 | #define SRC_SEL_W(x) (x) |
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| 159 | |||
| 160 | #define CF_DWORD0(addr) cpu_to_le32((addr)) |
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| 161 | // R7xx has another entry (COUNT3), but that is only used for adding a bit to count. |
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| 162 | // We allow one more bit for count in the argument of the macro on R7xx instead. |
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| 163 | // R6xx: [0,7] R7xx: [1,16] |
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| 164 | #define CF_DWORD1(pc, cf_const, cond, count, call_count, eop, vpm, cf_inst, wqm, b) \ |
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| 165 | cpu_to_le32((((pc) << 0) | ((cf_const) << 3) | ((cond) << 8) | (((count) & 7) << 10) | (((count) >> 3) << 19) | \ |
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| 166 | ((call_count) << 13) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31))) |
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| 167 | |||
| 168 | #define CF_ALU_DWORD0(addr, kb0, kb1, km0) cpu_to_le32((((addr) << 0) | ((kb0) << 22) | ((kb1) << 26) | ((km0) << 30))) |
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| 169 | #define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, uw, cf_inst, wqm, b) \ |
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| 170 | cpu_to_le32((((km1) << 0) | ((kcache_addr0) << 2) | ((kcache_addr1) << 10) | \ |
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| 171 | ((count) << 18) | ((uw) << 25) | ((cf_inst) << 26) | ((wqm) << 30) | ((b) << 31))) |
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| 172 | |||
| 173 | #define CF_ALLOC_IMP_EXP_DWORD0(array_base, type, rw_gpr, rr, index_gpr, es) \ |
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| 174 | cpu_to_le32((((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | ((index_gpr) << 23) | \ |
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| 175 | ((es) << 30))) |
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| 176 | // R7xx apparently doesn't have the ELEM_LOOP entry any more |
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| 177 | // We still expose it, but ELEM_LOOP is explicitely R6xx now. |
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| 178 | // TODO: is this just forgotten in the docs, or really not available any more? |
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| 179 | #define CF_ALLOC_IMP_EXP_DWORD1_BUF(array_size, comp_mask, el, bc, eop, vpm, cf_inst, wqm, b) \ |
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| 180 | cpu_to_le32((((array_size) << 0) | ((comp_mask) << 12) | ((el) << 16) | ((bc) << 17) | \ |
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| 181 | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31))) |
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| 182 | #define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, el, bc, eop, vpm, cf_inst, wqm, b) \ |
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| 183 | cpu_to_le32((((sel_x) << 0) | ((sel_y) << 3) | ((sel_z) << 6) | ((sel_w) << 9) | ((el) << 16) | \ |
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| 184 | ((bc) << 17) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | \ |
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| 185 | ((wqm) << 30) | ((b) << 31))) |
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| 186 | |||
| 187 | // ALU clause insts |
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| 188 | #define SRC0_SEL(x) (x) |
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| 189 | #define SRC1_SEL(x) (x) |
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| 190 | #define SRC2_SEL(x) (x) |
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| 191 | // src[0-2]_sel |
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| 192 | // 0-127 GPR |
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| 193 | // 128-159 kcache constants bank 0 |
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| 194 | // 160-191 kcache constants bank 1 |
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| 195 | // 248-255 special SQ_ALU_SRC_* (0, 1, etc.) |
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| 196 | #define ALU_SRC_GPR_BASE 0 |
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| 197 | #define ALU_SRC_KCACHE0_BASE 128 |
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| 198 | #define ALU_SRC_KCACHE1_BASE 160 |
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| 199 | #define ALU_SRC_CFILE_BASE 256 |
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| 200 | |||
| 201 | #define SRC0_REL(x) (x) |
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| 202 | #define SRC1_REL(x) (x) |
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| 203 | #define SRC2_REL(x) (x) |
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| 204 | // elem |
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| 205 | #define SRC0_ELEM(x) (x) |
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| 206 | #define SRC1_ELEM(x) (x) |
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| 207 | #define SRC2_ELEM(x) (x) |
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| 208 | #define ELEM_X 0 |
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| 209 | #define ELEM_Y 1 |
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| 210 | #define ELEM_Z 2 |
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| 211 | #define ELEM_W 3 |
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| 212 | // neg |
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| 213 | #define SRC0_NEG(x) (x) |
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| 214 | #define SRC1_NEG(x) (x) |
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| 215 | #define SRC2_NEG(x) (x) |
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| 216 | // im |
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| 217 | #define INDEX_MODE(x) (x) // SQ_INDEX_* |
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| 218 | // ps |
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| 219 | #define PRED_SEL(x) (x) // SQ_PRED_SEL_* |
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| 220 | // last |
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| 221 | #define LAST(x) (x) |
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| 222 | // abs |
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| 223 | #define SRC0_ABS(x) (x) |
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| 224 | #define SRC1_ABS(x) (x) |
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| 225 | // uem |
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| 226 | #define UPDATE_EXECUTE_MASK(x) (x) |
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| 227 | // up |
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| 228 | #define UPDATE_PRED(x) (x) |
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| 229 | // wm |
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| 230 | #define WRITE_MASK(x) (x) |
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| 231 | // fm |
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| 232 | #define FOG_MERGE(x) (x) |
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| 233 | // omod |
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| 234 | #define OMOD(x) (x) // SQ_ALU_OMOD_* |
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| 235 | // alu inst |
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| 236 | #define ALU_INST(x) (x) // SQ_ALU_INST_* |
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| 237 | //bs |
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| 238 | #define BANK_SWIZZLE(x) (x) // SQ_ALU_VEC_* |
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| 239 | #define DST_GPR(x) (x) |
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| 240 | #define DST_REL(x) (x) |
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| 241 | #define DST_ELEM(x) (x) |
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| 242 | #define CLAMP(x) (x) |
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| 243 | |||
| 244 | #define ALU_DWORD0(src0_sel, s0r, s0e, s0n, src1_sel, s1r, s1e, s1n, im, ps, last) \ |
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| 245 | cpu_to_le32((((src0_sel) << 0) | ((s0r) << 9) | ((s0e) << 10) | ((s0n) << 12) | \ |
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| 246 | ((src1_sel) << 13) | ((s1r) << 22) | ((s1e) << 23) | ((s1n) << 25) | \ |
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| 247 | ((im) << 26) | ((ps) << 29) | ((last) << 31))) |
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| 248 | // R7xx has alu_inst at a different slot, and no fog merge any more (no fix function fog any more) |
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| 249 | #define R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ |
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| 250 | cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \ |
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| 251 | ((fm) << 5) | ((omod) << 6) | ((alu_inst) << 8) | ((bs) << 18) | ((dst_gpr) << 21) | \ |
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| 252 | ((dr) << 28) | ((de) << 29) | ((clamp) << 31))) |
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| 253 | #define R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ |
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| 254 | cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \ |
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| 255 | ((omod) << 5) | ((alu_inst) << 7) | ((bs) << 18) | ((dst_gpr) << 21) | \ |
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| 256 | ((dr) << 28) | ((de) << 29) | ((clamp) << 31))) |
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| 257 | // This is a general chipset macro, but due to selection by chipid typically not usable in static arrays |
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| 258 | // Fog is NOT USED on R7xx, even if specified. |
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| 259 | #define ALU_DWORD1_OP2(chipfamily, s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \ |
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| 260 | ((chipfamily) < CHIP_FAMILY_RV770 ? \ |
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| 261 | R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) : \ |
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| 262 | R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp)) |
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| 263 | #define ALU_DWORD1_OP3(src2_sel, s2r, s2e, s2n, alu_inst, bs, dst_gpr, dr, de, clamp) \ |
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| 264 | cpu_to_le32((((src2_sel) << 0) | ((s2r) << 9) | ((s2e) << 10) | ((s2n) << 12) | \ |
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| 265 | ((alu_inst) << 13) | ((bs) << 18) | ((dst_gpr) << 21) | ((dr) << 28) | \ |
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| 266 | ((de) << 29) | ((clamp) << 31))) |
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| 267 | |||
| 268 | // VTX clause insts |
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| 269 | // vxt insts |
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| 270 | #define VTX_INST(x) (x) // SQ_VTX_INST_* |
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| 271 | |||
| 272 | // fetch type |
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| 273 | #define FETCH_TYPE(x) (x) // SQ_VTX_FETCH_* |
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| 274 | |||
| 275 | #define FETCH_WHOLE_QUAD(x) (x) |
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| 276 | #define BUFFER_ID(x) (x) |
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| 277 | #define SRC_GPR(x) (x) |
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| 278 | #define SRC_REL(x) (x) |
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| 279 | #define MEGA_FETCH_COUNT(x) ((x) ? ((x) - 1) : 0) |
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| 280 | |||
| 281 | #define SEMANTIC_ID(x) (x) |
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| 282 | #define DST_SEL_X(x) (x) |
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| 283 | #define DST_SEL_Y(x) (x) |
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| 284 | #define DST_SEL_Z(x) (x) |
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| 285 | #define DST_SEL_W(x) (x) |
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| 286 | #define USE_CONST_FIELDS(x) (x) |
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| 287 | #define DATA_FORMAT(x) (x) |
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| 288 | // num format |
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| 289 | #define NUM_FORMAT_ALL(x) (x) // SQ_NUM_FORMAT_* |
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| 290 | // format comp |
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| 291 | #define FORMAT_COMP_ALL(x) (x) // SQ_FORMAT_COMP_* |
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| 292 | // sma |
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| 293 | #define SRF_MODE_ALL(x) (x) |
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| 294 | #define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0 |
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| 295 | #define SRF_MODE_NO_ZERO 1 |
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| 296 | #define OFFSET(x) (x) |
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| 297 | // endian swap |
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| 298 | #define ENDIAN_SWAP(x) (x) // SQ_ENDIAN_* |
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| 299 | #define CONST_BUF_NO_STRIDE(x) (x) |
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| 300 | // mf |
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| 301 | #define MEGA_FETCH(x) (x) |
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| 302 | |||
| 303 | #define VTX_DWORD0(vtx_inst, ft, fwq, buffer_id, src_gpr, sr, ssx, mfc) \ |
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| 304 | cpu_to_le32((((vtx_inst) << 0) | ((ft) << 5) | ((fwq) << 7) | ((buffer_id) << 8) | \ |
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| 305 | ((src_gpr) << 16) | ((sr) << 23) | ((ssx) << 24) | ((mfc) << 26))) |
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| 306 | #define VTX_DWORD1_SEM(semantic_id, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \ |
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| 307 | cpu_to_le32((((semantic_id) << 0) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ |
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| 308 | ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31))) |
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| 309 | #define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \ |
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| 310 | cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ |
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| 311 | ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31))) |
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| 312 | #define VTX_DWORD2(offset, es, cbns, mf) \ |
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| 313 | cpu_to_le32((((offset) << 0) | ((es) << 16) | ((cbns) << 18) | ((mf) << 19))) |
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| 314 | #define VTX_DWORD_PAD cpu_to_le32(0x00000000) |
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| 315 | |||
| 316 | // TEX clause insts |
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| 317 | // tex insts |
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| 318 | #define TEX_INST(x) (x) // SQ_TEX_INST_* |
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| 319 | |||
| 320 | #define BC_FRAC_MODE(x) (x) |
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| 321 | #define FETCH_WHOLE_QUAD(x) (x) |
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| 322 | #define RESOURCE_ID(x) (x) |
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| 323 | #define R7xx_ALT_CONST(x) (x) |
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| 324 | |||
| 325 | #define LOD_BIAS(x) (x) |
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| 326 | //ct |
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| 327 | #define COORD_TYPE_X(x) (x) |
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| 328 | #define COORD_TYPE_Y(x) (x) |
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| 329 | #define COORD_TYPE_Z(x) (x) |
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| 330 | #define COORD_TYPE_W(x) (x) |
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| 331 | #define TEX_UNNORMALIZED 0 |
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| 332 | #define TEX_NORMALIZED 1 |
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| 333 | #define OFFSET_X(x) (((int)(x) * 2) & 0x1f) /* 4:1-bits 2's-complement fixed-point: [-8.0..7.5] */ |
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| 334 | #define OFFSET_Y(x) (((int)(x) * 2) & 0x1f) |
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| 335 | #define OFFSET_Z(x) (((int)(x) * 2) & 0x1f) |
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| 336 | #define SAMPLER_ID(x) (x) |
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| 337 | |||
| 338 | // R7xx has an additional parameter ALT_CONST. We always expose it, but ALT_CONST is R7xx only |
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| 339 | #define TEX_DWORD0(tex_inst, bfm, fwq, resource_id, src_gpr, sr, ac) \ |
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| 340 | cpu_to_le32((((tex_inst) << 0) | ((bfm) << 5) | ((fwq) << 7) | ((resource_id) << 8) | \ |
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| 341 | ((src_gpr) << 16) | ((sr) << 23) | ((ac) << 24))) |
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| 342 | #define TEX_DWORD1(dst_gpr, dr, dsx, dsy, dsz, dsw, lod_bias, ctx, cty, ctz, ctw) \ |
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| 343 | cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \ |
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| 344 | ((lod_bias) << 21) | ((ctx) << 28) | ((cty) << 29) | ((ctz) << 30) | ((ctw) << 31))) |
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| 345 | #define TEX_DWORD2(offset_x, offset_y, offset_z, sampler_id, ssx, ssy, ssz, ssw) \ |
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| 346 | cpu_to_le32((((offset_x) << 0) | ((offset_y) << 5) | ((offset_z) << 10) | ((sampler_id) << 15) | \ |
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| 347 | ((ssx) << 20) | ((ssy) << 23) | ((ssz) << 26) | ((ssw) << 29))) |
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| 348 | #define TEX_DWORD_PAD cpu_to_le32(0x00000000) |
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| 349 | |||
| 350 | #endif |