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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1428 | serge | 1 | /* |
| 2 | * RadeonHD R6xx, R7xx Register documentation |
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| 3 | * |
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| 4 | * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. |
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| 5 | * Copyright (C) 2008-2009 Matthias Hopf |
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| 6 | * |
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| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 8 | * copy of this software and associated documentation files (the "Software"), |
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| 9 | * to deal in the Software without restriction, including without limitation |
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| 10 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 11 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 12 | * Software is furnished to do so, subject to the following conditions: |
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| 13 | * |
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| 14 | * The above copyright notice and this permission notice shall be included |
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| 15 | * in all copies or substantial portions of the Software. |
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| 16 | * |
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| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 20 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 21 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 22 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | */ |
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| 24 | |||
| 25 | #ifndef _R600_REG_R6xx_H_ |
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| 26 | #define _R600_REG_R6xx_H_ |
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| 27 | |||
| 28 | /* |
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| 29 | * Registers for R6xx chips that are not documented yet |
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| 30 | */ |
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| 31 | |||
| 32 | enum { |
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| 33 | |||
| 34 | MM_INDEX = 0x0000, |
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| 35 | MM_DATA = 0x0004, |
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| 36 | |||
| 37 | SRBM_STATUS = 0x0e50, |
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| 38 | RLC_RQ_PENDING_bit = 1 << 3, |
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| 39 | RCU_RQ_PENDING_bit = 1 << 4, |
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| 40 | GRBM_RQ_PENDING_bit = 1 << 5, |
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| 41 | HI_RQ_PENDING_bit = 1 << 6, |
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| 42 | IO_EXTERN_SIGNAL_bit = 1 << 7, |
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| 43 | VMC_BUSY_bit = 1 << 8, |
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| 44 | MCB_BUSY_bit = 1 << 9, |
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| 45 | MCDZ_BUSY_bit = 1 << 10, |
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| 46 | MCDY_BUSY_bit = 1 << 11, |
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| 47 | MCDX_BUSY_bit = 1 << 12, |
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| 48 | MCDW_BUSY_bit = 1 << 13, |
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| 49 | SEM_BUSY_bit = 1 << 14, |
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| 50 | SRBM_STATUS__RLC_BUSY_bit = 1 << 15, |
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| 51 | PDMA_BUSY_bit = 1 << 16, |
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| 52 | IH_BUSY_bit = 1 << 17, |
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| 53 | CSC_BUSY_bit = 1 << 20, |
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| 54 | CMC7_BUSY_bit = 1 << 21, |
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| 55 | CMC6_BUSY_bit = 1 << 22, |
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| 56 | CMC5_BUSY_bit = 1 << 23, |
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| 57 | CMC4_BUSY_bit = 1 << 24, |
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| 58 | CMC3_BUSY_bit = 1 << 25, |
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| 59 | CMC2_BUSY_bit = 1 << 26, |
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| 60 | CMC1_BUSY_bit = 1 << 27, |
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| 61 | CMC0_BUSY_bit = 1 << 28, |
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| 62 | BIF_BUSY_bit = 1 << 29, |
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| 63 | IDCT_BUSY_bit = 1 << 30, |
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| 64 | |||
| 65 | SRBM_READ_ERROR = 0x0e98, |
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| 66 | READ_ADDRESS_mask = 0xffff << 2, |
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| 67 | READ_ADDRESS_shift = 2, |
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| 68 | READ_REQUESTER_HI_bit = 1 << 24, |
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| 69 | READ_REQUESTER_GRBM_bit = 1 << 25, |
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| 70 | READ_REQUESTER_RCU_bit = 1 << 26, |
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| 71 | READ_REQUESTER_RLC_bit = 1 << 27, |
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| 72 | READ_ERROR_bit = 1 << 31, |
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| 73 | |||
| 74 | SRBM_INT_STATUS = 0x0ea4, |
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| 75 | RDERR_INT_STAT_bit = 1 << 0, |
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| 76 | GFX_CNTX_SWITCH_INT_STAT_bit = 1 << 1, |
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| 77 | SRBM_INT_ACK = 0x0ea8, |
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| 78 | RDERR_INT_ACK_bit = 1 << 0, |
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| 79 | GFX_CNTX_SWITCH_INT_ACK_bit = 1 << 1, |
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| 80 | |||
| 81 | /* R6XX_MC_VM_FB_LOCATION = 0x2180, */ |
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| 82 | |||
| 83 | VENDOR_DEVICE_ID = 0x4000, |
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| 84 | |||
| 85 | HDP_MEM_COHERENCY_FLUSH_CNTL = 0x5480, |
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| 86 | |||
| 87 | /* D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110, */ |
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| 88 | /* D1GRPH_PITCH = 0x6120, */ |
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| 89 | /* D1GRPH_Y_END = 0x6138, */ |
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| 90 | |||
| 91 | GRBM_STATUS = 0x8010, |
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| 92 | R600_CMDFIFO_AVAIL_mask = 0x1f << 0, |
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| 93 | R700_CMDFIFO_AVAIL_mask = 0xf << 0, |
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| 94 | CMDFIFO_AVAIL_shift = 0, |
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| 95 | SRBM_RQ_PENDING_bit = 1 << 5, |
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| 96 | CP_RQ_PENDING_bit = 1 << 6, |
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| 97 | CF_RQ_PENDING_bit = 1 << 7, |
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| 98 | PF_RQ_PENDING_bit = 1 << 8, |
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| 99 | GRBM_EE_BUSY_bit = 1 << 10, |
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| 100 | GRBM_STATUS__VC_BUSY_bit = 1 << 11, |
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| 101 | DB03_CLEAN_bit = 1 << 12, |
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| 102 | CB03_CLEAN_bit = 1 << 13, |
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| 103 | VGT_BUSY_NO_DMA_bit = 1 << 16, |
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| 104 | GRBM_STATUS__VGT_BUSY_bit = 1 << 17, |
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| 105 | TA03_BUSY_bit = 1 << 18, |
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| 106 | GRBM_STATUS__TC_BUSY_bit = 1 << 19, |
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| 107 | SX_BUSY_bit = 1 << 20, |
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| 108 | SH_BUSY_bit = 1 << 21, |
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| 109 | SPI03_BUSY_bit = 1 << 22, |
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| 110 | SMX_BUSY_bit = 1 << 23, |
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| 111 | SC_BUSY_bit = 1 << 24, |
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| 112 | PA_BUSY_bit = 1 << 25, |
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| 113 | DB03_BUSY_bit = 1 << 26, |
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| 114 | CR_BUSY_bit = 1 << 27, |
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| 115 | CP_COHERENCY_BUSY_bit = 1 << 28, |
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| 116 | GRBM_STATUS__CP_BUSY_bit = 1 << 29, |
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| 117 | CB03_BUSY_bit = 1 << 30, |
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| 118 | GUI_ACTIVE_bit = 1 << 31, |
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| 119 | GRBM_STATUS2 = 0x8014, |
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| 120 | CR_CLEAN_bit = 1 << 0, |
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| 121 | SMX_CLEAN_bit = 1 << 1, |
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| 122 | SPI0_BUSY_bit = 1 << 8, |
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| 123 | SPI1_BUSY_bit = 1 << 9, |
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| 124 | SPI2_BUSY_bit = 1 << 10, |
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| 125 | SPI3_BUSY_bit = 1 << 11, |
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| 126 | TA0_BUSY_bit = 1 << 12, |
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| 127 | TA1_BUSY_bit = 1 << 13, |
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| 128 | TA2_BUSY_bit = 1 << 14, |
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| 129 | TA3_BUSY_bit = 1 << 15, |
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| 130 | DB0_BUSY_bit = 1 << 16, |
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| 131 | DB1_BUSY_bit = 1 << 17, |
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| 132 | DB2_BUSY_bit = 1 << 18, |
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| 133 | DB3_BUSY_bit = 1 << 19, |
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| 134 | CB0_BUSY_bit = 1 << 20, |
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| 135 | CB1_BUSY_bit = 1 << 21, |
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| 136 | CB2_BUSY_bit = 1 << 22, |
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| 137 | CB3_BUSY_bit = 1 << 23, |
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| 138 | GRBM_SOFT_RESET = 0x8020, |
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| 139 | SOFT_RESET_CP_bit = 1 << 0, |
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| 140 | SOFT_RESET_CB_bit = 1 << 1, |
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| 141 | SOFT_RESET_CR_bit = 1 << 2, |
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| 142 | SOFT_RESET_DB_bit = 1 << 3, |
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| 143 | SOFT_RESET_PA_bit = 1 << 5, |
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| 144 | SOFT_RESET_SC_bit = 1 << 6, |
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| 145 | SOFT_RESET_SMX_bit = 1 << 7, |
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| 146 | SOFT_RESET_SPI_bit = 1 << 8, |
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| 147 | SOFT_RESET_SH_bit = 1 << 9, |
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| 148 | SOFT_RESET_SX_bit = 1 << 10, |
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| 149 | SOFT_RESET_TC_bit = 1 << 11, |
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| 150 | SOFT_RESET_TA_bit = 1 << 12, |
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| 151 | SOFT_RESET_VC_bit = 1 << 13, |
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| 152 | SOFT_RESET_VGT_bit = 1 << 14, |
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| 153 | SOFT_RESET_GRBM_GCA_bit = 1 << 15, |
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| 154 | |||
| 155 | WAIT_UNTIL = 0x8040, |
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| 156 | WAIT_CP_DMA_IDLE_bit = 1 << 8, |
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| 157 | WAIT_CMDFIFO_bit = 1 << 10, |
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| 158 | WAIT_2D_IDLE_bit = 1 << 14, |
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| 159 | WAIT_3D_IDLE_bit = 1 << 15, |
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| 160 | WAIT_2D_IDLECLEAN_bit = 1 << 16, |
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| 161 | WAIT_3D_IDLECLEAN_bit = 1 << 17, |
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| 162 | WAIT_EXTERN_SIG_bit = 1 << 19, |
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| 163 | CMDFIFO_ENTRIES_mask = 0x1f << 20, |
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| 164 | CMDFIFO_ENTRIES_shift = 20, |
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| 165 | |||
| 166 | GRBM_READ_ERROR = 0x8058, |
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| 167 | /* READ_ADDRESS_mask = 0xffff << 2, */ |
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| 168 | /* READ_ADDRESS_shift = 2, */ |
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| 169 | READ_REQUESTER_SRBM_bit = 1 << 28, |
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| 170 | READ_REQUESTER_CP_bit = 1 << 29, |
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| 171 | READ_REQUESTER_WU_POLL_bit = 1 << 30, |
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| 172 | /* READ_ERROR_bit = 1 << 31, */ |
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| 173 | |||
| 174 | SCRATCH_REG0 = 0x8500, |
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| 175 | SCRATCH_REG1 = 0x8504, |
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| 176 | SCRATCH_REG2 = 0x8508, |
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| 177 | SCRATCH_REG3 = 0x850c, |
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| 178 | SCRATCH_REG4 = 0x8510, |
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| 179 | SCRATCH_REG5 = 0x8514, |
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| 180 | SCRATCH_REG6 = 0x8518, |
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| 181 | SCRATCH_REG7 = 0x851c, |
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| 182 | SCRATCH_UMSK = 0x8540, |
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| 183 | SCRATCH_ADDR = 0x8544, |
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| 184 | |||
| 185 | CP_COHER_CNTL = 0x85f0, |
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| 186 | DEST_BASE_0_ENA_bit = 1 << 0, |
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| 187 | DEST_BASE_1_ENA_bit = 1 << 1, |
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| 188 | SO0_DEST_BASE_ENA_bit = 1 << 2, |
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| 189 | SO1_DEST_BASE_ENA_bit = 1 << 3, |
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| 190 | SO2_DEST_BASE_ENA_bit = 1 << 4, |
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| 191 | SO3_DEST_BASE_ENA_bit = 1 << 5, |
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| 192 | CB0_DEST_BASE_ENA_bit = 1 << 6, |
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| 193 | CB1_DEST_BASE_ENA_bit = 1 << 7, |
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| 194 | CB2_DEST_BASE_ENA_bit = 1 << 8, |
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| 195 | CB3_DEST_BASE_ENA_bit = 1 << 9, |
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| 196 | CB4_DEST_BASE_ENA_bit = 1 << 10, |
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| 197 | CB5_DEST_BASE_ENA_bit = 1 << 11, |
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| 198 | CB6_DEST_BASE_ENA_bit = 1 << 12, |
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| 199 | CB7_DEST_BASE_ENA_bit = 1 << 13, |
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| 200 | DB_DEST_BASE_ENA_bit = 1 << 14, |
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| 201 | CR_DEST_BASE_ENA_bit = 1 << 15, |
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| 202 | TC_ACTION_ENA_bit = 1 << 23, |
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| 203 | VC_ACTION_ENA_bit = 1 << 24, |
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| 204 | CB_ACTION_ENA_bit = 1 << 25, |
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| 205 | DB_ACTION_ENA_bit = 1 << 26, |
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| 206 | SH_ACTION_ENA_bit = 1 << 27, |
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| 207 | SMX_ACTION_ENA_bit = 1 << 28, |
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| 208 | CR0_ACTION_ENA_bit = 1 << 29, |
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| 209 | CR1_ACTION_ENA_bit = 1 << 30, |
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| 210 | CR2_ACTION_ENA_bit = 1 << 31, |
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| 211 | CP_COHER_SIZE = 0x85f4, |
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| 212 | CP_COHER_BASE = 0x85f8, |
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| 213 | CP_COHER_STATUS = 0x85fc, |
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| 214 | MATCHING_GFX_CNTX_mask = 0xff << 0, |
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| 215 | MATCHING_GFX_CNTX_shift = 0, |
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| 216 | MATCHING_CR_CNTX_mask = 0xffff << 8, |
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| 217 | MATCHING_CR_CNTX_shift = 8, |
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| 218 | STATUS_bit = 1 << 31, |
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| 219 | |||
| 220 | CP_STALLED_STAT1 = 0x8674, |
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| 221 | RBIU_TO_DMA_NOT_RDY_TO_RCV_bit = 1 << 0, |
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| 222 | RBIU_TO_IBS_NOT_RDY_TO_RCV_bit = 1 << 1, |
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| 223 | RBIU_TO_SEM_NOT_RDY_TO_RCV_bit = 1 << 2, |
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| 224 | RBIU_TO_2DREGS_NOT_RDY_TO_RCV_bit = 1 << 3, |
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| 225 | RBIU_TO_MEMWR_NOT_RDY_TO_RCV_bit = 1 << 4, |
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| 226 | RBIU_TO_MEMRD_NOT_RDY_TO_RCV_bit = 1 << 5, |
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| 227 | RBIU_TO_EOPD_NOT_RDY_TO_RCV_bit = 1 << 6, |
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| 228 | RBIU_TO_RECT_NOT_RDY_TO_RCV_bit = 1 << 7, |
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| 229 | RBIU_TO_STRMO_NOT_RDY_TO_RCV_bit = 1 << 8, |
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| 230 | RBIU_TO_PSTAT_NOT_RDY_TO_RCV_bit = 1 << 9, |
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| 231 | MIU_WAITING_ON_RDREQ_FREE_bit = 1 << 16, |
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| 232 | MIU_WAITING_ON_WRREQ_FREE_bit = 1 << 17, |
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| 233 | MIU_NEEDS_AVAIL_WRREQ_PHASE_bit = 1 << 18, |
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| 234 | RCIU_WAITING_ON_GRBM_FREE_bit = 1 << 24, |
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| 235 | RCIU_WAITING_ON_VGT_FREE_bit = 1 << 25, |
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| 236 | RCIU_STALLED_ON_ME_READ_bit = 1 << 26, |
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| 237 | RCIU_STALLED_ON_DMA_READ_bit = 1 << 27, |
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| 238 | RCIU_HALTED_BY_REG_VIOLATION_bit = 1 << 28, |
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| 239 | CP_STALLED_STAT2 = 0x8678, |
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| 240 | PFP_TO_CSF_NOT_RDY_TO_RCV_bit = 1 << 0, |
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| 241 | PFP_TO_MEQ_NOT_RDY_TO_RCV_bit = 1 << 1, |
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| 242 | PFP_TO_VGT_NOT_RDY_TO_RCV_bit = 1 << 2, |
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| 243 | PFP_HALTED_BY_INSTR_VIOLATION_bit = 1 << 3, |
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| 244 | MULTIPASS_IB_PENDING_IN_PFP_bit = 1 << 4, |
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| 245 | ME_BRUSH_WC_NOT_RDY_TO_RCV_bit = 1 << 8, |
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| 246 | ME_STALLED_ON_BRUSH_LOGIC_bit = 1 << 9, |
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| 247 | CR_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 10, |
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| 248 | GFX_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 11, |
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| 249 | ME_RCIU_NOT_RDY_TO_RCV_bit = 1 << 12, |
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| 250 | ME_TO_CONST_NOT_RDY_TO_RCV_bit = 1 << 13, |
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| 251 | ME_WAITING_DATA_FROM_PFP_bit = 1 << 14, |
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| 252 | ME_WAITING_ON_PARTIAL_FLUSH_bit = 1 << 15, |
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| 253 | RECT_FIFO_NEEDS_CR_RECT_DONE_bit = 1 << 16, |
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| 254 | RECT_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 17, |
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| 255 | EOPD_FIFO_NEEDS_SC_EOP_DONE_bit = 1 << 18, |
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| 256 | EOPD_FIFO_NEEDS_SMX_EOP_DONE_bit = 1 << 19, |
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| 257 | EOPD_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 20, |
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| 258 | EOPD_FIFO_NEEDS_SIGNAL_SEM_bit = 1 << 21, |
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| 259 | SO_NUMPRIM_FIFO_NEEDS_SOADDR_bit = 1 << 22, |
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| 260 | SO_NUMPRIM_FIFO_NEEDS_NUMPRIM_bit = 1 << 23, |
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| 261 | PIPE_STATS_FIFO_NEEDS_SAMPLE_bit = 1 << 24, |
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| 262 | SURF_SYNC_NEEDS_IDLE_CNTXS_bit = 1 << 30, |
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| 263 | SURF_SYNC_NEEDS_ALL_CLEAN_bit = 1 << 31, |
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| 264 | CP_BUSY_STAT = 0x867c, |
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| 265 | REG_BUS_FIFO_BUSY_bit = 1 << 0, |
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| 266 | RING_FETCHING_DATA_bit = 1 << 1, |
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| 267 | INDR1_FETCHING_DATA_bit = 1 << 2, |
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| 268 | INDR2_FETCHING_DATA_bit = 1 << 3, |
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| 269 | STATE_FETCHING_DATA_bit = 1 << 4, |
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| 270 | PRED_FETCHING_DATA_bit = 1 << 5, |
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| 271 | COHER_CNTR_NEQ_ZERO_bit = 1 << 6, |
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| 272 | PFP_PARSING_PACKETS_bit = 1 << 7, |
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| 273 | ME_PARSING_PACKETS_bit = 1 << 8, |
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| 274 | RCIU_PFP_BUSY_bit = 1 << 9, |
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| 275 | RCIU_ME_BUSY_bit = 1 << 10, |
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| 276 | OUTSTANDING_READ_TAGS_bit = 1 << 11, |
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| 277 | SEM_CMDFIFO_NOT_EMPTY_bit = 1 << 12, |
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| 278 | SEM_FAILED_AND_HOLDING_bit = 1 << 13, |
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| 279 | SEM_POLLING_FOR_PASS_bit = 1 << 14, |
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| 280 | _3D_BUSY_bit = 1 << 15, |
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| 281 | _2D_BUSY_bit = 1 << 16, |
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| 282 | CP_STAT = 0x8680, |
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| 283 | CSF_RING_BUSY_bit = 1 << 0, |
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| 284 | CSF_WPTR_POLL_BUSY_bit = 1 << 1, |
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| 285 | CSF_INDIRECT1_BUSY_bit = 1 << 2, |
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| 286 | CSF_INDIRECT2_BUSY_bit = 1 << 3, |
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| 287 | CSF_STATE_BUSY_bit = 1 << 4, |
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| 288 | CSF_PREDICATE_BUSY_bit = 1 << 5, |
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| 289 | CSF_BUSY_bit = 1 << 6, |
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| 290 | MIU_RDREQ_BUSY_bit = 1 << 7, |
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| 291 | MIU_WRREQ_BUSY_bit = 1 << 8, |
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| 292 | ROQ_RING_BUSY_bit = 1 << 9, |
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| 293 | ROQ_INDIRECT1_BUSY_bit = 1 << 10, |
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| 294 | ROQ_INDIRECT2_BUSY_bit = 1 << 11, |
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| 295 | ROQ_STATE_BUSY_bit = 1 << 12, |
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| 296 | ROQ_PREDICATE_BUSY_bit = 1 << 13, |
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| 297 | ROQ_ALIGN_BUSY_bit = 1 << 14, |
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| 298 | PFP_BUSY_bit = 1 << 15, |
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| 299 | MEQ_BUSY_bit = 1 << 16, |
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| 300 | ME_BUSY_bit = 1 << 17, |
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| 301 | QUERY_BUSY_bit = 1 << 18, |
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| 302 | SEMAPHORE_BUSY_bit = 1 << 19, |
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| 303 | INTERRUPT_BUSY_bit = 1 << 20, |
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| 304 | SURFACE_SYNC_BUSY_bit = 1 << 21, |
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| 305 | DMA_BUSY_bit = 1 << 22, |
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| 306 | RCIU_BUSY_bit = 1 << 23, |
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| 307 | CP_STAT__CP_BUSY_bit = 1 << 31, |
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| 308 | |||
| 309 | CP_ME_CNTL = 0x86d8, |
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| 310 | ME_STATMUX_mask = 0xff << 0, |
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| 311 | ME_STATMUX_shift = 0, |
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| 312 | ME_HALT_bit = 1 << 28, |
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| 313 | CP_ME_STATUS = 0x86dc, |
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| 314 | |||
| 315 | CP_RB_RPTR = 0x8700, |
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| 316 | RB_RPTR_mask = 0xfffff << 0, |
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| 317 | RB_RPTR_shift = 0, |
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| 318 | CP_RB_WPTR_DELAY = 0x8704, |
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| 319 | PRE_WRITE_TIMER_mask = 0xfffffff << 0, |
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| 320 | PRE_WRITE_TIMER_shift = 0, |
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| 321 | PRE_WRITE_LIMIT_mask = 0x0f << 28, |
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| 322 | PRE_WRITE_LIMIT_shift = 28, |
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| 323 | |||
| 324 | CP_ROQ_RB_STAT = 0x8780, |
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| 325 | ROQ_RPTR_PRIMARY_mask = 0x3ff << 0, |
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| 326 | ROQ_RPTR_PRIMARY_shift = 0, |
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| 327 | ROQ_WPTR_PRIMARY_mask = 0x3ff << 16, |
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| 328 | ROQ_WPTR_PRIMARY_shift = 16, |
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| 329 | CP_ROQ_IB1_STAT = 0x8784, |
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| 330 | ROQ_RPTR_INDIRECT1_mask = 0x3ff << 0, |
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| 331 | ROQ_RPTR_INDIRECT1_shift = 0, |
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| 332 | ROQ_WPTR_INDIRECT1_mask = 0x3ff << 16, |
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| 333 | ROQ_WPTR_INDIRECT1_shift = 16, |
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| 334 | CP_ROQ_IB2_STAT = 0x8788, |
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| 335 | ROQ_RPTR_INDIRECT2_mask = 0x3ff << 0, |
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| 336 | ROQ_RPTR_INDIRECT2_shift = 0, |
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| 337 | ROQ_WPTR_INDIRECT2_mask = 0x3ff << 16, |
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| 338 | ROQ_WPTR_INDIRECT2_shift = 16, |
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| 339 | |||
| 340 | CP_MEQ_STAT = 0x8794, |
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| 341 | MEQ_RPTR_mask = 0x3ff << 0, |
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| 342 | MEQ_RPTR_shift = 0, |
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| 343 | MEQ_WPTR_mask = 0x3ff << 16, |
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| 344 | MEQ_WPTR_shift = 16, |
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| 345 | |||
| 346 | CC_GC_SHADER_PIPE_CONFIG = 0x8950, |
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| 347 | INACTIVE_QD_PIPES_mask = 0xff << 8, |
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| 348 | INACTIVE_QD_PIPES_shift = 8, |
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| 349 | R6XX_MAX_QD_PIPES = 8, |
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| 350 | INACTIVE_SIMDS_mask = 0xff << 16, |
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| 351 | INACTIVE_SIMDS_shift = 16, |
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| 352 | R6XX_MAX_SIMDS = 8, |
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| 353 | GC_USER_SHADER_PIPE_CONFIG = 0x8954, |
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| 354 | |||
| 355 | VC_ENHANCE = 0x9714, |
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| 356 | DB_DEBUG = 0x9830, |
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| 357 | PREZ_MUST_WAIT_FOR_POSTZ_DONE = 1 << 31, |
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| 358 | |||
| 359 | DB_WATERMARKS = 0x00009838, |
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| 360 | DEPTH_FREE_mask = 0x1f << 0, |
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| 361 | DEPTH_FREE_shift = 0, |
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| 362 | DEPTH_FLUSH_mask = 0x3f << 5, |
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| 363 | DEPTH_FLUSH_shift = 5, |
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| 364 | FORCE_SUMMARIZE_mask = 0x0f << 11, |
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| 365 | FORCE_SUMMARIZE_shift = 11, |
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| 366 | DEPTH_PENDING_FREE_mask = 0x1f << 15, |
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| 367 | DEPTH_PENDING_FREE_shift = 15, |
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| 368 | DEPTH_CACHELINE_FREE_mask = 0x1f << 20, |
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| 369 | DEPTH_CACHELINE_FREE_shift = 20, |
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| 370 | EARLY_Z_PANIC_DISABLE_bit = 1 << 25, |
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| 371 | LATE_Z_PANIC_DISABLE_bit = 1 << 26, |
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| 372 | RE_Z_PANIC_DISABLE_bit = 1 << 27, |
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| 373 | DB_EXTRA_DEBUG_mask = 0x0f << 28, |
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| 374 | DB_EXTRA_DEBUG_shift = 28, |
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| 375 | |||
| 376 | CP_RB_BASE = 0xc100, |
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| 377 | CP_RB_CNTL = 0xc104, |
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| 378 | RB_BUFSZ_mask = 0x3f << 0, |
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| 379 | CP_RB_WPTR = 0xc114, |
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| 380 | RB_WPTR_mask = 0xfffff << 0, |
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| 381 | RB_WPTR_shift = 0, |
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| 382 | CP_RB_RPTR_WR = 0xc108, |
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| 383 | RB_RPTR_WR_mask = 0xfffff << 0, |
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| 384 | RB_RPTR_WR_shift = 0, |
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| 385 | |||
| 386 | CP_INT_STATUS = 0xc128, |
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| 387 | DISABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 0, |
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| 388 | ENABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 1, |
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| 389 | SEM_SIGNAL_INT_STAT_bit = 1 << 18, |
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| 390 | CNTX_BUSY_INT_STAT_bit = 1 << 19, |
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| 391 | CNTX_EMPTY_INT_STAT_bit = 1 << 20, |
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| 392 | WAITMEM_SEM_INT_STAT_bit = 1 << 21, |
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| 393 | PRIV_INSTR_INT_STAT_bit = 1 << 22, |
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| 394 | PRIV_REG_INT_STAT_bit = 1 << 23, |
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| 395 | OPCODE_ERROR_INT_STAT_bit = 1 << 24, |
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| 396 | SCRATCH_INT_STAT_bit = 1 << 25, |
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| 397 | TIME_STAMP_INT_STAT_bit = 1 << 26, |
||
| 398 | RESERVED_BIT_ERROR_INT_STAT_bit = 1 << 27, |
||
| 399 | DMA_INT_STAT_bit = 1 << 28, |
||
| 400 | IB2_INT_STAT_bit = 1 << 29, |
||
| 401 | IB1_INT_STAT_bit = 1 << 30, |
||
| 402 | RB_INT_STAT_bit = 1 << 31, |
||
| 403 | |||
| 404 | /* SX_ALPHA_TEST_CONTROL = 0x00028410, */ |
||
| 405 | ALPHA_FUNC__REF_NEVER = 0, |
||
| 406 | ALPHA_FUNC__REF_ALWAYS = 7, |
||
| 407 | /* DB_SHADER_CONTROL = 0x0002880c, */ |
||
| 408 | Z_ORDER__EARLY_Z_THEN_LATE_Z = 2, |
||
| 409 | /* PA_SU_SC_MODE_CNTL = 0x00028814, */ |
||
| 410 | /* POLY_MODE_mask = 0x03 << 3, */ |
||
| 411 | POLY_MODE__TRIANGLES = 0, POLY_MODE__DUAL_MODE, |
||
| 412 | /* POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, */ |
||
| 413 | POLYMODE_PTYPE__POINTS = 0, POLYMODE_PTYPE__LINES, POLYMODE_PTYPE__TRIANGLES, |
||
| 414 | PA_SC_AA_SAMPLE_LOCS_8S_WD1_M = 0x00028c20, |
||
| 415 | DB_SRESULTS_COMPARE_STATE0 = 0x00028d28, /* See autoregs: DB_SRESULTS_COMPARE_STATE1 */ |
||
| 416 | /* DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c, */ |
||
| 417 | DB_ALPHA_TO_MASK = 0x00028d44, |
||
| 418 | ALPHA_TO_MASK_ENABLE = 1 << 0, |
||
| 419 | ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8, |
||
| 420 | ALPHA_TO_MASK_OFFSET0_shift = 8, |
||
| 421 | ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 8, |
||
| 422 | ALPHA_TO_MASK_OFFSET1_shift = 10, |
||
| 423 | ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 8, |
||
| 424 | ALPHA_TO_MASK_OFFSET2_shift = 12, |
||
| 425 | ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 8, |
||
| 426 | ALPHA_TO_MASK_OFFSET3_shift = 14, |
||
| 427 | |||
| 428 | /* SQ_VTX_CONSTANT_WORD2_0 = 0x00038008, */ |
||
| 429 | /* SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, */ |
||
| 430 | FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2, |
||
| 431 | FMT_16=5, FMT_16_FLOAT, FMT_8_8, |
||
| 432 | FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4, |
||
| 433 | FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16, |
||
| 434 | FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8, |
||
| 435 | FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10, |
||
| 436 | FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2, |
||
| 437 | FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16, |
||
| 438 | FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT, |
||
| 439 | FMT_1 = 37, FMT_GB_GR=39, |
||
| 440 | FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP, |
||
| 441 | FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32, |
||
| 442 | FMT_32_32_32_FLOAT=48, |
||
| 443 | |||
| 444 | /* High level register file lengths */ |
||
| 445 | SQ_ALU_CONSTANT = SQ_ALU_CONSTANT0_0, /* 256 PS, 256 VS */ |
||
| 446 | SQ_ALU_CONSTANT_ps_num = 256, |
||
| 447 | SQ_ALU_CONSTANT_vs_num = 256, |
||
| 448 | SQ_ALU_CONSTANT_all_num = 512, |
||
| 449 | SQ_ALU_CONSTANT_offset = 16, |
||
| 450 | SQ_ALU_CONSTANT_ps = 0, |
||
| 451 | SQ_ALU_CONSTANT_vs = SQ_ALU_CONSTANT_ps + SQ_ALU_CONSTANT_ps_num, |
||
| 452 | SQ_TEX_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */ |
||
| 453 | SQ_TEX_RESOURCE_ps_num = 160, |
||
| 454 | SQ_TEX_RESOURCE_vs_num = 160, |
||
| 455 | SQ_TEX_RESOURCE_fs_num = 16, |
||
| 456 | SQ_TEX_RESOURCE_gs_num = 160, |
||
| 457 | SQ_TEX_RESOURCE_all_num = 496, |
||
| 458 | SQ_TEX_RESOURCE_offset = 28, |
||
| 459 | SQ_TEX_RESOURCE_ps = 0, |
||
| 460 | SQ_TEX_RESOURCE_vs = SQ_TEX_RESOURCE_ps + SQ_TEX_RESOURCE_ps_num, |
||
| 461 | SQ_TEX_RESOURCE_fs = SQ_TEX_RESOURCE_vs + SQ_TEX_RESOURCE_vs_num, |
||
| 462 | SQ_TEX_RESOURCE_gs = SQ_TEX_RESOURCE_fs + SQ_TEX_RESOURCE_fs_num, |
||
| 463 | SQ_VTX_RESOURCE = SQ_VTX_CONSTANT_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */ |
||
| 464 | SQ_VTX_RESOURCE_ps_num = 160, |
||
| 465 | SQ_VTX_RESOURCE_vs_num = 160, |
||
| 466 | SQ_VTX_RESOURCE_fs_num = 16, |
||
| 467 | SQ_VTX_RESOURCE_gs_num = 160, |
||
| 468 | SQ_VTX_RESOURCE_all_num = 496, |
||
| 469 | SQ_VTX_RESOURCE_offset = 28, |
||
| 470 | SQ_VTX_RESOURCE_ps = 0, |
||
| 471 | SQ_VTX_RESOURCE_vs = SQ_VTX_RESOURCE_ps + SQ_VTX_RESOURCE_ps_num, |
||
| 472 | SQ_VTX_RESOURCE_fs = SQ_VTX_RESOURCE_vs + SQ_VTX_RESOURCE_vs_num, |
||
| 473 | SQ_VTX_RESOURCE_gs = SQ_VTX_RESOURCE_fs + SQ_VTX_RESOURCE_fs_num, |
||
| 474 | SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, /* 18 per PS, VS, GS */ |
||
| 475 | SQ_TEX_SAMPLER_WORD_ps_num = 18, |
||
| 476 | SQ_TEX_SAMPLER_WORD_vs_num = 18, |
||
| 477 | SQ_TEX_SAMPLER_WORD_gs_num = 18, |
||
| 478 | SQ_TEX_SAMPLER_WORD_all_num = 54, |
||
| 479 | SQ_TEX_SAMPLER_WORD_offset = 12, |
||
| 480 | SQ_TEX_SAMPLER_WORD_ps = 0, |
||
| 481 | SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num, |
||
| 482 | SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num, |
||
| 483 | SQ_LOOP_CONST = SQ_LOOP_CONST_0, /* 32 per PS, VS, GS */ |
||
| 484 | SQ_LOOP_CONST_ps_num = 32, |
||
| 485 | SQ_LOOP_CONST_vs_num = 32, |
||
| 486 | SQ_LOOP_CONST_gs_num = 32, |
||
| 487 | SQ_LOOP_CONST_all_num = 96, |
||
| 488 | SQ_LOOP_CONST_offset = 4, |
||
| 489 | SQ_LOOP_CONST_ps = 0, |
||
| 490 | SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num, |
||
| 491 | SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num, |
||
| 492 | SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits per PS, VS, GS */ |
||
| 493 | SQ_BOOL_CONST_ps_num = 1, |
||
| 494 | SQ_BOOL_CONST_vs_num = 1, |
||
| 495 | SQ_BOOL_CONST_gs_num = 1, |
||
| 496 | SQ_BOOL_CONST_all_num = 3, |
||
| 497 | SQ_BOOL_CONST_offset = 4, |
||
| 498 | SQ_BOOL_CONST_ps = 0, |
||
| 499 | SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num, |
||
| 500 | SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num |
||
| 501 | }; |
||
| 502 | |||
| 503 | |||
| 504 | #endif |