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Rev | Author | Line No. | Line |
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1403 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Christian König. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Christian König |
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25 | */ |
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3764 | Serge | 26 | #include |
2997 | Serge | 27 | #include |
28 | #include |
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1403 | serge | 29 | #include "radeon.h" |
1963 | serge | 30 | #include "radeon_asic.h" |
2997 | Serge | 31 | #include "r600d.h" |
1403 | serge | 32 | #include "atom.h" |
33 | |||
34 | /* |
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35 | * HDMI color format |
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36 | */ |
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37 | enum r600_hdmi_color_format { |
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38 | RGB = 0, |
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39 | YCC_422 = 1, |
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40 | YCC_444 = 2 |
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41 | }; |
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42 | |||
43 | /* |
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44 | * IEC60958 status bits |
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45 | */ |
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46 | enum r600_hdmi_iec_status_bits { |
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47 | AUDIO_STATUS_DIG_ENABLE = 0x01, |
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48 | AUDIO_STATUS_V = 0x02, |
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49 | AUDIO_STATUS_VCFG = 0x04, |
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50 | AUDIO_STATUS_EMPHASIS = 0x08, |
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51 | AUDIO_STATUS_COPYRIGHT = 0x10, |
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52 | AUDIO_STATUS_NONAUDIO = 0x20, |
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53 | AUDIO_STATUS_PROFESSIONAL = 0x40, |
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54 | AUDIO_STATUS_LEVEL = 0x80 |
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55 | }; |
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56 | |||
2997 | Serge | 57 | static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { |
1403 | serge | 58 | /* 32kHz 44.1kHz 48kHz */ |
59 | /* Clock N CTS N CTS N CTS */ |
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5078 | serge | 60 | { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */ |
1403 | serge | 61 | { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ |
62 | { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ |
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63 | { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ |
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64 | { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ |
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65 | { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ |
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5078 | serge | 66 | { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */ |
1403 | serge | 67 | { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ |
5078 | serge | 68 | { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */ |
1403 | serge | 69 | { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ |
70 | }; |
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71 | |||
5078 | serge | 72 | |
1403 | serge | 73 | /* |
5271 | serge | 74 | * check if the chipset is supported |
75 | */ |
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76 | static int r600_audio_chipset_supported(struct radeon_device *rdev) |
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77 | { |
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78 | return ASIC_IS_DCE2(rdev) && !ASIC_IS_NODCE(rdev); |
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79 | } |
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80 | |||
81 | static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev) |
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82 | { |
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83 | struct r600_audio_pin status; |
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84 | uint32_t value; |
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85 | |||
86 | value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL); |
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87 | |||
88 | /* number of channels */ |
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89 | status.channels = (value & 0x7) + 1; |
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90 | |||
91 | /* bits per sample */ |
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92 | switch ((value & 0xF0) >> 4) { |
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93 | case 0x0: |
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94 | status.bits_per_sample = 8; |
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95 | break; |
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96 | case 0x1: |
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97 | status.bits_per_sample = 16; |
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98 | break; |
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99 | case 0x2: |
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100 | status.bits_per_sample = 20; |
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101 | break; |
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102 | case 0x3: |
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103 | status.bits_per_sample = 24; |
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104 | break; |
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105 | case 0x4: |
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106 | status.bits_per_sample = 32; |
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107 | break; |
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108 | default: |
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109 | dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n", |
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110 | (int)value); |
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111 | status.bits_per_sample = 16; |
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112 | } |
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113 | |||
114 | /* current sampling rate in HZ */ |
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115 | if (value & 0x4000) |
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116 | status.rate = 44100; |
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117 | else |
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118 | status.rate = 48000; |
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119 | status.rate *= ((value >> 11) & 0x7) + 1; |
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120 | status.rate /= ((value >> 8) & 0x7) + 1; |
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121 | |||
122 | value = RREG32(R600_AUDIO_STATUS_BITS); |
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123 | |||
124 | /* iec 60958 status bits */ |
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125 | status.status_bits = value & 0xff; |
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126 | |||
127 | /* iec 60958 category code */ |
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128 | status.category_code = (value >> 8) & 0xff; |
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129 | |||
130 | return status; |
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131 | } |
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132 | |||
133 | /* |
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134 | * update all hdmi interfaces with current audio parameters |
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135 | */ |
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136 | void r600_audio_update_hdmi(struct work_struct *work) |
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137 | { |
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138 | struct radeon_device *rdev = container_of(work, struct radeon_device, |
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139 | audio_work); |
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140 | struct drm_device *dev = rdev->ddev; |
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141 | struct r600_audio_pin audio_status = r600_audio_status(rdev); |
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142 | struct drm_encoder *encoder; |
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143 | bool changed = false; |
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144 | |||
145 | if (rdev->audio.pin[0].channels != audio_status.channels || |
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146 | rdev->audio.pin[0].rate != audio_status.rate || |
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147 | rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample || |
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148 | rdev->audio.pin[0].status_bits != audio_status.status_bits || |
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149 | rdev->audio.pin[0].category_code != audio_status.category_code) { |
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150 | rdev->audio.pin[0] = audio_status; |
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151 | changed = true; |
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152 | } |
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153 | |||
154 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
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155 | if (!radeon_encoder_is_digital(encoder)) |
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156 | continue; |
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157 | if (changed || r600_hdmi_buffer_status_changed(encoder)) |
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158 | r600_hdmi_update_audio_settings(encoder); |
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159 | } |
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160 | } |
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161 | |||
162 | /* enable the audio stream */ |
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163 | void r600_audio_enable(struct radeon_device *rdev, |
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164 | struct r600_audio_pin *pin, |
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165 | u8 enable_mask) |
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166 | { |
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167 | u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); |
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168 | |||
169 | if (!pin) |
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170 | return; |
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171 | |||
172 | if (enable_mask) { |
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173 | tmp |= AUDIO_ENABLED; |
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174 | if (enable_mask & 1) |
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175 | tmp |= PIN0_AUDIO_ENABLED; |
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176 | if (enable_mask & 2) |
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177 | tmp |= PIN1_AUDIO_ENABLED; |
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178 | if (enable_mask & 4) |
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179 | tmp |= PIN2_AUDIO_ENABLED; |
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180 | if (enable_mask & 8) |
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181 | tmp |= PIN3_AUDIO_ENABLED; |
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182 | } else { |
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183 | tmp &= ~(AUDIO_ENABLED | |
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184 | PIN0_AUDIO_ENABLED | |
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185 | PIN1_AUDIO_ENABLED | |
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186 | PIN2_AUDIO_ENABLED | |
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187 | PIN3_AUDIO_ENABLED); |
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188 | } |
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189 | |||
190 | WREG32(AZ_HOT_PLUG_CONTROL, tmp); |
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191 | } |
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192 | |||
193 | /* |
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194 | * initialize the audio vars |
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195 | */ |
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196 | int r600_audio_init(struct radeon_device *rdev) |
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197 | { |
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198 | if (!radeon_audio || !r600_audio_chipset_supported(rdev)) |
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199 | return 0; |
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200 | |||
201 | rdev->audio.enabled = true; |
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202 | |||
203 | rdev->audio.num_pins = 1; |
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204 | rdev->audio.pin[0].channels = -1; |
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205 | rdev->audio.pin[0].rate = -1; |
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206 | rdev->audio.pin[0].bits_per_sample = -1; |
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207 | rdev->audio.pin[0].status_bits = 0; |
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208 | rdev->audio.pin[0].category_code = 0; |
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209 | rdev->audio.pin[0].id = 0; |
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210 | /* disable audio. it will be set up later */ |
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211 | r600_audio_enable(rdev, &rdev->audio.pin[0], 0); |
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212 | |||
213 | return 0; |
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214 | } |
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215 | |||
216 | /* |
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217 | * release the audio timer |
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218 | * TODO: How to do this correctly on SMP systems? |
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219 | */ |
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220 | void r600_audio_fini(struct radeon_device *rdev) |
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221 | { |
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222 | if (!rdev->audio.enabled) |
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223 | return; |
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224 | |||
225 | r600_audio_enable(rdev, &rdev->audio.pin[0], 0); |
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226 | |||
227 | rdev->audio.enabled = false; |
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228 | } |
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229 | |||
230 | struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev) |
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231 | { |
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232 | /* only one pin on 6xx-NI */ |
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233 | return &rdev->audio.pin[0]; |
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234 | } |
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235 | |||
236 | /* |
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5078 | serge | 237 | * calculate CTS and N values if they are not found in the table |
1403 | serge | 238 | */ |
5078 | serge | 239 | static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int *N, int freq) |
1403 | serge | 240 | { |
5078 | serge | 241 | int n, cts; |
242 | unsigned long div, mul; |
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243 | |||
244 | /* Safe, but overly large values */ |
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245 | n = 128 * freq; |
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246 | cts = clock * 1000; |
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247 | |||
248 | /* Smallest valid fraction */ |
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249 | div = gcd(n, cts); |
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250 | |||
251 | n /= div; |
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252 | cts /= div; |
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253 | |||
254 | /* |
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255 | * The optimal N is 128*freq/1000. Calculate the closest larger |
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256 | * value that doesn't truncate any bits. |
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257 | */ |
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258 | mul = ((128*freq/1000) + (n-1))/n; |
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259 | |||
260 | n *= mul; |
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261 | cts *= mul; |
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262 | |||
263 | /* Check that we are in spec (not always possible) */ |
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264 | if (n < (128*freq/1500)) |
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265 | printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n"); |
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266 | if (n > (128*freq/300)) |
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267 | printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n"); |
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268 | |||
269 | *N = n; |
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270 | *CTS = cts; |
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271 | |||
272 | DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n", |
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273 | *N, *CTS, freq); |
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1403 | serge | 274 | } |
275 | |||
2997 | Serge | 276 | struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) |
277 | { |
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278 | struct radeon_hdmi_acr res; |
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279 | u8 i; |
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280 | |||
5078 | serge | 281 | /* Precalculated values for common clocks */ |
282 | for (i = 0; i < ARRAY_SIZE(r600_hdmi_predefined_acr); i++) { |
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283 | if (r600_hdmi_predefined_acr[i].clock == clock) |
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284 | return r600_hdmi_predefined_acr[i]; |
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285 | } |
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2997 | Serge | 286 | |
5078 | serge | 287 | /* And odd clocks get manually calculated */ |
288 | r600_hdmi_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000); |
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289 | r600_hdmi_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100); |
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290 | r600_hdmi_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000); |
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2997 | Serge | 291 | |
292 | return res; |
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293 | } |
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294 | |||
1403 | serge | 295 | /* |
296 | * update the N and CTS parameters for a given pixel clock rate |
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297 | */ |
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5078 | serge | 298 | void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
1403 | serge | 299 | { |
300 | struct drm_device *dev = encoder->dev; |
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301 | struct radeon_device *rdev = dev->dev_private; |
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2997 | Serge | 302 | struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); |
303 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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304 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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305 | uint32_t offset = dig->afmt->offset; |
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1403 | serge | 306 | |
5078 | serge | 307 | WREG32_P(HDMI0_ACR_32_0 + offset, |
308 | HDMI0_ACR_CTS_32(acr.cts_32khz), |
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309 | ~HDMI0_ACR_CTS_32_MASK); |
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310 | WREG32_P(HDMI0_ACR_32_1 + offset, |
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311 | HDMI0_ACR_N_32(acr.n_32khz), |
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312 | ~HDMI0_ACR_N_32_MASK); |
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1403 | serge | 313 | |
5078 | serge | 314 | WREG32_P(HDMI0_ACR_44_0 + offset, |
315 | HDMI0_ACR_CTS_44(acr.cts_44_1khz), |
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316 | ~HDMI0_ACR_CTS_44_MASK); |
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317 | WREG32_P(HDMI0_ACR_44_1 + offset, |
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318 | HDMI0_ACR_N_44(acr.n_44_1khz), |
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319 | ~HDMI0_ACR_N_44_MASK); |
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1403 | serge | 320 | |
5078 | serge | 321 | WREG32_P(HDMI0_ACR_48_0 + offset, |
322 | HDMI0_ACR_CTS_48(acr.cts_48khz), |
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323 | ~HDMI0_ACR_CTS_48_MASK); |
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324 | WREG32_P(HDMI0_ACR_48_1 + offset, |
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325 | HDMI0_ACR_N_48(acr.n_48khz), |
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326 | ~HDMI0_ACR_N_48_MASK); |
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1403 | serge | 327 | } |
328 | |||
329 | /* |
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330 | * build a HDMI Video Info Frame |
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331 | */ |
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5078 | serge | 332 | void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer, |
333 | size_t size) |
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1403 | serge | 334 | { |
335 | struct drm_device *dev = encoder->dev; |
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336 | struct radeon_device *rdev = dev->dev_private; |
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2997 | Serge | 337 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
338 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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339 | uint32_t offset = dig->afmt->offset; |
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3764 | Serge | 340 | uint8_t *frame = buffer + 3; |
5078 | serge | 341 | uint8_t *header = buffer; |
1403 | serge | 342 | |
2997 | Serge | 343 | WREG32(HDMI0_AVI_INFO0 + offset, |
1403 | serge | 344 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
2997 | Serge | 345 | WREG32(HDMI0_AVI_INFO1 + offset, |
1403 | serge | 346 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
2997 | Serge | 347 | WREG32(HDMI0_AVI_INFO2 + offset, |
1403 | serge | 348 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
2997 | Serge | 349 | WREG32(HDMI0_AVI_INFO3 + offset, |
5078 | serge | 350 | frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); |
1403 | serge | 351 | } |
352 | |||
353 | /* |
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354 | * build a Audio Info Frame |
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355 | */ |
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3764 | Serge | 356 | static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder, |
357 | const void *buffer, size_t size) |
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1403 | serge | 358 | { |
359 | struct drm_device *dev = encoder->dev; |
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360 | struct radeon_device *rdev = dev->dev_private; |
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2997 | Serge | 361 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
362 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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363 | uint32_t offset = dig->afmt->offset; |
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3764 | Serge | 364 | const u8 *frame = buffer + 3; |
1403 | serge | 365 | |
2997 | Serge | 366 | WREG32(HDMI0_AUDIO_INFO0 + offset, |
1403 | serge | 367 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
2997 | Serge | 368 | WREG32(HDMI0_AUDIO_INFO1 + offset, |
1403 | serge | 369 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); |
370 | } |
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371 | |||
372 | /* |
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373 | * test if audio buffer is filled enough to start playing |
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374 | */ |
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2997 | Serge | 375 | static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) |
1403 | serge | 376 | { |
377 | struct drm_device *dev = encoder->dev; |
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378 | struct radeon_device *rdev = dev->dev_private; |
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2997 | Serge | 379 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
380 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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381 | uint32_t offset = dig->afmt->offset; |
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1403 | serge | 382 | |
2997 | Serge | 383 | return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; |
1403 | serge | 384 | } |
385 | |||
386 | /* |
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387 | * have buffer status changed since last call? |
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388 | */ |
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389 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) |
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390 | { |
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391 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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2997 | Serge | 392 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
1403 | serge | 393 | int status, result; |
394 | |||
2997 | Serge | 395 | if (!dig->afmt || !dig->afmt->enabled) |
1403 | serge | 396 | return 0; |
397 | |||
398 | status = r600_hdmi_is_audio_buffer_filled(encoder); |
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2997 | Serge | 399 | result = dig->afmt->last_buffer_filled_status != status; |
400 | dig->afmt->last_buffer_filled_status = status; |
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1403 | serge | 401 | |
402 | return result; |
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403 | } |
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404 | |||
405 | /* |
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406 | * write the audio workaround status to the hardware |
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407 | */ |
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5078 | serge | 408 | void r600_hdmi_audio_workaround(struct drm_encoder *encoder) |
1403 | serge | 409 | { |
410 | struct drm_device *dev = encoder->dev; |
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411 | struct radeon_device *rdev = dev->dev_private; |
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412 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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2997 | Serge | 413 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
414 | uint32_t offset = dig->afmt->offset; |
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415 | bool hdmi_audio_workaround = false; /* FIXME */ |
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416 | u32 value; |
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1403 | serge | 417 | |
2997 | Serge | 418 | if (!hdmi_audio_workaround || |
419 | r600_hdmi_is_audio_buffer_filled(encoder)) |
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420 | value = 0; /* disable workaround */ |
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421 | else |
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422 | value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ |
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423 | WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, |
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424 | value, ~HDMI0_AUDIO_TEST_EN); |
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1403 | serge | 425 | } |
426 | |||
3764 | Serge | 427 | void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) |
428 | { |
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429 | struct drm_device *dev = encoder->dev; |
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430 | struct radeon_device *rdev = dev->dev_private; |
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431 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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432 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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433 | u32 base_rate = 24000; |
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5078 | serge | 434 | u32 max_ratio = clock / base_rate; |
435 | u32 dto_phase; |
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436 | u32 dto_modulo = clock; |
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437 | u32 wallclock_ratio; |
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438 | u32 dto_cntl; |
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1403 | serge | 439 | |
3764 | Serge | 440 | if (!dig || !dig->afmt) |
441 | return; |
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442 | |||
5078 | serge | 443 | if (max_ratio >= 8) { |
444 | dto_phase = 192 * 1000; |
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445 | wallclock_ratio = 3; |
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446 | } else if (max_ratio >= 4) { |
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447 | dto_phase = 96 * 1000; |
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448 | wallclock_ratio = 2; |
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449 | } else if (max_ratio >= 2) { |
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450 | dto_phase = 48 * 1000; |
||
451 | wallclock_ratio = 1; |
||
452 | } else { |
||
453 | dto_phase = 24 * 1000; |
||
454 | wallclock_ratio = 0; |
||
455 | } |
||
456 | |||
3764 | Serge | 457 | /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. |
458 | * doesn't matter which one you use. Just use the first one. |
||
459 | */ |
||
460 | /* XXX two dtos; generally use dto0 for hdmi */ |
||
461 | /* Express [24MHz / target pixel clock] as an exact rational |
||
462 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
||
463 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
||
464 | */ |
||
5078 | serge | 465 | if (ASIC_IS_DCE32(rdev)) { |
466 | if (dig->dig_encoder == 0) { |
||
467 | dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
||
468 | dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
||
469 | WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); |
||
470 | WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); |
||
471 | WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); |
||
472 | WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ |
||
473 | } else { |
||
474 | dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
||
475 | dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
||
476 | WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl); |
||
477 | WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase); |
||
478 | WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo); |
||
479 | WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ |
||
480 | } |
||
481 | } else { |
||
3764 | Serge | 482 | /* according to the reg specs, this should DCE3.2 only, but in |
5078 | serge | 483 | * practice it seems to cover DCE2.0/3.0/3.1 as well. |
3764 | Serge | 484 | */ |
5078 | serge | 485 | if (dig->dig_encoder == 0) { |
3764 | Serge | 486 | WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); |
487 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); |
||
488 | WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ |
||
489 | } else { |
||
5078 | serge | 490 | WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100); |
491 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100); |
||
492 | WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ |
||
493 | } |
||
3764 | Serge | 494 | } |
495 | } |
||
496 | |||
1403 | serge | 497 | /* |
498 | * update the info frames with the data from the current display mode |
||
499 | */ |
||
500 | void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) |
||
501 | { |
||
502 | struct drm_device *dev = encoder->dev; |
||
503 | struct radeon_device *rdev = dev->dev_private; |
||
2997 | Serge | 504 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
505 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
||
3764 | Serge | 506 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
507 | struct hdmi_avi_infoframe frame; |
||
2997 | Serge | 508 | uint32_t offset; |
5078 | serge | 509 | uint32_t acr_ctl; |
3764 | Serge | 510 | ssize_t err; |
1403 | serge | 511 | |
5078 | serge | 512 | if (!dig || !dig->afmt) |
513 | return; |
||
514 | |||
2997 | Serge | 515 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
516 | if (!dig->afmt->enabled) |
||
1963 | serge | 517 | return; |
2997 | Serge | 518 | offset = dig->afmt->offset; |
1963 | serge | 519 | |
5078 | serge | 520 | /* disable audio prior to setting up hw */ |
521 | dig->afmt->pin = r600_audio_get_pin(rdev); |
||
5271 | serge | 522 | r600_audio_enable(rdev, dig->afmt->pin, 0xf); |
1403 | serge | 523 | |
5078 | serge | 524 | r600_audio_set_dto(encoder, mode->clock); |
1403 | serge | 525 | |
5078 | serge | 526 | WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, |
2997 | Serge | 527 | HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ |
528 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ |
||
529 | HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ |
||
5078 | serge | 530 | HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */ |
531 | ~(HDMI0_AUDIO_SAMPLE_SEND | |
||
532 | HDMI0_AUDIO_DELAY_EN_MASK | |
||
533 | HDMI0_AUDIO_PACKETS_PER_LINE_MASK | |
||
534 | HDMI0_60958_CS_UPDATE)); |
||
1403 | serge | 535 | |
5078 | serge | 536 | /* DCE 3.0 uses register that's normally for CRC_CONTROL */ |
537 | acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL : |
||
538 | HDMI0_ACR_PACKET_CONTROL; |
||
539 | WREG32_P(acr_ctl + offset, |
||
540 | HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */ |
||
541 | HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */ |
||
542 | ~(HDMI0_ACR_SOURCE | |
||
543 | HDMI0_ACR_AUTO_SEND)); |
||
1403 | serge | 544 | |
5078 | serge | 545 | WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset, |
2997 | Serge | 546 | HDMI0_NULL_SEND | /* send null packets when required */ |
547 | HDMI0_GC_SEND | /* send general control packets */ |
||
548 | HDMI0_GC_CONT); /* send general control packets every frame */ |
||
1403 | serge | 549 | |
5078 | serge | 550 | WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, |
2997 | Serge | 551 | HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ |
552 | HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ |
||
553 | HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
||
5078 | serge | 554 | HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ |
2997 | Serge | 555 | |
5078 | serge | 556 | WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset, |
2997 | Serge | 557 | HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ |
5078 | serge | 558 | HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */ |
559 | ~(HDMI0_AVI_INFO_LINE_MASK | |
||
560 | HDMI0_AUDIO_INFO_LINE_MASK)); |
||
2997 | Serge | 561 | |
5078 | serge | 562 | WREG32_AND(HDMI0_GC + offset, |
563 | ~HDMI0_GC_AVMUTE); /* unset HDMI0_GC_AVMUTE */ |
||
2997 | Serge | 564 | |
3764 | Serge | 565 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
566 | if (err < 0) { |
||
567 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); |
||
568 | return; |
||
569 | } |
||
1403 | serge | 570 | |
3764 | Serge | 571 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
572 | if (err < 0) { |
||
573 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); |
||
574 | return; |
||
575 | } |
||
576 | |||
577 | r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
||
5078 | serge | 578 | |
579 | /* fglrx duplicates INFOFRAME_CONTROL0 & INFOFRAME_CONTROL1 ops here */ |
||
580 | |||
581 | WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset, |
||
582 | ~(HDMI0_GENERIC0_SEND | |
||
583 | HDMI0_GENERIC0_CONT | |
||
584 | HDMI0_GENERIC0_UPDATE | |
||
585 | HDMI0_GENERIC1_SEND | |
||
586 | HDMI0_GENERIC1_CONT | |
||
587 | HDMI0_GENERIC0_LINE_MASK | |
||
588 | HDMI0_GENERIC1_LINE_MASK)); |
||
589 | |||
2997 | Serge | 590 | r600_hdmi_update_ACR(encoder, mode->clock); |
591 | |||
5078 | serge | 592 | WREG32_P(HDMI0_60958_0 + offset, |
593 | HDMI0_60958_CS_CHANNEL_NUMBER_L(1), |
||
594 | ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK | |
||
595 | HDMI0_60958_CS_CLOCK_ACCURACY_MASK)); |
||
596 | |||
597 | WREG32_P(HDMI0_60958_1 + offset, |
||
598 | HDMI0_60958_CS_CHANNEL_NUMBER_R(2), |
||
599 | ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK); |
||
600 | |||
1963 | serge | 601 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
2997 | Serge | 602 | WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
603 | WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); |
||
604 | WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); |
||
605 | WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); |
||
1403 | serge | 606 | |
5078 | serge | 607 | /* enable audio after to setting up hw */ |
5271 | serge | 608 | r600_audio_enable(rdev, dig->afmt->pin, 0xf); |
1403 | serge | 609 | } |
610 | |||
5078 | serge | 611 | /** |
612 | * r600_hdmi_update_audio_settings - Update audio infoframe |
||
613 | * |
||
614 | * @encoder: drm encoder |
||
615 | * |
||
616 | * Gets info about current audio stream and updates audio infoframe. |
||
1403 | serge | 617 | */ |
1963 | serge | 618 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) |
1403 | serge | 619 | { |
620 | struct drm_device *dev = encoder->dev; |
||
621 | struct radeon_device *rdev = dev->dev_private; |
||
2997 | Serge | 622 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
623 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
||
5078 | serge | 624 | struct r600_audio_pin audio = r600_audio_status(rdev); |
3764 | Serge | 625 | uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; |
626 | struct hdmi_audio_infoframe frame; |
||
2997 | Serge | 627 | uint32_t offset; |
5078 | serge | 628 | uint32_t value; |
3764 | Serge | 629 | ssize_t err; |
1403 | serge | 630 | |
2997 | Serge | 631 | if (!dig->afmt || !dig->afmt->enabled) |
1403 | serge | 632 | return; |
2997 | Serge | 633 | offset = dig->afmt->offset; |
1403 | serge | 634 | |
635 | DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", |
||
636 | r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", |
||
2997 | Serge | 637 | audio.channels, audio.rate, audio.bits_per_sample); |
1403 | serge | 638 | DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", |
2997 | Serge | 639 | (int)audio.status_bits, (int)audio.category_code); |
1403 | serge | 640 | |
3764 | Serge | 641 | err = hdmi_audio_infoframe_init(&frame); |
642 | if (err < 0) { |
||
643 | DRM_ERROR("failed to setup audio infoframe\n"); |
||
644 | return; |
||
645 | } |
||
1403 | serge | 646 | |
3764 | Serge | 647 | frame.channels = audio.channels; |
648 | |||
649 | err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); |
||
650 | if (err < 0) { |
||
651 | DRM_ERROR("failed to pack audio infoframe\n"); |
||
652 | return; |
||
653 | } |
||
654 | |||
5078 | serge | 655 | value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset); |
656 | if (value & HDMI0_AUDIO_TEST_EN) |
||
657 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, |
||
658 | value & ~HDMI0_AUDIO_TEST_EN); |
||
659 | |||
660 | WREG32_OR(HDMI0_CONTROL + offset, |
||
661 | HDMI0_ERROR_ACK); |
||
662 | |||
663 | WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset, |
||
664 | ~HDMI0_AUDIO_INFO_SOURCE); |
||
665 | |||
3764 | Serge | 666 | r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer)); |
5078 | serge | 667 | |
668 | WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, |
||
669 | HDMI0_AUDIO_INFO_CONT | |
||
670 | HDMI0_AUDIO_INFO_UPDATE); |
||
1963 | serge | 671 | } |
672 | |||
1403 | serge | 673 | /* |
1963 | serge | 674 | * enable the HDMI engine |
1403 | serge | 675 | */ |
3764 | Serge | 676 | void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) |
1403 | serge | 677 | { |
678 | struct drm_device *dev = encoder->dev; |
||
679 | struct radeon_device *rdev = dev->dev_private; |
||
680 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
2997 | Serge | 681 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
3764 | Serge | 682 | u32 hdmi = HDMI0_ERROR_ACK; |
1403 | serge | 683 | |
5078 | serge | 684 | if (!dig || !dig->afmt) |
685 | return; |
||
686 | |||
2997 | Serge | 687 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
3764 | Serge | 688 | if (enable && dig->afmt->enabled) |
1963 | serge | 689 | return; |
3764 | Serge | 690 | if (!enable && !dig->afmt->enabled) |
691 | return; |
||
1403 | serge | 692 | |
5271 | serge | 693 | if (!enable && dig->afmt->pin) { |
694 | r600_audio_enable(rdev, dig->afmt->pin, 0); |
||
695 | dig->afmt->pin = NULL; |
||
696 | } |
||
697 | |||
2997 | Serge | 698 | /* Older chipsets require setting HDMI and routing manually */ |
3764 | Serge | 699 | if (!ASIC_IS_DCE3(rdev)) { |
700 | if (enable) |
||
701 | hdmi |= HDMI0_ENABLE; |
||
1403 | serge | 702 | switch (radeon_encoder->encoder_id) { |
703 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
||
3764 | Serge | 704 | if (enable) { |
705 | WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); |
||
2997 | Serge | 706 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); |
3764 | Serge | 707 | } else { |
708 | WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); |
||
709 | } |
||
1403 | serge | 710 | break; |
711 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
||
3764 | Serge | 712 | if (enable) { |
713 | WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); |
||
2997 | Serge | 714 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); |
3764 | Serge | 715 | } else { |
716 | WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); |
||
717 | } |
||
2997 | Serge | 718 | break; |
719 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
||
3764 | Serge | 720 | if (enable) { |
721 | WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); |
||
2997 | Serge | 722 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); |
3764 | Serge | 723 | } else { |
724 | WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); |
||
725 | } |
||
2997 | Serge | 726 | break; |
727 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
||
3764 | Serge | 728 | if (enable) |
2997 | Serge | 729 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); |
1403 | serge | 730 | break; |
731 | default: |
||
2997 | Serge | 732 | dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", |
733 | radeon_encoder->encoder_id); |
||
1403 | serge | 734 | break; |
735 | } |
||
3764 | Serge | 736 | WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi); |
1963 | serge | 737 | } |
738 | |||
2997 | Serge | 739 | if (rdev->irq.installed) { |
1963 | serge | 740 | /* if irq is available use it */ |
3764 | Serge | 741 | /* XXX: shouldn't need this on any asics. Double check DCE2/3 */ |
742 | // if (enable) |
||
743 | // radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); |
||
744 | // else |
||
745 | // radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); |
||
2997 | Serge | 746 | } |
1963 | serge | 747 | |
3764 | Serge | 748 | dig->afmt->enabled = enable; |
2997 | Serge | 749 | |
3764 | Serge | 750 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
751 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); |
||
1403 | serge | 752 | }>>>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>> |
753 |