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Rev | Author | Line No. | Line |
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1403 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Christian König. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Christian König |
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25 | */ |
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3764 | Serge | 26 | #include |
2997 | Serge | 27 | #include |
28 | #include |
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1403 | serge | 29 | #include "radeon.h" |
1963 | serge | 30 | #include "radeon_asic.h" |
2997 | Serge | 31 | #include "r600d.h" |
1403 | serge | 32 | #include "atom.h" |
33 | |||
34 | /* |
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35 | * HDMI color format |
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36 | */ |
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37 | enum r600_hdmi_color_format { |
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38 | RGB = 0, |
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39 | YCC_422 = 1, |
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40 | YCC_444 = 2 |
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41 | }; |
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42 | |||
43 | /* |
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44 | * IEC60958 status bits |
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45 | */ |
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46 | enum r600_hdmi_iec_status_bits { |
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47 | AUDIO_STATUS_DIG_ENABLE = 0x01, |
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48 | AUDIO_STATUS_V = 0x02, |
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49 | AUDIO_STATUS_VCFG = 0x04, |
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50 | AUDIO_STATUS_EMPHASIS = 0x08, |
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51 | AUDIO_STATUS_COPYRIGHT = 0x10, |
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52 | AUDIO_STATUS_NONAUDIO = 0x20, |
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53 | AUDIO_STATUS_PROFESSIONAL = 0x40, |
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54 | AUDIO_STATUS_LEVEL = 0x80 |
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55 | }; |
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56 | |||
2997 | Serge | 57 | static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { |
1403 | serge | 58 | /* 32kHz 44.1kHz 48kHz */ |
59 | /* Clock N CTS N CTS N CTS */ |
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60 | { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ |
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61 | { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ |
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62 | { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ |
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63 | { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ |
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64 | { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ |
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65 | { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ |
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66 | { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ |
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67 | { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ |
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68 | { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ |
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69 | { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ |
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70 | { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ |
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71 | }; |
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72 | |||
73 | /* |
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74 | * calculate CTS value if it's not found in the table |
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75 | */ |
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2997 | Serge | 76 | static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq) |
1403 | serge | 77 | { |
78 | if (*CTS == 0) |
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1963 | serge | 79 | *CTS = clock * N / (128 * freq) * 1000; |
1403 | serge | 80 | DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", |
81 | N, *CTS, freq); |
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82 | } |
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83 | |||
2997 | Serge | 84 | struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) |
85 | { |
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86 | struct radeon_hdmi_acr res; |
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87 | u8 i; |
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88 | |||
89 | for (i = 0; r600_hdmi_predefined_acr[i].clock != clock && |
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90 | r600_hdmi_predefined_acr[i].clock != 0; i++) |
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91 | ; |
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92 | res = r600_hdmi_predefined_acr[i]; |
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93 | |||
94 | /* In case some CTS are missing */ |
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95 | r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000); |
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96 | r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100); |
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97 | r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000); |
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98 | |||
99 | return res; |
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100 | } |
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101 | |||
1403 | serge | 102 | /* |
103 | * update the N and CTS parameters for a given pixel clock rate |
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104 | */ |
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105 | static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
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106 | { |
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107 | struct drm_device *dev = encoder->dev; |
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108 | struct radeon_device *rdev = dev->dev_private; |
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2997 | Serge | 109 | struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); |
110 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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111 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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112 | uint32_t offset = dig->afmt->offset; |
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1403 | serge | 113 | |
2997 | Serge | 114 | WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz)); |
115 | WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz); |
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1403 | serge | 116 | |
2997 | Serge | 117 | WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz)); |
118 | WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz); |
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1403 | serge | 119 | |
2997 | Serge | 120 | WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz)); |
121 | WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz); |
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1403 | serge | 122 | } |
123 | |||
124 | /* |
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125 | * build a HDMI Video Info Frame |
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126 | */ |
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3764 | Serge | 127 | static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, |
128 | void *buffer, size_t size) |
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1403 | serge | 129 | { |
130 | struct drm_device *dev = encoder->dev; |
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131 | struct radeon_device *rdev = dev->dev_private; |
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2997 | Serge | 132 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
133 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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134 | uint32_t offset = dig->afmt->offset; |
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3764 | Serge | 135 | uint8_t *frame = buffer + 3; |
1403 | serge | 136 | |
2997 | Serge | 137 | /* Our header values (type, version, length) should be alright, Intel |
138 | * is using the same. Checksum function also seems to be OK, it works |
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139 | * fine for audio infoframe. However calculated value is always lower |
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140 | * by 2 in comparison to fglrx. It breaks displaying anything in case |
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141 | * of TVs that strictly check the checksum. Hack it manually here to |
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142 | * workaround this issue. */ |
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143 | frame[0x0] += 2; |
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1403 | serge | 144 | |
2997 | Serge | 145 | WREG32(HDMI0_AVI_INFO0 + offset, |
1403 | serge | 146 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
2997 | Serge | 147 | WREG32(HDMI0_AVI_INFO1 + offset, |
1403 | serge | 148 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
2997 | Serge | 149 | WREG32(HDMI0_AVI_INFO2 + offset, |
1403 | serge | 150 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
2997 | Serge | 151 | WREG32(HDMI0_AVI_INFO3 + offset, |
1403 | serge | 152 | frame[0xC] | (frame[0xD] << 8)); |
153 | } |
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154 | |||
155 | /* |
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156 | * build a Audio Info Frame |
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157 | */ |
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3764 | Serge | 158 | static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder, |
159 | const void *buffer, size_t size) |
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1403 | serge | 160 | { |
161 | struct drm_device *dev = encoder->dev; |
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162 | struct radeon_device *rdev = dev->dev_private; |
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2997 | Serge | 163 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
164 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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165 | uint32_t offset = dig->afmt->offset; |
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3764 | Serge | 166 | const u8 *frame = buffer + 3; |
1403 | serge | 167 | |
2997 | Serge | 168 | WREG32(HDMI0_AUDIO_INFO0 + offset, |
1403 | serge | 169 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
2997 | Serge | 170 | WREG32(HDMI0_AUDIO_INFO1 + offset, |
1403 | serge | 171 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); |
172 | } |
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173 | |||
174 | /* |
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175 | * test if audio buffer is filled enough to start playing |
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176 | */ |
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2997 | Serge | 177 | static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) |
1403 | serge | 178 | { |
179 | struct drm_device *dev = encoder->dev; |
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180 | struct radeon_device *rdev = dev->dev_private; |
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2997 | Serge | 181 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
182 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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183 | uint32_t offset = dig->afmt->offset; |
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1403 | serge | 184 | |
2997 | Serge | 185 | return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; |
1403 | serge | 186 | } |
187 | |||
188 | /* |
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189 | * have buffer status changed since last call? |
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190 | */ |
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191 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) |
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192 | { |
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193 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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2997 | Serge | 194 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
1403 | serge | 195 | int status, result; |
196 | |||
2997 | Serge | 197 | if (!dig->afmt || !dig->afmt->enabled) |
1403 | serge | 198 | return 0; |
199 | |||
200 | status = r600_hdmi_is_audio_buffer_filled(encoder); |
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2997 | Serge | 201 | result = dig->afmt->last_buffer_filled_status != status; |
202 | dig->afmt->last_buffer_filled_status = status; |
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1403 | serge | 203 | |
204 | return result; |
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205 | } |
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206 | |||
207 | /* |
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208 | * write the audio workaround status to the hardware |
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209 | */ |
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2997 | Serge | 210 | static void r600_hdmi_audio_workaround(struct drm_encoder *encoder) |
1403 | serge | 211 | { |
212 | struct drm_device *dev = encoder->dev; |
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213 | struct radeon_device *rdev = dev->dev_private; |
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214 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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2997 | Serge | 215 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
216 | uint32_t offset = dig->afmt->offset; |
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217 | bool hdmi_audio_workaround = false; /* FIXME */ |
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218 | u32 value; |
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1403 | serge | 219 | |
2997 | Serge | 220 | if (!hdmi_audio_workaround || |
221 | r600_hdmi_is_audio_buffer_filled(encoder)) |
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222 | value = 0; /* disable workaround */ |
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223 | else |
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224 | value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ |
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225 | WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, |
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226 | value, ~HDMI0_AUDIO_TEST_EN); |
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1403 | serge | 227 | } |
228 | |||
3764 | Serge | 229 | void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) |
230 | { |
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231 | struct drm_device *dev = encoder->dev; |
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232 | struct radeon_device *rdev = dev->dev_private; |
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233 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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234 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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235 | u32 base_rate = 24000; |
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1403 | serge | 236 | |
3764 | Serge | 237 | if (!dig || !dig->afmt) |
238 | return; |
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239 | |||
240 | /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. |
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241 | * doesn't matter which one you use. Just use the first one. |
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242 | */ |
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243 | /* XXX two dtos; generally use dto0 for hdmi */ |
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244 | /* Express [24MHz / target pixel clock] as an exact rational |
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245 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
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246 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
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247 | */ |
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248 | if (ASIC_IS_DCE3(rdev)) { |
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249 | /* according to the reg specs, this should DCE3.2 only, but in |
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250 | * practice it seems to cover DCE3.0 as well. |
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251 | */ |
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252 | WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); |
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253 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); |
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254 | WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ |
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255 | } else { |
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256 | /* according to the reg specs, this should be DCE2.0 and DCE3.0 */ |
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257 | WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) | |
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258 | AUDIO_DTO_MODULE(clock / 10)); |
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259 | } |
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260 | } |
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261 | |||
1403 | serge | 262 | /* |
263 | * update the info frames with the data from the current display mode |
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264 | */ |
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265 | void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) |
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266 | { |
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267 | struct drm_device *dev = encoder->dev; |
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268 | struct radeon_device *rdev = dev->dev_private; |
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2997 | Serge | 269 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
270 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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3764 | Serge | 271 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
272 | struct hdmi_avi_infoframe frame; |
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2997 | Serge | 273 | uint32_t offset; |
3764 | Serge | 274 | ssize_t err; |
1403 | serge | 275 | |
2997 | Serge | 276 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
277 | if (!dig->afmt->enabled) |
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1963 | serge | 278 | return; |
2997 | Serge | 279 | offset = dig->afmt->offset; |
1963 | serge | 280 | |
2997 | Serge | 281 | // r600_audio_set_clock(encoder, mode->clock); |
1403 | serge | 282 | |
2997 | Serge | 283 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, |
284 | HDMI0_NULL_SEND); /* send null packets when required */ |
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1403 | serge | 285 | |
2997 | Serge | 286 | WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); |
1403 | serge | 287 | |
2997 | Serge | 288 | if (ASIC_IS_DCE32(rdev)) { |
289 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, |
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290 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ |
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291 | HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
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292 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, |
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293 | AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ |
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294 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
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295 | } else { |
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296 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, |
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297 | HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ |
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298 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ |
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299 | HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ |
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300 | HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
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301 | } |
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1403 | serge | 302 | |
2997 | Serge | 303 | WREG32(HDMI0_ACR_PACKET_CONTROL + offset, |
304 | HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ |
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305 | HDMI0_ACR_SOURCE); /* select SW CTS value */ |
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1403 | serge | 306 | |
2997 | Serge | 307 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, |
308 | HDMI0_NULL_SEND | /* send null packets when required */ |
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309 | HDMI0_GC_SEND | /* send general control packets */ |
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310 | HDMI0_GC_CONT); /* send general control packets every frame */ |
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1403 | serge | 311 | |
2997 | Serge | 312 | /* TODO: HDMI0_AUDIO_INFO_UPDATE */ |
313 | WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, |
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314 | HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ |
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315 | HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ |
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316 | HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
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317 | HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */ |
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318 | |||
319 | WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, |
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320 | HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ |
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321 | HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */ |
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322 | |||
323 | WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */ |
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324 | |||
3764 | Serge | 325 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
326 | if (err < 0) { |
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327 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); |
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328 | return; |
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329 | } |
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1403 | serge | 330 | |
3764 | Serge | 331 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
332 | if (err < 0) { |
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333 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); |
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334 | return; |
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335 | } |
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336 | |||
337 | r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
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2997 | Serge | 338 | r600_hdmi_update_ACR(encoder, mode->clock); |
339 | |||
1963 | serge | 340 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
2997 | Serge | 341 | WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
342 | WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); |
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343 | WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); |
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344 | WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); |
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1403 | serge | 345 | |
346 | r600_hdmi_audio_workaround(encoder); |
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347 | } |
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348 | |||
2997 | Serge | 349 | #if 0 |
1403 | serge | 350 | /* |
351 | * update settings with current parameters from audio engine |
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352 | */ |
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1963 | serge | 353 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) |
1403 | serge | 354 | { |
355 | struct drm_device *dev = encoder->dev; |
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356 | struct radeon_device *rdev = dev->dev_private; |
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2997 | Serge | 357 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
358 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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359 | struct r600_audio audio = r600_audio_status(rdev); |
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3764 | Serge | 360 | uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; |
361 | struct hdmi_audio_infoframe frame; |
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2997 | Serge | 362 | uint32_t offset; |
1403 | serge | 363 | uint32_t iec; |
3764 | Serge | 364 | ssize_t err; |
1403 | serge | 365 | |
2997 | Serge | 366 | if (!dig->afmt || !dig->afmt->enabled) |
1403 | serge | 367 | return; |
2997 | Serge | 368 | offset = dig->afmt->offset; |
1403 | serge | 369 | |
370 | DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", |
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371 | r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", |
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2997 | Serge | 372 | audio.channels, audio.rate, audio.bits_per_sample); |
1403 | serge | 373 | DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", |
2997 | Serge | 374 | (int)audio.status_bits, (int)audio.category_code); |
1403 | serge | 375 | |
376 | iec = 0; |
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2997 | Serge | 377 | if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL) |
1403 | serge | 378 | iec |= 1 << 0; |
2997 | Serge | 379 | if (audio.status_bits & AUDIO_STATUS_NONAUDIO) |
1403 | serge | 380 | iec |= 1 << 1; |
2997 | Serge | 381 | if (audio.status_bits & AUDIO_STATUS_COPYRIGHT) |
1403 | serge | 382 | iec |= 1 << 2; |
2997 | Serge | 383 | if (audio.status_bits & AUDIO_STATUS_EMPHASIS) |
1403 | serge | 384 | iec |= 1 << 3; |
385 | |||
2997 | Serge | 386 | iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code); |
1403 | serge | 387 | |
2997 | Serge | 388 | switch (audio.rate) { |
389 | case 32000: |
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390 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3); |
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391 | break; |
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392 | case 44100: |
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393 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0); |
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394 | break; |
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395 | case 48000: |
||
396 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2); |
||
397 | break; |
||
398 | case 88200: |
||
399 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8); |
||
400 | break; |
||
401 | case 96000: |
||
402 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa); |
||
403 | break; |
||
404 | case 176400: |
||
405 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc); |
||
406 | break; |
||
407 | case 192000: |
||
408 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe); |
||
409 | break; |
||
1403 | serge | 410 | } |
411 | |||
2997 | Serge | 412 | WREG32(HDMI0_60958_0 + offset, iec); |
1403 | serge | 413 | |
414 | iec = 0; |
||
2997 | Serge | 415 | switch (audio.bits_per_sample) { |
416 | case 16: |
||
417 | iec |= HDMI0_60958_CS_WORD_LENGTH(0x2); |
||
1963 | serge | 418 | break; |
2997 | Serge | 419 | case 20: |
420 | iec |= HDMI0_60958_CS_WORD_LENGTH(0x3); |
||
1963 | serge | 421 | break; |
2997 | Serge | 422 | case 24: |
423 | iec |= HDMI0_60958_CS_WORD_LENGTH(0xb); |
||
1963 | serge | 424 | break; |
425 | } |
||
2997 | Serge | 426 | if (audio.status_bits & AUDIO_STATUS_V) |
427 | iec |= 0x5 << 16; |
||
428 | WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f); |
||
1963 | serge | 429 | |
3764 | Serge | 430 | err = hdmi_audio_infoframe_init(&frame); |
431 | if (err < 0) { |
||
432 | DRM_ERROR("failed to setup audio infoframe\n"); |
||
433 | return; |
||
434 | } |
||
1403 | serge | 435 | |
3764 | Serge | 436 | frame.channels = audio.channels; |
437 | |||
438 | err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); |
||
439 | if (err < 0) { |
||
440 | DRM_ERROR("failed to pack audio infoframe\n"); |
||
441 | return; |
||
442 | } |
||
443 | |||
444 | r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer)); |
||
2997 | Serge | 445 | r600_hdmi_audio_workaround(encoder); |
1963 | serge | 446 | } |
2997 | Serge | 447 | #endif |
1963 | serge | 448 | |
1403 | serge | 449 | /* |
1963 | serge | 450 | * enable the HDMI engine |
1403 | serge | 451 | */ |
3764 | Serge | 452 | void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) |
1403 | serge | 453 | { |
454 | struct drm_device *dev = encoder->dev; |
||
455 | struct radeon_device *rdev = dev->dev_private; |
||
456 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
2997 | Serge | 457 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
3764 | Serge | 458 | u32 hdmi = HDMI0_ERROR_ACK; |
1403 | serge | 459 | |
2997 | Serge | 460 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
3764 | Serge | 461 | if (enable && dig->afmt->enabled) |
1963 | serge | 462 | return; |
3764 | Serge | 463 | if (!enable && !dig->afmt->enabled) |
464 | return; |
||
1403 | serge | 465 | |
2997 | Serge | 466 | /* Older chipsets require setting HDMI and routing manually */ |
3764 | Serge | 467 | if (!ASIC_IS_DCE3(rdev)) { |
468 | if (enable) |
||
469 | hdmi |= HDMI0_ENABLE; |
||
1403 | serge | 470 | switch (radeon_encoder->encoder_id) { |
471 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
||
3764 | Serge | 472 | if (enable) { |
473 | WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); |
||
2997 | Serge | 474 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); |
3764 | Serge | 475 | } else { |
476 | WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); |
||
477 | } |
||
1403 | serge | 478 | break; |
479 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
||
3764 | Serge | 480 | if (enable) { |
481 | WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); |
||
2997 | Serge | 482 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); |
3764 | Serge | 483 | } else { |
484 | WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); |
||
485 | } |
||
2997 | Serge | 486 | break; |
487 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
||
3764 | Serge | 488 | if (enable) { |
489 | WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); |
||
2997 | Serge | 490 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); |
3764 | Serge | 491 | } else { |
492 | WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); |
||
493 | } |
||
2997 | Serge | 494 | break; |
495 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
||
3764 | Serge | 496 | if (enable) |
2997 | Serge | 497 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); |
1403 | serge | 498 | break; |
499 | default: |
||
2997 | Serge | 500 | dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", |
501 | radeon_encoder->encoder_id); |
||
1403 | serge | 502 | break; |
503 | } |
||
3764 | Serge | 504 | WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi); |
1963 | serge | 505 | } |
506 | |||
2997 | Serge | 507 | if (rdev->irq.installed) { |
1963 | serge | 508 | /* if irq is available use it */ |
3764 | Serge | 509 | /* XXX: shouldn't need this on any asics. Double check DCE2/3 */ |
510 | // if (enable) |
||
511 | // radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); |
||
512 | // else |
||
513 | // radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); |
||
2997 | Serge | 514 | } |
1963 | serge | 515 | |
3764 | Serge | 516 | dig->afmt->enabled = enable; |
2997 | Serge | 517 | |
3764 | Serge | 518 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
519 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); |
||
1403 | serge | 520 | }>>><>><>><>><>><>>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
521 |