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5078 | serge | 1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | * Authors: Alex Deucher |
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23 | */ |
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24 | #include |
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25 | #include "radeon.h" |
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26 | #include "radeon_asic.h" |
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27 | #include "r600d.h" |
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28 | |||
29 | u32 r600_gpu_check_soft_reset(struct radeon_device *rdev); |
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30 | |||
31 | /* |
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32 | * DMA |
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33 | * Starting with R600, the GPU has an asynchronous |
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34 | * DMA engine. The programming model is very similar |
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35 | * to the 3D engine (ring buffer, IBs, etc.), but the |
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36 | * DMA controller has it's own packet format that is |
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37 | * different form the PM4 format used by the 3D engine. |
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38 | * It supports copying data, writing embedded data, |
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39 | * solid fills, and a number of other things. It also |
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40 | * has support for tiling/detiling of buffers. |
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41 | */ |
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42 | |||
43 | /** |
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44 | * r600_dma_get_rptr - get the current read pointer |
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45 | * |
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46 | * @rdev: radeon_device pointer |
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47 | * @ring: radeon ring pointer |
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48 | * |
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49 | * Get the current rptr from the hardware (r6xx+). |
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50 | */ |
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51 | uint32_t r600_dma_get_rptr(struct radeon_device *rdev, |
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52 | struct radeon_ring *ring) |
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53 | { |
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54 | u32 rptr; |
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55 | |||
56 | if (rdev->wb.enabled) |
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57 | rptr = rdev->wb.wb[ring->rptr_offs/4]; |
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58 | else |
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59 | rptr = RREG32(DMA_RB_RPTR); |
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60 | |||
61 | return (rptr & 0x3fffc) >> 2; |
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62 | } |
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63 | |||
64 | /** |
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65 | * r600_dma_get_wptr - get the current write pointer |
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66 | * |
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67 | * @rdev: radeon_device pointer |
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68 | * @ring: radeon ring pointer |
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69 | * |
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70 | * Get the current wptr from the hardware (r6xx+). |
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71 | */ |
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72 | uint32_t r600_dma_get_wptr(struct radeon_device *rdev, |
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73 | struct radeon_ring *ring) |
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74 | { |
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75 | return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2; |
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76 | } |
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77 | |||
78 | /** |
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79 | * r600_dma_set_wptr - commit the write pointer |
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80 | * |
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81 | * @rdev: radeon_device pointer |
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82 | * @ring: radeon ring pointer |
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83 | * |
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84 | * Write the wptr back to the hardware (r6xx+). |
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85 | */ |
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86 | void r600_dma_set_wptr(struct radeon_device *rdev, |
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87 | struct radeon_ring *ring) |
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88 | { |
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89 | WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc); |
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90 | } |
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91 | |||
92 | /** |
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93 | * r600_dma_stop - stop the async dma engine |
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94 | * |
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95 | * @rdev: radeon_device pointer |
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96 | * |
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97 | * Stop the async dma engine (r6xx-evergreen). |
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98 | */ |
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99 | void r600_dma_stop(struct radeon_device *rdev) |
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100 | { |
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101 | u32 rb_cntl = RREG32(DMA_RB_CNTL); |
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102 | |||
103 | if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) |
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104 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
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105 | |||
106 | rb_cntl &= ~DMA_RB_ENABLE; |
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107 | WREG32(DMA_RB_CNTL, rb_cntl); |
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108 | |||
109 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; |
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110 | } |
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111 | |||
112 | /** |
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113 | * r600_dma_resume - setup and start the async dma engine |
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114 | * |
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115 | * @rdev: radeon_device pointer |
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116 | * |
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117 | * Set up the DMA ring buffer and enable it. (r6xx-evergreen). |
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118 | * Returns 0 for success, error for failure. |
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119 | */ |
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120 | int r600_dma_resume(struct radeon_device *rdev) |
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121 | { |
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122 | struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
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123 | u32 rb_cntl, dma_cntl, ib_cntl; |
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124 | u32 rb_bufsz; |
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125 | int r; |
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126 | |||
127 | WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0); |
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128 | WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); |
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129 | |||
130 | /* Set ring buffer size in dwords */ |
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131 | rb_bufsz = order_base_2(ring->ring_size / 4); |
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132 | rb_cntl = rb_bufsz << 1; |
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133 | #ifdef __BIG_ENDIAN |
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134 | rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; |
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135 | #endif |
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136 | WREG32(DMA_RB_CNTL, rb_cntl); |
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137 | |||
138 | /* Initialize the ring buffer's read and write pointers */ |
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139 | WREG32(DMA_RB_RPTR, 0); |
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140 | WREG32(DMA_RB_WPTR, 0); |
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141 | |||
142 | /* set the wb address whether it's enabled or not */ |
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143 | WREG32(DMA_RB_RPTR_ADDR_HI, |
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144 | upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); |
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145 | WREG32(DMA_RB_RPTR_ADDR_LO, |
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146 | ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); |
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147 | |||
148 | if (rdev->wb.enabled) |
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149 | rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; |
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150 | |||
151 | WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); |
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152 | |||
153 | /* enable DMA IBs */ |
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154 | ib_cntl = DMA_IB_ENABLE; |
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155 | #ifdef __BIG_ENDIAN |
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156 | ib_cntl |= DMA_IB_SWAP_ENABLE; |
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157 | #endif |
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158 | WREG32(DMA_IB_CNTL, ib_cntl); |
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159 | |||
160 | dma_cntl = RREG32(DMA_CNTL); |
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161 | dma_cntl &= ~CTXEMPTY_INT_ENABLE; |
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162 | WREG32(DMA_CNTL, dma_cntl); |
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163 | |||
164 | if (rdev->family >= CHIP_RV770) |
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165 | WREG32(DMA_MODE, 1); |
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166 | |||
167 | ring->wptr = 0; |
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168 | WREG32(DMA_RB_WPTR, ring->wptr << 2); |
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169 | |||
170 | WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); |
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171 | |||
172 | ring->ready = true; |
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173 | |||
174 | r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring); |
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175 | if (r) { |
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176 | ring->ready = false; |
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177 | return r; |
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178 | } |
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179 | |||
180 | if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) |
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181 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
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182 | |||
183 | return 0; |
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184 | } |
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185 | |||
186 | /** |
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187 | * r600_dma_fini - tear down the async dma engine |
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188 | * |
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189 | * @rdev: radeon_device pointer |
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190 | * |
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191 | * Stop the async dma engine and free the ring (r6xx-evergreen). |
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192 | */ |
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193 | void r600_dma_fini(struct radeon_device *rdev) |
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194 | { |
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195 | r600_dma_stop(rdev); |
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196 | radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); |
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197 | } |
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198 | |||
199 | /** |
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200 | * r600_dma_is_lockup - Check if the DMA engine is locked up |
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201 | * |
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202 | * @rdev: radeon_device pointer |
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203 | * @ring: radeon_ring structure holding ring information |
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204 | * |
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205 | * Check if the async DMA engine is locked up. |
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206 | * Returns true if the engine appears to be locked up, false if not. |
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207 | */ |
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208 | bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
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209 | { |
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210 | u32 reset_mask = r600_gpu_check_soft_reset(rdev); |
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211 | |||
212 | if (!(reset_mask & RADEON_RESET_DMA)) { |
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213 | radeon_ring_lockup_update(rdev, ring); |
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214 | return false; |
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215 | } |
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216 | return radeon_ring_test_lockup(rdev, ring); |
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217 | } |
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218 | |||
219 | |||
220 | /** |
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221 | * r600_dma_ring_test - simple async dma engine test |
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222 | * |
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223 | * @rdev: radeon_device pointer |
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224 | * @ring: radeon_ring structure holding ring information |
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225 | * |
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226 | * Test the DMA engine by writing using it to write an |
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227 | * value to memory. (r6xx-SI). |
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228 | * Returns 0 for success, error for failure. |
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229 | */ |
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230 | int r600_dma_ring_test(struct radeon_device *rdev, |
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231 | struct radeon_ring *ring) |
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232 | { |
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233 | unsigned i; |
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234 | int r; |
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5179 | serge | 235 | unsigned index; |
5078 | serge | 236 | u32 tmp; |
5179 | serge | 237 | u64 gpu_addr; |
5078 | serge | 238 | |
5179 | serge | 239 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
240 | index = R600_WB_DMA_RING_TEST_OFFSET; |
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241 | else |
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242 | index = CAYMAN_WB_DMA1_RING_TEST_OFFSET; |
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5078 | serge | 243 | |
5179 | serge | 244 | gpu_addr = rdev->wb.gpu_addr + index; |
245 | |||
5078 | serge | 246 | tmp = 0xCAFEDEAD; |
5179 | serge | 247 | rdev->wb.wb[index/4] = cpu_to_le32(tmp); |
5078 | serge | 248 | |
249 | r = radeon_ring_lock(rdev, ring, 4); |
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250 | if (r) { |
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251 | DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); |
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252 | return r; |
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253 | } |
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254 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); |
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5179 | serge | 255 | radeon_ring_write(ring, lower_32_bits(gpu_addr)); |
256 | radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); |
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5078 | serge | 257 | radeon_ring_write(ring, 0xDEADBEEF); |
258 | radeon_ring_unlock_commit(rdev, ring, false); |
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259 | |||
260 | for (i = 0; i < rdev->usec_timeout; i++) { |
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5179 | serge | 261 | tmp = le32_to_cpu(rdev->wb.wb[index/4]); |
5078 | serge | 262 | if (tmp == 0xDEADBEEF) |
263 | break; |
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264 | DRM_UDELAY(1); |
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265 | } |
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266 | |||
267 | if (i < rdev->usec_timeout) { |
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268 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); |
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269 | } else { |
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270 | DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", |
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271 | ring->idx, tmp); |
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272 | r = -EINVAL; |
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273 | } |
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274 | return r; |
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275 | } |
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276 | |||
277 | /** |
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278 | * r600_dma_fence_ring_emit - emit a fence on the DMA ring |
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279 | * |
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280 | * @rdev: radeon_device pointer |
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281 | * @fence: radeon fence object |
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282 | * |
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283 | * Add a DMA fence packet to the ring to write |
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284 | * the fence seq number and DMA trap packet to generate |
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285 | * an interrupt if needed (r6xx-r7xx). |
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286 | */ |
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287 | void r600_dma_fence_ring_emit(struct radeon_device *rdev, |
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288 | struct radeon_fence *fence) |
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289 | { |
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290 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
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291 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
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292 | |||
293 | /* write the fence */ |
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294 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0)); |
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295 | radeon_ring_write(ring, addr & 0xfffffffc); |
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296 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); |
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297 | radeon_ring_write(ring, lower_32_bits(fence->seq)); |
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298 | /* generate an interrupt */ |
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299 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0)); |
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300 | } |
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301 | |||
302 | /** |
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303 | * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring |
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304 | * |
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305 | * @rdev: radeon_device pointer |
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306 | * @ring: radeon_ring structure holding ring information |
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307 | * @semaphore: radeon semaphore object |
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308 | * @emit_wait: wait or signal semaphore |
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309 | * |
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310 | * Add a DMA semaphore packet to the ring wait on or signal |
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311 | * other rings (r6xx-SI). |
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312 | */ |
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313 | bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev, |
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314 | struct radeon_ring *ring, |
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315 | struct radeon_semaphore *semaphore, |
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316 | bool emit_wait) |
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317 | { |
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318 | u64 addr = semaphore->gpu_addr; |
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319 | u32 s = emit_wait ? 0 : 1; |
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320 | |||
321 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0)); |
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322 | radeon_ring_write(ring, addr & 0xfffffffc); |
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323 | radeon_ring_write(ring, upper_32_bits(addr) & 0xff); |
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324 | |||
325 | return true; |
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326 | } |
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327 | |||
328 | /** |
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329 | * r600_dma_ib_test - test an IB on the DMA engine |
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330 | * |
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331 | * @rdev: radeon_device pointer |
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332 | * @ring: radeon_ring structure holding ring information |
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333 | * |
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334 | * Test a simple IB in the DMA ring (r6xx-SI). |
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335 | * Returns 0 on success, error on failure. |
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336 | */ |
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337 | int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
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338 | { |
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339 | struct radeon_ib ib; |
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340 | unsigned i; |
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341 | int r; |
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342 | void __iomem *ptr = (void *)rdev->vram_scratch.ptr; |
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343 | u32 tmp = 0; |
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344 | |||
345 | if (!ptr) { |
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346 | DRM_ERROR("invalid vram scratch pointer\n"); |
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347 | return -EINVAL; |
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348 | } |
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349 | |||
350 | tmp = 0xCAFEDEAD; |
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351 | writel(tmp, ptr); |
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352 | |||
353 | r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); |
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354 | if (r) { |
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355 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); |
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356 | return r; |
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357 | } |
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358 | |||
359 | ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1); |
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360 | ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; |
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361 | ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff; |
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362 | ib.ptr[3] = 0xDEADBEEF; |
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363 | ib.length_dw = 4; |
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364 | |||
365 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
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366 | if (r) { |
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367 | radeon_ib_free(rdev, &ib); |
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368 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
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369 | return r; |
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370 | } |
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371 | r = radeon_fence_wait(ib.fence, false); |
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372 | if (r) { |
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373 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); |
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374 | return r; |
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375 | } |
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376 | for (i = 0; i < rdev->usec_timeout; i++) { |
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377 | tmp = readl(ptr); |
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378 | if (tmp == 0xDEADBEEF) |
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379 | break; |
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380 | DRM_UDELAY(1); |
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381 | } |
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382 | if (i < rdev->usec_timeout) { |
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383 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); |
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384 | } else { |
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385 | DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); |
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386 | r = -EINVAL; |
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387 | } |
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388 | radeon_ib_free(rdev, &ib); |
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389 | return r; |
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390 | } |
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391 | |||
392 | /** |
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393 | * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine |
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394 | * |
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395 | * @rdev: radeon_device pointer |
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396 | * @ib: IB object to schedule |
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397 | * |
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398 | * Schedule an IB in the DMA ring (r6xx-r7xx). |
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399 | */ |
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400 | void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
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401 | { |
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402 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
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403 | |||
404 | if (rdev->wb.enabled) { |
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405 | u32 next_rptr = ring->wptr + 4; |
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406 | while ((next_rptr & 7) != 5) |
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407 | next_rptr++; |
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408 | next_rptr += 3; |
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409 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); |
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410 | radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); |
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411 | radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); |
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412 | radeon_ring_write(ring, next_rptr); |
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413 | } |
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414 | |||
415 | /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. |
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416 | * Pad as necessary with NOPs. |
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417 | */ |
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418 | while ((ring->wptr & 7) != 5) |
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419 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
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420 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0)); |
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421 | radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); |
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422 | radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); |
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423 | |||
424 | } |
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425 | |||
426 | /** |
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427 | * r600_copy_dma - copy pages using the DMA engine |
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428 | * |
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429 | * @rdev: radeon_device pointer |
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430 | * @src_offset: src GPU address |
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431 | * @dst_offset: dst GPU address |
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432 | * @num_gpu_pages: number of GPU pages to xfer |
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433 | * @fence: radeon fence object |
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434 | * |
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435 | * Copy GPU paging using the DMA engine (r6xx). |
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436 | * Used by the radeon ttm implementation to move pages if |
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437 | * registered as the asic copy callback. |
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438 | */ |
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439 | int r600_copy_dma(struct radeon_device *rdev, |
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440 | uint64_t src_offset, uint64_t dst_offset, |
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441 | unsigned num_gpu_pages, |
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442 | struct radeon_fence **fence) |
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443 | { |
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444 | struct radeon_semaphore *sem = NULL; |
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445 | int ring_index = rdev->asic->copy.dma_ring_index; |
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446 | struct radeon_ring *ring = &rdev->ring[ring_index]; |
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447 | u32 size_in_dw, cur_size_in_dw; |
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448 | int i, num_loops; |
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449 | int r = 0; |
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450 | |||
451 | r = radeon_semaphore_create(rdev, &sem); |
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452 | if (r) { |
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453 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
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454 | return r; |
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455 | } |
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456 | |||
457 | size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; |
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458 | num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE); |
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459 | r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8); |
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460 | if (r) { |
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461 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
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462 | radeon_semaphore_free(rdev, &sem, NULL); |
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463 | return r; |
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464 | } |
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465 | |||
466 | radeon_semaphore_sync_to(sem, *fence); |
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467 | radeon_semaphore_sync_rings(rdev, sem, ring->idx); |
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468 | |||
469 | for (i = 0; i < num_loops; i++) { |
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470 | cur_size_in_dw = size_in_dw; |
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471 | if (cur_size_in_dw > 0xFFFE) |
||
472 | cur_size_in_dw = 0xFFFE; |
||
473 | size_in_dw -= cur_size_in_dw; |
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474 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); |
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475 | radeon_ring_write(ring, dst_offset & 0xfffffffc); |
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476 | radeon_ring_write(ring, src_offset & 0xfffffffc); |
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477 | radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | |
||
478 | (upper_32_bits(src_offset) & 0xff))); |
||
479 | src_offset += cur_size_in_dw * 4; |
||
480 | dst_offset += cur_size_in_dw * 4; |
||
481 | } |
||
482 | |||
483 | r = radeon_fence_emit(rdev, fence, ring->idx); |
||
484 | if (r) { |
||
485 | radeon_ring_unlock_undo(rdev, ring); |
||
486 | radeon_semaphore_free(rdev, &sem, NULL); |
||
487 | return r; |
||
488 | } |
||
489 | |||
490 | radeon_ring_unlock_commit(rdev, ring, false); |
||
491 | radeon_semaphore_free(rdev, &sem, *fence); |
||
492 | |||
493 | return r; |
||
494 | }><>>><>><>>>>>><>><>><> |