WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r600.c

Rev	Author	Line No.	Line
1128	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1233	serge	28	#include
1221	serge	29	#include
1128	serge	30	#include "drmP.h"
1221	serge	31	#include "radeon_drm.h"
1128	serge	32	#include "radeon.h"
1221	serge	33	#include "radeon_mode.h"
		34	#include "r600d.h"
		35	#include "atom.h"
		36	#include "avivod.h"
1128	serge	37
1221	serge	38	#define PFP_UCODE_SIZE 576
		39	#define PM4_UCODE_SIZE 1792
1321	serge	40	#define RLC_UCODE_SIZE 768
1221	serge	41	#define R700_PFP_UCODE_SIZE 848
		42	#define R700_PM4_UCODE_SIZE 1360
1321	serge	43	#define R700_RLC_UCODE_SIZE 1024
1128	serge	44
1221	serge	45	/* Firmware Names */
		46	MODULE_FIRMWARE("radeon/R600_pfp.bin");
		47	MODULE_FIRMWARE("radeon/R600_me.bin");
		48	MODULE_FIRMWARE("radeon/RV610_pfp.bin");
		49	MODULE_FIRMWARE("radeon/RV610_me.bin");
		50	MODULE_FIRMWARE("radeon/RV630_pfp.bin");
		51	MODULE_FIRMWARE("radeon/RV630_me.bin");
		52	MODULE_FIRMWARE("radeon/RV620_pfp.bin");
		53	MODULE_FIRMWARE("radeon/RV620_me.bin");
		54	MODULE_FIRMWARE("radeon/RV635_pfp.bin");
		55	MODULE_FIRMWARE("radeon/RV635_me.bin");
		56	MODULE_FIRMWARE("radeon/RV670_pfp.bin");
		57	MODULE_FIRMWARE("radeon/RV670_me.bin");
		58	MODULE_FIRMWARE("radeon/RS780_pfp.bin");
		59	MODULE_FIRMWARE("radeon/RS780_me.bin");
		60	MODULE_FIRMWARE("radeon/RV770_pfp.bin");
		61	MODULE_FIRMWARE("radeon/RV770_me.bin");
		62	MODULE_FIRMWARE("radeon/RV730_pfp.bin");
		63	MODULE_FIRMWARE("radeon/RV730_me.bin");
		64	MODULE_FIRMWARE("radeon/RV710_pfp.bin");
		65	MODULE_FIRMWARE("radeon/RV710_me.bin");
1321	serge	66	MODULE_FIRMWARE("radeon/R600_rlc.bin");
		67	MODULE_FIRMWARE("radeon/R700_rlc.bin");
1221	serge	68
		69	int r600_debugfs_mc_info_init(struct radeon_device *rdev);
		70
		71	/* r600,rv610,rv630,rv620,rv635,rv670 */
1128	serge	72	int r600_mc_wait_for_idle(struct radeon_device *rdev);
		73	void r600_gpu_init(struct radeon_device *rdev);
1221	serge	74	void r600_fini(struct radeon_device *rdev);
1128	serge	75
1321	serge	76	/* hpd for digital panel detect/disconnect */
		77	bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
		78	{
		79	bool connected = false;
		80
		81	if (ASIC_IS_DCE3(rdev)) {
		82	switch (hpd) {
		83	case RADEON_HPD_1:
		84	if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
		85	connected = true;
		86	break;
		87	case RADEON_HPD_2:
		88	if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
		89	connected = true;
		90	break;
		91	case RADEON_HPD_3:
		92	if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
		93	connected = true;
		94	break;
		95	case RADEON_HPD_4:
		96	if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
		97	connected = true;
		98	break;
		99	/* DCE 3.2 */
		100	case RADEON_HPD_5:
		101	if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
		102	connected = true;
		103	break;
		104	case RADEON_HPD_6:
		105	if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
		106	connected = true;
		107	break;
		108	default:
		109	break;
		110	}
		111	} else {
		112	switch (hpd) {
		113	case RADEON_HPD_1:
		114	if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
		115	connected = true;
		116	break;
		117	case RADEON_HPD_2:
		118	if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
		119	connected = true;
		120	break;
		121	case RADEON_HPD_3:
		122	if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
		123	connected = true;
		124	break;
		125	default:
		126	break;
		127	}
		128	}
		129	return connected;
		130	}
		131
		132	void r600_hpd_set_polarity(struct radeon_device *rdev,
		133	enum radeon_hpd_id hpd)
		134	{
		135	u32 tmp;
		136	bool connected = r600_hpd_sense(rdev, hpd);
		137
		138	if (ASIC_IS_DCE3(rdev)) {
		139	switch (hpd) {
		140	case RADEON_HPD_1:
		141	tmp = RREG32(DC_HPD1_INT_CONTROL);
		142	if (connected)
		143	tmp &= ~DC_HPDx_INT_POLARITY;
		144	else
		145	tmp \|= DC_HPDx_INT_POLARITY;
		146	WREG32(DC_HPD1_INT_CONTROL, tmp);
		147	break;
		148	case RADEON_HPD_2:
		149	tmp = RREG32(DC_HPD2_INT_CONTROL);
		150	if (connected)
		151	tmp &= ~DC_HPDx_INT_POLARITY;
		152	else
		153	tmp \|= DC_HPDx_INT_POLARITY;
		154	WREG32(DC_HPD2_INT_CONTROL, tmp);
		155	break;
		156	case RADEON_HPD_3:
		157	tmp = RREG32(DC_HPD3_INT_CONTROL);
		158	if (connected)
		159	tmp &= ~DC_HPDx_INT_POLARITY;
		160	else
		161	tmp \|= DC_HPDx_INT_POLARITY;
		162	WREG32(DC_HPD3_INT_CONTROL, tmp);
		163	break;
		164	case RADEON_HPD_4:
		165	tmp = RREG32(DC_HPD4_INT_CONTROL);
		166	if (connected)
		167	tmp &= ~DC_HPDx_INT_POLARITY;
		168	else
		169	tmp \|= DC_HPDx_INT_POLARITY;
		170	WREG32(DC_HPD4_INT_CONTROL, tmp);
		171	break;
		172	case RADEON_HPD_5:
		173	tmp = RREG32(DC_HPD5_INT_CONTROL);
		174	if (connected)
		175	tmp &= ~DC_HPDx_INT_POLARITY;
		176	else
		177	tmp \|= DC_HPDx_INT_POLARITY;
		178	WREG32(DC_HPD5_INT_CONTROL, tmp);
		179	break;
		180	/* DCE 3.2 */
		181	case RADEON_HPD_6:
		182	tmp = RREG32(DC_HPD6_INT_CONTROL);
		183	if (connected)
		184	tmp &= ~DC_HPDx_INT_POLARITY;
		185	else
		186	tmp \|= DC_HPDx_INT_POLARITY;
		187	WREG32(DC_HPD6_INT_CONTROL, tmp);
		188	break;
		189	default:
		190	break;
		191	}
		192	} else {
		193	switch (hpd) {
		194	case RADEON_HPD_1:
		195	tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
		196	if (connected)
		197	tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
		198	else
		199	tmp \|= DC_HOT_PLUG_DETECTx_INT_POLARITY;
		200	WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
		201	break;
		202	case RADEON_HPD_2:
		203	tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
		204	if (connected)
		205	tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
		206	else
		207	tmp \|= DC_HOT_PLUG_DETECTx_INT_POLARITY;
		208	WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
		209	break;
		210	case RADEON_HPD_3:
		211	tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
		212	if (connected)
		213	tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
		214	else
		215	tmp \|= DC_HOT_PLUG_DETECTx_INT_POLARITY;
		216	WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
		217	break;
		218	default:
		219	break;
		220	}
		221	}
		222	}
		223
		224	void r600_hpd_init(struct radeon_device *rdev)
		225	{
		226	struct drm_device *dev = rdev->ddev;
		227	struct drm_connector *connector;
		228
		229	if (ASIC_IS_DCE3(rdev)) {
		230	u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) \| DC_HPDx_RX_INT_TIMER(0xfa);
		231	if (ASIC_IS_DCE32(rdev))
		232	tmp \|= DC_HPDx_EN;
		233
		234	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		235	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		236	switch (radeon_connector->hpd.hpd) {
		237	case RADEON_HPD_1:
		238	WREG32(DC_HPD1_CONTROL, tmp);
		239	rdev->irq.hpd[0] = true;
		240	break;
		241	case RADEON_HPD_2:
		242	WREG32(DC_HPD2_CONTROL, tmp);
		243	rdev->irq.hpd[1] = true;
		244	break;
		245	case RADEON_HPD_3:
		246	WREG32(DC_HPD3_CONTROL, tmp);
		247	rdev->irq.hpd[2] = true;
		248	break;
		249	case RADEON_HPD_4:
		250	WREG32(DC_HPD4_CONTROL, tmp);
		251	rdev->irq.hpd[3] = true;
		252	break;
		253	/* DCE 3.2 */
		254	case RADEON_HPD_5:
		255	WREG32(DC_HPD5_CONTROL, tmp);
		256	rdev->irq.hpd[4] = true;
		257	break;
		258	case RADEON_HPD_6:
		259	WREG32(DC_HPD6_CONTROL, tmp);
		260	rdev->irq.hpd[5] = true;
		261	break;
		262	default:
		263	break;
		264	}
		265	}
		266	} else {
		267	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		268	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		269	switch (radeon_connector->hpd.hpd) {
		270	case RADEON_HPD_1:
		271	WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
		272	rdev->irq.hpd[0] = true;
		273	break;
		274	case RADEON_HPD_2:
		275	WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
		276	rdev->irq.hpd[1] = true;
		277	break;
		278	case RADEON_HPD_3:
		279	WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
		280	rdev->irq.hpd[2] = true;
		281	break;
		282	default:
		283	break;
		284	}
		285	}
		286	}
		287	r600_irq_set(rdev);
		288	}
		289
		290	void r600_hpd_fini(struct radeon_device *rdev)
		291	{
		292	struct drm_device *dev = rdev->ddev;
		293	struct drm_connector *connector;
		294
		295	if (ASIC_IS_DCE3(rdev)) {
		296	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		297	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		298	switch (radeon_connector->hpd.hpd) {
		299	case RADEON_HPD_1:
		300	WREG32(DC_HPD1_CONTROL, 0);
		301	rdev->irq.hpd[0] = false;
		302	break;
		303	case RADEON_HPD_2:
		304	WREG32(DC_HPD2_CONTROL, 0);
		305	rdev->irq.hpd[1] = false;
		306	break;
		307	case RADEON_HPD_3:
		308	WREG32(DC_HPD3_CONTROL, 0);
		309	rdev->irq.hpd[2] = false;
		310	break;
		311	case RADEON_HPD_4:
		312	WREG32(DC_HPD4_CONTROL, 0);
		313	rdev->irq.hpd[3] = false;
		314	break;
		315	/* DCE 3.2 */
		316	case RADEON_HPD_5:
		317	WREG32(DC_HPD5_CONTROL, 0);
		318	rdev->irq.hpd[4] = false;
		319	break;
		320	case RADEON_HPD_6:
		321	WREG32(DC_HPD6_CONTROL, 0);
		322	rdev->irq.hpd[5] = false;
		323	break;
		324	default:
		325	break;
		326	}
		327	}
		328	} else {
		329	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		330	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		331	switch (radeon_connector->hpd.hpd) {
		332	case RADEON_HPD_1:
		333	WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
		334	rdev->irq.hpd[0] = false;
		335	break;
		336	case RADEON_HPD_2:
		337	WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
		338	rdev->irq.hpd[1] = false;
		339	break;
		340	case RADEON_HPD_3:
		341	WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
		342	rdev->irq.hpd[2] = false;
		343	break;
		344	default:
		345	break;
		346	}
		347	}
		348	}
		349	}
		350
1128	serge	351	/*
1221	serge	352	* R600 PCIE GART
1128	serge	353	*/
1221	serge	354	int r600_gart_clear_page(struct radeon_device *rdev, int i)
1128	serge	355	{
1221	serge	356	void __iomem ptr = (void )rdev->gart.table.vram.ptr;
		357	u64 pte;
1128	serge	358
1221	serge	359	if (i < 0 \|\| i > rdev->gart.num_gpu_pages)
		360	return -EINVAL;
		361	pte = 0;
		362	writeq(pte, ((void __iomem )ptr) + (i 8));
		363	return 0;
		364	}
1128	serge	365
1221	serge	366	void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
		367	{
		368	unsigned i;
		369	u32 tmp;
1128	serge	370
1221	serge	371	WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
		372	WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
		373	WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
		374	for (i = 0; i < rdev->usec_timeout; i++) {
		375	/* read MC_STATUS */
		376	tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
		377	tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
		378	if (tmp == 2) {
		379	printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
		380	return;
		381	}
		382	if (tmp) {
		383	return;
		384	}
		385	udelay(1);
1128	serge	386	}
1221	serge	387	}
1128	serge	388
1221	serge	389	int r600_pcie_gart_init(struct radeon_device *rdev)
		390	{
		391	int r;
		392
		393	if (rdev->gart.table.vram.robj) {
		394	WARN(1, "R600 PCIE GART already initialized.\n");
		395	return 0;
		396	}
		397	/* Initialize common gart structure */
		398	r = radeon_gart_init(rdev);
		399	if (r)
		400	return r;
		401	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
		402	return radeon_gart_table_vram_alloc(rdev);
		403	}
		404
		405	int r600_pcie_gart_enable(struct radeon_device *rdev)
		406	{
		407	u32 tmp;
		408	int r, i;
		409
		410	if (rdev->gart.table.vram.robj == NULL) {
		411	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
		412	return -EINVAL;
		413	}
		414	r = radeon_gart_table_vram_pin(rdev);
		415	if (r)
		416	return r;
		417
		418	/* Setup L2 cache */
		419	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \|
		420	ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE \|
		421	EFFECTIVE_L2_QUEUE_SIZE(7));
		422	WREG32(VM_L2_CNTL2, 0);
		423	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) \| BANK_SELECT_1(1));
		424	/* Setup TLB control */
		425	tmp = ENABLE_L1_TLB \| ENABLE_L1_FRAGMENT_PROCESSING \|
		426	SYSTEM_ACCESS_MODE_NOT_IN_SYS \|
		427	EFFECTIVE_L1_TLB_SIZE(5) \| EFFECTIVE_L1_QUEUE_SIZE(5) \|
		428	ENABLE_WAIT_L2_QUERY;
		429	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
		430	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
		431	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp \| ENABLE_L1_STRICT_ORDERING);
		432	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
		433	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
		434	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
		435	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
		436	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
		437	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
		438	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
		439	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
		440	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
		441	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp \| ENABLE_SEMAPHORE_MODE);
		442	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp \| ENABLE_SEMAPHORE_MODE);
		443	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
		444	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
		445	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
		446	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT \| PAGE_TABLE_DEPTH(0) \|
		447	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
		448	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
		449	(u32)(rdev->dummy_page.addr >> 12));
		450	for (i = 1; i < 7; i++)
		451	WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
		452
		453	r600_pcie_gart_tlb_flush(rdev);
		454	rdev->gart.ready = true;
1128	serge	455	return 0;
		456	}
		457
1221	serge	458	void r600_pcie_gart_disable(struct radeon_device *rdev)
1128	serge	459	{
1221	serge	460	u32 tmp;
1321	serge	461	int i, r;
1221	serge	462
		463	/* Disable all tables */
		464	for (i = 0; i < 7; i++)
		465	WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
		466
		467	/* Disable L2 cache */
		468	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING \|
		469	EFFECTIVE_L2_QUEUE_SIZE(7));
		470	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) \| BANK_SELECT_1(1));
		471	/* Setup L1 TLB control */
		472	tmp = EFFECTIVE_L1_TLB_SIZE(5) \| EFFECTIVE_L1_QUEUE_SIZE(5) \|
		473	ENABLE_WAIT_L2_QUERY;
		474	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
		475	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
		476	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
		477	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
		478	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
		479	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
		480	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
		481	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
		482	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
		483	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
		484	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
		485	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
		486	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
		487	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
		488	if (rdev->gart.table.vram.robj) {
1233	serge	489	// radeon_object_kunmap(rdev->gart.table.vram.robj);
		490	// radeon_object_unpin(rdev->gart.table.vram.robj);
1221	serge	491	}
1128	serge	492	}
		493
1221	serge	494	void r600_pcie_gart_fini(struct radeon_device *rdev)
		495	{
		496	r600_pcie_gart_disable(rdev);
		497	radeon_gart_table_vram_free(rdev);
		498	radeon_gart_fini(rdev);
		499	}
1128	serge	500
1221	serge	501	void r600_agp_enable(struct radeon_device *rdev)
1128	serge	502	{
1221	serge	503	u32 tmp;
		504	int i;
		505
		506	/* Setup L2 cache */
		507	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE \| ENABLE_L2_FRAGMENT_PROCESSING \|
		508	ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE \|
		509	EFFECTIVE_L2_QUEUE_SIZE(7));
		510	WREG32(VM_L2_CNTL2, 0);
		511	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) \| BANK_SELECT_1(1));
		512	/* Setup TLB control */
		513	tmp = ENABLE_L1_TLB \| ENABLE_L1_FRAGMENT_PROCESSING \|
		514	SYSTEM_ACCESS_MODE_NOT_IN_SYS \|
		515	EFFECTIVE_L1_TLB_SIZE(5) \| EFFECTIVE_L1_QUEUE_SIZE(5) \|
		516	ENABLE_WAIT_L2_QUERY;
		517	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
		518	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
		519	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp \| ENABLE_L1_STRICT_ORDERING);
		520	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
		521	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
		522	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
		523	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
		524	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
		525	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
		526	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
		527	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
		528	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
		529	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp \| ENABLE_SEMAPHORE_MODE);
		530	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp \| ENABLE_SEMAPHORE_MODE);
		531	for (i = 0; i < 7; i++)
		532	WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1128	serge	533	}
		534
		535	int r600_mc_wait_for_idle(struct radeon_device *rdev)
		536	{
1221	serge	537	unsigned i;
		538	u32 tmp;
		539
		540	for (i = 0; i < rdev->usec_timeout; i++) {
		541	/* read MC_STATUS */
		542	tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
		543	if (!tmp)
1128	serge	544	return 0;
1221	serge	545	udelay(1);
		546	}
		547	return -1;
1128	serge	548	}
		549
1221	serge	550	static void r600_mc_program(struct radeon_device *rdev)
1128	serge	551	{
1221	serge	552	struct rv515_mc_save save;
		553	u32 tmp;
		554	int i, j;
		555
		556	/* Initialize HDP */
		557	for (i = 0, j = 0; i < 32; i++, j += 0x18) {
		558	WREG32((0x2c14 + j), 0x00000000);
		559	WREG32((0x2c18 + j), 0x00000000);
		560	WREG32((0x2c1c + j), 0x00000000);
		561	WREG32((0x2c20 + j), 0x00000000);
		562	WREG32((0x2c24 + j), 0x00000000);
		563	}
		564	WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
		565
		566	rv515_mc_stop(rdev, &save);
		567	if (r600_mc_wait_for_idle(rdev)) {
		568	dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
		569	}
		570	/* Lockout access through VGA aperture (doesn't exist before R600) */
		571	WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
		572	/* Update configuration */
		573	if (rdev->flags & RADEON_IS_AGP) {
		574	if (rdev->mc.vram_start < rdev->mc.gtt_start) {
		575	/* VRAM before AGP */
		576	WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
		577	rdev->mc.vram_start >> 12);
		578	WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
		579	rdev->mc.gtt_end >> 12);
		580	} else {
		581	/* VRAM after AGP */
		582	WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
		583	rdev->mc.gtt_start >> 12);
		584	WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
		585	rdev->mc.vram_end >> 12);
		586	}
		587	} else {
		588	WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
		589	WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
		590	}
		591	WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
		592	tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
		593	tmp \|= ((rdev->mc.vram_start >> 24) & 0xFFFF);
		594	WREG32(MC_VM_FB_LOCATION, tmp);
		595	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
		596	WREG32(HDP_NONSURFACE_INFO, (2 << 7));
		597	WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size \| 0x3FF);
		598	if (rdev->flags & RADEON_IS_AGP) {
		599	WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
		600	WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
		601	WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
		602	} else {
		603	WREG32(MC_VM_AGP_BASE, 0);
		604	WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
		605	WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
		606	}
		607	if (r600_mc_wait_for_idle(rdev)) {
		608	dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
		609	}
		610	rv515_mc_resume(rdev, &save);
		611	/* we need to own VRAM, so turn off the VGA renderer here
		612	* to stop it overwriting our objects */
		613	rv515_vga_render_disable(rdev);
1128	serge	614	}
		615
1221	serge	616	int r600_mc_init(struct radeon_device *rdev)
1128	serge	617	{
1221	serge	618	fixed20_12 a;
		619	u32 tmp;
1268	serge	620	int chansize, numchan;
1221	serge	621	int r;
1128	serge	622
1221	serge	623	/* Get VRAM informations */
1128	serge	624	rdev->mc.vram_is_ddr = true;
1221	serge	625	tmp = RREG32(RAMCFG);
		626	if (tmp & CHANSIZE_OVERRIDE) {
1128	serge	627	chansize = 16;
1221	serge	628	} else if (tmp & CHANSIZE_MASK) {
1128	serge	629	chansize = 64;
		630	} else {
		631	chansize = 32;
		632	}
1268	serge	633	tmp = RREG32(CHMAP);
		634	switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
		635	case 0:
		636	default:
		637	numchan = 1;
		638	break;
		639	case 1:
		640	numchan = 2;
		641	break;
		642	case 2:
		643	numchan = 4;
		644	break;
		645	case 3:
		646	numchan = 8;
		647	break;
1128	serge	648	}
1268	serge	649	rdev->mc.vram_width = numchan * chansize;
1221	serge	650	/* Could aper size report 0 ? */
		651	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
		652	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
		653	/* Setup GPU memory space */
		654	rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
		655	rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
		656
		657	if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
		658	rdev->mc.mc_vram_size = rdev->mc.aper_size;
		659
		660	if (rdev->mc.real_vram_size > rdev->mc.aper_size)
		661	rdev->mc.real_vram_size = rdev->mc.aper_size;
		662
		663	if (rdev->flags & RADEON_IS_AGP) {
		664	r = radeon_agp_init(rdev);
		665	if (r)
		666	return r;
		667	/* gtt_size is setup by radeon_agp_init */
		668	rdev->mc.gtt_location = rdev->mc.agp_base;
		669	tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
		670	/* Try to put vram before or after AGP because we
		671	* we want SYSTEM_APERTURE to cover both VRAM and
		672	* AGP so that GPU can catch out of VRAM/AGP access
		673	*/
		674	if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
1313	serge	675	/* Enough place before */
1221	serge	676	rdev->mc.vram_location = rdev->mc.gtt_location -
		677	rdev->mc.mc_vram_size;
		678	} else if (tmp > rdev->mc.mc_vram_size) {
1313	serge	679	/* Enough place after */
1221	serge	680	rdev->mc.vram_location = rdev->mc.gtt_location +
		681	rdev->mc.gtt_size;
		682	} else {
		683	/* Try to setup VRAM then AGP might not
		684	* not work on some card
		685	*/
		686	rdev->mc.vram_location = 0x00000000UL;
		687	rdev->mc.gtt_location = rdev->mc.mc_vram_size;
		688	}
		689	} else {
1268	serge	690	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
1221	serge	691	rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
		692	0xFFFF) << 24;
		693	tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
		694	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
		695	/* Enough place after vram */
		696	rdev->mc.gtt_location = tmp;
		697	} else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
		698	/* Enough place before vram */
		699	rdev->mc.gtt_location = 0;
		700	} else {
		701	/* Not enough place after or before shrink
		702	* gart size
		703	*/
		704	if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
		705	rdev->mc.gtt_location = 0;
		706	rdev->mc.gtt_size = rdev->mc.vram_location;
		707	} else {
		708	rdev->mc.gtt_location = tmp;
		709	rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
		710	}
		711	}
		712	rdev->mc.gtt_location = rdev->mc.mc_vram_size;
		713	}
		714	rdev->mc.vram_start = rdev->mc.vram_location;
		715	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
		716	rdev->mc.gtt_start = rdev->mc.gtt_location;
		717	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
		718	/* FIXME: we should enforce default clock in case GPU is not in
		719	* default setup
		720	*/
		721	a.full = rfixed_const(100);
		722	rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
		723	rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
		724	return 0;
1128	serge	725	}
		726
1221	serge	727	/* We doesn't check that the GPU really needs a reset we simply do the
		728	* reset, it's up to the caller to determine if the GPU needs one. We
		729	* might add an helper function to check that.
		730	*/
		731	int r600_gpu_soft_reset(struct radeon_device *rdev)
1128	serge	732	{
1221	serge	733	struct rv515_mc_save save;
		734	u32 grbm_busy_mask = S_008010_VC_BUSY(1) \| S_008010_VGT_BUSY_NO_DMA(1) \|
		735	S_008010_VGT_BUSY(1) \| S_008010_TA03_BUSY(1) \|
		736	S_008010_TC_BUSY(1) \| S_008010_SX_BUSY(1) \|
		737	S_008010_SH_BUSY(1) \| S_008010_SPI03_BUSY(1) \|
		738	S_008010_SMX_BUSY(1) \| S_008010_SC_BUSY(1) \|
		739	S_008010_PA_BUSY(1) \| S_008010_DB03_BUSY(1) \|
		740	S_008010_CR_BUSY(1) \| S_008010_CB03_BUSY(1) \|
		741	S_008010_GUI_ACTIVE(1);
		742	u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) \| S_008014_SPI1_BUSY(1) \|
		743	S_008014_SPI2_BUSY(1) \| S_008014_SPI3_BUSY(1) \|
		744	S_008014_TA0_BUSY(1) \| S_008014_TA1_BUSY(1) \|
		745	S_008014_TA2_BUSY(1) \| S_008014_TA3_BUSY(1) \|
		746	S_008014_DB0_BUSY(1) \| S_008014_DB1_BUSY(1) \|
		747	S_008014_DB2_BUSY(1) \| S_008014_DB3_BUSY(1) \|
		748	S_008014_CB0_BUSY(1) \| S_008014_CB1_BUSY(1) \|
		749	S_008014_CB2_BUSY(1) \| S_008014_CB3_BUSY(1);
		750	u32 srbm_reset = 0;
		751	u32 tmp;
1128	serge	752
1221	serge	753	dev_info(rdev->dev, "GPU softreset \n");
		754	dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
		755	RREG32(R_008010_GRBM_STATUS));
		756	dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
		757	RREG32(R_008014_GRBM_STATUS2));
		758	dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
		759	RREG32(R_000E50_SRBM_STATUS));
		760	rv515_mc_stop(rdev, &save);
		761	if (r600_mc_wait_for_idle(rdev)) {
		762	dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
		763	}
		764	/* Disable CP parsing/prefetching */
		765	WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
		766	/* Check if any of the rendering block is busy and reset it */
		767	if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) \|\|
		768	(RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
		769	tmp = S_008020_SOFT_RESET_CR(1) \|
		770	S_008020_SOFT_RESET_DB(1) \|
		771	S_008020_SOFT_RESET_CB(1) \|
		772	S_008020_SOFT_RESET_PA(1) \|
		773	S_008020_SOFT_RESET_SC(1) \|
		774	S_008020_SOFT_RESET_SMX(1) \|
		775	S_008020_SOFT_RESET_SPI(1) \|
		776	S_008020_SOFT_RESET_SX(1) \|
		777	S_008020_SOFT_RESET_SH(1) \|
		778	S_008020_SOFT_RESET_TC(1) \|
		779	S_008020_SOFT_RESET_TA(1) \|
		780	S_008020_SOFT_RESET_VC(1) \|
		781	S_008020_SOFT_RESET_VGT(1);
		782	dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
		783	WREG32(R_008020_GRBM_SOFT_RESET, tmp);
		784	(void)RREG32(R_008020_GRBM_SOFT_RESET);
		785	udelay(50);
		786	WREG32(R_008020_GRBM_SOFT_RESET, 0);
		787	(void)RREG32(R_008020_GRBM_SOFT_RESET);
		788	}
		789	/* Reset CP (we always reset CP) */
		790	tmp = S_008020_SOFT_RESET_CP(1);
		791	dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
		792	WREG32(R_008020_GRBM_SOFT_RESET, tmp);
		793	(void)RREG32(R_008020_GRBM_SOFT_RESET);
		794	udelay(50);
		795	WREG32(R_008020_GRBM_SOFT_RESET, 0);
		796	(void)RREG32(R_008020_GRBM_SOFT_RESET);
		797	/* Reset others GPU block if necessary */
		798	if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		799	srbm_reset \|= S_000E60_SOFT_RESET_RLC(1);
		800	if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
		801	srbm_reset \|= S_000E60_SOFT_RESET_GRBM(1);
		802	if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
		803	srbm_reset \|= S_000E60_SOFT_RESET_IH(1);
		804	if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		805	srbm_reset \|= S_000E60_SOFT_RESET_VMC(1);
		806	if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		807	srbm_reset \|= S_000E60_SOFT_RESET_MC(1);
		808	if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		809	srbm_reset \|= S_000E60_SOFT_RESET_MC(1);
		810	if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		811	srbm_reset \|= S_000E60_SOFT_RESET_MC(1);
		812	if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		813	srbm_reset \|= S_000E60_SOFT_RESET_MC(1);
		814	if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		815	srbm_reset \|= S_000E60_SOFT_RESET_MC(1);
		816	if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		817	srbm_reset \|= S_000E60_SOFT_RESET_RLC(1);
		818	if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		819	srbm_reset \|= S_000E60_SOFT_RESET_SEM(1);
		820	if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
		821	srbm_reset \|= S_000E60_SOFT_RESET_BIF(1);
		822	dev_info(rdev->dev, " R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
		823	WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
		824	(void)RREG32(R_000E60_SRBM_SOFT_RESET);
		825	udelay(50);
		826	WREG32(R_000E60_SRBM_SOFT_RESET, 0);
		827	(void)RREG32(R_000E60_SRBM_SOFT_RESET);
		828	WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
		829	(void)RREG32(R_000E60_SRBM_SOFT_RESET);
		830	udelay(50);
		831	WREG32(R_000E60_SRBM_SOFT_RESET, 0);
		832	(void)RREG32(R_000E60_SRBM_SOFT_RESET);
		833	/* Wait a little for things to settle down */
		834	udelay(50);
		835	dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
		836	RREG32(R_008010_GRBM_STATUS));
		837	dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
		838	RREG32(R_008014_GRBM_STATUS2));
		839	dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
		840	RREG32(R_000E50_SRBM_STATUS));
		841	/* After reset we need to reinit the asic as GPU often endup in an
		842	* incoherent state.
		843	*/
		844	atom_asic_init(rdev->mode_info.atom_context);
		845	rv515_mc_resume(rdev, &save);
		846	return 0;
1128	serge	847	}
		848
1221	serge	849	int r600_gpu_reset(struct radeon_device *rdev)
		850	{
		851	return r600_gpu_soft_reset(rdev);
		852	}
		853
		854	static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
		855	u32 num_backends,
		856	u32 backend_disable_mask)
		857	{
		858	u32 backend_map = 0;
		859	u32 enabled_backends_mask;
		860	u32 enabled_backends_count;
		861	u32 cur_pipe;
		862	u32 swizzle_pipe[R6XX_MAX_PIPES];
		863	u32 cur_backend;
		864	u32 i;
		865
		866	if (num_tile_pipes > R6XX_MAX_PIPES)
		867	num_tile_pipes = R6XX_MAX_PIPES;
		868	if (num_tile_pipes < 1)
		869	num_tile_pipes = 1;
		870	if (num_backends > R6XX_MAX_BACKENDS)
		871	num_backends = R6XX_MAX_BACKENDS;
		872	if (num_backends < 1)
		873	num_backends = 1;
		874
		875	enabled_backends_mask = 0;
		876	enabled_backends_count = 0;
		877	for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
		878	if (((backend_disable_mask >> i) & 1) == 0) {
		879	enabled_backends_mask \|= (1 << i);
		880	++enabled_backends_count;
		881	}
		882	if (enabled_backends_count == num_backends)
		883	break;
		884	}
		885
		886	if (enabled_backends_count == 0) {
		887	enabled_backends_mask = 1;
		888	enabled_backends_count = 1;
		889	}
		890
		891	if (enabled_backends_count != num_backends)
		892	num_backends = enabled_backends_count;
		893
		894	memset((uint8_t )&swizzle_pipe[0], 0, sizeof(u32) R6XX_MAX_PIPES);
		895	switch (num_tile_pipes) {
		896	case 1:
		897	swizzle_pipe[0] = 0;
		898	break;
		899	case 2:
		900	swizzle_pipe[0] = 0;
		901	swizzle_pipe[1] = 1;
		902	break;
		903	case 3:
		904	swizzle_pipe[0] = 0;
		905	swizzle_pipe[1] = 1;
		906	swizzle_pipe[2] = 2;
		907	break;
		908	case 4:
		909	swizzle_pipe[0] = 0;
		910	swizzle_pipe[1] = 1;
		911	swizzle_pipe[2] = 2;
		912	swizzle_pipe[3] = 3;
		913	break;
		914	case 5:
		915	swizzle_pipe[0] = 0;
		916	swizzle_pipe[1] = 1;
		917	swizzle_pipe[2] = 2;
		918	swizzle_pipe[3] = 3;
		919	swizzle_pipe[4] = 4;
		920	break;
		921	case 6:
		922	swizzle_pipe[0] = 0;
		923	swizzle_pipe[1] = 2;
		924	swizzle_pipe[2] = 4;
		925	swizzle_pipe[3] = 5;
		926	swizzle_pipe[4] = 1;
		927	swizzle_pipe[5] = 3;
		928	break;
		929	case 7:
		930	swizzle_pipe[0] = 0;
		931	swizzle_pipe[1] = 2;
		932	swizzle_pipe[2] = 4;
		933	swizzle_pipe[3] = 6;
		934	swizzle_pipe[4] = 1;
		935	swizzle_pipe[5] = 3;
		936	swizzle_pipe[6] = 5;
		937	break;
		938	case 8:
		939	swizzle_pipe[0] = 0;
		940	swizzle_pipe[1] = 2;
		941	swizzle_pipe[2] = 4;
		942	swizzle_pipe[3] = 6;
		943	swizzle_pipe[4] = 1;
		944	swizzle_pipe[5] = 3;
		945	swizzle_pipe[6] = 5;
		946	swizzle_pipe[7] = 7;
		947	break;
		948	}
		949
		950	cur_backend = 0;
		951	for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
		952	while (((1 << cur_backend) & enabled_backends_mask) == 0)
		953	cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
		954
		955	backend_map \|= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
		956
		957	cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
		958	}
		959
		960	return backend_map;
		961	}
		962
		963	int r600_count_pipe_bits(uint32_t val)
		964	{
		965	int i, ret = 0;
		966
		967	for (i = 0; i < 32; i++) {
		968	ret += val & 1;
		969	val >>= 1;
		970	}
		971	return ret;
		972	}
		973
		974	void r600_gpu_init(struct radeon_device *rdev)
		975	{
		976	u32 tiling_config;
		977	u32 ramcfg;
		978	u32 tmp;
		979	int i, j;
		980	u32 sq_config;
		981	u32 sq_gpr_resource_mgmt_1 = 0;
		982	u32 sq_gpr_resource_mgmt_2 = 0;
		983	u32 sq_thread_resource_mgmt = 0;
		984	u32 sq_stack_resource_mgmt_1 = 0;
		985	u32 sq_stack_resource_mgmt_2 = 0;
		986
		987	/* FIXME: implement */
		988	switch (rdev->family) {
		989	case CHIP_R600:
		990	rdev->config.r600.max_pipes = 4;
		991	rdev->config.r600.max_tile_pipes = 8;
		992	rdev->config.r600.max_simds = 4;
		993	rdev->config.r600.max_backends = 4;
		994	rdev->config.r600.max_gprs = 256;
		995	rdev->config.r600.max_threads = 192;
		996	rdev->config.r600.max_stack_entries = 256;
		997	rdev->config.r600.max_hw_contexts = 8;
		998	rdev->config.r600.max_gs_threads = 16;
		999	rdev->config.r600.sx_max_export_size = 128;
		1000	rdev->config.r600.sx_max_export_pos_size = 16;
		1001	rdev->config.r600.sx_max_export_smx_size = 128;
		1002	rdev->config.r600.sq_num_cf_insts = 2;
		1003	break;
		1004	case CHIP_RV630:
		1005	case CHIP_RV635:
		1006	rdev->config.r600.max_pipes = 2;
		1007	rdev->config.r600.max_tile_pipes = 2;
		1008	rdev->config.r600.max_simds = 3;
		1009	rdev->config.r600.max_backends = 1;
		1010	rdev->config.r600.max_gprs = 128;
		1011	rdev->config.r600.max_threads = 192;
		1012	rdev->config.r600.max_stack_entries = 128;
		1013	rdev->config.r600.max_hw_contexts = 8;
		1014	rdev->config.r600.max_gs_threads = 4;
		1015	rdev->config.r600.sx_max_export_size = 128;
		1016	rdev->config.r600.sx_max_export_pos_size = 16;
		1017	rdev->config.r600.sx_max_export_smx_size = 128;
		1018	rdev->config.r600.sq_num_cf_insts = 2;
		1019	break;
		1020	case CHIP_RV610:
		1021	case CHIP_RV620:
		1022	case CHIP_RS780:
		1023	case CHIP_RS880:
		1024	rdev->config.r600.max_pipes = 1;
		1025	rdev->config.r600.max_tile_pipes = 1;
		1026	rdev->config.r600.max_simds = 2;
		1027	rdev->config.r600.max_backends = 1;
		1028	rdev->config.r600.max_gprs = 128;
		1029	rdev->config.r600.max_threads = 192;
		1030	rdev->config.r600.max_stack_entries = 128;
		1031	rdev->config.r600.max_hw_contexts = 4;
		1032	rdev->config.r600.max_gs_threads = 4;
		1033	rdev->config.r600.sx_max_export_size = 128;
		1034	rdev->config.r600.sx_max_export_pos_size = 16;
		1035	rdev->config.r600.sx_max_export_smx_size = 128;
		1036	rdev->config.r600.sq_num_cf_insts = 1;
		1037	break;
		1038	case CHIP_RV670:
		1039	rdev->config.r600.max_pipes = 4;
		1040	rdev->config.r600.max_tile_pipes = 4;
		1041	rdev->config.r600.max_simds = 4;
		1042	rdev->config.r600.max_backends = 4;
		1043	rdev->config.r600.max_gprs = 192;
		1044	rdev->config.r600.max_threads = 192;
		1045	rdev->config.r600.max_stack_entries = 256;
		1046	rdev->config.r600.max_hw_contexts = 8;
		1047	rdev->config.r600.max_gs_threads = 16;
		1048	rdev->config.r600.sx_max_export_size = 128;
		1049	rdev->config.r600.sx_max_export_pos_size = 16;
		1050	rdev->config.r600.sx_max_export_smx_size = 128;
		1051	rdev->config.r600.sq_num_cf_insts = 2;
		1052	break;
		1053	default:
		1054	break;
		1055	}
		1056
		1057	/* Initialize HDP */
		1058	for (i = 0, j = 0; i < 32; i++, j += 0x18) {
		1059	WREG32((0x2c14 + j), 0x00000000);
		1060	WREG32((0x2c18 + j), 0x00000000);
		1061	WREG32((0x2c1c + j), 0x00000000);
		1062	WREG32((0x2c20 + j), 0x00000000);
		1063	WREG32((0x2c24 + j), 0x00000000);
		1064	}
		1065
		1066	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
		1067
		1068	/* Setup tiling */
		1069	tiling_config = 0;
		1070	ramcfg = RREG32(RAMCFG);
		1071	switch (rdev->config.r600.max_tile_pipes) {
		1072	case 1:
		1073	tiling_config \|= PIPE_TILING(0);
		1074	break;
		1075	case 2:
		1076	tiling_config \|= PIPE_TILING(1);
		1077	break;
		1078	case 4:
		1079	tiling_config \|= PIPE_TILING(2);
		1080	break;
		1081	case 8:
		1082	tiling_config \|= PIPE_TILING(3);
		1083	break;
		1084	default:
		1085	break;
		1086	}
		1087	tiling_config \|= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
		1088	tiling_config \|= GROUP_SIZE(0);
		1089	tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
		1090	if (tmp > 3) {
		1091	tiling_config \|= ROW_TILING(3);
		1092	tiling_config \|= SAMPLE_SPLIT(3);
		1093	} else {
		1094	tiling_config \|= ROW_TILING(tmp);
		1095	tiling_config \|= SAMPLE_SPLIT(tmp);
		1096	}
		1097	tiling_config \|= BANK_SWAPS(1);
		1098	tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
		1099	rdev->config.r600.max_backends,
		1100	(0xff << rdev->config.r600.max_backends) & 0xff);
		1101	tiling_config \|= BACKEND_MAP(tmp);
		1102	WREG32(GB_TILING_CONFIG, tiling_config);
		1103	WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
		1104	WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
		1105
		1106	tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
		1107	WREG32(CC_RB_BACKEND_DISABLE, tmp);
		1108
		1109	/* Setup pipes */
		1110	tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
		1111	tmp \|= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
		1112	WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
		1113	WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
		1114
		1115	tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
		1116	WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
		1117	WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
		1118
		1119	/* Setup some CP states */
		1120	WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) \| ROQ_IB2_START(0x2b)));
		1121	WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) \| ROQ_END(0x40)));
		1122
		1123	WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO \| SYNC_GRADIENT \|
		1124	SYNC_WALKER \| SYNC_ALIGNER));
		1125	/* Setup various GPU states */
		1126	if (rdev->family == CHIP_RV670)
		1127	WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
		1128
		1129	tmp = RREG32(SX_DEBUG_1);
		1130	tmp \|= SMX_EVENT_RELEASE;
		1131	if ((rdev->family > CHIP_R600))
		1132	tmp \|= ENABLE_NEW_SMX_ADDRESS;
		1133	WREG32(SX_DEBUG_1, tmp);
		1134
		1135	if (((rdev->family) == CHIP_R600) \|\|
		1136	((rdev->family) == CHIP_RV630) \|\|
		1137	((rdev->family) == CHIP_RV610) \|\|
		1138	((rdev->family) == CHIP_RV620) \|\|
1268	serge	1139	((rdev->family) == CHIP_RS780) \|\|
		1140	((rdev->family) == CHIP_RS880)) {
1221	serge	1141	WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
		1142	} else {
		1143	WREG32(DB_DEBUG, 0);
		1144	}
		1145	WREG32(DB_WATERMARKS, (DEPTH_FREE(4) \| DEPTH_CACHELINE_FREE(16) \|
		1146	DEPTH_FLUSH(16) \| DEPTH_PENDING_FREE(4)));
		1147
		1148	WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
		1149	WREG32(VGT_NUM_INSTANCES, 0);
		1150
		1151	WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
		1152	WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
		1153
		1154	tmp = RREG32(SQ_MS_FIFO_SIZES);
		1155	if (((rdev->family) == CHIP_RV610) \|\|
		1156	((rdev->family) == CHIP_RV620) \|\|
1268	serge	1157	((rdev->family) == CHIP_RS780) \|\|
		1158	((rdev->family) == CHIP_RS880)) {
1221	serge	1159	tmp = (CACHE_FIFO_SIZE(0xa) \|
		1160	FETCH_FIFO_HIWATER(0xa) \|
		1161	DONE_FIFO_HIWATER(0xe0) \|
		1162	ALU_UPDATE_FIFO_HIWATER(0x8));
		1163	} else if (((rdev->family) == CHIP_R600) \|\|
		1164	((rdev->family) == CHIP_RV630)) {
		1165	tmp &= ~DONE_FIFO_HIWATER(0xff);
		1166	tmp \|= DONE_FIFO_HIWATER(0x4);
		1167	}
		1168	WREG32(SQ_MS_FIFO_SIZES, tmp);
		1169
		1170	/* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
		1171	* should be adjusted as needed by the 2D/3D drivers. This just sets default values
		1172	*/
		1173	sq_config = RREG32(SQ_CONFIG);
		1174	sq_config &= ~(PS_PRIO(3) \|
		1175	VS_PRIO(3) \|
		1176	GS_PRIO(3) \|
		1177	ES_PRIO(3));
		1178	sq_config \|= (DX9_CONSTS \|
		1179	VC_ENABLE \|
		1180	PS_PRIO(0) \|
		1181	VS_PRIO(1) \|
		1182	GS_PRIO(2) \|
		1183	ES_PRIO(3));
		1184
		1185	if ((rdev->family) == CHIP_R600) {
		1186	sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) \|
		1187	NUM_VS_GPRS(124) \|
		1188	NUM_CLAUSE_TEMP_GPRS(4));
		1189	sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) \|
		1190	NUM_ES_GPRS(0));
		1191	sq_thread_resource_mgmt = (NUM_PS_THREADS(136) \|
		1192	NUM_VS_THREADS(48) \|
		1193	NUM_GS_THREADS(4) \|
		1194	NUM_ES_THREADS(4));
		1195	sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) \|
		1196	NUM_VS_STACK_ENTRIES(128));
		1197	sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) \|
		1198	NUM_ES_STACK_ENTRIES(0));
		1199	} else if (((rdev->family) == CHIP_RV610) \|\|
		1200	((rdev->family) == CHIP_RV620) \|\|
1268	serge	1201	((rdev->family) == CHIP_RS780) \|\|
		1202	((rdev->family) == CHIP_RS880)) {
1221	serge	1203	/* no vertex cache */
		1204	sq_config &= ~VC_ENABLE;
		1205
		1206	sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) \|
		1207	NUM_VS_GPRS(44) \|
		1208	NUM_CLAUSE_TEMP_GPRS(2));
		1209	sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) \|
		1210	NUM_ES_GPRS(17));
		1211	sq_thread_resource_mgmt = (NUM_PS_THREADS(79) \|
		1212	NUM_VS_THREADS(78) \|
		1213	NUM_GS_THREADS(4) \|
		1214	NUM_ES_THREADS(31));
		1215	sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) \|
		1216	NUM_VS_STACK_ENTRIES(40));
		1217	sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) \|
		1218	NUM_ES_STACK_ENTRIES(16));
		1219	} else if (((rdev->family) == CHIP_RV630) \|\|
		1220	((rdev->family) == CHIP_RV635)) {
		1221	sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) \|
		1222	NUM_VS_GPRS(44) \|
		1223	NUM_CLAUSE_TEMP_GPRS(2));
		1224	sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) \|
		1225	NUM_ES_GPRS(18));
		1226	sq_thread_resource_mgmt = (NUM_PS_THREADS(79) \|
		1227	NUM_VS_THREADS(78) \|
		1228	NUM_GS_THREADS(4) \|
		1229	NUM_ES_THREADS(31));
		1230	sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) \|
		1231	NUM_VS_STACK_ENTRIES(40));
		1232	sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) \|
		1233	NUM_ES_STACK_ENTRIES(16));
		1234	} else if ((rdev->family) == CHIP_RV670) {
		1235	sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) \|
		1236	NUM_VS_GPRS(44) \|
		1237	NUM_CLAUSE_TEMP_GPRS(2));
		1238	sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) \|
		1239	NUM_ES_GPRS(17));
		1240	sq_thread_resource_mgmt = (NUM_PS_THREADS(79) \|
		1241	NUM_VS_THREADS(78) \|
		1242	NUM_GS_THREADS(4) \|
		1243	NUM_ES_THREADS(31));
		1244	sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) \|
		1245	NUM_VS_STACK_ENTRIES(64));
		1246	sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) \|
		1247	NUM_ES_STACK_ENTRIES(64));
		1248	}
		1249
		1250	WREG32(SQ_CONFIG, sq_config);
		1251	WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
		1252	WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
		1253	WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
		1254	WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
		1255	WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
		1256
		1257	if (((rdev->family) == CHIP_RV610) \|\|
		1258	((rdev->family) == CHIP_RV620) \|\|
1268	serge	1259	((rdev->family) == CHIP_RS780) \|\|
		1260	((rdev->family) == CHIP_RS880)) {
1221	serge	1261	WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
		1262	} else {
		1263	WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
		1264	}
		1265
		1266	/* More default values. 2D/3D driver should adjust as needed */
		1267	WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) \| S0_Y(0x4) \|
		1268	S1_X(0x4) \| S1_Y(0xc)));
		1269	WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) \| S0_Y(0xe) \|
		1270	S1_X(0x2) \| S1_Y(0x2) \|
		1271	S2_X(0xa) \| S2_Y(0x6) \|
		1272	S3_X(0x6) \| S3_Y(0xa)));
		1273	WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) \| S0_Y(0xb) \|
		1274	S1_X(0x4) \| S1_Y(0xc) \|
		1275	S2_X(0x1) \| S2_Y(0x6) \|
		1276	S3_X(0xa) \| S3_Y(0xe)));
		1277	WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) \| S4_Y(0x1) \|
		1278	S5_X(0x0) \| S5_Y(0x0) \|
		1279	S6_X(0xb) \| S6_Y(0x4) \|
		1280	S7_X(0x7) \| S7_Y(0x8)));
		1281
		1282	WREG32(VGT_STRMOUT_EN, 0);
		1283	tmp = rdev->config.r600.max_pipes * 16;
		1284	switch (rdev->family) {
		1285	case CHIP_RV610:
1268	serge	1286	case CHIP_RV620:
1221	serge	1287	case CHIP_RS780:
1268	serge	1288	case CHIP_RS880:
1221	serge	1289	tmp += 32;
		1290	break;
		1291	case CHIP_RV670:
		1292	tmp += 128;
		1293	break;
		1294	default:
		1295	break;
		1296	}
		1297	if (tmp > 256) {
		1298	tmp = 256;
		1299	}
		1300	WREG32(VGT_ES_PER_GS, 128);
		1301	WREG32(VGT_GS_PER_ES, tmp);
		1302	WREG32(VGT_GS_PER_VS, 2);
		1303	WREG32(VGT_GS_VERTEX_REUSE, 16);
		1304
		1305	/* more default values. 2D/3D driver should adjust as needed */
		1306	WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
		1307	WREG32(VGT_STRMOUT_EN, 0);
		1308	WREG32(SX_MISC, 0);
		1309	WREG32(PA_SC_MODE_CNTL, 0);
		1310	WREG32(PA_SC_AA_CONFIG, 0);
		1311	WREG32(PA_SC_LINE_STIPPLE, 0);
		1312	WREG32(SPI_INPUT_Z, 0);
		1313	WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
		1314	WREG32(CB_COLOR7_FRAG, 0);
		1315
		1316	/* Clear render buffer base addresses */
		1317	WREG32(CB_COLOR0_BASE, 0);
		1318	WREG32(CB_COLOR1_BASE, 0);
		1319	WREG32(CB_COLOR2_BASE, 0);
		1320	WREG32(CB_COLOR3_BASE, 0);
		1321	WREG32(CB_COLOR4_BASE, 0);
		1322	WREG32(CB_COLOR5_BASE, 0);
		1323	WREG32(CB_COLOR6_BASE, 0);
		1324	WREG32(CB_COLOR7_BASE, 0);
		1325	WREG32(CB_COLOR7_FRAG, 0);
		1326
		1327	switch (rdev->family) {
		1328	case CHIP_RV610:
1268	serge	1329	case CHIP_RV620:
1221	serge	1330	case CHIP_RS780:
1268	serge	1331	case CHIP_RS880:
1221	serge	1332	tmp = TC_L2_SIZE(8);
		1333	break;
		1334	case CHIP_RV630:
		1335	case CHIP_RV635:
		1336	tmp = TC_L2_SIZE(4);
		1337	break;
		1338	case CHIP_R600:
		1339	tmp = TC_L2_SIZE(0) \| L2_DISABLE_LATE_HIT;
		1340	break;
		1341	default:
		1342	tmp = TC_L2_SIZE(0);
		1343	break;
		1344	}
		1345	WREG32(TC_CNTL, tmp);
		1346
		1347	tmp = RREG32(HDP_HOST_PATH_CNTL);
		1348	WREG32(HDP_HOST_PATH_CNTL, tmp);
		1349
		1350	tmp = RREG32(ARB_POP);
		1351	tmp \|= ENABLE_TC128;
		1352	WREG32(ARB_POP, tmp);
		1353
		1354	WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
		1355	WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA \|
		1356	NUM_CLIP_SEQ(3)));
		1357	WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
		1358	}
		1359
		1360
1128	serge	1361	/*
		1362	* Indirect registers accessor
		1363	*/
1221	serge	1364	u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1128	serge	1365	{
1221	serge	1366	u32 r;
1128	serge	1367
1221	serge	1368	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
		1369	(void)RREG32(PCIE_PORT_INDEX);
		1370	r = RREG32(PCIE_PORT_DATA);
1128	serge	1371	return r;
		1372	}
		1373
1221	serge	1374	void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1128	serge	1375	{
1221	serge	1376	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
		1377	(void)RREG32(PCIE_PORT_INDEX);
		1378	WREG32(PCIE_PORT_DATA, (v));
		1379	(void)RREG32(PCIE_PORT_DATA);
1128	serge	1380	}
1221	serge	1381
1321	serge	1382	void r600_hdp_flush(struct radeon_device *rdev)
		1383	{
		1384	WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
		1385	}
1221	serge	1386
		1387	/*
		1388	* CP & Ring
		1389	*/
		1390	void r600_cp_stop(struct radeon_device *rdev)
		1391	{
		1392	WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
		1393	}
		1394	int r600_cp_start(struct radeon_device *rdev)
		1395	{
		1396	int r;
		1397	uint32_t cp_me;
		1398
		1399	r = radeon_ring_lock(rdev, 7);
		1400	if (r) {
		1401	DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
		1402	return r;
		1403	}
		1404	radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
		1405	radeon_ring_write(rdev, 0x1);
		1406	if (rdev->family < CHIP_RV770) {
		1407	radeon_ring_write(rdev, 0x3);
		1408	radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
		1409	} else {
		1410	radeon_ring_write(rdev, 0x0);
		1411	radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
		1412	}
		1413	radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
		1414	radeon_ring_write(rdev, 0);
		1415	radeon_ring_write(rdev, 0);
		1416	radeon_ring_unlock_commit(rdev);
		1417
		1418	cp_me = 0xff;
		1419	WREG32(R_0086D8_CP_ME_CNTL, cp_me);
		1420	return 0;
		1421	}
		1422	void r600_cp_commit(struct radeon_device *rdev)
		1423	{
		1424	WREG32(CP_RB_WPTR, rdev->cp.wptr);
		1425	(void)RREG32(CP_RB_WPTR);
		1426	}
		1427
1233	serge	1428	void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
		1429	{
		1430	u32 rb_bufsz;
1221	serge	1431
1233	serge	1432	/* Align ring size */
		1433	rb_bufsz = drm_order(ring_size / 8);
		1434	ring_size = (1 << (rb_bufsz + 1)) * 4;
		1435	rdev->cp.ring_size = ring_size;
		1436	rdev->cp.align_mask = 16 - 1;
		1437	}
		1438
		1439
		1440	/*
		1441	* GPU scratch registers helpers function.
		1442	*/
		1443	void r600_scratch_init(struct radeon_device *rdev)
		1444	{
		1445	int i;
		1446
		1447	rdev->scratch.num_reg = 7;
		1448	for (i = 0; i < rdev->scratch.num_reg; i++) {
		1449	rdev->scratch.free[i] = true;
		1450	rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
		1451	}
		1452	}
1221	serge	1453	int r600_set_surface_reg(struct radeon_device *rdev, int reg,
		1454	uint32_t tiling_flags, uint32_t pitch,
		1455	uint32_t offset, uint32_t obj_size)
		1456	{
		1457	/* FIXME: implement */
		1458	return 0;
		1459	}
		1460
		1461	void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
		1462	{
		1463	/* FIXME: implement */
		1464	}
		1465
		1466
		1467	bool r600_card_posted(struct radeon_device *rdev)
		1468	{
		1469	uint32_t reg;
		1470
		1471	/* first check CRTCs */
		1472	reg = RREG32(D1CRTC_CONTROL) \|
		1473	RREG32(D2CRTC_CONTROL);
		1474	if (reg & CRTC_EN)
		1475	return true;
		1476
		1477	/* then check MEM_SIZE, in case the crtcs are off */
		1478	if (RREG32(CONFIG_MEMSIZE))
		1479	return true;
		1480
		1481	return false;
		1482	}
		1483
		1484	int r600_startup(struct radeon_device *rdev)
		1485	{
		1486	int r;
		1487
		1488	r600_mc_program(rdev);
		1489	if (rdev->flags & RADEON_IS_AGP) {
		1490	r600_agp_enable(rdev);
		1491	} else {
		1492	r = r600_pcie_gart_enable(rdev);
		1493	if (r)
		1494	return r;
		1495	}
		1496	r600_gpu_init(rdev);
		1497
1233	serge	1498	// r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
		1499	// &rdev->r600_blit.shader_gpu_addr);
		1500	// if (r) {
		1501	// DRM_ERROR("failed to pin blit object %d\n", r);
		1502	// return r;
		1503	// }
1221	serge	1504
1233	serge	1505	// r = radeon_ring_init(rdev, rdev->cp.ring_size);
		1506	// if (r)
		1507	// return r;
		1508	// r = r600_cp_load_microcode(rdev);
		1509	// if (r)
		1510	// return r;
		1511	// r = r600_cp_resume(rdev);
		1512	// if (r)
		1513	// return r;
1221	serge	1514	/* write back buffer are not vital so don't worry about failure */
1233	serge	1515	// r600_wb_enable(rdev);
1221	serge	1516	return 0;
		1517	}
		1518
		1519	void r600_vga_set_state(struct radeon_device *rdev, bool state)
		1520	{
		1521	uint32_t temp;
		1522
		1523	temp = RREG32(CONFIG_CNTL);
		1524	if (state == false) {
		1525	temp &= ~(1<<0);
		1526	temp \|= (1<<1);
		1527	} else {
		1528	temp &= ~(1<<1);
		1529	}
		1530	WREG32(CONFIG_CNTL, temp);
		1531	}
		1532
		1533
		1534
		1535
		1536
		1537	/* Plan is to move initialization in that function and use
		1538	* helper function so that radeon_device_init pretty much
		1539	* do nothing more than calling asic specific function. This
		1540	* should also allow to remove a bunch of callback function
		1541	* like vram_info.
		1542	*/
		1543	int r600_init(struct radeon_device *rdev)
		1544	{
		1545	int r;
		1546
		1547	r = radeon_dummy_page_init(rdev);
		1548	if (r)
		1549	return r;
		1550	if (r600_debugfs_mc_info_init(rdev)) {
		1551	DRM_ERROR("Failed to register debugfs file for mc !\n");
		1552	}
		1553	/* This don't do much */
		1554	r = radeon_gem_init(rdev);
		1555	if (r)
		1556	return r;
		1557	/* Read BIOS */
		1558	if (!radeon_get_bios(rdev)) {
		1559	if (ASIC_IS_AVIVO(rdev))
		1560	return -EINVAL;
		1561	}
		1562	/* Must be an ATOMBIOS */
		1563	if (!rdev->is_atom_bios) {
		1564	dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
		1565	return -EINVAL;
		1566	}
		1567	r = radeon_atombios_init(rdev);
		1568	if (r)
		1569	return r;
		1570	/* Post card if necessary */
1321	serge	1571	if (!r600_card_posted(rdev)) {
		1572	if (!rdev->bios) {
		1573	dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
		1574	return -EINVAL;
		1575	}
1221	serge	1576	DRM_INFO("GPU not posted. posting now...\n");
		1577	atom_asic_init(rdev->mode_info.atom_context);
		1578	}
		1579	/* Initialize scratch registers */
		1580	r600_scratch_init(rdev);
		1581	/* Initialize surface registers */
		1582	radeon_surface_init(rdev);
1268	serge	1583	/* Initialize clocks */
1221	serge	1584	radeon_get_clock_info(rdev->ddev);
		1585	r = radeon_clocks_init(rdev);
		1586	if (r)
		1587	return r;
1268	serge	1588	/* Initialize power management */
		1589	radeon_pm_init(rdev);
1221	serge	1590	/* Fence driver */
		1591	// r = radeon_fence_driver_init(rdev);
		1592	// if (r)
		1593	// return r;
		1594	r = r600_mc_init(rdev);
1246	serge	1595	dbgprintf("mc vram location %x\n", rdev->mc.vram_location);
1221	serge	1596	if (r)
		1597	return r;
		1598	/* Memory manager */
1321	serge	1599	r = radeon_bo_init(rdev);
1221	serge	1600	if (r)
		1601	return r;
1321	serge	1602
		1603	// r = radeon_irq_kms_init(rdev);
		1604	// if (r)
		1605	// return r;
		1606
1233	serge	1607	// rdev->cp.ring_obj = NULL;
		1608	// r600_ring_init(rdev, 1024 * 1024);
1221	serge	1609
1321	serge	1610	// rdev->ih.ring_obj = NULL;
		1611	// r600_ih_ring_init(rdev, 64 * 1024);
1221	serge	1612
		1613	r = r600_pcie_gart_init(rdev);
		1614	if (r)
		1615	return r;
		1616
1233	serge	1617	// r = r600_blit_init(rdev);
		1618	// if (r) {
		1619	// DRM_ERROR("radeon: failled blitter (%d).\n", r);
		1620	// return r;
		1621	// }
1221	serge	1622
1321	serge	1623	rdev->accel_working = true;
1221	serge	1624	r = r600_startup(rdev);
		1625	if (r) {
		1626	// r600_suspend(rdev);
		1627	// r600_wb_fini(rdev);
		1628	// radeon_ring_fini(rdev);
		1629	r600_pcie_gart_fini(rdev);
		1630	rdev->accel_working = false;
		1631	}
		1632	if (rdev->accel_working) {
		1633	// r = radeon_ib_pool_init(rdev);
		1634	// if (r) {
		1635	// DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
		1636	// rdev->accel_working = false;
		1637	// }
		1638	// r = r600_ib_test(rdev);
		1639	// if (r) {
		1640	// DRM_ERROR("radeon: failled testing IB (%d).\n", r);
		1641	// rdev->accel_working = false;
		1642	// }
		1643	}
		1644	return 0;
		1645	}
		1646
		1647
		1648
		1649
		1650
		1651
		1652
		1653
		1654
		1655	/*
		1656	* Debugfs info
		1657	*/
		1658	#if defined(CONFIG_DEBUG_FS)
		1659
		1660	static int r600_debugfs_cp_ring_info(struct seq_file m, void data)
		1661	{
		1662	struct drm_info_node node = (struct drm_info_node ) m->private;
		1663	struct drm_device *dev = node->minor->dev;
		1664	struct radeon_device *rdev = dev->dev_private;
		1665	unsigned count, i, j;
		1666
		1667	radeon_ring_free_size(rdev);
1321	serge	1668	count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
1221	serge	1669	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
1321	serge	1670	seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
		1671	seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
		1672	seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
		1673	seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
1221	serge	1674	seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
		1675	seq_printf(m, "%u dwords in ring\n", count);
1321	serge	1676	i = rdev->cp.rptr;
1221	serge	1677	for (j = 0; j <= count; j++) {
		1678	seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1321	serge	1679	i = (i + 1) & rdev->cp.ptr_mask;
1221	serge	1680	}
		1681	return 0;
		1682	}
		1683
		1684	static int r600_debugfs_mc_info(struct seq_file m, void data)
		1685	{
		1686	struct drm_info_node node = (struct drm_info_node ) m->private;
		1687	struct drm_device *dev = node->minor->dev;
		1688	struct radeon_device *rdev = dev->dev_private;
		1689
		1690	DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
		1691	DREG32_SYS(m, rdev, VM_L2_STATUS);
		1692	return 0;
		1693	}
		1694
		1695	static struct drm_info_list r600_mc_info_list[] = {
		1696	{"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
		1697	{"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
		1698	};
		1699	#endif
		1700
		1701	int r600_debugfs_mc_info_init(struct radeon_device *rdev)
		1702	{
		1703	#if defined(CONFIG_DEBUG_FS)
		1704	return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
		1705	#else
		1706	return 0;
		1707	#endif
		1708	}

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(root)/drivers/video/drm/radeon/r600.c – Rev 1321