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1128 serge 1
/*
2
 * Copyright 2008 Advanced Micro Devices, Inc.
3
 * Copyright 2008 Red Hat Inc.
4
 * Copyright 2009 Jerome Glisse.
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a
7
 * copy of this software and associated documentation files (the "Software"),
8
 * to deal in the Software without restriction, including without limitation
9
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10
 * and/or sell copies of the Software, and to permit persons to whom the
11
 * Software is furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22
 * OTHER DEALINGS IN THE SOFTWARE.
23
 *
24
 * Authors: Dave Airlie
25
 *          Alex Deucher
26
 *          Jerome Glisse
27
 */
1221 serge 28
#include 
29
#include 
1128 serge 30
#include "drmP.h"
1221 serge 31
#include "radeon_drm.h"
1128 serge 32
#include "radeon.h"
1221 serge 33
#include "radeon_mode.h"
34
#include "r600d.h"
35
#include "atom.h"
36
#include "avivod.h"
1128 serge 37
 
1221 serge 38
#define PFP_UCODE_SIZE 576
39
#define PM4_UCODE_SIZE 1792
40
#define R700_PFP_UCODE_SIZE 848
41
#define R700_PM4_UCODE_SIZE 1360
1128 serge 42
 
1221 serge 43
/* Firmware Names */
44
MODULE_FIRMWARE("radeon/R600_pfp.bin");
45
MODULE_FIRMWARE("radeon/R600_me.bin");
46
MODULE_FIRMWARE("radeon/RV610_pfp.bin");
47
MODULE_FIRMWARE("radeon/RV610_me.bin");
48
MODULE_FIRMWARE("radeon/RV630_pfp.bin");
49
MODULE_FIRMWARE("radeon/RV630_me.bin");
50
MODULE_FIRMWARE("radeon/RV620_pfp.bin");
51
MODULE_FIRMWARE("radeon/RV620_me.bin");
52
MODULE_FIRMWARE("radeon/RV635_pfp.bin");
53
MODULE_FIRMWARE("radeon/RV635_me.bin");
54
MODULE_FIRMWARE("radeon/RV670_pfp.bin");
55
MODULE_FIRMWARE("radeon/RV670_me.bin");
56
MODULE_FIRMWARE("radeon/RS780_pfp.bin");
57
MODULE_FIRMWARE("radeon/RS780_me.bin");
58
MODULE_FIRMWARE("radeon/RV770_pfp.bin");
59
MODULE_FIRMWARE("radeon/RV770_me.bin");
60
MODULE_FIRMWARE("radeon/RV730_pfp.bin");
61
MODULE_FIRMWARE("radeon/RV730_me.bin");
62
MODULE_FIRMWARE("radeon/RV710_pfp.bin");
63
MODULE_FIRMWARE("radeon/RV710_me.bin");
64
 
65
int r600_debugfs_mc_info_init(struct radeon_device *rdev);
66
 
67
/* r600,rv610,rv630,rv620,rv635,rv670 */
1128 serge 68
int r600_mc_wait_for_idle(struct radeon_device *rdev);
69
void r600_gpu_init(struct radeon_device *rdev);
1221 serge 70
void r600_fini(struct radeon_device *rdev);
1128 serge 71
 
72
/*
1221 serge 73
 * R600 PCIE GART
1128 serge 74
 */
1221 serge 75
int r600_gart_clear_page(struct radeon_device *rdev, int i)
1128 serge 76
{
1221 serge 77
	void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
78
	u64 pte;
1128 serge 79
 
1221 serge 80
	if (i < 0 || i > rdev->gart.num_gpu_pages)
81
		return -EINVAL;
82
	pte = 0;
83
	writeq(pte, ((void __iomem *)ptr) + (i * 8));
84
	return 0;
85
}
1128 serge 86
 
1221 serge 87
void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
88
{
89
	unsigned i;
90
	u32 tmp;
1128 serge 91
 
1221 serge 92
	WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
93
	WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
94
	WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
95
	for (i = 0; i < rdev->usec_timeout; i++) {
96
		/* read MC_STATUS */
97
		tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
98
		tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
99
		if (tmp == 2) {
100
			printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
101
			return;
102
		}
103
		if (tmp) {
104
			return;
105
		}
106
		udelay(1);
1128 serge 107
	}
1221 serge 108
}
1128 serge 109
 
1221 serge 110
int r600_pcie_gart_init(struct radeon_device *rdev)
111
{
112
	int r;
113
 
114
	if (rdev->gart.table.vram.robj) {
115
		WARN(1, "R600 PCIE GART already initialized.\n");
116
		return 0;
117
	}
118
	/* Initialize common gart structure */
119
	r = radeon_gart_init(rdev);
120
	if (r)
121
		return r;
122
	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
123
	return radeon_gart_table_vram_alloc(rdev);
124
}
125
 
126
int r600_pcie_gart_enable(struct radeon_device *rdev)
127
{
128
	u32 tmp;
129
	int r, i;
130
 
131
	if (rdev->gart.table.vram.robj == NULL) {
132
		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
133
		return -EINVAL;
134
	}
135
	r = radeon_gart_table_vram_pin(rdev);
136
	if (r)
137
		return r;
138
 
139
	/* Setup L2 cache */
140
	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
141
				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
142
				EFFECTIVE_L2_QUEUE_SIZE(7));
143
	WREG32(VM_L2_CNTL2, 0);
144
	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
145
	/* Setup TLB control */
146
	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
147
		SYSTEM_ACCESS_MODE_NOT_IN_SYS |
148
		EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
149
		ENABLE_WAIT_L2_QUERY;
150
	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
151
	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
152
	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
153
	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
154
	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
155
	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
156
	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
157
	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
158
	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
159
	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
160
	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
161
	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
162
	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
163
	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
164
	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
165
	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
166
	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
167
	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
168
				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
169
	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
170
			(u32)(rdev->dummy_page.addr >> 12));
171
	for (i = 1; i < 7; i++)
172
		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
173
 
174
	r600_pcie_gart_tlb_flush(rdev);
175
	rdev->gart.ready = true;
1128 serge 176
	return 0;
177
}
178
 
1221 serge 179
void r600_pcie_gart_disable(struct radeon_device *rdev)
1128 serge 180
{
1221 serge 181
	u32 tmp;
182
	int i;
183
 
184
	/* Disable all tables */
185
	for (i = 0; i < 7; i++)
186
		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
187
 
188
	/* Disable L2 cache */
189
	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
190
				EFFECTIVE_L2_QUEUE_SIZE(7));
191
	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
192
	/* Setup L1 TLB control */
193
	tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
194
		ENABLE_WAIT_L2_QUERY;
195
	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
196
	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
197
	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
198
	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
199
	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
200
	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
201
	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
202
	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
203
	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
204
	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
205
	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
206
	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
207
	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
208
	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
209
	if (rdev->gart.table.vram.robj) {
210
		radeon_object_kunmap(rdev->gart.table.vram.robj);
211
		radeon_object_unpin(rdev->gart.table.vram.robj);
212
	}
1128 serge 213
}
214
 
1221 serge 215
void r600_pcie_gart_fini(struct radeon_device *rdev)
216
{
217
	r600_pcie_gart_disable(rdev);
218
	radeon_gart_table_vram_free(rdev);
219
	radeon_gart_fini(rdev);
220
}
1128 serge 221
 
1221 serge 222
void r600_agp_enable(struct radeon_device *rdev)
1128 serge 223
{
1221 serge 224
	u32 tmp;
225
	int i;
226
 
227
	/* Setup L2 cache */
228
	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
229
				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
230
				EFFECTIVE_L2_QUEUE_SIZE(7));
231
	WREG32(VM_L2_CNTL2, 0);
232
	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
233
	/* Setup TLB control */
234
	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
235
		SYSTEM_ACCESS_MODE_NOT_IN_SYS |
236
		EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
237
		ENABLE_WAIT_L2_QUERY;
238
	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
239
	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
240
	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
241
	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
242
	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
243
	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
244
	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
245
	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
246
	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
247
	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
248
	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
249
	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
250
	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
251
	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
252
	for (i = 0; i < 7; i++)
253
		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1128 serge 254
}
255
 
256
int r600_mc_wait_for_idle(struct radeon_device *rdev)
257
{
1221 serge 258
	unsigned i;
259
	u32 tmp;
260
 
261
	for (i = 0; i < rdev->usec_timeout; i++) {
262
		/* read MC_STATUS */
263
		tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
264
		if (!tmp)
1128 serge 265
	return 0;
1221 serge 266
		udelay(1);
267
	}
268
	return -1;
1128 serge 269
}
270
 
1221 serge 271
static void r600_mc_program(struct radeon_device *rdev)
1128 serge 272
{
1221 serge 273
	struct rv515_mc_save save;
274
	u32 tmp;
275
	int i, j;
276
 
277
	/* Initialize HDP */
278
	for (i = 0, j = 0; i < 32; i++, j += 0x18) {
279
		WREG32((0x2c14 + j), 0x00000000);
280
		WREG32((0x2c18 + j), 0x00000000);
281
		WREG32((0x2c1c + j), 0x00000000);
282
		WREG32((0x2c20 + j), 0x00000000);
283
		WREG32((0x2c24 + j), 0x00000000);
284
	}
285
	WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
286
 
287
	rv515_mc_stop(rdev, &save);
288
	if (r600_mc_wait_for_idle(rdev)) {
289
		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
290
	}
291
	/* Lockout access through VGA aperture (doesn't exist before R600) */
292
	WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
293
	/* Update configuration */
294
	if (rdev->flags & RADEON_IS_AGP) {
295
		if (rdev->mc.vram_start < rdev->mc.gtt_start) {
296
			/* VRAM before AGP */
297
			WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
298
				rdev->mc.vram_start >> 12);
299
			WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
300
				rdev->mc.gtt_end >> 12);
301
		} else {
302
			/* VRAM after AGP */
303
			WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
304
				rdev->mc.gtt_start >> 12);
305
			WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
306
				rdev->mc.vram_end >> 12);
307
		}
308
	} else {
309
		WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
310
		WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
311
	}
312
	WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
313
	tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
314
	tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
315
	WREG32(MC_VM_FB_LOCATION, tmp);
316
	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
317
	WREG32(HDP_NONSURFACE_INFO, (2 << 7));
318
	WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
319
	if (rdev->flags & RADEON_IS_AGP) {
320
		WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
321
		WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
322
		WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
323
	} else {
324
		WREG32(MC_VM_AGP_BASE, 0);
325
		WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
326
		WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
327
	}
328
	if (r600_mc_wait_for_idle(rdev)) {
329
		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
330
	}
331
	rv515_mc_resume(rdev, &save);
332
	/* we need to own VRAM, so turn off the VGA renderer here
333
	 * to stop it overwriting our objects */
334
	rv515_vga_render_disable(rdev);
1128 serge 335
}
336
 
1221 serge 337
int r600_mc_init(struct radeon_device *rdev)
1128 serge 338
{
1221 serge 339
	fixed20_12 a;
340
	u32 tmp;
1128 serge 341
	int chansize;
1221 serge 342
	int r;
1128 serge 343
 
1221 serge 344
	/* Get VRAM informations */
1128 serge 345
	rdev->mc.vram_width = 128;
346
	rdev->mc.vram_is_ddr = true;
1221 serge 347
	tmp = RREG32(RAMCFG);
348
	if (tmp & CHANSIZE_OVERRIDE) {
1128 serge 349
		chansize = 16;
1221 serge 350
	} else if (tmp & CHANSIZE_MASK) {
1128 serge 351
		chansize = 64;
352
	} else {
353
		chansize = 32;
354
	}
355
	if (rdev->family == CHIP_R600) {
356
		rdev->mc.vram_width = 8 * chansize;
357
	} else if (rdev->family == CHIP_RV670) {
358
		rdev->mc.vram_width = 4 * chansize;
359
	} else if ((rdev->family == CHIP_RV610) ||
360
			(rdev->family == CHIP_RV620)) {
361
		rdev->mc.vram_width = chansize;
362
	} else if ((rdev->family == CHIP_RV630) ||
363
			(rdev->family == CHIP_RV635)) {
364
		rdev->mc.vram_width = 2 * chansize;
365
	}
1221 serge 366
	/* Could aper size report 0 ? */
367
	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
368
	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
369
	/* Setup GPU memory space */
370
	rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
371
	rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
372
 
373
	if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
374
		rdev->mc.mc_vram_size = rdev->mc.aper_size;
375
 
376
	if (rdev->mc.real_vram_size > rdev->mc.aper_size)
377
		rdev->mc.real_vram_size = rdev->mc.aper_size;
378
 
379
	if (rdev->flags & RADEON_IS_AGP) {
380
		r = radeon_agp_init(rdev);
381
		if (r)
382
			return r;
383
		/* gtt_size is setup by radeon_agp_init */
384
		rdev->mc.gtt_location = rdev->mc.agp_base;
385
		tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
386
		/* Try to put vram before or after AGP because we
387
		 * we want SYSTEM_APERTURE to cover both VRAM and
388
		 * AGP so that GPU can catch out of VRAM/AGP access
389
		 */
390
		if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
391
			/* Enought place before */
392
			rdev->mc.vram_location = rdev->mc.gtt_location -
393
							rdev->mc.mc_vram_size;
394
		} else if (tmp > rdev->mc.mc_vram_size) {
395
			/* Enought place after */
396
			rdev->mc.vram_location = rdev->mc.gtt_location +
397
							rdev->mc.gtt_size;
398
		} else {
399
			/* Try to setup VRAM then AGP might not
400
			 * not work on some card
401
			 */
402
			rdev->mc.vram_location = 0x00000000UL;
403
			rdev->mc.gtt_location = rdev->mc.mc_vram_size;
404
		}
405
	} else {
406
		if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
407
			rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
408
								0xFFFF) << 24;
409
			rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
410
			tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
411
			if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
412
				/* Enough place after vram */
413
				rdev->mc.gtt_location = tmp;
414
			} else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
415
				/* Enough place before vram */
416
				rdev->mc.gtt_location = 0;
417
			} else {
418
				/* Not enough place after or before shrink
419
				 * gart size
420
				 */
421
				if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
422
					rdev->mc.gtt_location = 0;
423
					rdev->mc.gtt_size = rdev->mc.vram_location;
424
				} else {
425
					rdev->mc.gtt_location = tmp;
426
					rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
427
				}
428
			}
429
			rdev->mc.gtt_location = rdev->mc.mc_vram_size;
430
		} else {
431
			rdev->mc.vram_location = 0x00000000UL;
432
			rdev->mc.gtt_location = rdev->mc.mc_vram_size;
433
			rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
434
		}
435
	}
436
	rdev->mc.vram_start = rdev->mc.vram_location;
437
	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
438
	rdev->mc.gtt_start = rdev->mc.gtt_location;
439
	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
440
	/* FIXME: we should enforce default clock in case GPU is not in
441
	 * default setup
442
	 */
443
	a.full = rfixed_const(100);
444
	rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
445
	rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
446
	return 0;
1128 serge 447
}
448
 
1221 serge 449
/* We doesn't check that the GPU really needs a reset we simply do the
450
 * reset, it's up to the caller to determine if the GPU needs one. We
451
 * might add an helper function to check that.
452
 */
453
int r600_gpu_soft_reset(struct radeon_device *rdev)
1128 serge 454
{
1221 serge 455
	struct rv515_mc_save save;
456
	u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
457
				S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
458
				S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
459
				S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
460
				S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
461
				S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
462
				S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
463
				S_008010_GUI_ACTIVE(1);
464
	u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
465
			S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
466
			S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
467
			S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
468
			S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
469
			S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
470
			S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
471
			S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
472
	u32 srbm_reset = 0;
473
	u32 tmp;
1128 serge 474
 
1221 serge 475
	dev_info(rdev->dev, "GPU softreset \n");
476
	dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
477
		RREG32(R_008010_GRBM_STATUS));
478
	dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
479
		RREG32(R_008014_GRBM_STATUS2));
480
	dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
481
		RREG32(R_000E50_SRBM_STATUS));
482
	rv515_mc_stop(rdev, &save);
483
	if (r600_mc_wait_for_idle(rdev)) {
484
		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
485
	}
486
	/* Disable CP parsing/prefetching */
487
	WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
488
	/* Check if any of the rendering block is busy and reset it */
489
	if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
490
	    (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
491
		tmp = S_008020_SOFT_RESET_CR(1) |
492
			S_008020_SOFT_RESET_DB(1) |
493
			S_008020_SOFT_RESET_CB(1) |
494
			S_008020_SOFT_RESET_PA(1) |
495
			S_008020_SOFT_RESET_SC(1) |
496
			S_008020_SOFT_RESET_SMX(1) |
497
			S_008020_SOFT_RESET_SPI(1) |
498
			S_008020_SOFT_RESET_SX(1) |
499
			S_008020_SOFT_RESET_SH(1) |
500
			S_008020_SOFT_RESET_TC(1) |
501
			S_008020_SOFT_RESET_TA(1) |
502
			S_008020_SOFT_RESET_VC(1) |
503
			S_008020_SOFT_RESET_VGT(1);
504
		dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
505
		WREG32(R_008020_GRBM_SOFT_RESET, tmp);
506
		(void)RREG32(R_008020_GRBM_SOFT_RESET);
507
		udelay(50);
508
		WREG32(R_008020_GRBM_SOFT_RESET, 0);
509
		(void)RREG32(R_008020_GRBM_SOFT_RESET);
510
	}
511
	/* Reset CP (we always reset CP) */
512
	tmp = S_008020_SOFT_RESET_CP(1);
513
	dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
514
	WREG32(R_008020_GRBM_SOFT_RESET, tmp);
515
	(void)RREG32(R_008020_GRBM_SOFT_RESET);
516
	udelay(50);
517
	WREG32(R_008020_GRBM_SOFT_RESET, 0);
518
	(void)RREG32(R_008020_GRBM_SOFT_RESET);
519
	/* Reset others GPU block if necessary */
520
	if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
521
		srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
522
	if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
523
		srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
524
	if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
525
		srbm_reset |= S_000E60_SOFT_RESET_IH(1);
526
	if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
527
		srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
528
	if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
529
		srbm_reset |= S_000E60_SOFT_RESET_MC(1);
530
	if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
531
		srbm_reset |= S_000E60_SOFT_RESET_MC(1);
532
	if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
533
		srbm_reset |= S_000E60_SOFT_RESET_MC(1);
534
	if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
535
		srbm_reset |= S_000E60_SOFT_RESET_MC(1);
536
	if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
537
		srbm_reset |= S_000E60_SOFT_RESET_MC(1);
538
	if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
539
		srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
540
	if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
541
		srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
542
	if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
543
		srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
544
	dev_info(rdev->dev, "  R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
545
	WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
546
	(void)RREG32(R_000E60_SRBM_SOFT_RESET);
547
	udelay(50);
548
	WREG32(R_000E60_SRBM_SOFT_RESET, 0);
549
	(void)RREG32(R_000E60_SRBM_SOFT_RESET);
550
	WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
551
	(void)RREG32(R_000E60_SRBM_SOFT_RESET);
552
	udelay(50);
553
	WREG32(R_000E60_SRBM_SOFT_RESET, 0);
554
	(void)RREG32(R_000E60_SRBM_SOFT_RESET);
555
	/* Wait a little for things to settle down */
556
	udelay(50);
557
	dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
558
		RREG32(R_008010_GRBM_STATUS));
559
	dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
560
		RREG32(R_008014_GRBM_STATUS2));
561
	dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
562
		RREG32(R_000E50_SRBM_STATUS));
563
	/* After reset we need to reinit the asic as GPU often endup in an
564
	 * incoherent state.
565
	 */
566
	atom_asic_init(rdev->mode_info.atom_context);
567
	rv515_mc_resume(rdev, &save);
568
	return 0;
1128 serge 569
}
570
 
1221 serge 571
int r600_gpu_reset(struct radeon_device *rdev)
572
{
573
	return r600_gpu_soft_reset(rdev);
574
}
575
 
576
static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
577
					     u32 num_backends,
578
					     u32 backend_disable_mask)
579
{
580
	u32 backend_map = 0;
581
	u32 enabled_backends_mask;
582
	u32 enabled_backends_count;
583
	u32 cur_pipe;
584
	u32 swizzle_pipe[R6XX_MAX_PIPES];
585
	u32 cur_backend;
586
	u32 i;
587
 
588
	if (num_tile_pipes > R6XX_MAX_PIPES)
589
		num_tile_pipes = R6XX_MAX_PIPES;
590
	if (num_tile_pipes < 1)
591
		num_tile_pipes = 1;
592
	if (num_backends > R6XX_MAX_BACKENDS)
593
		num_backends = R6XX_MAX_BACKENDS;
594
	if (num_backends < 1)
595
		num_backends = 1;
596
 
597
	enabled_backends_mask = 0;
598
	enabled_backends_count = 0;
599
	for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
600
		if (((backend_disable_mask >> i) & 1) == 0) {
601
			enabled_backends_mask |= (1 << i);
602
			++enabled_backends_count;
603
		}
604
		if (enabled_backends_count == num_backends)
605
			break;
606
	}
607
 
608
	if (enabled_backends_count == 0) {
609
		enabled_backends_mask = 1;
610
		enabled_backends_count = 1;
611
	}
612
 
613
	if (enabled_backends_count != num_backends)
614
		num_backends = enabled_backends_count;
615
 
616
	memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
617
	switch (num_tile_pipes) {
618
	case 1:
619
		swizzle_pipe[0] = 0;
620
		break;
621
	case 2:
622
		swizzle_pipe[0] = 0;
623
		swizzle_pipe[1] = 1;
624
		break;
625
	case 3:
626
		swizzle_pipe[0] = 0;
627
		swizzle_pipe[1] = 1;
628
		swizzle_pipe[2] = 2;
629
		break;
630
	case 4:
631
		swizzle_pipe[0] = 0;
632
		swizzle_pipe[1] = 1;
633
		swizzle_pipe[2] = 2;
634
		swizzle_pipe[3] = 3;
635
		break;
636
	case 5:
637
		swizzle_pipe[0] = 0;
638
		swizzle_pipe[1] = 1;
639
		swizzle_pipe[2] = 2;
640
		swizzle_pipe[3] = 3;
641
		swizzle_pipe[4] = 4;
642
		break;
643
	case 6:
644
		swizzle_pipe[0] = 0;
645
		swizzle_pipe[1] = 2;
646
		swizzle_pipe[2] = 4;
647
		swizzle_pipe[3] = 5;
648
		swizzle_pipe[4] = 1;
649
		swizzle_pipe[5] = 3;
650
		break;
651
	case 7:
652
		swizzle_pipe[0] = 0;
653
		swizzle_pipe[1] = 2;
654
		swizzle_pipe[2] = 4;
655
		swizzle_pipe[3] = 6;
656
		swizzle_pipe[4] = 1;
657
		swizzle_pipe[5] = 3;
658
		swizzle_pipe[6] = 5;
659
		break;
660
	case 8:
661
		swizzle_pipe[0] = 0;
662
		swizzle_pipe[1] = 2;
663
		swizzle_pipe[2] = 4;
664
		swizzle_pipe[3] = 6;
665
		swizzle_pipe[4] = 1;
666
		swizzle_pipe[5] = 3;
667
		swizzle_pipe[6] = 5;
668
		swizzle_pipe[7] = 7;
669
		break;
670
	}
671
 
672
	cur_backend = 0;
673
	for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
674
		while (((1 << cur_backend) & enabled_backends_mask) == 0)
675
			cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
676
 
677
		backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
678
 
679
		cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
680
	}
681
 
682
	return backend_map;
683
}
684
 
685
int r600_count_pipe_bits(uint32_t val)
686
{
687
	int i, ret = 0;
688
 
689
	for (i = 0; i < 32; i++) {
690
		ret += val & 1;
691
		val >>= 1;
692
	}
693
	return ret;
694
}
695
 
696
void r600_gpu_init(struct radeon_device *rdev)
697
{
698
	u32 tiling_config;
699
	u32 ramcfg;
700
	u32 tmp;
701
	int i, j;
702
	u32 sq_config;
703
	u32 sq_gpr_resource_mgmt_1 = 0;
704
	u32 sq_gpr_resource_mgmt_2 = 0;
705
	u32 sq_thread_resource_mgmt = 0;
706
	u32 sq_stack_resource_mgmt_1 = 0;
707
	u32 sq_stack_resource_mgmt_2 = 0;
708
 
709
	/* FIXME: implement */
710
	switch (rdev->family) {
711
	case CHIP_R600:
712
		rdev->config.r600.max_pipes = 4;
713
		rdev->config.r600.max_tile_pipes = 8;
714
		rdev->config.r600.max_simds = 4;
715
		rdev->config.r600.max_backends = 4;
716
		rdev->config.r600.max_gprs = 256;
717
		rdev->config.r600.max_threads = 192;
718
		rdev->config.r600.max_stack_entries = 256;
719
		rdev->config.r600.max_hw_contexts = 8;
720
		rdev->config.r600.max_gs_threads = 16;
721
		rdev->config.r600.sx_max_export_size = 128;
722
		rdev->config.r600.sx_max_export_pos_size = 16;
723
		rdev->config.r600.sx_max_export_smx_size = 128;
724
		rdev->config.r600.sq_num_cf_insts = 2;
725
		break;
726
	case CHIP_RV630:
727
	case CHIP_RV635:
728
		rdev->config.r600.max_pipes = 2;
729
		rdev->config.r600.max_tile_pipes = 2;
730
		rdev->config.r600.max_simds = 3;
731
		rdev->config.r600.max_backends = 1;
732
		rdev->config.r600.max_gprs = 128;
733
		rdev->config.r600.max_threads = 192;
734
		rdev->config.r600.max_stack_entries = 128;
735
		rdev->config.r600.max_hw_contexts = 8;
736
		rdev->config.r600.max_gs_threads = 4;
737
		rdev->config.r600.sx_max_export_size = 128;
738
		rdev->config.r600.sx_max_export_pos_size = 16;
739
		rdev->config.r600.sx_max_export_smx_size = 128;
740
		rdev->config.r600.sq_num_cf_insts = 2;
741
		break;
742
	case CHIP_RV610:
743
	case CHIP_RV620:
744
	case CHIP_RS780:
745
	case CHIP_RS880:
746
		rdev->config.r600.max_pipes = 1;
747
		rdev->config.r600.max_tile_pipes = 1;
748
		rdev->config.r600.max_simds = 2;
749
		rdev->config.r600.max_backends = 1;
750
		rdev->config.r600.max_gprs = 128;
751
		rdev->config.r600.max_threads = 192;
752
		rdev->config.r600.max_stack_entries = 128;
753
		rdev->config.r600.max_hw_contexts = 4;
754
		rdev->config.r600.max_gs_threads = 4;
755
		rdev->config.r600.sx_max_export_size = 128;
756
		rdev->config.r600.sx_max_export_pos_size = 16;
757
		rdev->config.r600.sx_max_export_smx_size = 128;
758
		rdev->config.r600.sq_num_cf_insts = 1;
759
		break;
760
	case CHIP_RV670:
761
		rdev->config.r600.max_pipes = 4;
762
		rdev->config.r600.max_tile_pipes = 4;
763
		rdev->config.r600.max_simds = 4;
764
		rdev->config.r600.max_backends = 4;
765
		rdev->config.r600.max_gprs = 192;
766
		rdev->config.r600.max_threads = 192;
767
		rdev->config.r600.max_stack_entries = 256;
768
		rdev->config.r600.max_hw_contexts = 8;
769
		rdev->config.r600.max_gs_threads = 16;
770
		rdev->config.r600.sx_max_export_size = 128;
771
		rdev->config.r600.sx_max_export_pos_size = 16;
772
		rdev->config.r600.sx_max_export_smx_size = 128;
773
		rdev->config.r600.sq_num_cf_insts = 2;
774
		break;
775
	default:
776
		break;
777
	}
778
 
779
	/* Initialize HDP */
780
	for (i = 0, j = 0; i < 32; i++, j += 0x18) {
781
		WREG32((0x2c14 + j), 0x00000000);
782
		WREG32((0x2c18 + j), 0x00000000);
783
		WREG32((0x2c1c + j), 0x00000000);
784
		WREG32((0x2c20 + j), 0x00000000);
785
		WREG32((0x2c24 + j), 0x00000000);
786
	}
787
 
788
	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
789
 
790
	/* Setup tiling */
791
	tiling_config = 0;
792
	ramcfg = RREG32(RAMCFG);
793
	switch (rdev->config.r600.max_tile_pipes) {
794
	case 1:
795
		tiling_config |= PIPE_TILING(0);
796
		break;
797
	case 2:
798
		tiling_config |= PIPE_TILING(1);
799
		break;
800
	case 4:
801
		tiling_config |= PIPE_TILING(2);
802
		break;
803
	case 8:
804
		tiling_config |= PIPE_TILING(3);
805
		break;
806
	default:
807
		break;
808
	}
809
	tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
810
	tiling_config |= GROUP_SIZE(0);
811
	tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
812
	if (tmp > 3) {
813
		tiling_config |= ROW_TILING(3);
814
		tiling_config |= SAMPLE_SPLIT(3);
815
	} else {
816
		tiling_config |= ROW_TILING(tmp);
817
		tiling_config |= SAMPLE_SPLIT(tmp);
818
	}
819
	tiling_config |= BANK_SWAPS(1);
820
	tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
821
						rdev->config.r600.max_backends,
822
						(0xff << rdev->config.r600.max_backends) & 0xff);
823
	tiling_config |= BACKEND_MAP(tmp);
824
	WREG32(GB_TILING_CONFIG, tiling_config);
825
	WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
826
	WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
827
 
828
	tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
829
	WREG32(CC_RB_BACKEND_DISABLE, tmp);
830
 
831
	/* Setup pipes */
832
	tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
833
	tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
834
	WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
835
	WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
836
 
837
	tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
838
	WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
839
	WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
840
 
841
	/* Setup some CP states */
842
	WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
843
	WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
844
 
845
	WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
846
			     SYNC_WALKER | SYNC_ALIGNER));
847
	/* Setup various GPU states */
848
	if (rdev->family == CHIP_RV670)
849
		WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
850
 
851
	tmp = RREG32(SX_DEBUG_1);
852
	tmp |= SMX_EVENT_RELEASE;
853
	if ((rdev->family > CHIP_R600))
854
		tmp |= ENABLE_NEW_SMX_ADDRESS;
855
	WREG32(SX_DEBUG_1, tmp);
856
 
857
	if (((rdev->family) == CHIP_R600) ||
858
	    ((rdev->family) == CHIP_RV630) ||
859
	    ((rdev->family) == CHIP_RV610) ||
860
	    ((rdev->family) == CHIP_RV620) ||
861
	    ((rdev->family) == CHIP_RS780)) {
862
		WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
863
	} else {
864
		WREG32(DB_DEBUG, 0);
865
	}
866
	WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
867
			       DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
868
 
869
	WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
870
	WREG32(VGT_NUM_INSTANCES, 0);
871
 
872
	WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
873
	WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
874
 
875
	tmp = RREG32(SQ_MS_FIFO_SIZES);
876
	if (((rdev->family) == CHIP_RV610) ||
877
	    ((rdev->family) == CHIP_RV620) ||
878
	    ((rdev->family) == CHIP_RS780)) {
879
		tmp = (CACHE_FIFO_SIZE(0xa) |
880
		       FETCH_FIFO_HIWATER(0xa) |
881
		       DONE_FIFO_HIWATER(0xe0) |
882
		       ALU_UPDATE_FIFO_HIWATER(0x8));
883
	} else if (((rdev->family) == CHIP_R600) ||
884
		   ((rdev->family) == CHIP_RV630)) {
885
		tmp &= ~DONE_FIFO_HIWATER(0xff);
886
		tmp |= DONE_FIFO_HIWATER(0x4);
887
	}
888
	WREG32(SQ_MS_FIFO_SIZES, tmp);
889
 
890
	/* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
891
	 * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
892
	 */
893
	sq_config = RREG32(SQ_CONFIG);
894
	sq_config &= ~(PS_PRIO(3) |
895
		       VS_PRIO(3) |
896
		       GS_PRIO(3) |
897
		       ES_PRIO(3));
898
	sq_config |= (DX9_CONSTS |
899
		      VC_ENABLE |
900
		      PS_PRIO(0) |
901
		      VS_PRIO(1) |
902
		      GS_PRIO(2) |
903
		      ES_PRIO(3));
904
 
905
	if ((rdev->family) == CHIP_R600) {
906
		sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
907
					  NUM_VS_GPRS(124) |
908
					  NUM_CLAUSE_TEMP_GPRS(4));
909
		sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
910
					  NUM_ES_GPRS(0));
911
		sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
912
					   NUM_VS_THREADS(48) |
913
					   NUM_GS_THREADS(4) |
914
					   NUM_ES_THREADS(4));
915
		sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
916
					    NUM_VS_STACK_ENTRIES(128));
917
		sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
918
					    NUM_ES_STACK_ENTRIES(0));
919
	} else if (((rdev->family) == CHIP_RV610) ||
920
		   ((rdev->family) == CHIP_RV620) ||
921
		   ((rdev->family) == CHIP_RS780)) {
922
		/* no vertex cache */
923
		sq_config &= ~VC_ENABLE;
924
 
925
		sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
926
					  NUM_VS_GPRS(44) |
927
					  NUM_CLAUSE_TEMP_GPRS(2));
928
		sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
929
					  NUM_ES_GPRS(17));
930
		sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
931
					   NUM_VS_THREADS(78) |
932
					   NUM_GS_THREADS(4) |
933
					   NUM_ES_THREADS(31));
934
		sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
935
					    NUM_VS_STACK_ENTRIES(40));
936
		sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
937
					    NUM_ES_STACK_ENTRIES(16));
938
	} else if (((rdev->family) == CHIP_RV630) ||
939
		   ((rdev->family) == CHIP_RV635)) {
940
		sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
941
					  NUM_VS_GPRS(44) |
942
					  NUM_CLAUSE_TEMP_GPRS(2));
943
		sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
944
					  NUM_ES_GPRS(18));
945
		sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
946
					   NUM_VS_THREADS(78) |
947
					   NUM_GS_THREADS(4) |
948
					   NUM_ES_THREADS(31));
949
		sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
950
					    NUM_VS_STACK_ENTRIES(40));
951
		sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
952
					    NUM_ES_STACK_ENTRIES(16));
953
	} else if ((rdev->family) == CHIP_RV670) {
954
		sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
955
					  NUM_VS_GPRS(44) |
956
					  NUM_CLAUSE_TEMP_GPRS(2));
957
		sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
958
					  NUM_ES_GPRS(17));
959
		sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
960
					   NUM_VS_THREADS(78) |
961
					   NUM_GS_THREADS(4) |
962
					   NUM_ES_THREADS(31));
963
		sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
964
					    NUM_VS_STACK_ENTRIES(64));
965
		sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
966
					    NUM_ES_STACK_ENTRIES(64));
967
	}
968
 
969
	WREG32(SQ_CONFIG, sq_config);
970
	WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
971
	WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
972
	WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
973
	WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
974
	WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
975
 
976
	if (((rdev->family) == CHIP_RV610) ||
977
	    ((rdev->family) == CHIP_RV620) ||
978
	    ((rdev->family) == CHIP_RS780)) {
979
		WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
980
	} else {
981
		WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
982
	}
983
 
984
	/* More default values. 2D/3D driver should adjust as needed */
985
	WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
986
					 S1_X(0x4) | S1_Y(0xc)));
987
	WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
988
					 S1_X(0x2) | S1_Y(0x2) |
989
					 S2_X(0xa) | S2_Y(0x6) |
990
					 S3_X(0x6) | S3_Y(0xa)));
991
	WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
992
					     S1_X(0x4) | S1_Y(0xc) |
993
					     S2_X(0x1) | S2_Y(0x6) |
994
					     S3_X(0xa) | S3_Y(0xe)));
995
	WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
996
					     S5_X(0x0) | S5_Y(0x0) |
997
					     S6_X(0xb) | S6_Y(0x4) |
998
					     S7_X(0x7) | S7_Y(0x8)));
999
 
1000
	WREG32(VGT_STRMOUT_EN, 0);
1001
	tmp = rdev->config.r600.max_pipes * 16;
1002
	switch (rdev->family) {
1003
	case CHIP_RV610:
1004
	case CHIP_RS780:
1005
	case CHIP_RV620:
1006
		tmp += 32;
1007
		break;
1008
	case CHIP_RV670:
1009
		tmp += 128;
1010
		break;
1011
	default:
1012
		break;
1013
	}
1014
	if (tmp > 256) {
1015
		tmp = 256;
1016
	}
1017
	WREG32(VGT_ES_PER_GS, 128);
1018
	WREG32(VGT_GS_PER_ES, tmp);
1019
	WREG32(VGT_GS_PER_VS, 2);
1020
	WREG32(VGT_GS_VERTEX_REUSE, 16);
1021
 
1022
	/* more default values. 2D/3D driver should adjust as needed */
1023
	WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1024
	WREG32(VGT_STRMOUT_EN, 0);
1025
	WREG32(SX_MISC, 0);
1026
	WREG32(PA_SC_MODE_CNTL, 0);
1027
	WREG32(PA_SC_AA_CONFIG, 0);
1028
	WREG32(PA_SC_LINE_STIPPLE, 0);
1029
	WREG32(SPI_INPUT_Z, 0);
1030
	WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1031
	WREG32(CB_COLOR7_FRAG, 0);
1032
 
1033
	/* Clear render buffer base addresses */
1034
	WREG32(CB_COLOR0_BASE, 0);
1035
	WREG32(CB_COLOR1_BASE, 0);
1036
	WREG32(CB_COLOR2_BASE, 0);
1037
	WREG32(CB_COLOR3_BASE, 0);
1038
	WREG32(CB_COLOR4_BASE, 0);
1039
	WREG32(CB_COLOR5_BASE, 0);
1040
	WREG32(CB_COLOR6_BASE, 0);
1041
	WREG32(CB_COLOR7_BASE, 0);
1042
	WREG32(CB_COLOR7_FRAG, 0);
1043
 
1044
	switch (rdev->family) {
1045
	case CHIP_RV610:
1046
	case CHIP_RS780:
1047
	case CHIP_RV620:
1048
		tmp = TC_L2_SIZE(8);
1049
		break;
1050
	case CHIP_RV630:
1051
	case CHIP_RV635:
1052
		tmp = TC_L2_SIZE(4);
1053
		break;
1054
	case CHIP_R600:
1055
		tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1056
		break;
1057
	default:
1058
		tmp = TC_L2_SIZE(0);
1059
		break;
1060
	}
1061
	WREG32(TC_CNTL, tmp);
1062
 
1063
	tmp = RREG32(HDP_HOST_PATH_CNTL);
1064
	WREG32(HDP_HOST_PATH_CNTL, tmp);
1065
 
1066
	tmp = RREG32(ARB_POP);
1067
	tmp |= ENABLE_TC128;
1068
	WREG32(ARB_POP, tmp);
1069
 
1070
	WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1071
	WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1072
			       NUM_CLIP_SEQ(3)));
1073
	WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1074
}
1075
 
1076
 
1128 serge 1077
/*
1078
 * Indirect registers accessor
1079
 */
1221 serge 1080
u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1128 serge 1081
{
1221 serge 1082
	u32 r;
1128 serge 1083
 
1221 serge 1084
	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1085
	(void)RREG32(PCIE_PORT_INDEX);
1086
	r = RREG32(PCIE_PORT_DATA);
1128 serge 1087
	return r;
1088
}
1089
 
1221 serge 1090
void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1128 serge 1091
{
1221 serge 1092
	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1093
	(void)RREG32(PCIE_PORT_INDEX);
1094
	WREG32(PCIE_PORT_DATA, (v));
1095
	(void)RREG32(PCIE_PORT_DATA);
1128 serge 1096
}
1221 serge 1097
 
1098
 
1099
/*
1100
 * CP & Ring
1101
 */
1102
void r600_cp_stop(struct radeon_device *rdev)
1103
{
1104
	WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1105
}
1106
int r600_cp_start(struct radeon_device *rdev)
1107
{
1108
	int r;
1109
	uint32_t cp_me;
1110
 
1111
	r = radeon_ring_lock(rdev, 7);
1112
	if (r) {
1113
		DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1114
		return r;
1115
	}
1116
	radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1117
	radeon_ring_write(rdev, 0x1);
1118
	if (rdev->family < CHIP_RV770) {
1119
		radeon_ring_write(rdev, 0x3);
1120
		radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1121
	} else {
1122
		radeon_ring_write(rdev, 0x0);
1123
		radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1124
	}
1125
	radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1126
	radeon_ring_write(rdev, 0);
1127
	radeon_ring_write(rdev, 0);
1128
	radeon_ring_unlock_commit(rdev);
1129
 
1130
	cp_me = 0xff;
1131
	WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1132
	return 0;
1133
}
1134
void r600_cp_commit(struct radeon_device *rdev)
1135
{
1136
	WREG32(CP_RB_WPTR, rdev->cp.wptr);
1137
	(void)RREG32(CP_RB_WPTR);
1138
}
1139
 
1140
 
1141
int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1142
			 uint32_t tiling_flags, uint32_t pitch,
1143
			 uint32_t offset, uint32_t obj_size)
1144
{
1145
	/* FIXME: implement */
1146
	return 0;
1147
}
1148
 
1149
void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1150
{
1151
	/* FIXME: implement */
1152
}
1153
 
1154
 
1155
bool r600_card_posted(struct radeon_device *rdev)
1156
{
1157
	uint32_t reg;
1158
 
1159
	/* first check CRTCs */
1160
	reg = RREG32(D1CRTC_CONTROL) |
1161
		RREG32(D2CRTC_CONTROL);
1162
	if (reg & CRTC_EN)
1163
		return true;
1164
 
1165
	/* then check MEM_SIZE, in case the crtcs are off */
1166
	if (RREG32(CONFIG_MEMSIZE))
1167
		return true;
1168
 
1169
	return false;
1170
}
1171
 
1172
int r600_startup(struct radeon_device *rdev)
1173
{
1174
	int r;
1175
 
1176
	r600_mc_program(rdev);
1177
	if (rdev->flags & RADEON_IS_AGP) {
1178
		r600_agp_enable(rdev);
1179
	} else {
1180
		r = r600_pcie_gart_enable(rdev);
1181
		if (r)
1182
			return r;
1183
	}
1184
	r600_gpu_init(rdev);
1185
 
1186
	r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1187
			      &rdev->r600_blit.shader_gpu_addr);
1188
	if (r) {
1189
		DRM_ERROR("failed to pin blit object %d\n", r);
1190
		return r;
1191
	}
1192
 
1193
	r = radeon_ring_init(rdev, rdev->cp.ring_size);
1194
	if (r)
1195
		return r;
1196
	r = r600_cp_load_microcode(rdev);
1197
	if (r)
1198
		return r;
1199
	r = r600_cp_resume(rdev);
1200
	if (r)
1201
		return r;
1202
	/* write back buffer are not vital so don't worry about failure */
1203
	r600_wb_enable(rdev);
1204
	return 0;
1205
}
1206
 
1207
void r600_vga_set_state(struct radeon_device *rdev, bool state)
1208
{
1209
	uint32_t temp;
1210
 
1211
	temp = RREG32(CONFIG_CNTL);
1212
	if (state == false) {
1213
		temp &= ~(1<<0);
1214
		temp |= (1<<1);
1215
	} else {
1216
		temp &= ~(1<<1);
1217
	}
1218
	WREG32(CONFIG_CNTL, temp);
1219
}
1220
 
1221
 
1222
 
1223
 
1224
 
1225
/* Plan is to move initialization in that function and use
1226
 * helper function so that radeon_device_init pretty much
1227
 * do nothing more than calling asic specific function. This
1228
 * should also allow to remove a bunch of callback function
1229
 * like vram_info.
1230
 */
1231
int r600_init(struct radeon_device *rdev)
1232
{
1233
	int r;
1234
 
1235
	r = radeon_dummy_page_init(rdev);
1236
	if (r)
1237
		return r;
1238
	if (r600_debugfs_mc_info_init(rdev)) {
1239
		DRM_ERROR("Failed to register debugfs file for mc !\n");
1240
	}
1241
	/* This don't do much */
1242
	r = radeon_gem_init(rdev);
1243
	if (r)
1244
		return r;
1245
	/* Read BIOS */
1246
	if (!radeon_get_bios(rdev)) {
1247
		if (ASIC_IS_AVIVO(rdev))
1248
			return -EINVAL;
1249
	}
1250
	/* Must be an ATOMBIOS */
1251
	if (!rdev->is_atom_bios) {
1252
		dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1253
		return -EINVAL;
1254
	}
1255
	r = radeon_atombios_init(rdev);
1256
	if (r)
1257
		return r;
1258
	/* Post card if necessary */
1259
	if (!r600_card_posted(rdev) && rdev->bios) {
1260
		DRM_INFO("GPU not posted. posting now...\n");
1261
		atom_asic_init(rdev->mode_info.atom_context);
1262
	}
1263
	/* Initialize scratch registers */
1264
	r600_scratch_init(rdev);
1265
	/* Initialize surface registers */
1266
	radeon_surface_init(rdev);
1267
	radeon_get_clock_info(rdev->ddev);
1268
	r = radeon_clocks_init(rdev);
1269
	if (r)
1270
		return r;
1271
	/* Fence driver */
1272
//	r = radeon_fence_driver_init(rdev);
1273
//	if (r)
1274
//		return r;
1275
	r = r600_mc_init(rdev);
1276
	if (r)
1277
		return r;
1278
	/* Memory manager */
1279
	r = radeon_object_init(rdev);
1280
	if (r)
1281
		return r;
1282
	rdev->cp.ring_obj = NULL;
1283
	r600_ring_init(rdev, 1024 * 1024);
1284
 
1285
	if (!rdev->me_fw || !rdev->pfp_fw) {
1286
		r = r600_cp_init_microcode(rdev);
1287
		if (r) {
1288
			DRM_ERROR("Failed to load firmware!\n");
1289
			return r;
1290
		}
1291
	}
1292
 
1293
	r = r600_pcie_gart_init(rdev);
1294
	if (r)
1295
		return r;
1296
 
1297
	rdev->accel_working = true;
1298
	r = r600_blit_init(rdev);
1299
	if (r) {
1300
		DRM_ERROR("radeon: failled blitter (%d).\n", r);
1301
		return r;
1302
	}
1303
 
1304
	r = r600_startup(rdev);
1305
	if (r) {
1306
//		r600_suspend(rdev);
1307
//		r600_wb_fini(rdev);
1308
//		radeon_ring_fini(rdev);
1309
		r600_pcie_gart_fini(rdev);
1310
		rdev->accel_working = false;
1311
	}
1312
	if (rdev->accel_working) {
1313
//		r = radeon_ib_pool_init(rdev);
1314
//		if (r) {
1315
//			DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
1316
//			rdev->accel_working = false;
1317
//		}
1318
//		r = r600_ib_test(rdev);
1319
//		if (r) {
1320
//			DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1321
//			rdev->accel_working = false;
1322
//		}
1323
	}
1324
	return 0;
1325
}
1326
 
1327
 
1328
 
1329
 
1330
 
1331
 
1332
 
1333
 
1334
 
1335
/*
1336
 * Debugfs info
1337
 */
1338
#if defined(CONFIG_DEBUG_FS)
1339
 
1340
static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
1341
{
1342
	struct drm_info_node *node = (struct drm_info_node *) m->private;
1343
	struct drm_device *dev = node->minor->dev;
1344
	struct radeon_device *rdev = dev->dev_private;
1345
	uint32_t rdp, wdp;
1346
	unsigned count, i, j;
1347
 
1348
	radeon_ring_free_size(rdev);
1349
	rdp = RREG32(CP_RB_RPTR);
1350
	wdp = RREG32(CP_RB_WPTR);
1351
	count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1352
	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
1353
	seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1354
	seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1355
	seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1356
	seq_printf(m, "%u dwords in ring\n", count);
1357
	for (j = 0; j <= count; j++) {
1358
		i = (rdp + j) & rdev->cp.ptr_mask;
1359
		seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1360
	}
1361
	return 0;
1362
}
1363
 
1364
static int r600_debugfs_mc_info(struct seq_file *m, void *data)
1365
{
1366
	struct drm_info_node *node = (struct drm_info_node *) m->private;
1367
	struct drm_device *dev = node->minor->dev;
1368
	struct radeon_device *rdev = dev->dev_private;
1369
 
1370
	DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
1371
	DREG32_SYS(m, rdev, VM_L2_STATUS);
1372
	return 0;
1373
}
1374
 
1375
static struct drm_info_list r600_mc_info_list[] = {
1376
	{"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
1377
	{"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
1378
};
1379
#endif
1380
 
1381
int r600_debugfs_mc_info_init(struct radeon_device *rdev)
1382
{
1383
#if defined(CONFIG_DEBUG_FS)
1384
	return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
1385
#else
1386
	return 0;
1387
#endif
1388
}