Rev 6104 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1117 | serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * Copyright 2009 Jerome Glisse. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: Dave Airlie |
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| 25 | * Alex Deucher |
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| 26 | * Jerome Glisse |
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| 27 | */ |
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| 2997 | Serge | 28 | #include |
| 1117 | serge | 29 | #include "radeon.h" |
| 1963 | serge | 30 | #include "radeon_asic.h" |
| 1221 | serge | 31 | #include "atom.h" |
| 32 | #include "r520d.h" |
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| 1117 | serge | 33 | |
| 1221 | serge | 34 | /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */ |
| 1117 | serge | 35 | |
| 2997 | Serge | 36 | int r520_mc_wait_for_idle(struct radeon_device *rdev) |
| 1117 | serge | 37 | { |
| 38 | unsigned i; |
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| 39 | uint32_t tmp; |
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| 40 | |||
| 41 | for (i = 0; i < rdev->usec_timeout; i++) { |
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| 42 | /* read MC_STATUS */ |
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| 43 | tmp = RREG32_MC(R520_MC_STATUS); |
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| 44 | if (tmp & R520_MC_STATUS_IDLE) { |
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| 45 | return 0; |
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| 46 | } |
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| 47 | DRM_UDELAY(1); |
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| 48 | } |
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| 49 | return -1; |
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| 50 | } |
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| 51 | |||
| 1221 | serge | 52 | static void r520_gpu_init(struct radeon_device *rdev) |
| 1117 | serge | 53 | { |
| 54 | unsigned pipe_select_current, gb_pipe_select, tmp; |
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| 55 | |||
| 1221 | serge | 56 | rv515_vga_render_disable(rdev); |
| 1117 | serge | 57 | /* |
| 58 | * DST_PIPE_CONFIG 0x170C |
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| 59 | * GB_TILE_CONFIG 0x4018 |
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| 60 | * GB_FIFO_SIZE 0x4024 |
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| 61 | * GB_PIPE_SELECT 0x402C |
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| 62 | * GB_PIPE_SELECT2 0x4124 |
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| 63 | * Z_PIPE_SHIFT 0 |
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| 64 | * Z_PIPE_MASK 0x000000003 |
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| 65 | * GB_FIFO_SIZE2 0x4128 |
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| 66 | * SC_SFIFO_SIZE_SHIFT 0 |
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| 67 | * SC_SFIFO_SIZE_MASK 0x000000003 |
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| 68 | * SC_MFIFO_SIZE_SHIFT 2 |
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| 69 | * SC_MFIFO_SIZE_MASK 0x00000000C |
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| 70 | * FG_SFIFO_SIZE_SHIFT 4 |
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| 71 | * FG_SFIFO_SIZE_MASK 0x000000030 |
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| 72 | * ZB_MFIFO_SIZE_SHIFT 6 |
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| 73 | * ZB_MFIFO_SIZE_MASK 0x0000000C0 |
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| 74 | * GA_ENHANCE 0x4274 |
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| 75 | * SU_REG_DEST 0x42C8 |
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| 76 | */ |
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| 77 | /* workaround for RV530 */ |
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| 78 | if (rdev->family == CHIP_RV530) { |
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| 79 | WREG32(0x4128, 0xFF); |
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| 80 | } |
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| 81 | r420_pipes_init(rdev); |
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| 1963 | serge | 82 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); |
| 83 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
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| 1117 | serge | 84 | pipe_select_current = (tmp >> 2) & 3; |
| 85 | tmp = (1 << pipe_select_current) | |
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| 86 | (((gb_pipe_select >> 8) & 0xF) << 4); |
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| 87 | WREG32_PLL(0x000D, tmp); |
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| 88 | if (r520_mc_wait_for_idle(rdev)) { |
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| 89 | printk(KERN_WARNING "Failed to wait MC idle while " |
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| 90 | "programming pipes. Bad things might happen.\n"); |
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| 91 | } |
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| 92 | } |
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| 93 | |||
| 94 | static void r520_vram_get_type(struct radeon_device *rdev) |
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| 95 | { |
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| 96 | uint32_t tmp; |
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| 97 | |||
| 98 | rdev->mc.vram_width = 128; |
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| 99 | rdev->mc.vram_is_ddr = true; |
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| 100 | tmp = RREG32_MC(R520_MC_CNTL0); |
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| 101 | switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { |
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| 102 | case 0: |
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| 103 | rdev->mc.vram_width = 32; |
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| 104 | break; |
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| 105 | case 1: |
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| 106 | rdev->mc.vram_width = 64; |
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| 107 | break; |
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| 108 | case 2: |
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| 109 | rdev->mc.vram_width = 128; |
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| 110 | break; |
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| 111 | case 3: |
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| 112 | rdev->mc.vram_width = 256; |
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| 113 | break; |
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| 114 | default: |
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| 115 | rdev->mc.vram_width = 128; |
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| 116 | break; |
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| 117 | } |
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| 118 | if (tmp & R520_MC_CHANNEL_SIZE) |
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| 119 | rdev->mc.vram_width *= 2; |
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| 120 | } |
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| 121 | |||
| 2997 | Serge | 122 | static void r520_mc_init(struct radeon_device *rdev) |
| 1117 | serge | 123 | { |
| 1179 | serge | 124 | |
| 1117 | serge | 125 | r520_vram_get_type(rdev); |
| 1179 | serge | 126 | r100_vram_init_sizes(rdev); |
| 1430 | serge | 127 | radeon_vram_location(rdev, &rdev->mc, 0); |
| 1963 | serge | 128 | rdev->mc.gtt_base_align = 0; |
| 1430 | serge | 129 | if (!(rdev->flags & RADEON_IS_AGP)) |
| 130 | radeon_gtt_location(rdev, &rdev->mc); |
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| 1963 | serge | 131 | radeon_update_bandwidth_info(rdev); |
| 1117 | serge | 132 | } |
| 133 | |||
| 2997 | Serge | 134 | static void r520_mc_program(struct radeon_device *rdev) |
| 1119 | serge | 135 | { |
| 1221 | serge | 136 | struct rv515_mc_save save; |
| 137 | |||
| 138 | /* Stops all mc clients */ |
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| 139 | rv515_mc_stop(rdev, &save); |
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| 140 | |||
| 141 | /* Wait for mc idle */ |
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| 142 | if (r520_mc_wait_for_idle(rdev)) |
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| 143 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
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| 144 | /* Write VRAM size in case we are limiting it */ |
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| 145 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
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| 146 | /* Program MC, should be a 32bits limited address space */ |
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| 147 | WREG32_MC(R_000004_MC_FB_LOCATION, |
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| 148 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
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| 149 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
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| 150 | WREG32(R_000134_HDP_FB_LOCATION, |
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| 151 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
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| 152 | if (rdev->flags & RADEON_IS_AGP) { |
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| 153 | WREG32_MC(R_000005_MC_AGP_LOCATION, |
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| 154 | S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
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| 155 | S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
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| 156 | WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
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| 157 | WREG32_MC(R_000007_AGP_BASE_2, |
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| 158 | S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); |
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| 159 | } else { |
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| 160 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF); |
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| 161 | WREG32_MC(R_000006_AGP_BASE, 0); |
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| 162 | WREG32_MC(R_000007_AGP_BASE_2, 0); |
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| 163 | } |
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| 164 | |||
| 165 | rv515_mc_resume(rdev, &save); |
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| 1119 | serge | 166 | } |
| 1221 | serge | 167 | |
| 168 | static int r520_startup(struct radeon_device *rdev) |
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| 169 | { |
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| 170 | int r; |
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| 171 | |||
| 172 | r520_mc_program(rdev); |
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| 173 | /* Resume clock */ |
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| 174 | rv515_clock_startup(rdev); |
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| 175 | /* Initialize GPU configuration (# pipes, ...) */ |
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| 176 | r520_gpu_init(rdev); |
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| 177 | /* Initialize GART (initialize after TTM so we can allocate |
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| 178 | * memory through TTM but finalize after TTM) */ |
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| 179 | if (rdev->flags & RADEON_IS_PCIE) { |
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| 180 | r = rv370_pcie_gart_enable(rdev); |
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| 181 | if (r) |
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| 182 | return r; |
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| 183 | } |
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| 2005 | serge | 184 | |
| 185 | /* allocate wb buffer */ |
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| 186 | r = radeon_wb_init(rdev); |
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| 187 | if (r) |
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| 188 | return r; |
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| 189 | |||
| 3120 | serge | 190 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
| 191 | if (r) { |
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| 192 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
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| 193 | return r; |
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| 194 | } |
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| 195 | |||
| 1221 | serge | 196 | /* Enable IRQ */ |
| 3764 | Serge | 197 | if (!rdev->irq.installed) { |
| 198 | r = radeon_irq_kms_init(rdev); |
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| 199 | if (r) |
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| 200 | return r; |
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| 201 | } |
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| 202 | |||
| 2005 | serge | 203 | rs600_irq_set(rdev); |
| 1413 | serge | 204 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
| 1221 | serge | 205 | /* 1M ring buffer */ |
| 6104 | serge | 206 | r = r100_cp_init(rdev, 1024 * 1024); |
| 207 | if (r) { |
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| 1963 | serge | 208 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
| 6104 | serge | 209 | return r; |
| 210 | } |
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| 2997 | Serge | 211 | |
| 212 | r = radeon_ib_pool_init(rdev); |
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| 2005 | serge | 213 | if (r) { |
| 2997 | Serge | 214 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
| 2005 | serge | 215 | return r; |
| 216 | } |
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| 2997 | Serge | 217 | |
| 1221 | serge | 218 | return 0; |
| 219 | } |
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| 220 | |||
| 221 | |||
| 222 | |||
| 223 | int r520_init(struct radeon_device *rdev) |
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| 224 | { |
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| 225 | int r; |
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| 226 | |||
| 227 | /* Initialize scratch registers */ |
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| 228 | radeon_scratch_init(rdev); |
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| 229 | /* Initialize surface registers */ |
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| 230 | radeon_surface_init(rdev); |
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| 1963 | serge | 231 | /* restore some register to sane defaults */ |
| 232 | r100_restore_sanity(rdev); |
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| 1221 | serge | 233 | /* TODO: disable VGA need to use VGA request */ |
| 234 | /* BIOS*/ |
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| 235 | if (!radeon_get_bios(rdev)) { |
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| 236 | if (ASIC_IS_AVIVO(rdev)) |
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| 237 | return -EINVAL; |
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| 238 | } |
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| 239 | if (rdev->is_atom_bios) { |
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| 240 | r = radeon_atombios_init(rdev); |
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| 241 | if (r) |
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| 242 | return r; |
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| 243 | } else { |
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| 244 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
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| 245 | return -EINVAL; |
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| 246 | } |
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| 247 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
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| 1963 | serge | 248 | if (radeon_asic_reset(rdev)) { |
| 1221 | serge | 249 | dev_warn(rdev->dev, |
| 250 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
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| 251 | RREG32(R_000E40_RBBM_STATUS), |
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| 252 | RREG32(R_0007C0_CP_STAT)); |
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| 253 | } |
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| 254 | /* check if cards are posted or not */ |
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| 1321 | serge | 255 | if (radeon_boot_test_post_card(rdev) == false) |
| 256 | return -EINVAL; |
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| 257 | |||
| 1221 | serge | 258 | if (!radeon_card_posted(rdev) && rdev->bios) { |
| 259 | DRM_INFO("GPU not posted. posting now...\n"); |
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| 260 | atom_asic_init(rdev->mode_info.atom_context); |
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| 261 | } |
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| 262 | /* Initialize clocks */ |
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| 263 | radeon_get_clock_info(rdev->ddev); |
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| 1430 | serge | 264 | /* initialize AGP */ |
| 265 | if (rdev->flags & RADEON_IS_AGP) { |
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| 266 | r = radeon_agp_init(rdev); |
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| 267 | if (r) { |
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| 268 | radeon_agp_disable(rdev); |
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| 269 | } |
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| 270 | } |
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| 271 | /* initialize memory controller */ |
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| 272 | r520_mc_init(rdev); |
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| 1221 | serge | 273 | rv515_debugfs(rdev); |
| 274 | /* Fence driver */ |
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| 2005 | serge | 275 | r = radeon_fence_driver_init(rdev); |
| 276 | if (r) |
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| 277 | return r; |
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| 1221 | serge | 278 | /* Memory manager */ |
| 1321 | serge | 279 | r = radeon_bo_init(rdev); |
| 1221 | serge | 280 | if (r) |
| 281 | return r; |
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| 282 | r = rv370_pcie_gart_init(rdev); |
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| 283 | if (r) |
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| 284 | return r; |
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| 285 | rv515_set_safe_registers(rdev); |
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| 2997 | Serge | 286 | |
| 5078 | serge | 287 | /* Initialize power management */ |
| 288 | radeon_pm_init(rdev); |
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| 289 | |||
| 1221 | serge | 290 | rdev->accel_working = true; |
| 291 | r = r520_startup(rdev); |
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| 292 | if (r) { |
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| 293 | /* Somethings want wront with the accel init stop accel */ |
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| 294 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
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| 6104 | serge | 295 | r100_cp_fini(rdev); |
| 296 | radeon_wb_fini(rdev); |
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| 297 | radeon_ib_pool_fini(rdev); |
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| 298 | radeon_irq_kms_fini(rdev); |
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| 1221 | serge | 299 | rv370_pcie_gart_fini(rdev); |
| 7146 | serge | 300 | radeon_agp_fini(rdev); |
| 1221 | serge | 301 | rdev->accel_working = false; |
| 302 | } |
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| 303 | return 0; |
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| 304 | } |