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Rev | Author | Line No. | Line |
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1179 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #include |
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1963 | serge | 29 | #include |
2997 | Serge | 30 | #include |
1179 | serge | 31 | #include "radeon_reg.h" |
32 | #include "radeon.h" |
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1963 | serge | 33 | #include "radeon_asic.h" |
1179 | serge | 34 | #include "atom.h" |
1403 | serge | 35 | #include "r100d.h" |
1179 | serge | 36 | #include "r420d.h" |
1403 | serge | 37 | #include "r420_reg_safe.h" |
1179 | serge | 38 | |
3764 | Serge | 39 | void r420_pm_init_profile(struct radeon_device *rdev) |
40 | { |
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41 | /* default */ |
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42 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
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43 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
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44 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
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45 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
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46 | /* low sh */ |
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47 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; |
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48 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; |
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49 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
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50 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
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51 | /* mid sh */ |
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52 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; |
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53 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; |
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54 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
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55 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; |
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56 | /* high sh */ |
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57 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; |
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58 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
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59 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
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60 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
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61 | /* low mh */ |
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62 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; |
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63 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
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64 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
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65 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
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66 | /* mid mh */ |
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67 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; |
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68 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
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69 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
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70 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; |
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71 | /* high mh */ |
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72 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; |
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73 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
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74 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
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75 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
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76 | } |
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77 | |||
1403 | serge | 78 | static void r420_set_reg_safe(struct radeon_device *rdev) |
79 | { |
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80 | rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; |
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81 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); |
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82 | } |
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83 | |||
1179 | serge | 84 | void r420_pipes_init(struct radeon_device *rdev) |
85 | { |
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86 | unsigned tmp; |
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87 | unsigned gb_pipe_select; |
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88 | unsigned num_pipes; |
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89 | |||
90 | /* GA_ENHANCE workaround TCL deadlock issue */ |
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1430 | serge | 91 | WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | |
92 | (1 << 2) | (1 << 3)); |
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1179 | serge | 93 | /* add idle wait as per freedesktop.org bug 24041 */ |
94 | if (r100_gui_wait_for_idle(rdev)) { |
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95 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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96 | "programming pipes. Bad things might happen.\n"); |
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97 | } |
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98 | /* get max number of pipes */ |
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1963 | serge | 99 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); |
1179 | serge | 100 | num_pipes = ((gb_pipe_select >> 12) & 3) + 1; |
1963 | serge | 101 | |
102 | /* SE chips have 1 pipe */ |
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103 | if ((rdev->pdev->device == 0x5e4c) || |
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104 | (rdev->pdev->device == 0x5e4f)) |
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105 | num_pipes = 1; |
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106 | |||
1179 | serge | 107 | rdev->num_gb_pipes = num_pipes; |
108 | tmp = 0; |
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109 | switch (num_pipes) { |
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110 | default: |
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111 | /* force to 1 pipe */ |
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112 | num_pipes = 1; |
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113 | case 1: |
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114 | tmp = (0 << 1); |
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115 | break; |
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116 | case 2: |
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117 | tmp = (3 << 1); |
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118 | break; |
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119 | case 3: |
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120 | tmp = (6 << 1); |
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121 | break; |
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122 | case 4: |
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123 | tmp = (7 << 1); |
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124 | break; |
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125 | } |
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1430 | serge | 126 | WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); |
1179 | serge | 127 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
1430 | serge | 128 | tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; |
129 | WREG32(R300_GB_TILE_CONFIG, tmp); |
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1179 | serge | 130 | if (r100_gui_wait_for_idle(rdev)) { |
131 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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132 | "programming pipes. Bad things might happen.\n"); |
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133 | } |
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134 | |||
1430 | serge | 135 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
136 | WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); |
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1179 | serge | 137 | |
138 | WREG32(R300_RB2D_DSTCACHE_MODE, |
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139 | RREG32(R300_RB2D_DSTCACHE_MODE) | |
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140 | R300_DC_AUTOFLUSH_ENABLE | |
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141 | R300_DC_DC_DISABLE_IGNORE_PE); |
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142 | |||
143 | if (r100_gui_wait_for_idle(rdev)) { |
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144 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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145 | "programming pipes. Bad things might happen.\n"); |
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146 | } |
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147 | |||
148 | if (rdev->family == CHIP_RV530) { |
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149 | tmp = RREG32(RV530_GB_PIPE_SELECT2); |
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150 | if ((tmp & 3) == 3) |
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151 | rdev->num_z_pipes = 2; |
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152 | else |
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153 | rdev->num_z_pipes = 1; |
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154 | } else |
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155 | rdev->num_z_pipes = 1; |
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156 | |||
157 | DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", |
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158 | rdev->num_gb_pipes, rdev->num_z_pipes); |
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159 | } |
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160 | |||
161 | u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) |
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162 | { |
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163 | u32 r; |
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164 | |||
165 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); |
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166 | r = RREG32(R_0001FC_MC_IND_DATA); |
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167 | return r; |
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168 | } |
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169 | |||
170 | void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
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171 | { |
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172 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | |
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173 | S_0001F8_MC_IND_WR_EN(1)); |
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174 | WREG32(R_0001FC_MC_IND_DATA, v); |
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175 | } |
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176 | |||
177 | static void r420_debugfs(struct radeon_device *rdev) |
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178 | { |
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179 | if (r100_debugfs_rbbm_init(rdev)) { |
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180 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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181 | } |
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182 | if (r420_debugfs_pipes_info_init(rdev)) { |
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183 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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184 | } |
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185 | } |
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186 | |||
187 | static void r420_clock_resume(struct radeon_device *rdev) |
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188 | { |
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189 | u32 sclk_cntl; |
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1221 | serge | 190 | |
191 | if (radeon_dynclks != -1 && radeon_dynclks) |
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192 | radeon_atom_set_clock_gating(rdev, 1); |
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1179 | serge | 193 | sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); |
194 | sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
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195 | if (rdev->family == CHIP_R420) |
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196 | sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); |
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197 | WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); |
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198 | } |
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199 | |||
1403 | serge | 200 | static void r420_cp_errata_init(struct radeon_device *rdev) |
201 | { |
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2997 | Serge | 202 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
203 | |||
1403 | serge | 204 | /* RV410 and R420 can lock up if CP DMA to host memory happens |
205 | * while the 2D engine is busy. |
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206 | * |
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207 | * The proper workaround is to queue a RESYNC at the beginning |
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208 | * of the CP init, apparently. |
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209 | */ |
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210 | radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); |
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2997 | Serge | 211 | radeon_ring_lock(rdev, ring, 8); |
212 | radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); |
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213 | radeon_ring_write(ring, rdev->config.r300.resync_scratch); |
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214 | radeon_ring_write(ring, 0xDEADBEEF); |
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215 | radeon_ring_unlock_commit(rdev, ring); |
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1403 | serge | 216 | } |
217 | |||
218 | static void r420_cp_errata_fini(struct radeon_device *rdev) |
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219 | { |
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2997 | Serge | 220 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
221 | |||
1403 | serge | 222 | /* Catch the RESYNC we dispatched all the way back, |
223 | * at the very beginning of the CP init. |
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224 | */ |
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2997 | Serge | 225 | radeon_ring_lock(rdev, ring, 8); |
226 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
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227 | radeon_ring_write(ring, R300_RB3D_DC_FINISH); |
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228 | radeon_ring_unlock_commit(rdev, ring); |
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1403 | serge | 229 | radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); |
230 | } |
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231 | |||
1179 | serge | 232 | static int r420_startup(struct radeon_device *rdev) |
233 | { |
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234 | int r; |
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235 | |||
1321 | serge | 236 | /* set common regs */ |
237 | r100_set_common_regs(rdev); |
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238 | /* program mc */ |
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1179 | serge | 239 | r300_mc_program(rdev); |
1221 | serge | 240 | /* Resume clock */ |
241 | r420_clock_resume(rdev); |
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1179 | serge | 242 | /* Initialize GART (initialize after TTM so we can allocate |
243 | * memory through TTM but finalize after TTM) */ |
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244 | if (rdev->flags & RADEON_IS_PCIE) { |
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245 | r = rv370_pcie_gart_enable(rdev); |
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246 | if (r) |
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247 | return r; |
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248 | } |
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249 | if (rdev->flags & RADEON_IS_PCI) { |
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250 | r = r100_pci_gart_enable(rdev); |
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251 | if (r) |
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252 | return r; |
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253 | } |
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254 | r420_pipes_init(rdev); |
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2005 | serge | 255 | |
256 | /* allocate wb buffer */ |
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257 | r = radeon_wb_init(rdev); |
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258 | if (r) |
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259 | return r; |
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260 | |||
3120 | serge | 261 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
262 | if (r) { |
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263 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
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264 | return r; |
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265 | } |
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266 | |||
1179 | serge | 267 | /* Enable IRQ */ |
3764 | Serge | 268 | if (!rdev->irq.installed) { |
269 | r = radeon_irq_kms_init(rdev); |
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270 | if (r) |
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271 | return r; |
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272 | } |
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273 | |||
2005 | serge | 274 | r100_irq_set(rdev); |
1403 | serge | 275 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1179 | serge | 276 | /* 1M ring buffer */ |
1412 | serge | 277 | r = r100_cp_init(rdev, 1024 * 1024); |
278 | if (r) { |
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1963 | serge | 279 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
1412 | serge | 280 | return r; |
281 | } |
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282 | r420_cp_errata_init(rdev); |
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2997 | Serge | 283 | |
284 | r = radeon_ib_pool_init(rdev); |
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2005 | serge | 285 | if (r) { |
2997 | Serge | 286 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
2005 | serge | 287 | return r; |
288 | } |
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2997 | Serge | 289 | |
1179 | serge | 290 | return 0; |
291 | } |
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292 | |||
293 | |||
294 | |||
295 | |||
2997 | Serge | 296 | |
297 | |||
1179 | serge | 298 | int r420_init(struct radeon_device *rdev) |
299 | { |
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300 | int r; |
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301 | |||
302 | /* Initialize scratch registers */ |
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303 | radeon_scratch_init(rdev); |
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304 | /* Initialize surface registers */ |
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305 | radeon_surface_init(rdev); |
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306 | /* TODO: disable VGA need to use VGA request */ |
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1963 | serge | 307 | /* restore some register to sane defaults */ |
308 | r100_restore_sanity(rdev); |
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1179 | serge | 309 | /* BIOS*/ |
310 | if (!radeon_get_bios(rdev)) { |
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311 | if (ASIC_IS_AVIVO(rdev)) |
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312 | return -EINVAL; |
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313 | } |
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314 | if (rdev->is_atom_bios) { |
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315 | r = radeon_atombios_init(rdev); |
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316 | if (r) { |
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317 | return r; |
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318 | } |
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319 | } else { |
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320 | r = radeon_combios_init(rdev); |
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321 | if (r) { |
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322 | return r; |
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323 | } |
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324 | } |
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325 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
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1963 | serge | 326 | if (radeon_asic_reset(rdev)) { |
1179 | serge | 327 | dev_warn(rdev->dev, |
328 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
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329 | RREG32(R_000E40_RBBM_STATUS), |
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330 | RREG32(R_0007C0_CP_STAT)); |
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331 | } |
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332 | /* check if cards are posted or not */ |
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1321 | serge | 333 | if (radeon_boot_test_post_card(rdev) == false) |
334 | return -EINVAL; |
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335 | |||
1179 | serge | 336 | /* Initialize clocks */ |
337 | radeon_get_clock_info(rdev->ddev); |
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1430 | serge | 338 | /* initialize AGP */ |
339 | if (rdev->flags & RADEON_IS_AGP) { |
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340 | r = radeon_agp_init(rdev); |
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1179 | serge | 341 | if (r) { |
1430 | serge | 342 | radeon_agp_disable(rdev); |
1179 | serge | 343 | } |
1430 | serge | 344 | } |
345 | /* initialize memory controller */ |
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346 | r300_mc_init(rdev); |
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1179 | serge | 347 | r420_debugfs(rdev); |
348 | /* Fence driver */ |
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2005 | serge | 349 | r = radeon_fence_driver_init(rdev); |
350 | if (r) { |
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351 | return r; |
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352 | } |
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1179 | serge | 353 | /* Memory manager */ |
1321 | serge | 354 | r = radeon_bo_init(rdev); |
1179 | serge | 355 | if (r) { |
356 | return r; |
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357 | } |
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1321 | serge | 358 | if (rdev->family == CHIP_R420) |
359 | r100_enable_bm(rdev); |
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360 | |||
1179 | serge | 361 | if (rdev->flags & RADEON_IS_PCIE) { |
362 | r = rv370_pcie_gart_init(rdev); |
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363 | if (r) |
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364 | return r; |
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365 | } |
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366 | if (rdev->flags & RADEON_IS_PCI) { |
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367 | r = r100_pci_gart_init(rdev); |
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368 | if (r) |
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369 | return r; |
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370 | } |
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1404 | serge | 371 | r420_set_reg_safe(rdev); |
2997 | Serge | 372 | |
1179 | serge | 373 | rdev->accel_working = true; |
374 | r = r420_startup(rdev); |
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375 | if (r) { |
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376 | /* Somethings want wront with the accel init stop accel */ |
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377 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
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378 | if (rdev->flags & RADEON_IS_PCIE) |
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379 | rv370_pcie_gart_fini(rdev); |
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380 | if (rdev->flags & RADEON_IS_PCI) |
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381 | r100_pci_gart_fini(rdev); |
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382 | rdev->accel_working = false; |
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383 | } |
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384 | return 0; |
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385 | } |
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386 | |||
387 | /* |
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388 | * Debugfs info |
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389 | */ |
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390 | #if defined(CONFIG_DEBUG_FS) |
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391 | static int r420_debugfs_pipes_info(struct seq_file *m, void *data) |
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392 | { |
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393 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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394 | struct drm_device *dev = node->minor->dev; |
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395 | struct radeon_device *rdev = dev->dev_private; |
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396 | uint32_t tmp; |
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397 | |||
398 | tmp = RREG32(R400_GB_PIPE_SELECT); |
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399 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
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400 | tmp = RREG32(R300_GB_TILE_CONFIG); |
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401 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
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402 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
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403 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
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404 | return 0; |
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405 | } |
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406 | |||
407 | static struct drm_info_list r420_pipes_info_list[] = { |
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408 | {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, |
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409 | }; |
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410 | #endif |
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411 | |||
412 | int r420_debugfs_pipes_info_init(struct radeon_device *rdev) |
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413 | { |
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414 | #if defined(CONFIG_DEBUG_FS) |
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415 | return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); |
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416 | #else |
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417 | return 0; |
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418 | #endif |
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419 | }><>><>><>><>><>><>><> |