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Rev | Author | Line No. | Line |
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1179 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #include |
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1963 | serge | 29 | #include |
2997 | Serge | 30 | #include |
1179 | serge | 31 | #include "radeon_reg.h" |
32 | #include "radeon.h" |
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1963 | serge | 33 | #include "radeon_asic.h" |
1179 | serge | 34 | #include "atom.h" |
1403 | serge | 35 | #include "r100d.h" |
1179 | serge | 36 | #include "r420d.h" |
1403 | serge | 37 | #include "r420_reg_safe.h" |
1179 | serge | 38 | |
1403 | serge | 39 | static void r420_set_reg_safe(struct radeon_device *rdev) |
40 | { |
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41 | rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; |
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42 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); |
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43 | } |
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44 | |||
1179 | serge | 45 | void r420_pipes_init(struct radeon_device *rdev) |
46 | { |
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47 | unsigned tmp; |
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48 | unsigned gb_pipe_select; |
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49 | unsigned num_pipes; |
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50 | |||
51 | /* GA_ENHANCE workaround TCL deadlock issue */ |
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1430 | serge | 52 | WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | |
53 | (1 << 2) | (1 << 3)); |
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1179 | serge | 54 | /* add idle wait as per freedesktop.org bug 24041 */ |
55 | if (r100_gui_wait_for_idle(rdev)) { |
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56 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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57 | "programming pipes. Bad things might happen.\n"); |
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58 | } |
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59 | /* get max number of pipes */ |
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1963 | serge | 60 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); |
1179 | serge | 61 | num_pipes = ((gb_pipe_select >> 12) & 3) + 1; |
1963 | serge | 62 | |
63 | /* SE chips have 1 pipe */ |
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64 | if ((rdev->pdev->device == 0x5e4c) || |
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65 | (rdev->pdev->device == 0x5e4f)) |
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66 | num_pipes = 1; |
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67 | |||
1179 | serge | 68 | rdev->num_gb_pipes = num_pipes; |
69 | tmp = 0; |
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70 | switch (num_pipes) { |
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71 | default: |
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72 | /* force to 1 pipe */ |
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73 | num_pipes = 1; |
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74 | case 1: |
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75 | tmp = (0 << 1); |
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76 | break; |
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77 | case 2: |
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78 | tmp = (3 << 1); |
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79 | break; |
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80 | case 3: |
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81 | tmp = (6 << 1); |
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82 | break; |
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83 | case 4: |
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84 | tmp = (7 << 1); |
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85 | break; |
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86 | } |
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1430 | serge | 87 | WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); |
1179 | serge | 88 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
1430 | serge | 89 | tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; |
90 | WREG32(R300_GB_TILE_CONFIG, tmp); |
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1179 | serge | 91 | if (r100_gui_wait_for_idle(rdev)) { |
92 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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93 | "programming pipes. Bad things might happen.\n"); |
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94 | } |
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95 | |||
1430 | serge | 96 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
97 | WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); |
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1179 | serge | 98 | |
99 | WREG32(R300_RB2D_DSTCACHE_MODE, |
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100 | RREG32(R300_RB2D_DSTCACHE_MODE) | |
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101 | R300_DC_AUTOFLUSH_ENABLE | |
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102 | R300_DC_DC_DISABLE_IGNORE_PE); |
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103 | |||
104 | if (r100_gui_wait_for_idle(rdev)) { |
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105 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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106 | "programming pipes. Bad things might happen.\n"); |
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107 | } |
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108 | |||
109 | if (rdev->family == CHIP_RV530) { |
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110 | tmp = RREG32(RV530_GB_PIPE_SELECT2); |
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111 | if ((tmp & 3) == 3) |
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112 | rdev->num_z_pipes = 2; |
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113 | else |
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114 | rdev->num_z_pipes = 1; |
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115 | } else |
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116 | rdev->num_z_pipes = 1; |
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117 | |||
118 | DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", |
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119 | rdev->num_gb_pipes, rdev->num_z_pipes); |
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120 | } |
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121 | |||
122 | u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) |
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123 | { |
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124 | u32 r; |
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125 | |||
126 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); |
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127 | r = RREG32(R_0001FC_MC_IND_DATA); |
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128 | return r; |
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129 | } |
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130 | |||
131 | void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
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132 | { |
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133 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | |
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134 | S_0001F8_MC_IND_WR_EN(1)); |
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135 | WREG32(R_0001FC_MC_IND_DATA, v); |
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136 | } |
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137 | |||
138 | static void r420_debugfs(struct radeon_device *rdev) |
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139 | { |
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140 | if (r100_debugfs_rbbm_init(rdev)) { |
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141 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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142 | } |
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143 | if (r420_debugfs_pipes_info_init(rdev)) { |
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144 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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145 | } |
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146 | } |
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147 | |||
148 | static void r420_clock_resume(struct radeon_device *rdev) |
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149 | { |
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150 | u32 sclk_cntl; |
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1221 | serge | 151 | |
152 | if (radeon_dynclks != -1 && radeon_dynclks) |
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153 | radeon_atom_set_clock_gating(rdev, 1); |
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1179 | serge | 154 | sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); |
155 | sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
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156 | if (rdev->family == CHIP_R420) |
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157 | sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); |
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158 | WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); |
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159 | } |
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160 | |||
1403 | serge | 161 | static void r420_cp_errata_init(struct radeon_device *rdev) |
162 | { |
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2997 | Serge | 163 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
164 | |||
1403 | serge | 165 | /* RV410 and R420 can lock up if CP DMA to host memory happens |
166 | * while the 2D engine is busy. |
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167 | * |
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168 | * The proper workaround is to queue a RESYNC at the beginning |
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169 | * of the CP init, apparently. |
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170 | */ |
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171 | radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); |
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2997 | Serge | 172 | radeon_ring_lock(rdev, ring, 8); |
173 | radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); |
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174 | radeon_ring_write(ring, rdev->config.r300.resync_scratch); |
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175 | radeon_ring_write(ring, 0xDEADBEEF); |
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176 | radeon_ring_unlock_commit(rdev, ring); |
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1403 | serge | 177 | } |
178 | |||
179 | static void r420_cp_errata_fini(struct radeon_device *rdev) |
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180 | { |
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2997 | Serge | 181 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
182 | |||
1403 | serge | 183 | /* Catch the RESYNC we dispatched all the way back, |
184 | * at the very beginning of the CP init. |
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185 | */ |
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2997 | Serge | 186 | radeon_ring_lock(rdev, ring, 8); |
187 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
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188 | radeon_ring_write(ring, R300_RB3D_DC_FINISH); |
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189 | radeon_ring_unlock_commit(rdev, ring); |
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1403 | serge | 190 | radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); |
191 | } |
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192 | |||
1179 | serge | 193 | static int r420_startup(struct radeon_device *rdev) |
194 | { |
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195 | int r; |
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196 | |||
1321 | serge | 197 | /* set common regs */ |
198 | r100_set_common_regs(rdev); |
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199 | /* program mc */ |
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1179 | serge | 200 | r300_mc_program(rdev); |
1221 | serge | 201 | /* Resume clock */ |
202 | r420_clock_resume(rdev); |
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1179 | serge | 203 | /* Initialize GART (initialize after TTM so we can allocate |
204 | * memory through TTM but finalize after TTM) */ |
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205 | if (rdev->flags & RADEON_IS_PCIE) { |
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206 | r = rv370_pcie_gart_enable(rdev); |
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207 | if (r) |
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208 | return r; |
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209 | } |
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210 | if (rdev->flags & RADEON_IS_PCI) { |
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211 | r = r100_pci_gart_enable(rdev); |
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212 | if (r) |
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213 | return r; |
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214 | } |
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215 | r420_pipes_init(rdev); |
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2005 | serge | 216 | |
217 | /* allocate wb buffer */ |
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218 | r = radeon_wb_init(rdev); |
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219 | if (r) |
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220 | return r; |
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221 | |||
1179 | serge | 222 | /* Enable IRQ */ |
2005 | serge | 223 | r100_irq_set(rdev); |
1403 | serge | 224 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1179 | serge | 225 | /* 1M ring buffer */ |
1412 | serge | 226 | r = r100_cp_init(rdev, 1024 * 1024); |
227 | if (r) { |
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1963 | serge | 228 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
1412 | serge | 229 | return r; |
230 | } |
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231 | r420_cp_errata_init(rdev); |
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2997 | Serge | 232 | |
233 | r = radeon_ib_pool_init(rdev); |
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2005 | serge | 234 | if (r) { |
2997 | Serge | 235 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
2005 | serge | 236 | return r; |
237 | } |
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2997 | Serge | 238 | |
1179 | serge | 239 | return 0; |
240 | } |
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241 | |||
242 | |||
243 | |||
244 | |||
2997 | Serge | 245 | |
246 | |||
1179 | serge | 247 | int r420_init(struct radeon_device *rdev) |
248 | { |
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249 | int r; |
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250 | |||
251 | /* Initialize scratch registers */ |
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252 | radeon_scratch_init(rdev); |
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253 | /* Initialize surface registers */ |
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254 | radeon_surface_init(rdev); |
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255 | /* TODO: disable VGA need to use VGA request */ |
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1963 | serge | 256 | /* restore some register to sane defaults */ |
257 | r100_restore_sanity(rdev); |
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1179 | serge | 258 | /* BIOS*/ |
259 | if (!radeon_get_bios(rdev)) { |
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260 | if (ASIC_IS_AVIVO(rdev)) |
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261 | return -EINVAL; |
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262 | } |
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263 | if (rdev->is_atom_bios) { |
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264 | r = radeon_atombios_init(rdev); |
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265 | if (r) { |
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266 | return r; |
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267 | } |
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268 | } else { |
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269 | r = radeon_combios_init(rdev); |
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270 | if (r) { |
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271 | return r; |
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272 | } |
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273 | } |
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274 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
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1963 | serge | 275 | if (radeon_asic_reset(rdev)) { |
1179 | serge | 276 | dev_warn(rdev->dev, |
277 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
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278 | RREG32(R_000E40_RBBM_STATUS), |
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279 | RREG32(R_0007C0_CP_STAT)); |
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280 | } |
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281 | /* check if cards are posted or not */ |
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1321 | serge | 282 | if (radeon_boot_test_post_card(rdev) == false) |
283 | return -EINVAL; |
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284 | |||
1179 | serge | 285 | /* Initialize clocks */ |
286 | radeon_get_clock_info(rdev->ddev); |
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1430 | serge | 287 | /* initialize AGP */ |
288 | if (rdev->flags & RADEON_IS_AGP) { |
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289 | r = radeon_agp_init(rdev); |
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1179 | serge | 290 | if (r) { |
1430 | serge | 291 | radeon_agp_disable(rdev); |
1179 | serge | 292 | } |
1430 | serge | 293 | } |
294 | /* initialize memory controller */ |
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295 | r300_mc_init(rdev); |
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1179 | serge | 296 | r420_debugfs(rdev); |
297 | /* Fence driver */ |
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2005 | serge | 298 | r = radeon_fence_driver_init(rdev); |
299 | if (r) { |
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300 | return r; |
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301 | } |
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302 | r = radeon_irq_kms_init(rdev); |
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303 | if (r) { |
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304 | return r; |
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305 | } |
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1179 | serge | 306 | /* Memory manager */ |
1321 | serge | 307 | r = radeon_bo_init(rdev); |
1179 | serge | 308 | if (r) { |
309 | return r; |
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310 | } |
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1321 | serge | 311 | if (rdev->family == CHIP_R420) |
312 | r100_enable_bm(rdev); |
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313 | |||
1179 | serge | 314 | if (rdev->flags & RADEON_IS_PCIE) { |
315 | r = rv370_pcie_gart_init(rdev); |
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316 | if (r) |
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317 | return r; |
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318 | } |
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319 | if (rdev->flags & RADEON_IS_PCI) { |
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320 | r = r100_pci_gart_init(rdev); |
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321 | if (r) |
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322 | return r; |
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323 | } |
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1404 | serge | 324 | r420_set_reg_safe(rdev); |
2997 | Serge | 325 | |
1179 | serge | 326 | rdev->accel_working = true; |
327 | r = r420_startup(rdev); |
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328 | if (r) { |
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329 | /* Somethings want wront with the accel init stop accel */ |
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330 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
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331 | if (rdev->flags & RADEON_IS_PCIE) |
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332 | rv370_pcie_gart_fini(rdev); |
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333 | if (rdev->flags & RADEON_IS_PCI) |
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334 | r100_pci_gart_fini(rdev); |
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335 | rdev->accel_working = false; |
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336 | } |
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337 | return 0; |
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338 | } |
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339 | |||
340 | /* |
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341 | * Debugfs info |
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342 | */ |
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343 | #if defined(CONFIG_DEBUG_FS) |
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344 | static int r420_debugfs_pipes_info(struct seq_file *m, void *data) |
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345 | { |
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346 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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347 | struct drm_device *dev = node->minor->dev; |
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348 | struct radeon_device *rdev = dev->dev_private; |
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349 | uint32_t tmp; |
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350 | |||
351 | tmp = RREG32(R400_GB_PIPE_SELECT); |
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352 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
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353 | tmp = RREG32(R300_GB_TILE_CONFIG); |
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354 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
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355 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
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356 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
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357 | return 0; |
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358 | } |
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359 | |||
360 | static struct drm_info_list r420_pipes_info_list[] = { |
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361 | {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, |
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362 | }; |
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363 | #endif |
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364 | |||
365 | int r420_debugfs_pipes_info_init(struct radeon_device *rdev) |
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366 | { |
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367 | #if defined(CONFIG_DEBUG_FS) |
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368 | return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); |
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369 | #else |
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370 | return 0; |
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371 | #endif |
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372 | }><>><>><>><>><>><>><> |