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Rev | Author | Line No. | Line |
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1179 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #include |
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29 | #include "drmP.h" |
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30 | #include "radeon_reg.h" |
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31 | #include "radeon.h" |
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32 | #include "atom.h" |
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1403 | serge | 33 | #include "r100d.h" |
1179 | serge | 34 | #include "r420d.h" |
1403 | serge | 35 | #include "r420_reg_safe.h" |
1179 | serge | 36 | |
1403 | serge | 37 | static void r420_set_reg_safe(struct radeon_device *rdev) |
38 | { |
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39 | rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; |
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40 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); |
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41 | } |
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42 | |||
1179 | serge | 43 | void r420_pipes_init(struct radeon_device *rdev) |
44 | { |
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45 | unsigned tmp; |
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46 | unsigned gb_pipe_select; |
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47 | unsigned num_pipes; |
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48 | |||
49 | /* GA_ENHANCE workaround TCL deadlock issue */ |
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1430 | serge | 50 | WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | |
51 | (1 << 2) | (1 << 3)); |
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1179 | serge | 52 | /* add idle wait as per freedesktop.org bug 24041 */ |
53 | if (r100_gui_wait_for_idle(rdev)) { |
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54 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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55 | "programming pipes. Bad things might happen.\n"); |
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56 | } |
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57 | /* get max number of pipes */ |
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58 | gb_pipe_select = RREG32(0x402C); |
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59 | num_pipes = ((gb_pipe_select >> 12) & 3) + 1; |
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60 | rdev->num_gb_pipes = num_pipes; |
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61 | tmp = 0; |
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62 | switch (num_pipes) { |
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63 | default: |
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64 | /* force to 1 pipe */ |
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65 | num_pipes = 1; |
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66 | case 1: |
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67 | tmp = (0 << 1); |
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68 | break; |
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69 | case 2: |
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70 | tmp = (3 << 1); |
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71 | break; |
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72 | case 3: |
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73 | tmp = (6 << 1); |
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74 | break; |
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75 | case 4: |
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76 | tmp = (7 << 1); |
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77 | break; |
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78 | } |
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1430 | serge | 79 | WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); |
1179 | serge | 80 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
1430 | serge | 81 | tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; |
82 | WREG32(R300_GB_TILE_CONFIG, tmp); |
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1179 | serge | 83 | if (r100_gui_wait_for_idle(rdev)) { |
84 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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85 | "programming pipes. Bad things might happen.\n"); |
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86 | } |
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87 | |||
1430 | serge | 88 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
89 | WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); |
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1179 | serge | 90 | |
91 | WREG32(R300_RB2D_DSTCACHE_MODE, |
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92 | RREG32(R300_RB2D_DSTCACHE_MODE) | |
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93 | R300_DC_AUTOFLUSH_ENABLE | |
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94 | R300_DC_DC_DISABLE_IGNORE_PE); |
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95 | |||
96 | if (r100_gui_wait_for_idle(rdev)) { |
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97 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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98 | "programming pipes. Bad things might happen.\n"); |
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99 | } |
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100 | |||
101 | if (rdev->family == CHIP_RV530) { |
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102 | tmp = RREG32(RV530_GB_PIPE_SELECT2); |
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103 | if ((tmp & 3) == 3) |
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104 | rdev->num_z_pipes = 2; |
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105 | else |
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106 | rdev->num_z_pipes = 1; |
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107 | } else |
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108 | rdev->num_z_pipes = 1; |
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109 | |||
110 | DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", |
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111 | rdev->num_gb_pipes, rdev->num_z_pipes); |
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112 | } |
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113 | |||
114 | u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) |
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115 | { |
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116 | u32 r; |
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117 | |||
118 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); |
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119 | r = RREG32(R_0001FC_MC_IND_DATA); |
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120 | return r; |
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121 | } |
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122 | |||
123 | void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
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124 | { |
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125 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | |
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126 | S_0001F8_MC_IND_WR_EN(1)); |
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127 | WREG32(R_0001FC_MC_IND_DATA, v); |
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128 | } |
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129 | |||
130 | static void r420_debugfs(struct radeon_device *rdev) |
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131 | { |
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132 | if (r100_debugfs_rbbm_init(rdev)) { |
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133 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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134 | } |
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135 | if (r420_debugfs_pipes_info_init(rdev)) { |
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136 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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137 | } |
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138 | } |
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139 | |||
140 | static void r420_clock_resume(struct radeon_device *rdev) |
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141 | { |
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142 | u32 sclk_cntl; |
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1221 | serge | 143 | |
144 | if (radeon_dynclks != -1 && radeon_dynclks) |
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145 | radeon_atom_set_clock_gating(rdev, 1); |
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1179 | serge | 146 | sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); |
147 | sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
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148 | if (rdev->family == CHIP_R420) |
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149 | sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); |
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150 | WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); |
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151 | } |
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152 | |||
1403 | serge | 153 | static void r420_cp_errata_init(struct radeon_device *rdev) |
154 | { |
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155 | /* RV410 and R420 can lock up if CP DMA to host memory happens |
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156 | * while the 2D engine is busy. |
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157 | * |
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158 | * The proper workaround is to queue a RESYNC at the beginning |
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159 | * of the CP init, apparently. |
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160 | */ |
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161 | radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); |
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162 | radeon_ring_lock(rdev, 8); |
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163 | radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1)); |
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164 | radeon_ring_write(rdev, rdev->config.r300.resync_scratch); |
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165 | radeon_ring_write(rdev, 0xDEADBEEF); |
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166 | radeon_ring_unlock_commit(rdev); |
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167 | } |
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168 | |||
169 | static void r420_cp_errata_fini(struct radeon_device *rdev) |
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170 | { |
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171 | /* Catch the RESYNC we dispatched all the way back, |
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172 | * at the very beginning of the CP init. |
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173 | */ |
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174 | radeon_ring_lock(rdev, 8); |
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175 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
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176 | radeon_ring_write(rdev, R300_RB3D_DC_FINISH); |
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177 | radeon_ring_unlock_commit(rdev); |
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178 | radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); |
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179 | } |
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180 | |||
1179 | serge | 181 | static int r420_startup(struct radeon_device *rdev) |
182 | { |
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183 | int r; |
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184 | |||
1321 | serge | 185 | /* set common regs */ |
186 | r100_set_common_regs(rdev); |
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187 | /* program mc */ |
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1179 | serge | 188 | r300_mc_program(rdev); |
1221 | serge | 189 | /* Resume clock */ |
190 | r420_clock_resume(rdev); |
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1179 | serge | 191 | /* Initialize GART (initialize after TTM so we can allocate |
192 | * memory through TTM but finalize after TTM) */ |
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193 | if (rdev->flags & RADEON_IS_PCIE) { |
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194 | r = rv370_pcie_gart_enable(rdev); |
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195 | if (r) |
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196 | return r; |
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197 | } |
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198 | if (rdev->flags & RADEON_IS_PCI) { |
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199 | r = r100_pci_gart_enable(rdev); |
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200 | if (r) |
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201 | return r; |
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202 | } |
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203 | r420_pipes_init(rdev); |
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204 | /* Enable IRQ */ |
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205 | // r100_irq_set(rdev); |
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1403 | serge | 206 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1179 | serge | 207 | /* 1M ring buffer */ |
1412 | serge | 208 | r = r100_cp_init(rdev, 1024 * 1024); |
209 | if (r) { |
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210 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
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211 | return r; |
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212 | } |
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213 | r420_cp_errata_init(rdev); |
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1179 | serge | 214 | // r = r100_wb_init(rdev); |
215 | // if (r) { |
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216 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
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217 | // } |
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218 | // r = r100_ib_init(rdev); |
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219 | // if (r) { |
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220 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
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221 | // return r; |
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222 | // } |
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223 | return 0; |
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224 | } |
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225 | |||
226 | int r420_resume(struct radeon_device *rdev) |
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227 | { |
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228 | /* Make sur GART are not working */ |
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229 | if (rdev->flags & RADEON_IS_PCIE) |
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230 | rv370_pcie_gart_disable(rdev); |
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231 | if (rdev->flags & RADEON_IS_PCI) |
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232 | r100_pci_gart_disable(rdev); |
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233 | /* Resume clock before doing reset */ |
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234 | r420_clock_resume(rdev); |
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235 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
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236 | if (radeon_gpu_reset(rdev)) { |
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237 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
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238 | RREG32(R_000E40_RBBM_STATUS), |
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239 | RREG32(R_0007C0_CP_STAT)); |
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240 | } |
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241 | /* check if cards are posted or not */ |
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242 | if (rdev->is_atom_bios) { |
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243 | atom_asic_init(rdev->mode_info.atom_context); |
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244 | } else { |
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245 | radeon_combios_asic_init(rdev->ddev); |
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246 | } |
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247 | /* Resume clock after posting */ |
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248 | r420_clock_resume(rdev); |
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1321 | serge | 249 | /* Initialize surface registers */ |
250 | radeon_surface_init(rdev); |
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1179 | serge | 251 | return r420_startup(rdev); |
252 | } |
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253 | |||
254 | |||
255 | |||
256 | int r420_init(struct radeon_device *rdev) |
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257 | { |
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258 | int r; |
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259 | |||
260 | /* Initialize scratch registers */ |
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261 | radeon_scratch_init(rdev); |
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262 | /* Initialize surface registers */ |
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263 | radeon_surface_init(rdev); |
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264 | /* TODO: disable VGA need to use VGA request */ |
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265 | /* BIOS*/ |
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266 | if (!radeon_get_bios(rdev)) { |
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267 | if (ASIC_IS_AVIVO(rdev)) |
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268 | return -EINVAL; |
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269 | } |
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270 | if (rdev->is_atom_bios) { |
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271 | r = radeon_atombios_init(rdev); |
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272 | if (r) { |
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273 | return r; |
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274 | } |
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275 | } else { |
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276 | r = radeon_combios_init(rdev); |
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277 | if (r) { |
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278 | return r; |
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279 | } |
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280 | } |
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281 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
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282 | if (radeon_gpu_reset(rdev)) { |
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283 | dev_warn(rdev->dev, |
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284 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
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285 | RREG32(R_000E40_RBBM_STATUS), |
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286 | RREG32(R_0007C0_CP_STAT)); |
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287 | } |
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288 | /* check if cards are posted or not */ |
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1321 | serge | 289 | if (radeon_boot_test_post_card(rdev) == false) |
290 | return -EINVAL; |
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291 | |||
1179 | serge | 292 | /* Initialize clocks */ |
293 | radeon_get_clock_info(rdev->ddev); |
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1268 | serge | 294 | /* Initialize power management */ |
295 | radeon_pm_init(rdev); |
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1430 | serge | 296 | /* initialize AGP */ |
297 | if (rdev->flags & RADEON_IS_AGP) { |
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298 | r = radeon_agp_init(rdev); |
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1179 | serge | 299 | if (r) { |
1430 | serge | 300 | radeon_agp_disable(rdev); |
1179 | serge | 301 | } |
1430 | serge | 302 | } |
303 | /* initialize memory controller */ |
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304 | r300_mc_init(rdev); |
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1179 | serge | 305 | r420_debugfs(rdev); |
306 | /* Fence driver */ |
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307 | // r = radeon_fence_driver_init(rdev); |
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308 | // if (r) { |
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309 | // return r; |
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310 | // } |
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311 | // r = radeon_irq_kms_init(rdev); |
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312 | // if (r) { |
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313 | // return r; |
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314 | // } |
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315 | /* Memory manager */ |
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1321 | serge | 316 | r = radeon_bo_init(rdev); |
1179 | serge | 317 | if (r) { |
318 | return r; |
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319 | } |
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1321 | serge | 320 | if (rdev->family == CHIP_R420) |
321 | r100_enable_bm(rdev); |
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322 | |||
1179 | serge | 323 | if (rdev->flags & RADEON_IS_PCIE) { |
324 | r = rv370_pcie_gart_init(rdev); |
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325 | if (r) |
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326 | return r; |
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327 | } |
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328 | if (rdev->flags & RADEON_IS_PCI) { |
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329 | r = r100_pci_gart_init(rdev); |
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330 | if (r) |
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331 | return r; |
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332 | } |
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1404 | serge | 333 | r420_set_reg_safe(rdev); |
1179 | serge | 334 | rdev->accel_working = true; |
335 | r = r420_startup(rdev); |
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336 | if (r) { |
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337 | /* Somethings want wront with the accel init stop accel */ |
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338 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
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339 | // r100_cp_fini(rdev); |
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340 | // r100_wb_fini(rdev); |
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341 | // r100_ib_fini(rdev); |
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342 | if (rdev->flags & RADEON_IS_PCIE) |
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343 | rv370_pcie_gart_fini(rdev); |
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344 | if (rdev->flags & RADEON_IS_PCI) |
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345 | r100_pci_gart_fini(rdev); |
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346 | // radeon_agp_fini(rdev); |
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347 | rdev->accel_working = false; |
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348 | } |
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349 | return 0; |
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350 | } |
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351 | |||
352 | /* |
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353 | * Debugfs info |
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354 | */ |
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355 | #if defined(CONFIG_DEBUG_FS) |
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356 | static int r420_debugfs_pipes_info(struct seq_file *m, void *data) |
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357 | { |
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358 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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359 | struct drm_device *dev = node->minor->dev; |
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360 | struct radeon_device *rdev = dev->dev_private; |
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361 | uint32_t tmp; |
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362 | |||
363 | tmp = RREG32(R400_GB_PIPE_SELECT); |
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364 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
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365 | tmp = RREG32(R300_GB_TILE_CONFIG); |
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366 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
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367 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
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368 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
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369 | return 0; |
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370 | } |
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371 | |||
372 | static struct drm_info_list r420_pipes_info_list[] = { |
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373 | {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, |
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374 | }; |
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375 | #endif |
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376 | |||
377 | int r420_debugfs_pipes_info_init(struct radeon_device *rdev) |
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378 | { |
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379 | #if defined(CONFIG_DEBUG_FS) |
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380 | return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); |
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381 | #else |
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382 | return 0; |
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383 | #endif |
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384 | }><>><>><>><>><>><>><> |