WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r300.c

Rev	Author	Line No.	Line
1120	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1179	serge	28	#include
1963	serge	29	#include
		30	#include
		31	#include
		32	#include
1120	serge	33	#include "radeon_reg.h"
		34	#include "radeon.h"
1963	serge	35	#include "radeon_asic.h"
2997	Serge	36	#include
5078	serge	37	#include "r100_track.h"
1179	serge	38	#include "r300d.h"
1221	serge	39	#include "rv350d.h"
1179	serge	40	#include "r300_reg_safe.h"
		41
1403	serge	42	/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
		43	*
		44	* GPU Errata:
		45	* - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
		46	* using MMIO to flush host path read cache, this lead to HARDLOCKUP.
		47	* However, scheduling such write to the ring seems harmless, i suspect
		48	* the CP read collide with the flush somehow, or maybe the MC, hard to
		49	* tell. (Jerome Glisse)
		50	*/
1120	serge	51
		52	/*
6104	serge	53	* Indirect registers accessor
		54	*/
		55	uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
		56	{
		57	unsigned long flags;
		58	uint32_t r;
		59
		60	spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
		61	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
		62	r = RREG32(RADEON_PCIE_DATA);
		63	spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
		64	return r;
		65	}
		66
		67	void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		68	{
		69	unsigned long flags;
		70
		71	spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
		72	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
		73	WREG32(RADEON_PCIE_DATA, (v));
		74	spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
		75	}
		76
		77	/*
1120	serge	78	* rv370,rv380 PCIE GART
		79	*/
1221	serge	80	static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
		81
1120	serge	82	void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
		83	{
		84	uint32_t tmp;
		85	int i;
		86
		87	/* Workaround HW bug do flush 2 times */
		88	for (i = 0; i < 2; i++) {
		89	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		90	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp \| RADEON_PCIE_TX_GART_INVALIDATE_TLB);
		91	(void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		92	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
1179	serge	93	}
6104	serge	94	mb();
1179	serge	95	}
		96
5078	serge	97	#define R300_PTE_UNSNOOPED (1 << 0)
1963	serge	98	#define R300_PTE_WRITEABLE (1 << 2)
		99	#define R300_PTE_READABLE (1 << 3)
		100
6104	serge	101	uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags)
1179	serge	102	{
		103	addr = (lower_32_bits(addr) >> 8) \|
5078	serge	104	((upper_32_bits(addr) & 0xff) << 24);
		105	if (flags & RADEON_GART_PAGE_READ)
		106	addr \|= R300_PTE_READABLE;
		107	if (flags & RADEON_GART_PAGE_WRITE)
		108	addr \|= R300_PTE_WRITEABLE;
		109	if (!(flags & RADEON_GART_PAGE_SNOOP))
		110	addr \|= R300_PTE_UNSNOOPED;
6104	serge	111	return addr;
		112	}
		113
		114	void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
		115	uint64_t entry)
		116	{
		117	void __iomem *ptr = rdev->gart.ptr;
		118
1179	serge	119	/* on x86 we want this to be CPU endian, on powerpc
		120	* on powerpc without HW swappers, it'll get swapped on way
		121	* into VRAM - so no need for cpu_to_le32 on VRAM tables */
6104	serge	122	writel(entry, ((void __iomem )ptr) + (i 4));
1120	serge	123	}
		124
1179	serge	125	int rv370_pcie_gart_init(struct radeon_device *rdev)
1120	serge	126	{
		127	int r;
		128
2997	Serge	129	if (rdev->gart.robj) {
1963	serge	130	WARN(1, "RV370 PCIE GART already initialized\n");
1179	serge	131	return 0;
		132	}
1120	serge	133	/* Initialize common gart structure */
		134	r = radeon_gart_init(rdev);
1179	serge	135	if (r)
1120	serge	136	return r;
1129	serge	137	r = rv370_debugfs_pcie_gart_info_init(rdev);
1179	serge	138	if (r)
1129	serge	139	DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
1179	serge	140	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
2997	Serge	141	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
6104	serge	142	rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
2997	Serge	143	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
1179	serge	144	return radeon_gart_table_vram_alloc(rdev);
		145	}
		146
		147	int rv370_pcie_gart_enable(struct radeon_device *rdev)
		148	{
		149	uint32_t table_addr;
		150	uint32_t tmp;
		151	int r;
		152
2997	Serge	153	if (rdev->gart.robj == NULL) {
1179	serge	154	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
		155	return -EINVAL;
1129	serge	156	}
1179	serge	157	r = radeon_gart_table_vram_pin(rdev);
		158	if (r)
1120	serge	159	return r;
		160	/* discard memory request outside of configured range */
		161	tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		162	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
1430	serge	163	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
		164	tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
1120	serge	165	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
		166	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
		167	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
		168	table_addr = rdev->gart.table_addr;
		169	WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
		170	/* FIXME: setup default page */
1430	serge	171	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
1120	serge	172	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
		173	/* Clear error */
1963	serge	174	WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
1120	serge	175	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		176	tmp \|= RADEON_PCIE_TX_GART_EN;
		177	tmp \|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		178	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
		179	rv370_pcie_gart_tlb_flush(rdev);
2997	Serge	180	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
		181	(unsigned)(rdev->mc.gtt_size >> 20),
		182	(unsigned long long)table_addr);
1120	serge	183	rdev->gart.ready = true;
		184	return 0;
		185	}
		186
		187	void rv370_pcie_gart_disable(struct radeon_device *rdev)
		188	{
1321	serge	189	u32 tmp;
1120	serge	190
1963	serge	191	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
		192	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
		193	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
		194	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
1120	serge	195	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		196	tmp \|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		197	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
2997	Serge	198	radeon_gart_table_vram_unpin(rdev);
1120	serge	199	}
		200
1179	serge	201	void rv370_pcie_gart_fini(struct radeon_device *rdev)
1120	serge	202	{
1963	serge	203	radeon_gart_fini(rdev);
6104	serge	204	rv370_pcie_gart_disable(rdev);
1179	serge	205	radeon_gart_table_vram_free(rdev);
1120	serge	206	}
		207
		208	void r300_fence_ring_emit(struct radeon_device *rdev,
		209	struct radeon_fence *fence)
		210	{
2997	Serge	211	struct radeon_ring *ring = &rdev->ring[fence->ring];
		212
1120	serge	213	/* Who ever call radeon_fence_emit should call ring_lock and ask
		214	* for enough space (today caller are ib schedule and buffer move) */
		215	/* Write SC register so SC & US assert idle */
2997	Serge	216	radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
		217	radeon_ring_write(ring, 0);
		218	radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
		219	radeon_ring_write(ring, 0);
1120	serge	220	/* Flush 3D cache */
2997	Serge	221	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
		222	radeon_ring_write(ring, R300_RB3D_DC_FLUSH);
		223	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
		224	radeon_ring_write(ring, R300_ZC_FLUSH);
1120	serge	225	/* Wait until IDLE & CLEAN */
2997	Serge	226	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
		227	radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN \|
1430	serge	228	RADEON_WAIT_2D_IDLECLEAN \|
		229	RADEON_WAIT_DMA_GUI_IDLE));
2997	Serge	230	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		231	radeon_ring_write(ring, rdev->config.r300.hdp_cntl \|
1403	serge	232	RADEON_HDP_READ_BUFFER_INVALIDATE);
2997	Serge	233	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		234	radeon_ring_write(ring, rdev->config.r300.hdp_cntl);
1120	serge	235	/* Emit fence sequence & fire IRQ */
2997	Serge	236	radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
		237	radeon_ring_write(ring, fence->seq);
		238	radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
		239	radeon_ring_write(ring, RADEON_SW_INT_FIRE);
1120	serge	240	}
		241
2997	Serge	242	void r300_ring_start(struct radeon_device rdev, struct radeon_ring ring)
1120	serge	243	{
		244	unsigned gb_tile_config;
		245	int r;
		246
		247	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
		248	gb_tile_config = (R300_ENABLE_TILING \| R300_TILE_SIZE_16);
		249	switch(rdev->num_gb_pipes) {
		250	case 2:
		251	gb_tile_config \|= R300_PIPE_COUNT_R300;
		252	break;
		253	case 3:
		254	gb_tile_config \|= R300_PIPE_COUNT_R420_3P;
		255	break;
		256	case 4:
		257	gb_tile_config \|= R300_PIPE_COUNT_R420;
		258	break;
		259	case 1:
		260	default:
		261	gb_tile_config \|= R300_PIPE_COUNT_RV350;
		262	break;
		263	}
		264
2997	Serge	265	r = radeon_ring_lock(rdev, ring, 64);
1120	serge	266	if (r) {
		267	return;
		268	}
2997	Serge	269	radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
		270	radeon_ring_write(ring,
1120	serge	271	RADEON_ISYNC_ANY2D_IDLE3D \|
		272	RADEON_ISYNC_ANY3D_IDLE2D \|
		273	RADEON_ISYNC_WAIT_IDLEGUI \|
		274	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
2997	Serge	275	radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));
		276	radeon_ring_write(ring, gb_tile_config);
		277	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
		278	radeon_ring_write(ring,
1120	serge	279	RADEON_WAIT_2D_IDLECLEAN \|
		280	RADEON_WAIT_3D_IDLECLEAN);
2997	Serge	281	radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
		282	radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
		283	radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));
		284	radeon_ring_write(ring, 0);
		285	radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));
		286	radeon_ring_write(ring, 0);
		287	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
		288	radeon_ring_write(ring, R300_RB3D_DC_FLUSH \| R300_RB3D_DC_FREE);
		289	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
		290	radeon_ring_write(ring, R300_ZC_FLUSH \| R300_ZC_FREE);
		291	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
		292	radeon_ring_write(ring,
1120	serge	293	RADEON_WAIT_2D_IDLECLEAN \|
		294	RADEON_WAIT_3D_IDLECLEAN);
2997	Serge	295	radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));
		296	radeon_ring_write(ring, 0);
		297	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
		298	radeon_ring_write(ring, R300_RB3D_DC_FLUSH \| R300_RB3D_DC_FREE);
		299	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
		300	radeon_ring_write(ring, R300_ZC_FLUSH \| R300_ZC_FREE);
		301	radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));
		302	radeon_ring_write(ring,
1120	serge	303	((6 << R300_MS_X0_SHIFT) \|
		304	(6 << R300_MS_Y0_SHIFT) \|
		305	(6 << R300_MS_X1_SHIFT) \|
		306	(6 << R300_MS_Y1_SHIFT) \|
		307	(6 << R300_MS_X2_SHIFT) \|
		308	(6 << R300_MS_Y2_SHIFT) \|
		309	(6 << R300_MSBD0_Y_SHIFT) \|
		310	(6 << R300_MSBD0_X_SHIFT)));
2997	Serge	311	radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));
		312	radeon_ring_write(ring,
1120	serge	313	((6 << R300_MS_X3_SHIFT) \|
		314	(6 << R300_MS_Y3_SHIFT) \|
		315	(6 << R300_MS_X4_SHIFT) \|
		316	(6 << R300_MS_Y4_SHIFT) \|
		317	(6 << R300_MS_X5_SHIFT) \|
		318	(6 << R300_MS_Y5_SHIFT) \|
		319	(6 << R300_MSBD1_SHIFT)));
2997	Serge	320	radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));
		321	radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL \| R300_GA_FASTSYNC_CNTL);
		322	radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));
		323	radeon_ring_write(ring,
1120	serge	324	R300_FRONT_PTYPE_TRIANGE \| R300_BACK_PTYPE_TRIANGE);
2997	Serge	325	radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));
		326	radeon_ring_write(ring,
1120	serge	327	R300_GEOMETRY_ROUND_NEAREST \|
		328	R300_COLOR_ROUND_NEAREST);
5078	serge	329	radeon_ring_unlock_commit(rdev, ring, false);
1120	serge	330	}
		331
2997	Serge	332	static void r300_errata(struct radeon_device *rdev)
1120	serge	333	{
		334	rdev->pll_errata = 0;
		335
		336	if (rdev->family == CHIP_R300 &&
		337	(RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
		338	rdev->pll_errata \|= CHIP_ERRATA_R300_CG;
		339	}
		340	}
		341
		342	int r300_mc_wait_for_idle(struct radeon_device *rdev)
		343	{
		344	unsigned i;
		345	uint32_t tmp;
		346
		347	for (i = 0; i < rdev->usec_timeout; i++) {
		348	/* read MC_STATUS */
1430	serge	349	tmp = RREG32(RADEON_MC_STATUS);
		350	if (tmp & R300_MC_IDLE) {
1120	serge	351	return 0;
		352	}
		353	DRM_UDELAY(1);
		354	}
		355	return -1;
		356	}
		357
2997	Serge	358	static void r300_gpu_init(struct radeon_device *rdev)
1120	serge	359	{
		360	uint32_t gb_tile_config, tmp;
		361
1963	serge	362	if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) \|\|
		363	(rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
1120	serge	364	/* r300,r350 */
		365	rdev->num_gb_pipes = 2;
		366	} else {
1963	serge	367	/* rv350,rv370,rv380,r300 AD, r350 AH */
1120	serge	368	rdev->num_gb_pipes = 1;
		369	}
1179	serge	370	rdev->num_z_pipes = 1;
1120	serge	371	gb_tile_config = (R300_ENABLE_TILING \| R300_TILE_SIZE_16);
		372	switch (rdev->num_gb_pipes) {
		373	case 2:
		374	gb_tile_config \|= R300_PIPE_COUNT_R300;
		375	break;
		376	case 3:
		377	gb_tile_config \|= R300_PIPE_COUNT_R420_3P;
		378	break;
		379	case 4:
		380	gb_tile_config \|= R300_PIPE_COUNT_R420;
		381	break;
		382	default:
		383	case 1:
		384	gb_tile_config \|= R300_PIPE_COUNT_RV350;
		385	break;
		386	}
		387	WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
		388
		389	if (r100_gui_wait_for_idle(rdev)) {
		390	printk(KERN_WARNING "Failed to wait GUI idle while "
		391	"programming pipes. Bad things might happen.\n");
		392	}
		393
1430	serge	394	tmp = RREG32(R300_DST_PIPE_CONFIG);
		395	WREG32(R300_DST_PIPE_CONFIG, tmp \| R300_PIPE_AUTO_CONFIG);
1120	serge	396
		397	WREG32(R300_RB2D_DSTCACHE_MODE,
		398	R300_DC_AUTOFLUSH_ENABLE \|
		399	R300_DC_DC_DISABLE_IGNORE_PE);
		400
		401	if (r100_gui_wait_for_idle(rdev)) {
		402	printk(KERN_WARNING "Failed to wait GUI idle while "
		403	"programming pipes. Bad things might happen.\n");
		404	}
		405	if (r300_mc_wait_for_idle(rdev)) {
		406	printk(KERN_WARNING "Failed to wait MC idle while "
		407	"programming pipes. Bad things might happen.\n");
		408	}
1179	serge	409	DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
		410	rdev->num_gb_pipes, rdev->num_z_pipes);
1120	serge	411	}
		412
1963	serge	413	int r300_asic_reset(struct radeon_device *rdev)
1120	serge	414	{
1963	serge	415	struct r100_mc_save save;
		416	u32 status, tmp;
		417	int ret = 0;
1120	serge	418
1963	serge	419	status = RREG32(R_000E40_RBBM_STATUS);
		420	if (!G_000E40_GUI_ACTIVE(status)) {
		421	return 0;
1120	serge	422	}
1963	serge	423	r100_mc_stop(rdev, &save);
		424	status = RREG32(R_000E40_RBBM_STATUS);
		425	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		426	/* stop CP */
		427	WREG32(RADEON_CP_CSQ_CNTL, 0);
		428	tmp = RREG32(RADEON_CP_RB_CNTL);
		429	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);
		430	WREG32(RADEON_CP_RB_RPTR_WR, 0);
		431	WREG32(RADEON_CP_RB_WPTR, 0);
		432	WREG32(RADEON_CP_RB_CNTL, tmp);
		433	/* save PCI state */
		434	// pci_save_state(rdev->pdev);
		435	/* disable bus mastering */
		436	r100_bm_disable(rdev);
		437	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) \|
		438	S_0000F0_SOFT_RESET_GA(1));
		439	RREG32(R_0000F0_RBBM_SOFT_RESET);
		440	mdelay(500);
		441	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		442	mdelay(1);
		443	status = RREG32(R_000E40_RBBM_STATUS);
		444	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		445	/* resetting the CP seems to be problematic sometimes it end up
		446	* hard locking the computer, but it's necessary for successful
		447	* reset more test & playing is needed on R3XX/R4XX to find a
		448	* reliable (if any solution)
		449	*/
		450	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
		451	RREG32(R_0000F0_RBBM_SOFT_RESET);
		452	mdelay(500);
		453	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		454	mdelay(1);
		455	status = RREG32(R_000E40_RBBM_STATUS);
		456	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		457	/* restore PCI & busmastering */
		458	// pci_restore_state(rdev->pdev);
		459	r100_enable_bm(rdev);
1120	serge	460	/* Check if GPU is idle */
1963	serge	461	if (G_000E40_GA_BUSY(status) \|\| G_000E40_VAP_BUSY(status)) {
		462	dev_err(rdev->dev, "failed to reset GPU\n");
		463	ret = -1;
		464	} else
		465	dev_info(rdev->dev, "GPU reset succeed\n");
		466	r100_mc_resume(rdev, &save);
		467	return ret;
1120	serge	468	}
		469
		470	/*
		471	* r300,r350,rv350,rv380 VRAM info
		472	*/
1430	serge	473	void r300_mc_init(struct radeon_device *rdev)
1120	serge	474	{
1430	serge	475	u64 base;
		476	u32 tmp;
1120	serge	477
		478	/* DDR for all card after R300 & IGP */
		479	rdev->mc.vram_is_ddr = true;
		480	tmp = RREG32(RADEON_MEM_CNTL);
1404	serge	481	tmp &= R300_MEM_NUM_CHANNELS_MASK;
		482	switch (tmp) {
		483	case 0: rdev->mc.vram_width = 64; break;
		484	case 1: rdev->mc.vram_width = 128; break;
		485	case 2: rdev->mc.vram_width = 256; break;
		486	default: rdev->mc.vram_width = 128; break;
1120	serge	487	}
1179	serge	488	r100_vram_init_sizes(rdev);
1430	serge	489	base = rdev->mc.aper_base;
		490	if (rdev->flags & RADEON_IS_IGP)
		491	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
		492	radeon_vram_location(rdev, &rdev->mc, base);
1963	serge	493	rdev->mc.gtt_base_align = 0;
1430	serge	494	if (!(rdev->flags & RADEON_IS_AGP))
		495	radeon_gtt_location(rdev, &rdev->mc);
1963	serge	496	radeon_update_bandwidth_info(rdev);
1120	serge	497	}
		498
		499	void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
		500	{
		501	uint32_t link_width_cntl, mask;
		502
		503	if (rdev->flags & RADEON_IS_IGP)
		504	return;
		505
		506	if (!(rdev->flags & RADEON_IS_PCIE))
		507	return;
		508
		509	/* FIXME wait for idle */
		510
		511	switch (lanes) {
		512	case 0:
		513	mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
		514	break;
		515	case 1:
		516	mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
		517	break;
		518	case 2:
		519	mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
		520	break;
		521	case 4:
		522	mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
		523	break;
		524	case 8:
		525	mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
		526	break;
		527	case 12:
		528	mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
		529	break;
		530	case 16:
		531	default:
		532	mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
		533	break;
		534	}
		535
		536	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		537
		538	if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
		539	(mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
		540	return;
		541
		542	link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK \|
		543	RADEON_PCIE_LC_RECONFIG_NOW \|
		544	RADEON_PCIE_LC_RECONFIG_LATER \|
		545	RADEON_PCIE_LC_SHORT_RECONFIG_EN);
		546	link_width_cntl \|= mask;
		547	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
		548	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl \|
		549	RADEON_PCIE_LC_RECONFIG_NOW));
		550
		551	/* wait for lane set to complete */
		552	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		553	while (link_width_cntl == 0xffffffff)
		554	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		555
		556	}
		557
1430	serge	558	int rv370_get_pcie_lanes(struct radeon_device *rdev)
		559	{
		560	u32 link_width_cntl;
		561
		562	if (rdev->flags & RADEON_IS_IGP)
		563	return 0;
		564
		565	if (!(rdev->flags & RADEON_IS_PCIE))
		566	return 0;
		567
		568	/* FIXME wait for idle */
		569
6104	serge	570	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
1430	serge	571
		572	switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
		573	case RADEON_PCIE_LC_LINK_WIDTH_X0:
		574	return 0;
		575	case RADEON_PCIE_LC_LINK_WIDTH_X1:
		576	return 1;
		577	case RADEON_PCIE_LC_LINK_WIDTH_X2:
		578	return 2;
		579	case RADEON_PCIE_LC_LINK_WIDTH_X4:
		580	return 4;
		581	case RADEON_PCIE_LC_LINK_WIDTH_X8:
		582	return 8;
		583	case RADEON_PCIE_LC_LINK_WIDTH_X16:
		584	default:
		585	return 16;
		586	}
		587	}
		588
1120	serge	589	#if defined(CONFIG_DEBUG_FS)
		590	static int rv370_debugfs_pcie_gart_info(struct seq_file m, void data)
		591	{
		592	struct drm_info_node node = (struct drm_info_node ) m->private;
		593	struct drm_device *dev = node->minor->dev;
		594	struct radeon_device *rdev = dev->dev_private;
		595	uint32_t tmp;
		596
		597	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		598	seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
		599	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
		600	seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
		601	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
		602	seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
		603	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
		604	seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
		605	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
		606	seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
		607	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
		608	seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
		609	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
		610	seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
		611	return 0;
		612	}
		613
		614	static struct drm_info_list rv370_pcie_gart_info_list[] = {
		615	{"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
		616	};
		617	#endif
		618
1221	serge	619	static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
1120	serge	620	{
		621	#if defined(CONFIG_DEBUG_FS)
		622	return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
		623	#else
		624	return 0;
		625	#endif
		626	}
		627
		628	static int r300_packet0_check(struct radeon_cs_parser *p,
		629	struct radeon_cs_packet *pkt,
		630	unsigned idx, unsigned reg)
		631	{
5271	serge	632	struct radeon_bo_list *reloc;
1179	serge	633	struct r100_cs_track *track;
1120	serge	634	volatile uint32_t *ib;
1179	serge	635	uint32_t tmp, tile_flags = 0;
1120	serge	636	unsigned i;
		637	int r;
1221	serge	638	u32 idx_value;
1120	serge	639
2997	Serge	640	ib = p->ib.ptr;
1179	serge	641	track = (struct r100_cs_track *)p->track;
1221	serge	642	idx_value = radeon_get_ib_value(p, idx);
		643
1120	serge	644	switch(reg) {
1179	serge	645	case AVIVO_D1MODE_VLINE_START_END:
		646	case RADEON_CRTC_GUI_TRIG_VLINE:
		647	r = r100_cs_packet_parse_vline(p);
1120	serge	648	if (r) {
		649	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		650	idx, reg);
3764	Serge	651	radeon_cs_dump_packet(p, pkt);
1120	serge	652	return r;
		653	}
		654	break;
1179	serge	655	case RADEON_DST_PITCH_OFFSET:
		656	case RADEON_SRC_PITCH_OFFSET:
		657	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		658	if (r)
		659	return r;
		660	break;
1120	serge	661	case R300_RB3D_COLOROFFSET0:
		662	case R300_RB3D_COLOROFFSET1:
		663	case R300_RB3D_COLOROFFSET2:
		664	case R300_RB3D_COLOROFFSET3:
		665	i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
3764	Serge	666	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1120	serge	667	if (r) {
		668	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		669	idx, reg);
3764	Serge	670	radeon_cs_dump_packet(p, pkt);
1120	serge	671	return r;
		672	}
		673	track->cb[i].robj = reloc->robj;
1221	serge	674	track->cb[i].offset = idx_value;
1963	serge	675	track->cb_dirty = true;
5078	serge	676	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1120	serge	677	break;
		678	case R300_ZB_DEPTHOFFSET:
3764	Serge	679	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1120	serge	680	if (r) {
		681	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		682	idx, reg);
3764	Serge	683	radeon_cs_dump_packet(p, pkt);
1120	serge	684	return r;
		685	}
		686	track->zb.robj = reloc->robj;
1221	serge	687	track->zb.offset = idx_value;
1963	serge	688	track->zb_dirty = true;
5078	serge	689	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1120	serge	690	break;
		691	case R300_TX_OFFSET_0:
		692	case R300_TX_OFFSET_0+4:
		693	case R300_TX_OFFSET_0+8:
		694	case R300_TX_OFFSET_0+12:
		695	case R300_TX_OFFSET_0+16:
		696	case R300_TX_OFFSET_0+20:
		697	case R300_TX_OFFSET_0+24:
		698	case R300_TX_OFFSET_0+28:
		699	case R300_TX_OFFSET_0+32:
		700	case R300_TX_OFFSET_0+36:
		701	case R300_TX_OFFSET_0+40:
		702	case R300_TX_OFFSET_0+44:
		703	case R300_TX_OFFSET_0+48:
		704	case R300_TX_OFFSET_0+52:
		705	case R300_TX_OFFSET_0+56:
		706	case R300_TX_OFFSET_0+60:
		707	i = (reg - R300_TX_OFFSET_0) >> 2;
3764	Serge	708	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1120	serge	709	if (r) {
		710	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		711	idx, reg);
3764	Serge	712	radeon_cs_dump_packet(p, pkt);
1120	serge	713	return r;
		714	}
1403	serge	715
2997	Serge	716	if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {
		717	ib[idx] = (idx_value & 31) \| /* keep the 1st 5 bits */
5078	serge	718	((idx_value & ~31) + (u32)reloc->gpu_offset);
2997	Serge	719	} else {
5078	serge	720	if (reloc->tiling_flags & RADEON_TILING_MACRO)
6104	serge	721	tile_flags \|= R300_TXO_MACRO_TILE;
5078	serge	722	if (reloc->tiling_flags & RADEON_TILING_MICRO)
6104	serge	723	tile_flags \|= R300_TXO_MICRO_TILE;
5078	serge	724	else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
6104	serge	725	tile_flags \|= R300_TXO_MICRO_TILE_SQUARE;
1403	serge	726
5078	serge	727	tmp = idx_value + ((u32)reloc->gpu_offset);
6104	serge	728	tmp \|= tile_flags;
		729	ib[idx] = tmp;
2997	Serge	730	}
1120	serge	731	track->textures[i].robj = reloc->robj;
1963	serge	732	track->tex_dirty = true;
1120	serge	733	break;
		734	/* Tracked registers */
		735	case 0x2084:
		736	/* VAP_VF_CNTL */
1221	serge	737	track->vap_vf_cntl = idx_value;
1120	serge	738	break;
		739	case 0x20B4:
		740	/* VAP_VTX_SIZE */
1221	serge	741	track->vtx_size = idx_value & 0x7F;
1120	serge	742	break;
		743	case 0x2134:
		744	/* VAP_VF_MAX_VTX_INDX */
1221	serge	745	track->max_indx = idx_value & 0x00FFFFFFUL;
1120	serge	746	break;
1963	serge	747	case 0x2088:
		748	/* VAP_ALT_NUM_VERTICES - only valid on r500 */
		749	if (p->rdev->family < CHIP_RV515)
		750	goto fail;
		751	track->vap_alt_nverts = idx_value & 0xFFFFFF;
		752	break;
1120	serge	753	case 0x43E4:
		754	/* SC_SCISSOR1 */
1221	serge	755	track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
1120	serge	756	if (p->rdev->family < CHIP_RV515) {
		757	track->maxy -= 1440;
		758	}
1963	serge	759	track->cb_dirty = true;
		760	track->zb_dirty = true;
1120	serge	761	break;
		762	case 0x4E00:
		763	/* RB3D_CCTL */
1963	serge	764	if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
		765	p->rdev->cmask_filp != p->filp) {
		766	DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n");
		767	return -EINVAL;
		768	}
1221	serge	769	track->num_cb = ((idx_value >> 5) & 0x3) + 1;
1963	serge	770	track->cb_dirty = true;
1120	serge	771	break;
		772	case 0x4E38:
		773	case 0x4E3C:
		774	case 0x4E40:
		775	case 0x4E44:
		776	/* RB3D_COLORPITCH0 */
		777	/* RB3D_COLORPITCH1 */
		778	/* RB3D_COLORPITCH2 */
		779	/* RB3D_COLORPITCH3 */
2997	Serge	780	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
3764	Serge	781	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
6104	serge	782	if (r) {
		783	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		784	idx, reg);
3764	Serge	785	radeon_cs_dump_packet(p, pkt);
6104	serge	786	return r;
		787	}
1179	serge	788
5078	serge	789	if (reloc->tiling_flags & RADEON_TILING_MACRO)
6104	serge	790	tile_flags \|= R300_COLOR_TILE_ENABLE;
5078	serge	791	if (reloc->tiling_flags & RADEON_TILING_MICRO)
6104	serge	792	tile_flags \|= R300_COLOR_MICROTILE_ENABLE;
5078	serge	793	else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
6104	serge	794	tile_flags \|= R300_COLOR_MICROTILE_SQUARE_ENABLE;
1179	serge	795
6104	serge	796	tmp = idx_value & ~(0x7 << 16);
		797	tmp \|= tile_flags;
		798	ib[idx] = tmp;
2997	Serge	799	}
1120	serge	800	i = (reg - 0x4E38) >> 2;
1221	serge	801	track->cb[i].pitch = idx_value & 0x3FFE;
		802	switch (((idx_value >> 21) & 0xF)) {
1120	serge	803	case 9:
		804	case 11:
		805	case 12:
		806	track->cb[i].cpp = 1;
		807	break;
		808	case 3:
		809	case 4:
		810	case 13:
		811	case 15:
		812	track->cb[i].cpp = 2;
		813	break;
1963	serge	814	case 5:
		815	if (p->rdev->family < CHIP_RV515) {
		816	DRM_ERROR("Invalid color buffer format (%d)!\n",
		817	((idx_value >> 21) & 0xF));
		818	return -EINVAL;
		819	}
		820	/* Pass through. */
1120	serge	821	case 6:
		822	track->cb[i].cpp = 4;
		823	break;
		824	case 10:
		825	track->cb[i].cpp = 8;
		826	break;
		827	case 7:
		828	track->cb[i].cpp = 16;
		829	break;
		830	default:
		831	DRM_ERROR("Invalid color buffer format (%d) !\n",
1221	serge	832	((idx_value >> 21) & 0xF));
1120	serge	833	return -EINVAL;
		834	}
1963	serge	835	track->cb_dirty = true;
1120	serge	836	break;
		837	case 0x4F00:
		838	/* ZB_CNTL */
1221	serge	839	if (idx_value & 2) {
1120	serge	840	track->z_enabled = true;
		841	} else {
		842	track->z_enabled = false;
		843	}
1963	serge	844	track->zb_dirty = true;
1120	serge	845	break;
		846	case 0x4F10:
		847	/* ZB_FORMAT */
1221	serge	848	switch ((idx_value & 0xF)) {
1120	serge	849	case 0:
		850	case 1:
		851	track->zb.cpp = 2;
		852	break;
		853	case 2:
		854	track->zb.cpp = 4;
		855	break;
		856	default:
		857	DRM_ERROR("Invalid z buffer format (%d) !\n",
1221	serge	858	(idx_value & 0xF));
1120	serge	859	return -EINVAL;
		860	}
1963	serge	861	track->zb_dirty = true;
1120	serge	862	break;
		863	case 0x4F24:
		864	/* ZB_DEPTHPITCH */
2997	Serge	865	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
3764	Serge	866	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
6104	serge	867	if (r) {
		868	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		869	idx, reg);
3764	Serge	870	radeon_cs_dump_packet(p, pkt);
6104	serge	871	return r;
		872	}
1179	serge	873
5078	serge	874	if (reloc->tiling_flags & RADEON_TILING_MACRO)
6104	serge	875	tile_flags \|= R300_DEPTHMACROTILE_ENABLE;
5078	serge	876	if (reloc->tiling_flags & RADEON_TILING_MICRO)
6104	serge	877	tile_flags \|= R300_DEPTHMICROTILE_TILED;
5078	serge	878	else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
6104	serge	879	tile_flags \|= R300_DEPTHMICROTILE_TILED_SQUARE;
1179	serge	880
6104	serge	881	tmp = idx_value & ~(0x7 << 16);
		882	tmp \|= tile_flags;
		883	ib[idx] = tmp;
2997	Serge	884	}
1221	serge	885	track->zb.pitch = idx_value & 0x3FFC;
1963	serge	886	track->zb_dirty = true;
1120	serge	887	break;
		888	case 0x4104:
1963	serge	889	/* TX_ENABLE */
1120	serge	890	for (i = 0; i < 16; i++) {
		891	bool enabled;
		892
1221	serge	893	enabled = !!(idx_value & (1 << i));
1120	serge	894	track->textures[i].enabled = enabled;
		895	}
1963	serge	896	track->tex_dirty = true;
1120	serge	897	break;
		898	case 0x44C0:
		899	case 0x44C4:
		900	case 0x44C8:
		901	case 0x44CC:
		902	case 0x44D0:
		903	case 0x44D4:
		904	case 0x44D8:
		905	case 0x44DC:
		906	case 0x44E0:
		907	case 0x44E4:
		908	case 0x44E8:
		909	case 0x44EC:
		910	case 0x44F0:
		911	case 0x44F4:
		912	case 0x44F8:
		913	case 0x44FC:
		914	/* TX_FORMAT1_[0-15] */
		915	i = (reg - 0x44C0) >> 2;
1221	serge	916	tmp = (idx_value >> 25) & 0x3;
1120	serge	917	track->textures[i].tex_coord_type = tmp;
1221	serge	918	switch ((idx_value & 0x1F)) {
1179	serge	919	case R300_TX_FORMAT_X8:
		920	case R300_TX_FORMAT_Y4X4:
		921	case R300_TX_FORMAT_Z3Y3X2:
1120	serge	922	track->textures[i].cpp = 1;
1963	serge	923	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1120	serge	924	break;
1179	serge	925	case R300_TX_FORMAT_X16:
1963	serge	926	case R300_TX_FORMAT_FL_I16:
1179	serge	927	case R300_TX_FORMAT_Y8X8:
		928	case R300_TX_FORMAT_Z5Y6X5:
		929	case R300_TX_FORMAT_Z6Y5X5:
		930	case R300_TX_FORMAT_W4Z4Y4X4:
		931	case R300_TX_FORMAT_W1Z5Y5X5:
		932	case R300_TX_FORMAT_D3DMFT_CxV8U8:
		933	case R300_TX_FORMAT_B8G8_B8G8:
		934	case R300_TX_FORMAT_G8R8_G8B8:
1120	serge	935	track->textures[i].cpp = 2;
1963	serge	936	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1120	serge	937	break;
1179	serge	938	case R300_TX_FORMAT_Y16X16:
1963	serge	939	case R300_TX_FORMAT_FL_I16A16:
1179	serge	940	case R300_TX_FORMAT_Z11Y11X10:
		941	case R300_TX_FORMAT_Z10Y11X11:
		942	case R300_TX_FORMAT_W8Z8Y8X8:
		943	case R300_TX_FORMAT_W2Z10Y10X10:
		944	case 0x17:
		945	case R300_TX_FORMAT_FL_I32:
		946	case 0x1e:
1120	serge	947	track->textures[i].cpp = 4;
1963	serge	948	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1120	serge	949	break;
1179	serge	950	case R300_TX_FORMAT_W16Z16Y16X16:
		951	case R300_TX_FORMAT_FL_R16G16B16A16:
		952	case R300_TX_FORMAT_FL_I32A32:
1120	serge	953	track->textures[i].cpp = 8;
1963	serge	954	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1120	serge	955	break;
1179	serge	956	case R300_TX_FORMAT_FL_R32G32B32A32:
1120	serge	957	track->textures[i].cpp = 16;
1963	serge	958	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1120	serge	959	break;
1403	serge	960	case R300_TX_FORMAT_DXT1:
		961	track->textures[i].cpp = 1;
		962	track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
		963	break;
		964	case R300_TX_FORMAT_ATI2N:
		965	if (p->rdev->family < CHIP_R420) {
		966	DRM_ERROR("Invalid texture format %u\n",
		967	(idx_value & 0x1F));
		968	return -EINVAL;
		969	}
		970	/* The same rules apply as for DXT3/5. */
		971	/* Pass through. */
		972	case R300_TX_FORMAT_DXT3:
		973	case R300_TX_FORMAT_DXT5:
		974	track->textures[i].cpp = 1;
		975	track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
		976	break;
1120	serge	977	default:
		978	DRM_ERROR("Invalid texture format %u\n",
1221	serge	979	(idx_value & 0x1F));
1120	serge	980	return -EINVAL;
		981	}
1963	serge	982	track->tex_dirty = true;
1120	serge	983	break;
		984	case 0x4400:
		985	case 0x4404:
		986	case 0x4408:
		987	case 0x440C:
		988	case 0x4410:
		989	case 0x4414:
		990	case 0x4418:
		991	case 0x441C:
		992	case 0x4420:
		993	case 0x4424:
		994	case 0x4428:
		995	case 0x442C:
		996	case 0x4430:
		997	case 0x4434:
		998	case 0x4438:
		999	case 0x443C:
		1000	/* TX_FILTER0_[0-15] */
		1001	i = (reg - 0x4400) >> 2;
1221	serge	1002	tmp = idx_value & 0x7;
1120	serge	1003	if (tmp == 2 \|\| tmp == 4 \|\| tmp == 6) {
		1004	track->textures[i].roundup_w = false;
		1005	}
1221	serge	1006	tmp = (idx_value >> 3) & 0x7;
1120	serge	1007	if (tmp == 2 \|\| tmp == 4 \|\| tmp == 6) {
		1008	track->textures[i].roundup_h = false;
		1009	}
1963	serge	1010	track->tex_dirty = true;
1120	serge	1011	break;
		1012	case 0x4500:
		1013	case 0x4504:
		1014	case 0x4508:
		1015	case 0x450C:
		1016	case 0x4510:
		1017	case 0x4514:
		1018	case 0x4518:
		1019	case 0x451C:
		1020	case 0x4520:
		1021	case 0x4524:
		1022	case 0x4528:
		1023	case 0x452C:
		1024	case 0x4530:
		1025	case 0x4534:
		1026	case 0x4538:
		1027	case 0x453C:
		1028	/* TX_FORMAT2_[0-15] */
		1029	i = (reg - 0x4500) >> 2;
1221	serge	1030	tmp = idx_value & 0x3FFF;
1120	serge	1031	track->textures[i].pitch = tmp + 1;
		1032	if (p->rdev->family >= CHIP_RV515) {
1221	serge	1033	tmp = ((idx_value >> 15) & 1) << 11;
1120	serge	1034	track->textures[i].width_11 = tmp;
1221	serge	1035	tmp = ((idx_value >> 16) & 1) << 11;
1120	serge	1036	track->textures[i].height_11 = tmp;
1403	serge	1037
		1038	/* ATI1N */
		1039	if (idx_value & (1 << 14)) {
		1040	/* The same rules apply as for DXT1. */
		1041	track->textures[i].compress_format =
		1042	R100_TRACK_COMP_DXT1;
		1043	}
		1044	} else if (idx_value & (1 << 14)) {
		1045	DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
		1046	return -EINVAL;
1120	serge	1047	}
1963	serge	1048	track->tex_dirty = true;
1120	serge	1049	break;
		1050	case 0x4480:
		1051	case 0x4484:
		1052	case 0x4488:
		1053	case 0x448C:
		1054	case 0x4490:
		1055	case 0x4494:
		1056	case 0x4498:
		1057	case 0x449C:
		1058	case 0x44A0:
		1059	case 0x44A4:
		1060	case 0x44A8:
		1061	case 0x44AC:
		1062	case 0x44B0:
		1063	case 0x44B4:
		1064	case 0x44B8:
		1065	case 0x44BC:
		1066	/* TX_FORMAT0_[0-15] */
		1067	i = (reg - 0x4480) >> 2;
1221	serge	1068	tmp = idx_value & 0x7FF;
1120	serge	1069	track->textures[i].width = tmp + 1;
1221	serge	1070	tmp = (idx_value >> 11) & 0x7FF;
1120	serge	1071	track->textures[i].height = tmp + 1;
1221	serge	1072	tmp = (idx_value >> 26) & 0xF;
1120	serge	1073	track->textures[i].num_levels = tmp;
1221	serge	1074	tmp = idx_value & (1 << 31);
1120	serge	1075	track->textures[i].use_pitch = !!tmp;
1221	serge	1076	tmp = (idx_value >> 22) & 0xF;
1120	serge	1077	track->textures[i].txdepth = tmp;
1963	serge	1078	track->tex_dirty = true;
1120	serge	1079	break;
1179	serge	1080	case R300_ZB_ZPASS_ADDR:
3764	Serge	1081	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1179	serge	1082	if (r) {
		1083	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1084	idx, reg);
3764	Serge	1085	radeon_cs_dump_packet(p, pkt);
1179	serge	1086	return r;
		1087	}
5078	serge	1088	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1179	serge	1089	break;
1403	serge	1090	case 0x4e0c:
		1091	/* RB3D_COLOR_CHANNEL_MASK */
		1092	track->color_channel_mask = idx_value;
1963	serge	1093	track->cb_dirty = true;
1403	serge	1094	break;
1963	serge	1095	case 0x43a4:
		1096	/* SC_HYPERZ_EN */
		1097	/* r300c emits this register - we need to disable hyperz for it
		1098	* without complaining */
		1099	if (p->rdev->hyperz_filp != p->filp) {
		1100	if (idx_value & 0x1)
		1101	ib[idx] = idx_value & ~1;
		1102	}
		1103	break;
		1104	case 0x4f1c:
1403	serge	1105	/* ZB_BW_CNTL */
1963	serge	1106	track->zb_cb_clear = !!(idx_value & (1 << 5));
		1107	track->cb_dirty = true;
		1108	track->zb_dirty = true;
		1109	if (p->rdev->hyperz_filp != p->filp) {
		1110	if (idx_value & (R300_HIZ_ENABLE \|
		1111	R300_RD_COMP_ENABLE \|
		1112	R300_WR_COMP_ENABLE \|
		1113	R300_FAST_FILL_ENABLE))
		1114	goto fail;
		1115	}
1403	serge	1116	break;
		1117	case 0x4e04:
		1118	/* RB3D_BLENDCNTL */
		1119	track->blend_read_enable = !!(idx_value & (1 << 2));
1963	serge	1120	track->cb_dirty = true;
1403	serge	1121	break;
1963	serge	1122	case R300_RB3D_AARESOLVE_OFFSET:
3764	Serge	1123	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1963	serge	1124	if (r) {
		1125	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1126	idx, reg);
3764	Serge	1127	radeon_cs_dump_packet(p, pkt);
1963	serge	1128	return r;
		1129	}
		1130	track->aa.robj = reloc->robj;
		1131	track->aa.offset = idx_value;
		1132	track->aa_dirty = true;
5078	serge	1133	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1963	serge	1134	break;
		1135	case R300_RB3D_AARESOLVE_PITCH:
		1136	track->aa.pitch = idx_value & 0x3FFE;
		1137	track->aa_dirty = true;
		1138	break;
		1139	case R300_RB3D_AARESOLVE_CTL:
		1140	track->aaresolve = idx_value & 0x1;
		1141	track->aa_dirty = true;
		1142	break;
		1143	case 0x4f30: /* ZB_MASK_OFFSET */
		1144	case 0x4f34: /* ZB_ZMASK_PITCH */
		1145	case 0x4f44: /* ZB_HIZ_OFFSET */
		1146	case 0x4f54: /* ZB_HIZ_PITCH */
		1147	if (idx_value && (p->rdev->hyperz_filp != p->filp))
		1148	goto fail;
		1149	break;
		1150	case 0x4028:
		1151	if (idx_value && (p->rdev->hyperz_filp != p->filp))
		1152	goto fail;
		1153	/* GB_Z_PEQ_CONFIG */
		1154	if (p->rdev->family >= CHIP_RV350)
		1155	break;
		1156	goto fail;
		1157	break;
1179	serge	1158	case 0x4be8:
		1159	/* valid register only on RV530 */
		1160	if (p->rdev->family == CHIP_RV530)
		1161	break;
		1162	/* fallthrough do not move */
1120	serge	1163	default:
1963	serge	1164	goto fail;
1120	serge	1165	}
		1166	return 0;
1963	serge	1167	fail:
		1168	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
		1169	reg, idx, idx_value);
6104	serge	1170	return -EINVAL;
1120	serge	1171	}
		1172
		1173	static int r300_packet3_check(struct radeon_cs_parser *p,
		1174	struct radeon_cs_packet *pkt)
		1175	{
5271	serge	1176	struct radeon_bo_list *reloc;
1179	serge	1177	struct r100_cs_track *track;
1120	serge	1178	volatile uint32_t *ib;
		1179	unsigned idx;
		1180	int r;
		1181
2997	Serge	1182	ib = p->ib.ptr;
1120	serge	1183	idx = pkt->idx + 1;
1179	serge	1184	track = (struct r100_cs_track *)p->track;
1120	serge	1185	switch(pkt->opcode) {
		1186	case PACKET3_3D_LOAD_VBPNTR:
1221	serge	1187	r = r100_packet3_load_vbpntr(p, pkt, idx);
		1188	if (r)
6104	serge	1189	return r;
1120	serge	1190	break;
		1191	case PACKET3_INDX_BUFFER:
3764	Serge	1192	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1120	serge	1193	if (r) {
		1194	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
3764	Serge	1195	radeon_cs_dump_packet(p, pkt);
1120	serge	1196	return r;
		1197	}
5078	serge	1198	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1120	serge	1199	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		1200	if (r) {
		1201	return r;
		1202	}
		1203	break;
		1204	/* Draw packet */
		1205	case PACKET3_3D_DRAW_IMMD:
		1206	/* Number of dwords is vtx_size * (num_vertices - 1)
		1207	* PRIM_WALK must be equal to 3 vertex data in embedded
		1208	* in cmd stream */
1221	serge	1209	if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1120	serge	1210	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1211	return -EINVAL;
		1212	}
1221	serge	1213	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1120	serge	1214	track->immd_dwords = pkt->count - 1;
1179	serge	1215	r = r100_cs_track_check(p->rdev, track);
1120	serge	1216	if (r) {
		1217	return r;
		1218	}
		1219	break;
		1220	case PACKET3_3D_DRAW_IMMD_2:
		1221	/* Number of dwords is vtx_size * (num_vertices - 1)
		1222	* PRIM_WALK must be equal to 3 vertex data in embedded
		1223	* in cmd stream */
1221	serge	1224	if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1120	serge	1225	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1226	return -EINVAL;
		1227	}
1221	serge	1228	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1120	serge	1229	track->immd_dwords = pkt->count;
1179	serge	1230	r = r100_cs_track_check(p->rdev, track);
1120	serge	1231	if (r) {
		1232	return r;
		1233	}
		1234	break;
		1235	case PACKET3_3D_DRAW_VBUF:
1221	serge	1236	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1237	r = r100_cs_track_check(p->rdev, track);
1120	serge	1238	if (r) {
		1239	return r;
		1240	}
		1241	break;
		1242	case PACKET3_3D_DRAW_VBUF_2:
1221	serge	1243	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1244	r = r100_cs_track_check(p->rdev, track);
1120	serge	1245	if (r) {
		1246	return r;
		1247	}
		1248	break;
		1249	case PACKET3_3D_DRAW_INDX:
1221	serge	1250	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1251	r = r100_cs_track_check(p->rdev, track);
1120	serge	1252	if (r) {
		1253	return r;
		1254	}
		1255	break;
		1256	case PACKET3_3D_DRAW_INDX_2:
1221	serge	1257	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1258	r = r100_cs_track_check(p->rdev, track);
1120	serge	1259	if (r) {
		1260	return r;
		1261	}
		1262	break;
1963	serge	1263	case PACKET3_3D_CLEAR_HIZ:
		1264	case PACKET3_3D_CLEAR_ZMASK:
		1265	if (p->rdev->hyperz_filp != p->filp)
		1266	return -EINVAL;
		1267	break;
		1268	case PACKET3_3D_CLEAR_CMASK:
		1269	if (p->rdev->cmask_filp != p->filp)
		1270	return -EINVAL;
		1271	break;
1120	serge	1272	case PACKET3_NOP:
		1273	break;
		1274	default:
		1275	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		1276	return -EINVAL;
		1277	}
		1278	return 0;
		1279	}
		1280
		1281	int r300_cs_parse(struct radeon_cs_parser *p)
		1282	{
		1283	struct radeon_cs_packet pkt;
1179	serge	1284	struct r100_cs_track *track;
1120	serge	1285	int r;
		1286
1179	serge	1287	track = kzalloc(sizeof(*track), GFP_KERNEL);
1963	serge	1288	if (track == NULL)
		1289	return -ENOMEM;
1179	serge	1290	r100_cs_track_clear(p->rdev, track);
		1291	p->track = track;
1120	serge	1292	do {
3764	Serge	1293	r = radeon_cs_packet_parse(p, &pkt, p->idx);
1120	serge	1294	if (r) {
		1295	return r;
		1296	}
		1297	p->idx += pkt.count + 2;
		1298	switch (pkt.type) {
3764	Serge	1299	case RADEON_PACKET_TYPE0:
1120	serge	1300	r = r100_cs_parse_packet0(p, &pkt,
		1301	p->rdev->config.r300.reg_safe_bm,
		1302	p->rdev->config.r300.reg_safe_bm_size,
		1303	&r300_packet0_check);
		1304	break;
3764	Serge	1305	case RADEON_PACKET_TYPE2:
1120	serge	1306	break;
3764	Serge	1307	case RADEON_PACKET_TYPE3:
1120	serge	1308	r = r300_packet3_check(p, &pkt);
		1309	break;
		1310	default:
		1311	DRM_ERROR("Unknown packet type %d !\n", pkt.type);
		1312	return -EINVAL;
		1313	}
		1314	if (r) {
		1315	return r;
		1316	}
5271	serge	1317	} while (p->idx < p->chunk_ib->length_dw);
1120	serge	1318	return 0;
		1319	}
1128	serge	1320
1179	serge	1321	void r300_set_reg_safe(struct radeon_device *rdev)
1120	serge	1322	{
		1323	rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
		1324	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1179	serge	1325	}
		1326
		1327	void r300_mc_program(struct radeon_device *rdev)
		1328	{
		1329	struct r100_mc_save save;
		1330	int r;
1120	serge	1331
1179	serge	1332	r = r100_debugfs_mc_info_init(rdev);
		1333	if (r) {
		1334	dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		1335	}
		1336
		1337	/* Stops all mc clients */
		1338	r100_mc_stop(rdev, &save);
		1339	if (rdev->flags & RADEON_IS_AGP) {
		1340	WREG32(R_00014C_MC_AGP_LOCATION,
		1341	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		1342	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		1343	WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		1344	WREG32(R_00015C_AGP_BASE_2,
		1345	upper_32_bits(rdev->mc.agp_base) & 0xff);
		1346	} else {
		1347	WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		1348	WREG32(R_000170_AGP_BASE, 0);
		1349	WREG32(R_00015C_AGP_BASE_2, 0);
		1350	}
		1351	/* Wait for mc idle */
		1352	if (r300_mc_wait_for_idle(rdev))
		1353	DRM_INFO("Failed to wait MC idle before programming MC.\n");
		1354	/* Program MC, should be a 32bits limited address space */
		1355	WREG32(R_000148_MC_FB_LOCATION,
		1356	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		1357	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		1358	r100_mc_resume(rdev, &save);
		1359	}
1221	serge	1360
		1361	void r300_clock_startup(struct radeon_device *rdev)
		1362	{
		1363	u32 tmp;
		1364
		1365	if (radeon_dynclks != -1 && radeon_dynclks)
		1366	radeon_legacy_set_clock_gating(rdev, 1);
		1367	/* We need to force on some of the block */
		1368	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
		1369	tmp \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		1370	if ((rdev->family == CHIP_RV350) \|\| (rdev->family == CHIP_RV380))
		1371	tmp \|= S_00000D_FORCE_VAP(1);
		1372	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
		1373	}
		1374
		1375	static int r300_startup(struct radeon_device *rdev)
		1376	{
		1377	int r;
		1378
1321	serge	1379	/* set common regs */
		1380	r100_set_common_regs(rdev);
		1381	/* program mc */
1221	serge	1382	r300_mc_program(rdev);
		1383	/* Resume clock */
		1384	r300_clock_startup(rdev);
		1385	/* Initialize GPU configuration (# pipes, ...) */
		1386	r300_gpu_init(rdev);
		1387	/* Initialize GART (initialize after TTM so we can allocate
		1388	* memory through TTM but finalize after TTM) */
		1389	if (rdev->flags & RADEON_IS_PCIE) {
		1390	r = rv370_pcie_gart_enable(rdev);
		1391	if (r)
		1392	return r;
		1393	}
1321	serge	1394
		1395	if (rdev->family == CHIP_R300 \|\|
		1396	rdev->family == CHIP_R350 \|\|
		1397	rdev->family == CHIP_RV350)
		1398	r100_enable_bm(rdev);
		1399
1221	serge	1400	if (rdev->flags & RADEON_IS_PCI) {
		1401	r = r100_pci_gart_enable(rdev);
		1402	if (r)
		1403	return r;
		1404	}
1963	serge	1405
2005	serge	1406	/* allocate wb buffer */
		1407	r = radeon_wb_init(rdev);
		1408	if (r)
		1409	return r;
1963	serge	1410
3120	serge	1411	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
		1412	if (r) {
		1413	dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
		1414	return r;
		1415	}
		1416
1221	serge	1417	/* Enable IRQ */
3764	Serge	1418	if (!rdev->irq.installed) {
		1419	r = radeon_irq_kms_init(rdev);
		1420	if (r)
		1421	return r;
		1422	}
		1423
2005	serge	1424	r100_irq_set(rdev);
1403	serge	1425	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1221	serge	1426	/* 1M ring buffer */
6104	serge	1427	r = r100_cp_init(rdev, 1024 * 1024);
		1428	if (r) {
1963	serge	1429	dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
6104	serge	1430	return r;
		1431	}
2997	Serge	1432
		1433	r = radeon_ib_pool_init(rdev);
2005	serge	1434	if (r) {
2997	Serge	1435	dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2005	serge	1436	return r;
		1437	}
2997	Serge	1438
1221	serge	1439	return 0;
		1440	}
		1441
		1442
		1443
		1444
6104	serge	1445	void r300_fini(struct radeon_device *rdev)
		1446	{
		1447	radeon_pm_fini(rdev);
		1448	r100_cp_fini(rdev);
		1449	radeon_wb_fini(rdev);
		1450	radeon_ib_pool_fini(rdev);
		1451	radeon_gem_fini(rdev);
		1452	if (rdev->flags & RADEON_IS_PCIE)
		1453	rv370_pcie_gart_fini(rdev);
		1454	if (rdev->flags & RADEON_IS_PCI)
		1455	r100_pci_gart_fini(rdev);
		1456	radeon_agp_fini(rdev);
		1457	radeon_irq_kms_fini(rdev);
		1458	radeon_fence_driver_fini(rdev);
		1459	radeon_bo_fini(rdev);
		1460	radeon_atombios_fini(rdev);
		1461	kfree(rdev->bios);
		1462	rdev->bios = NULL;
		1463	}
1221	serge	1464
		1465	int r300_init(struct radeon_device *rdev)
		1466	{
		1467	int r;
		1468
		1469	/* Disable VGA */
		1470	r100_vga_render_disable(rdev);
		1471	/* Initialize scratch registers */
		1472	radeon_scratch_init(rdev);
		1473	/* Initialize surface registers */
		1474	radeon_surface_init(rdev);
		1475	/* TODO: disable VGA need to use VGA request */
1963	serge	1476	/* restore some register to sane defaults */
		1477	r100_restore_sanity(rdev);
1221	serge	1478	/* BIOS*/
		1479	if (!radeon_get_bios(rdev)) {
		1480	if (ASIC_IS_AVIVO(rdev))
		1481	return -EINVAL;
		1482	}
		1483	if (rdev->is_atom_bios) {
		1484	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		1485	return -EINVAL;
		1486	} else {
		1487	r = radeon_combios_init(rdev);
		1488	if (r)
		1489	return r;
		1490	}
		1491	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
1963	serge	1492	if (radeon_asic_reset(rdev)) {
1221	serge	1493	dev_warn(rdev->dev,
		1494	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		1495	RREG32(R_000E40_RBBM_STATUS),
		1496	RREG32(R_0007C0_CP_STAT));
		1497	}
		1498	/* check if cards are posted or not */
1321	serge	1499	if (radeon_boot_test_post_card(rdev) == false)
		1500	return -EINVAL;
1221	serge	1501	/* Set asic errata */
		1502	r300_errata(rdev);
		1503	/* Initialize clocks */
		1504	radeon_get_clock_info(rdev->ddev);
1430	serge	1505	/* initialize AGP */
		1506	if (rdev->flags & RADEON_IS_AGP) {
		1507	r = radeon_agp_init(rdev);
		1508	if (r) {
		1509	radeon_agp_disable(rdev);
		1510	}
		1511	}
		1512	/* initialize memory controller */
		1513	r300_mc_init(rdev);
1221	serge	1514	/* Fence driver */
2005	serge	1515	r = radeon_fence_driver_init(rdev);
		1516	if (r)
		1517	return r;
1221	serge	1518	/* Memory manager */
1404	serge	1519	r = radeon_bo_init(rdev);
1221	serge	1520	if (r)
		1521	return r;
		1522	if (rdev->flags & RADEON_IS_PCIE) {
		1523	r = rv370_pcie_gart_init(rdev);
		1524	if (r)
		1525	return r;
		1526	}
		1527	if (rdev->flags & RADEON_IS_PCI) {
		1528	r = r100_pci_gart_init(rdev);
		1529	if (r)
		1530	return r;
		1531	}
		1532	r300_set_reg_safe(rdev);
2997	Serge	1533
5078	serge	1534	/* Initialize power management */
		1535	radeon_pm_init(rdev);
		1536
1221	serge	1537	rdev->accel_working = true;
		1538	r = r300_startup(rdev);
		1539	if (r) {
5078	serge	1540	/* Something went wrong with the accel init, so stop accel */
1221	serge	1541	dev_err(rdev->dev, "Disabling GPU acceleration\n");
6104	serge	1542	r100_cp_fini(rdev);
		1543	radeon_wb_fini(rdev);
		1544	radeon_ib_pool_fini(rdev);
		1545	radeon_irq_kms_fini(rdev);
1221	serge	1546	if (rdev->flags & RADEON_IS_PCIE)
		1547	rv370_pcie_gart_fini(rdev);
		1548	if (rdev->flags & RADEON_IS_PCI)
		1549	r100_pci_gart_fini(rdev);
		1550	rdev->accel_working = false;
		1551	}
		1552	return 0;
		1553	}

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(root)/drivers/video/drm/radeon/r300.c – Rev 6104