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Rev | Author | Line No. | Line |
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1120 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1179 | serge | 28 | #include |
1963 | serge | 29 | #include |
30 | #include |
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31 | #include |
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32 | #include |
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1120 | serge | 33 | #include "radeon_reg.h" |
34 | #include "radeon.h" |
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1963 | serge | 35 | #include "radeon_asic.h" |
2997 | Serge | 36 | #include |
1120 | serge | 37 | |
1179 | serge | 38 | #include "r300d.h" |
1221 | serge | 39 | #include "rv350d.h" |
1179 | serge | 40 | #include "r300_reg_safe.h" |
41 | |||
1403 | serge | 42 | /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 |
43 | * |
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44 | * GPU Errata: |
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45 | * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL |
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46 | * using MMIO to flush host path read cache, this lead to HARDLOCKUP. |
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47 | * However, scheduling such write to the ring seems harmless, i suspect |
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48 | * the CP read collide with the flush somehow, or maybe the MC, hard to |
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49 | * tell. (Jerome Glisse) |
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50 | */ |
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1120 | serge | 51 | |
52 | /* |
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53 | * rv370,rv380 PCIE GART |
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54 | */ |
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1221 | serge | 55 | static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
56 | |||
1120 | serge | 57 | void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) |
58 | { |
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59 | uint32_t tmp; |
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60 | int i; |
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61 | |||
62 | /* Workaround HW bug do flush 2 times */ |
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63 | for (i = 0; i < 2; i++) { |
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64 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
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65 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); |
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66 | (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
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67 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
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1179 | serge | 68 | } |
1120 | serge | 69 | mb(); |
1179 | serge | 70 | } |
71 | |||
1963 | serge | 72 | #define R300_PTE_WRITEABLE (1 << 2) |
73 | #define R300_PTE_READABLE (1 << 3) |
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74 | |||
1179 | serge | 75 | int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
76 | { |
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2997 | Serge | 77 | void __iomem *ptr = rdev->gart.ptr; |
1179 | serge | 78 | |
79 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
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80 | return -EINVAL; |
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1120 | serge | 81 | } |
1179 | serge | 82 | addr = (lower_32_bits(addr) >> 8) | |
83 | ((upper_32_bits(addr) & 0xff) << 24) | |
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1963 | serge | 84 | R300_PTE_WRITEABLE | R300_PTE_READABLE; |
1179 | serge | 85 | /* on x86 we want this to be CPU endian, on powerpc |
86 | * on powerpc without HW swappers, it'll get swapped on way |
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87 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ |
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88 | writel(addr, ((void __iomem *)ptr) + (i * 4)); |
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89 | return 0; |
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1120 | serge | 90 | } |
91 | |||
1179 | serge | 92 | int rv370_pcie_gart_init(struct radeon_device *rdev) |
1120 | serge | 93 | { |
94 | int r; |
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95 | |||
2997 | Serge | 96 | if (rdev->gart.robj) { |
1963 | serge | 97 | WARN(1, "RV370 PCIE GART already initialized\n"); |
1179 | serge | 98 | return 0; |
99 | } |
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1120 | serge | 100 | /* Initialize common gart structure */ |
101 | r = radeon_gart_init(rdev); |
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1179 | serge | 102 | if (r) |
1120 | serge | 103 | return r; |
1129 | serge | 104 | r = rv370_debugfs_pcie_gart_info_init(rdev); |
1179 | serge | 105 | if (r) |
1129 | serge | 106 | DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); |
1179 | serge | 107 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
2997 | Serge | 108 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; |
109 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; |
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1179 | serge | 110 | return radeon_gart_table_vram_alloc(rdev); |
111 | } |
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112 | |||
113 | int rv370_pcie_gart_enable(struct radeon_device *rdev) |
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114 | { |
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115 | uint32_t table_addr; |
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116 | uint32_t tmp; |
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117 | int r; |
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118 | |||
2997 | Serge | 119 | if (rdev->gart.robj == NULL) { |
1179 | serge | 120 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
121 | return -EINVAL; |
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1129 | serge | 122 | } |
1179 | serge | 123 | r = radeon_gart_table_vram_pin(rdev); |
124 | if (r) |
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1120 | serge | 125 | return r; |
1430 | serge | 126 | radeon_gart_restore(rdev); |
1120 | serge | 127 | /* discard memory request outside of configured range */ |
128 | tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
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129 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
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1430 | serge | 130 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); |
131 | tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; |
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1120 | serge | 132 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); |
133 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); |
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134 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); |
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135 | table_addr = rdev->gart.table_addr; |
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136 | WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); |
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137 | /* FIXME: setup default page */ |
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1430 | serge | 138 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); |
1120 | serge | 139 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); |
140 | /* Clear error */ |
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1963 | serge | 141 | WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); |
1120 | serge | 142 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
143 | tmp |= RADEON_PCIE_TX_GART_EN; |
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144 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
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145 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
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146 | rv370_pcie_gart_tlb_flush(rdev); |
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2997 | Serge | 147 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
148 | (unsigned)(rdev->mc.gtt_size >> 20), |
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149 | (unsigned long long)table_addr); |
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1120 | serge | 150 | rdev->gart.ready = true; |
151 | return 0; |
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152 | } |
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153 | |||
154 | void rv370_pcie_gart_disable(struct radeon_device *rdev) |
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155 | { |
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1321 | serge | 156 | u32 tmp; |
1120 | serge | 157 | |
1963 | serge | 158 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); |
159 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); |
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160 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); |
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161 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); |
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1120 | serge | 162 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
163 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
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164 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); |
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2997 | Serge | 165 | radeon_gart_table_vram_unpin(rdev); |
1120 | serge | 166 | } |
167 | |||
1179 | serge | 168 | void rv370_pcie_gart_fini(struct radeon_device *rdev) |
1120 | serge | 169 | { |
1963 | serge | 170 | radeon_gart_fini(rdev); |
1120 | serge | 171 | rv370_pcie_gart_disable(rdev); |
1179 | serge | 172 | radeon_gart_table_vram_free(rdev); |
1120 | serge | 173 | } |
174 | |||
175 | void r300_fence_ring_emit(struct radeon_device *rdev, |
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176 | struct radeon_fence *fence) |
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177 | { |
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2997 | Serge | 178 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
179 | |||
1120 | serge | 180 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
181 | * for enough space (today caller are ib schedule and buffer move) */ |
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182 | /* Write SC register so SC & US assert idle */ |
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2997 | Serge | 183 | radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); |
184 | radeon_ring_write(ring, 0); |
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185 | radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); |
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186 | radeon_ring_write(ring, 0); |
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1120 | serge | 187 | /* Flush 3D cache */ |
2997 | Serge | 188 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
189 | radeon_ring_write(ring, R300_RB3D_DC_FLUSH); |
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190 | radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
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191 | radeon_ring_write(ring, R300_ZC_FLUSH); |
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1120 | serge | 192 | /* Wait until IDLE & CLEAN */ |
2997 | Serge | 193 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
194 | radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN | |
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1430 | serge | 195 | RADEON_WAIT_2D_IDLECLEAN | |
196 | RADEON_WAIT_DMA_GUI_IDLE)); |
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2997 | Serge | 197 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
198 | radeon_ring_write(ring, rdev->config.r300.hdp_cntl | |
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1403 | serge | 199 | RADEON_HDP_READ_BUFFER_INVALIDATE); |
2997 | Serge | 200 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
201 | radeon_ring_write(ring, rdev->config.r300.hdp_cntl); |
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1120 | serge | 202 | /* Emit fence sequence & fire IRQ */ |
2997 | Serge | 203 | radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); |
204 | radeon_ring_write(ring, fence->seq); |
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205 | radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
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206 | radeon_ring_write(ring, RADEON_SW_INT_FIRE); |
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1120 | serge | 207 | } |
208 | |||
2997 | Serge | 209 | void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
1120 | serge | 210 | { |
211 | unsigned gb_tile_config; |
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212 | int r; |
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213 | |||
214 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
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215 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
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216 | switch(rdev->num_gb_pipes) { |
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217 | case 2: |
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218 | gb_tile_config |= R300_PIPE_COUNT_R300; |
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219 | break; |
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220 | case 3: |
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221 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
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222 | break; |
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223 | case 4: |
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224 | gb_tile_config |= R300_PIPE_COUNT_R420; |
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225 | break; |
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226 | case 1: |
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227 | default: |
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228 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
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229 | break; |
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230 | } |
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231 | |||
2997 | Serge | 232 | r = radeon_ring_lock(rdev, ring, 64); |
1120 | serge | 233 | if (r) { |
234 | return; |
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235 | } |
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2997 | Serge | 236 | radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); |
237 | radeon_ring_write(ring, |
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1120 | serge | 238 | RADEON_ISYNC_ANY2D_IDLE3D | |
239 | RADEON_ISYNC_ANY3D_IDLE2D | |
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240 | RADEON_ISYNC_WAIT_IDLEGUI | |
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241 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
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2997 | Serge | 242 | radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0)); |
243 | radeon_ring_write(ring, gb_tile_config); |
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244 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
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245 | radeon_ring_write(ring, |
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1120 | serge | 246 | RADEON_WAIT_2D_IDLECLEAN | |
247 | RADEON_WAIT_3D_IDLECLEAN); |
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2997 | Serge | 248 | radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); |
249 | radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); |
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250 | radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0)); |
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251 | radeon_ring_write(ring, 0); |
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252 | radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0)); |
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253 | radeon_ring_write(ring, 0); |
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254 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
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255 | radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
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256 | radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
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257 | radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); |
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258 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
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259 | radeon_ring_write(ring, |
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1120 | serge | 260 | RADEON_WAIT_2D_IDLECLEAN | |
261 | RADEON_WAIT_3D_IDLECLEAN); |
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2997 | Serge | 262 | radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0)); |
263 | radeon_ring_write(ring, 0); |
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264 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
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265 | radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
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266 | radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
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267 | radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); |
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268 | radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0)); |
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269 | radeon_ring_write(ring, |
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1120 | serge | 270 | ((6 << R300_MS_X0_SHIFT) | |
271 | (6 << R300_MS_Y0_SHIFT) | |
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272 | (6 << R300_MS_X1_SHIFT) | |
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273 | (6 << R300_MS_Y1_SHIFT) | |
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274 | (6 << R300_MS_X2_SHIFT) | |
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275 | (6 << R300_MS_Y2_SHIFT) | |
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276 | (6 << R300_MSBD0_Y_SHIFT) | |
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277 | (6 << R300_MSBD0_X_SHIFT))); |
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2997 | Serge | 278 | radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0)); |
279 | radeon_ring_write(ring, |
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1120 | serge | 280 | ((6 << R300_MS_X3_SHIFT) | |
281 | (6 << R300_MS_Y3_SHIFT) | |
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282 | (6 << R300_MS_X4_SHIFT) | |
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283 | (6 << R300_MS_Y4_SHIFT) | |
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284 | (6 << R300_MS_X5_SHIFT) | |
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285 | (6 << R300_MS_Y5_SHIFT) | |
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286 | (6 << R300_MSBD1_SHIFT))); |
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2997 | Serge | 287 | radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0)); |
288 | radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
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289 | radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0)); |
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290 | radeon_ring_write(ring, |
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1120 | serge | 291 | R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
2997 | Serge | 292 | radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0)); |
293 | radeon_ring_write(ring, |
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1120 | serge | 294 | R300_GEOMETRY_ROUND_NEAREST | |
295 | R300_COLOR_ROUND_NEAREST); |
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2997 | Serge | 296 | radeon_ring_unlock_commit(rdev, ring); |
1120 | serge | 297 | } |
298 | |||
2997 | Serge | 299 | static void r300_errata(struct radeon_device *rdev) |
1120 | serge | 300 | { |
301 | rdev->pll_errata = 0; |
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302 | |||
303 | if (rdev->family == CHIP_R300 && |
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304 | (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { |
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305 | rdev->pll_errata |= CHIP_ERRATA_R300_CG; |
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306 | } |
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307 | } |
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308 | |||
309 | int r300_mc_wait_for_idle(struct radeon_device *rdev) |
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310 | { |
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311 | unsigned i; |
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312 | uint32_t tmp; |
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313 | |||
314 | for (i = 0; i < rdev->usec_timeout; i++) { |
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315 | /* read MC_STATUS */ |
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1430 | serge | 316 | tmp = RREG32(RADEON_MC_STATUS); |
317 | if (tmp & R300_MC_IDLE) { |
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1120 | serge | 318 | return 0; |
319 | } |
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320 | DRM_UDELAY(1); |
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321 | } |
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322 | return -1; |
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323 | } |
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324 | |||
2997 | Serge | 325 | static void r300_gpu_init(struct radeon_device *rdev) |
1120 | serge | 326 | { |
327 | uint32_t gb_tile_config, tmp; |
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328 | |||
1963 | serge | 329 | if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || |
330 | (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { |
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1120 | serge | 331 | /* r300,r350 */ |
332 | rdev->num_gb_pipes = 2; |
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333 | } else { |
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1963 | serge | 334 | /* rv350,rv370,rv380,r300 AD, r350 AH */ |
1120 | serge | 335 | rdev->num_gb_pipes = 1; |
336 | } |
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1179 | serge | 337 | rdev->num_z_pipes = 1; |
1120 | serge | 338 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
339 | switch (rdev->num_gb_pipes) { |
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340 | case 2: |
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341 | gb_tile_config |= R300_PIPE_COUNT_R300; |
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342 | break; |
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343 | case 3: |
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344 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
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345 | break; |
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346 | case 4: |
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347 | gb_tile_config |= R300_PIPE_COUNT_R420; |
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348 | break; |
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349 | default: |
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350 | case 1: |
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351 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
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352 | break; |
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353 | } |
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354 | WREG32(R300_GB_TILE_CONFIG, gb_tile_config); |
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355 | |||
356 | if (r100_gui_wait_for_idle(rdev)) { |
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357 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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358 | "programming pipes. Bad things might happen.\n"); |
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359 | } |
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360 | |||
1430 | serge | 361 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
362 | WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); |
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1120 | serge | 363 | |
364 | WREG32(R300_RB2D_DSTCACHE_MODE, |
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365 | R300_DC_AUTOFLUSH_ENABLE | |
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366 | R300_DC_DC_DISABLE_IGNORE_PE); |
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367 | |||
368 | if (r100_gui_wait_for_idle(rdev)) { |
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369 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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370 | "programming pipes. Bad things might happen.\n"); |
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371 | } |
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372 | if (r300_mc_wait_for_idle(rdev)) { |
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373 | printk(KERN_WARNING "Failed to wait MC idle while " |
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374 | "programming pipes. Bad things might happen.\n"); |
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375 | } |
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1179 | serge | 376 | DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", |
377 | rdev->num_gb_pipes, rdev->num_z_pipes); |
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1120 | serge | 378 | } |
379 | |||
1963 | serge | 380 | int r300_asic_reset(struct radeon_device *rdev) |
1120 | serge | 381 | { |
1963 | serge | 382 | struct r100_mc_save save; |
383 | u32 status, tmp; |
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384 | int ret = 0; |
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1120 | serge | 385 | |
1963 | serge | 386 | status = RREG32(R_000E40_RBBM_STATUS); |
387 | if (!G_000E40_GUI_ACTIVE(status)) { |
||
388 | return 0; |
||
1120 | serge | 389 | } |
1963 | serge | 390 | r100_mc_stop(rdev, &save); |
391 | status = RREG32(R_000E40_RBBM_STATUS); |
||
392 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
||
393 | /* stop CP */ |
||
394 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
||
395 | tmp = RREG32(RADEON_CP_RB_CNTL); |
||
396 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
||
397 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
||
398 | WREG32(RADEON_CP_RB_WPTR, 0); |
||
399 | WREG32(RADEON_CP_RB_CNTL, tmp); |
||
400 | /* save PCI state */ |
||
401 | // pci_save_state(rdev->pdev); |
||
402 | /* disable bus mastering */ |
||
403 | r100_bm_disable(rdev); |
||
404 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | |
||
405 | S_0000F0_SOFT_RESET_GA(1)); |
||
406 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
||
407 | mdelay(500); |
||
408 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
||
409 | mdelay(1); |
||
410 | status = RREG32(R_000E40_RBBM_STATUS); |
||
411 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
||
412 | /* resetting the CP seems to be problematic sometimes it end up |
||
413 | * hard locking the computer, but it's necessary for successful |
||
414 | * reset more test & playing is needed on R3XX/R4XX to find a |
||
415 | * reliable (if any solution) |
||
416 | */ |
||
417 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
||
418 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
||
419 | mdelay(500); |
||
420 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
||
421 | mdelay(1); |
||
422 | status = RREG32(R_000E40_RBBM_STATUS); |
||
423 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
||
424 | /* restore PCI & busmastering */ |
||
425 | // pci_restore_state(rdev->pdev); |
||
426 | r100_enable_bm(rdev); |
||
1120 | serge | 427 | /* Check if GPU is idle */ |
1963 | serge | 428 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
429 | dev_err(rdev->dev, "failed to reset GPU\n"); |
||
430 | ret = -1; |
||
431 | } else |
||
432 | dev_info(rdev->dev, "GPU reset succeed\n"); |
||
433 | r100_mc_resume(rdev, &save); |
||
434 | return ret; |
||
1120 | serge | 435 | } |
436 | |||
437 | /* |
||
438 | * r300,r350,rv350,rv380 VRAM info |
||
439 | */ |
||
1430 | serge | 440 | void r300_mc_init(struct radeon_device *rdev) |
1120 | serge | 441 | { |
1430 | serge | 442 | u64 base; |
443 | u32 tmp; |
||
1120 | serge | 444 | |
445 | /* DDR for all card after R300 & IGP */ |
||
446 | rdev->mc.vram_is_ddr = true; |
||
447 | tmp = RREG32(RADEON_MEM_CNTL); |
||
1404 | serge | 448 | tmp &= R300_MEM_NUM_CHANNELS_MASK; |
449 | switch (tmp) { |
||
450 | case 0: rdev->mc.vram_width = 64; break; |
||
451 | case 1: rdev->mc.vram_width = 128; break; |
||
452 | case 2: rdev->mc.vram_width = 256; break; |
||
453 | default: rdev->mc.vram_width = 128; break; |
||
1120 | serge | 454 | } |
1179 | serge | 455 | r100_vram_init_sizes(rdev); |
1430 | serge | 456 | base = rdev->mc.aper_base; |
457 | if (rdev->flags & RADEON_IS_IGP) |
||
458 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; |
||
459 | radeon_vram_location(rdev, &rdev->mc, base); |
||
1963 | serge | 460 | rdev->mc.gtt_base_align = 0; |
1430 | serge | 461 | if (!(rdev->flags & RADEON_IS_AGP)) |
462 | radeon_gtt_location(rdev, &rdev->mc); |
||
1963 | serge | 463 | radeon_update_bandwidth_info(rdev); |
1120 | serge | 464 | } |
465 | |||
466 | void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) |
||
467 | { |
||
468 | uint32_t link_width_cntl, mask; |
||
469 | |||
470 | if (rdev->flags & RADEON_IS_IGP) |
||
471 | return; |
||
472 | |||
473 | if (!(rdev->flags & RADEON_IS_PCIE)) |
||
474 | return; |
||
475 | |||
476 | /* FIXME wait for idle */ |
||
477 | |||
478 | switch (lanes) { |
||
479 | case 0: |
||
480 | mask = RADEON_PCIE_LC_LINK_WIDTH_X0; |
||
481 | break; |
||
482 | case 1: |
||
483 | mask = RADEON_PCIE_LC_LINK_WIDTH_X1; |
||
484 | break; |
||
485 | case 2: |
||
486 | mask = RADEON_PCIE_LC_LINK_WIDTH_X2; |
||
487 | break; |
||
488 | case 4: |
||
489 | mask = RADEON_PCIE_LC_LINK_WIDTH_X4; |
||
490 | break; |
||
491 | case 8: |
||
492 | mask = RADEON_PCIE_LC_LINK_WIDTH_X8; |
||
493 | break; |
||
494 | case 12: |
||
495 | mask = RADEON_PCIE_LC_LINK_WIDTH_X12; |
||
496 | break; |
||
497 | case 16: |
||
498 | default: |
||
499 | mask = RADEON_PCIE_LC_LINK_WIDTH_X16; |
||
500 | break; |
||
501 | } |
||
502 | |||
503 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
||
504 | |||
505 | if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == |
||
506 | (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) |
||
507 | return; |
||
508 | |||
509 | link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | |
||
510 | RADEON_PCIE_LC_RECONFIG_NOW | |
||
511 | RADEON_PCIE_LC_RECONFIG_LATER | |
||
512 | RADEON_PCIE_LC_SHORT_RECONFIG_EN); |
||
513 | link_width_cntl |= mask; |
||
514 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
||
515 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | |
||
516 | RADEON_PCIE_LC_RECONFIG_NOW)); |
||
517 | |||
518 | /* wait for lane set to complete */ |
||
519 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
||
520 | while (link_width_cntl == 0xffffffff) |
||
521 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
||
522 | |||
523 | } |
||
524 | |||
1430 | serge | 525 | int rv370_get_pcie_lanes(struct radeon_device *rdev) |
526 | { |
||
527 | u32 link_width_cntl; |
||
528 | |||
529 | if (rdev->flags & RADEON_IS_IGP) |
||
530 | return 0; |
||
531 | |||
532 | if (!(rdev->flags & RADEON_IS_PCIE)) |
||
533 | return 0; |
||
534 | |||
535 | /* FIXME wait for idle */ |
||
536 | |||
537 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
||
538 | |||
539 | switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { |
||
540 | case RADEON_PCIE_LC_LINK_WIDTH_X0: |
||
541 | return 0; |
||
542 | case RADEON_PCIE_LC_LINK_WIDTH_X1: |
||
543 | return 1; |
||
544 | case RADEON_PCIE_LC_LINK_WIDTH_X2: |
||
545 | return 2; |
||
546 | case RADEON_PCIE_LC_LINK_WIDTH_X4: |
||
547 | return 4; |
||
548 | case RADEON_PCIE_LC_LINK_WIDTH_X8: |
||
549 | return 8; |
||
550 | case RADEON_PCIE_LC_LINK_WIDTH_X16: |
||
551 | default: |
||
552 | return 16; |
||
553 | } |
||
554 | } |
||
555 | |||
1120 | serge | 556 | #if defined(CONFIG_DEBUG_FS) |
557 | static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) |
||
558 | { |
||
559 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
560 | struct drm_device *dev = node->minor->dev; |
||
561 | struct radeon_device *rdev = dev->dev_private; |
||
562 | uint32_t tmp; |
||
563 | |||
564 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
||
565 | seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); |
||
566 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); |
||
567 | seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); |
||
568 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); |
||
569 | seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); |
||
570 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); |
||
571 | seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); |
||
572 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); |
||
573 | seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); |
||
574 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); |
||
575 | seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); |
||
576 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); |
||
577 | seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); |
||
578 | return 0; |
||
579 | } |
||
580 | |||
581 | static struct drm_info_list rv370_pcie_gart_info_list[] = { |
||
582 | {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, |
||
583 | }; |
||
584 | #endif |
||
585 | |||
1221 | serge | 586 | static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
1120 | serge | 587 | { |
588 | #if defined(CONFIG_DEBUG_FS) |
||
589 | return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); |
||
590 | #else |
||
591 | return 0; |
||
592 | #endif |
||
593 | } |
||
594 | |||
595 | |||
1128 | serge | 596 | #if 0 |
1221 | serge | 597 | |
1120 | serge | 598 | static int r300_packet0_check(struct radeon_cs_parser *p, |
599 | struct radeon_cs_packet *pkt, |
||
600 | unsigned idx, unsigned reg) |
||
601 | { |
||
602 | struct radeon_cs_reloc *reloc; |
||
1179 | serge | 603 | struct r100_cs_track *track; |
1120 | serge | 604 | volatile uint32_t *ib; |
1179 | serge | 605 | uint32_t tmp, tile_flags = 0; |
1120 | serge | 606 | unsigned i; |
607 | int r; |
||
1221 | serge | 608 | u32 idx_value; |
1120 | serge | 609 | |
2997 | Serge | 610 | ib = p->ib.ptr; |
1179 | serge | 611 | track = (struct r100_cs_track *)p->track; |
1221 | serge | 612 | idx_value = radeon_get_ib_value(p, idx); |
613 | |||
1120 | serge | 614 | switch(reg) { |
1179 | serge | 615 | case AVIVO_D1MODE_VLINE_START_END: |
616 | case RADEON_CRTC_GUI_TRIG_VLINE: |
||
617 | r = r100_cs_packet_parse_vline(p); |
||
1120 | serge | 618 | if (r) { |
619 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
620 | idx, reg); |
||
3764 | Serge | 621 | radeon_cs_dump_packet(p, pkt); |
1120 | serge | 622 | return r; |
623 | } |
||
624 | break; |
||
1179 | serge | 625 | case RADEON_DST_PITCH_OFFSET: |
626 | case RADEON_SRC_PITCH_OFFSET: |
||
627 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
||
628 | if (r) |
||
629 | return r; |
||
630 | break; |
||
1120 | serge | 631 | case R300_RB3D_COLOROFFSET0: |
632 | case R300_RB3D_COLOROFFSET1: |
||
633 | case R300_RB3D_COLOROFFSET2: |
||
634 | case R300_RB3D_COLOROFFSET3: |
||
635 | i = (reg - R300_RB3D_COLOROFFSET0) >> 2; |
||
3764 | Serge | 636 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1120 | serge | 637 | if (r) { |
638 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
639 | idx, reg); |
||
3764 | Serge | 640 | radeon_cs_dump_packet(p, pkt); |
1120 | serge | 641 | return r; |
642 | } |
||
643 | track->cb[i].robj = reloc->robj; |
||
1221 | serge | 644 | track->cb[i].offset = idx_value; |
1963 | serge | 645 | track->cb_dirty = true; |
1221 | serge | 646 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1120 | serge | 647 | break; |
648 | case R300_ZB_DEPTHOFFSET: |
||
3764 | Serge | 649 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1120 | serge | 650 | if (r) { |
651 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
652 | idx, reg); |
||
3764 | Serge | 653 | radeon_cs_dump_packet(p, pkt); |
1120 | serge | 654 | return r; |
655 | } |
||
656 | track->zb.robj = reloc->robj; |
||
1221 | serge | 657 | track->zb.offset = idx_value; |
1963 | serge | 658 | track->zb_dirty = true; |
1221 | serge | 659 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1120 | serge | 660 | break; |
661 | case R300_TX_OFFSET_0: |
||
662 | case R300_TX_OFFSET_0+4: |
||
663 | case R300_TX_OFFSET_0+8: |
||
664 | case R300_TX_OFFSET_0+12: |
||
665 | case R300_TX_OFFSET_0+16: |
||
666 | case R300_TX_OFFSET_0+20: |
||
667 | case R300_TX_OFFSET_0+24: |
||
668 | case R300_TX_OFFSET_0+28: |
||
669 | case R300_TX_OFFSET_0+32: |
||
670 | case R300_TX_OFFSET_0+36: |
||
671 | case R300_TX_OFFSET_0+40: |
||
672 | case R300_TX_OFFSET_0+44: |
||
673 | case R300_TX_OFFSET_0+48: |
||
674 | case R300_TX_OFFSET_0+52: |
||
675 | case R300_TX_OFFSET_0+56: |
||
676 | case R300_TX_OFFSET_0+60: |
||
677 | i = (reg - R300_TX_OFFSET_0) >> 2; |
||
3764 | Serge | 678 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1120 | serge | 679 | if (r) { |
680 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
681 | idx, reg); |
||
3764 | Serge | 682 | radeon_cs_dump_packet(p, pkt); |
1120 | serge | 683 | return r; |
684 | } |
||
1403 | serge | 685 | |
2997 | Serge | 686 | if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) { |
687 | ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ |
||
688 | ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset); |
||
689 | } else { |
||
1403 | serge | 690 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
691 | tile_flags |= R300_TXO_MACRO_TILE; |
||
692 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
||
693 | tile_flags |= R300_TXO_MICRO_TILE; |
||
1430 | serge | 694 | else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) |
695 | tile_flags |= R300_TXO_MICRO_TILE_SQUARE; |
||
1403 | serge | 696 | |
697 | tmp = idx_value + ((u32)reloc->lobj.gpu_offset); |
||
698 | tmp |= tile_flags; |
||
699 | ib[idx] = tmp; |
||
2997 | Serge | 700 | } |
1120 | serge | 701 | track->textures[i].robj = reloc->robj; |
1963 | serge | 702 | track->tex_dirty = true; |
1120 | serge | 703 | break; |
704 | /* Tracked registers */ |
||
705 | case 0x2084: |
||
706 | /* VAP_VF_CNTL */ |
||
1221 | serge | 707 | track->vap_vf_cntl = idx_value; |
1120 | serge | 708 | break; |
709 | case 0x20B4: |
||
710 | /* VAP_VTX_SIZE */ |
||
1221 | serge | 711 | track->vtx_size = idx_value & 0x7F; |
1120 | serge | 712 | break; |
713 | case 0x2134: |
||
714 | /* VAP_VF_MAX_VTX_INDX */ |
||
1221 | serge | 715 | track->max_indx = idx_value & 0x00FFFFFFUL; |
1120 | serge | 716 | break; |
1963 | serge | 717 | case 0x2088: |
718 | /* VAP_ALT_NUM_VERTICES - only valid on r500 */ |
||
719 | if (p->rdev->family < CHIP_RV515) |
||
720 | goto fail; |
||
721 | track->vap_alt_nverts = idx_value & 0xFFFFFF; |
||
722 | break; |
||
1120 | serge | 723 | case 0x43E4: |
724 | /* SC_SCISSOR1 */ |
||
1221 | serge | 725 | track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; |
1120 | serge | 726 | if (p->rdev->family < CHIP_RV515) { |
727 | track->maxy -= 1440; |
||
728 | } |
||
1963 | serge | 729 | track->cb_dirty = true; |
730 | track->zb_dirty = true; |
||
1120 | serge | 731 | break; |
732 | case 0x4E00: |
||
733 | /* RB3D_CCTL */ |
||
1963 | serge | 734 | if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ |
735 | p->rdev->cmask_filp != p->filp) { |
||
736 | DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); |
||
737 | return -EINVAL; |
||
738 | } |
||
1221 | serge | 739 | track->num_cb = ((idx_value >> 5) & 0x3) + 1; |
1963 | serge | 740 | track->cb_dirty = true; |
1120 | serge | 741 | break; |
742 | case 0x4E38: |
||
743 | case 0x4E3C: |
||
744 | case 0x4E40: |
||
745 | case 0x4E44: |
||
746 | /* RB3D_COLORPITCH0 */ |
||
747 | /* RB3D_COLORPITCH1 */ |
||
748 | /* RB3D_COLORPITCH2 */ |
||
749 | /* RB3D_COLORPITCH3 */ |
||
2997 | Serge | 750 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
3764 | Serge | 751 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1179 | serge | 752 | if (r) { |
753 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
754 | idx, reg); |
||
3764 | Serge | 755 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 756 | return r; |
757 | } |
||
758 | |||
759 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
||
760 | tile_flags |= R300_COLOR_TILE_ENABLE; |
||
761 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
||
762 | tile_flags |= R300_COLOR_MICROTILE_ENABLE; |
||
1430 | serge | 763 | else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) |
764 | tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; |
||
1179 | serge | 765 | |
1221 | serge | 766 | tmp = idx_value & ~(0x7 << 16); |
1179 | serge | 767 | tmp |= tile_flags; |
768 | ib[idx] = tmp; |
||
2997 | Serge | 769 | } |
1120 | serge | 770 | i = (reg - 0x4E38) >> 2; |
1221 | serge | 771 | track->cb[i].pitch = idx_value & 0x3FFE; |
772 | switch (((idx_value >> 21) & 0xF)) { |
||
1120 | serge | 773 | case 9: |
774 | case 11: |
||
775 | case 12: |
||
776 | track->cb[i].cpp = 1; |
||
777 | break; |
||
778 | case 3: |
||
779 | case 4: |
||
780 | case 13: |
||
781 | case 15: |
||
782 | track->cb[i].cpp = 2; |
||
783 | break; |
||
1963 | serge | 784 | case 5: |
785 | if (p->rdev->family < CHIP_RV515) { |
||
786 | DRM_ERROR("Invalid color buffer format (%d)!\n", |
||
787 | ((idx_value >> 21) & 0xF)); |
||
788 | return -EINVAL; |
||
789 | } |
||
790 | /* Pass through. */ |
||
1120 | serge | 791 | case 6: |
792 | track->cb[i].cpp = 4; |
||
793 | break; |
||
794 | case 10: |
||
795 | track->cb[i].cpp = 8; |
||
796 | break; |
||
797 | case 7: |
||
798 | track->cb[i].cpp = 16; |
||
799 | break; |
||
800 | default: |
||
801 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
||
1221 | serge | 802 | ((idx_value >> 21) & 0xF)); |
1120 | serge | 803 | return -EINVAL; |
804 | } |
||
1963 | serge | 805 | track->cb_dirty = true; |
1120 | serge | 806 | break; |
807 | case 0x4F00: |
||
808 | /* ZB_CNTL */ |
||
1221 | serge | 809 | if (idx_value & 2) { |
1120 | serge | 810 | track->z_enabled = true; |
811 | } else { |
||
812 | track->z_enabled = false; |
||
813 | } |
||
1963 | serge | 814 | track->zb_dirty = true; |
1120 | serge | 815 | break; |
816 | case 0x4F10: |
||
817 | /* ZB_FORMAT */ |
||
1221 | serge | 818 | switch ((idx_value & 0xF)) { |
1120 | serge | 819 | case 0: |
820 | case 1: |
||
821 | track->zb.cpp = 2; |
||
822 | break; |
||
823 | case 2: |
||
824 | track->zb.cpp = 4; |
||
825 | break; |
||
826 | default: |
||
827 | DRM_ERROR("Invalid z buffer format (%d) !\n", |
||
1221 | serge | 828 | (idx_value & 0xF)); |
1120 | serge | 829 | return -EINVAL; |
830 | } |
||
1963 | serge | 831 | track->zb_dirty = true; |
1120 | serge | 832 | break; |
833 | case 0x4F24: |
||
834 | /* ZB_DEPTHPITCH */ |
||
2997 | Serge | 835 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
3764 | Serge | 836 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1179 | serge | 837 | if (r) { |
838 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
839 | idx, reg); |
||
3764 | Serge | 840 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 841 | return r; |
842 | } |
||
843 | |||
844 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
||
845 | tile_flags |= R300_DEPTHMACROTILE_ENABLE; |
||
846 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
||
1430 | serge | 847 | tile_flags |= R300_DEPTHMICROTILE_TILED; |
848 | else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) |
||
849 | tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; |
||
1179 | serge | 850 | |
1221 | serge | 851 | tmp = idx_value & ~(0x7 << 16); |
1179 | serge | 852 | tmp |= tile_flags; |
853 | ib[idx] = tmp; |
||
2997 | Serge | 854 | } |
1221 | serge | 855 | track->zb.pitch = idx_value & 0x3FFC; |
1963 | serge | 856 | track->zb_dirty = true; |
1120 | serge | 857 | break; |
858 | case 0x4104: |
||
1963 | serge | 859 | /* TX_ENABLE */ |
1120 | serge | 860 | for (i = 0; i < 16; i++) { |
861 | bool enabled; |
||
862 | |||
1221 | serge | 863 | enabled = !!(idx_value & (1 << i)); |
1120 | serge | 864 | track->textures[i].enabled = enabled; |
865 | } |
||
1963 | serge | 866 | track->tex_dirty = true; |
1120 | serge | 867 | break; |
868 | case 0x44C0: |
||
869 | case 0x44C4: |
||
870 | case 0x44C8: |
||
871 | case 0x44CC: |
||
872 | case 0x44D0: |
||
873 | case 0x44D4: |
||
874 | case 0x44D8: |
||
875 | case 0x44DC: |
||
876 | case 0x44E0: |
||
877 | case 0x44E4: |
||
878 | case 0x44E8: |
||
879 | case 0x44EC: |
||
880 | case 0x44F0: |
||
881 | case 0x44F4: |
||
882 | case 0x44F8: |
||
883 | case 0x44FC: |
||
884 | /* TX_FORMAT1_[0-15] */ |
||
885 | i = (reg - 0x44C0) >> 2; |
||
1221 | serge | 886 | tmp = (idx_value >> 25) & 0x3; |
1120 | serge | 887 | track->textures[i].tex_coord_type = tmp; |
1221 | serge | 888 | switch ((idx_value & 0x1F)) { |
1179 | serge | 889 | case R300_TX_FORMAT_X8: |
890 | case R300_TX_FORMAT_Y4X4: |
||
891 | case R300_TX_FORMAT_Z3Y3X2: |
||
1120 | serge | 892 | track->textures[i].cpp = 1; |
1963 | serge | 893 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1120 | serge | 894 | break; |
1179 | serge | 895 | case R300_TX_FORMAT_X16: |
1963 | serge | 896 | case R300_TX_FORMAT_FL_I16: |
1179 | serge | 897 | case R300_TX_FORMAT_Y8X8: |
898 | case R300_TX_FORMAT_Z5Y6X5: |
||
899 | case R300_TX_FORMAT_Z6Y5X5: |
||
900 | case R300_TX_FORMAT_W4Z4Y4X4: |
||
901 | case R300_TX_FORMAT_W1Z5Y5X5: |
||
902 | case R300_TX_FORMAT_D3DMFT_CxV8U8: |
||
903 | case R300_TX_FORMAT_B8G8_B8G8: |
||
904 | case R300_TX_FORMAT_G8R8_G8B8: |
||
1120 | serge | 905 | track->textures[i].cpp = 2; |
1963 | serge | 906 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1120 | serge | 907 | break; |
1179 | serge | 908 | case R300_TX_FORMAT_Y16X16: |
1963 | serge | 909 | case R300_TX_FORMAT_FL_I16A16: |
1179 | serge | 910 | case R300_TX_FORMAT_Z11Y11X10: |
911 | case R300_TX_FORMAT_Z10Y11X11: |
||
912 | case R300_TX_FORMAT_W8Z8Y8X8: |
||
913 | case R300_TX_FORMAT_W2Z10Y10X10: |
||
914 | case 0x17: |
||
915 | case R300_TX_FORMAT_FL_I32: |
||
916 | case 0x1e: |
||
1120 | serge | 917 | track->textures[i].cpp = 4; |
1963 | serge | 918 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1120 | serge | 919 | break; |
1179 | serge | 920 | case R300_TX_FORMAT_W16Z16Y16X16: |
921 | case R300_TX_FORMAT_FL_R16G16B16A16: |
||
922 | case R300_TX_FORMAT_FL_I32A32: |
||
1120 | serge | 923 | track->textures[i].cpp = 8; |
1963 | serge | 924 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1120 | serge | 925 | break; |
1179 | serge | 926 | case R300_TX_FORMAT_FL_R32G32B32A32: |
1120 | serge | 927 | track->textures[i].cpp = 16; |
1963 | serge | 928 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1120 | serge | 929 | break; |
1403 | serge | 930 | case R300_TX_FORMAT_DXT1: |
931 | track->textures[i].cpp = 1; |
||
932 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
||
933 | break; |
||
934 | case R300_TX_FORMAT_ATI2N: |
||
935 | if (p->rdev->family < CHIP_R420) { |
||
936 | DRM_ERROR("Invalid texture format %u\n", |
||
937 | (idx_value & 0x1F)); |
||
938 | return -EINVAL; |
||
939 | } |
||
940 | /* The same rules apply as for DXT3/5. */ |
||
941 | /* Pass through. */ |
||
942 | case R300_TX_FORMAT_DXT3: |
||
943 | case R300_TX_FORMAT_DXT5: |
||
944 | track->textures[i].cpp = 1; |
||
945 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; |
||
946 | break; |
||
1120 | serge | 947 | default: |
948 | DRM_ERROR("Invalid texture format %u\n", |
||
1221 | serge | 949 | (idx_value & 0x1F)); |
1120 | serge | 950 | return -EINVAL; |
951 | } |
||
1963 | serge | 952 | track->tex_dirty = true; |
1120 | serge | 953 | break; |
954 | case 0x4400: |
||
955 | case 0x4404: |
||
956 | case 0x4408: |
||
957 | case 0x440C: |
||
958 | case 0x4410: |
||
959 | case 0x4414: |
||
960 | case 0x4418: |
||
961 | case 0x441C: |
||
962 | case 0x4420: |
||
963 | case 0x4424: |
||
964 | case 0x4428: |
||
965 | case 0x442C: |
||
966 | case 0x4430: |
||
967 | case 0x4434: |
||
968 | case 0x4438: |
||
969 | case 0x443C: |
||
970 | /* TX_FILTER0_[0-15] */ |
||
971 | i = (reg - 0x4400) >> 2; |
||
1221 | serge | 972 | tmp = idx_value & 0x7; |
1120 | serge | 973 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
974 | track->textures[i].roundup_w = false; |
||
975 | } |
||
1221 | serge | 976 | tmp = (idx_value >> 3) & 0x7; |
1120 | serge | 977 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
978 | track->textures[i].roundup_h = false; |
||
979 | } |
||
1963 | serge | 980 | track->tex_dirty = true; |
1120 | serge | 981 | break; |
982 | case 0x4500: |
||
983 | case 0x4504: |
||
984 | case 0x4508: |
||
985 | case 0x450C: |
||
986 | case 0x4510: |
||
987 | case 0x4514: |
||
988 | case 0x4518: |
||
989 | case 0x451C: |
||
990 | case 0x4520: |
||
991 | case 0x4524: |
||
992 | case 0x4528: |
||
993 | case 0x452C: |
||
994 | case 0x4530: |
||
995 | case 0x4534: |
||
996 | case 0x4538: |
||
997 | case 0x453C: |
||
998 | /* TX_FORMAT2_[0-15] */ |
||
999 | i = (reg - 0x4500) >> 2; |
||
1221 | serge | 1000 | tmp = idx_value & 0x3FFF; |
1120 | serge | 1001 | track->textures[i].pitch = tmp + 1; |
1002 | if (p->rdev->family >= CHIP_RV515) { |
||
1221 | serge | 1003 | tmp = ((idx_value >> 15) & 1) << 11; |
1120 | serge | 1004 | track->textures[i].width_11 = tmp; |
1221 | serge | 1005 | tmp = ((idx_value >> 16) & 1) << 11; |
1120 | serge | 1006 | track->textures[i].height_11 = tmp; |
1403 | serge | 1007 | |
1008 | /* ATI1N */ |
||
1009 | if (idx_value & (1 << 14)) { |
||
1010 | /* The same rules apply as for DXT1. */ |
||
1011 | track->textures[i].compress_format = |
||
1012 | R100_TRACK_COMP_DXT1; |
||
1013 | } |
||
1014 | } else if (idx_value & (1 << 14)) { |
||
1015 | DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); |
||
1016 | return -EINVAL; |
||
1120 | serge | 1017 | } |
1963 | serge | 1018 | track->tex_dirty = true; |
1120 | serge | 1019 | break; |
1020 | case 0x4480: |
||
1021 | case 0x4484: |
||
1022 | case 0x4488: |
||
1023 | case 0x448C: |
||
1024 | case 0x4490: |
||
1025 | case 0x4494: |
||
1026 | case 0x4498: |
||
1027 | case 0x449C: |
||
1028 | case 0x44A0: |
||
1029 | case 0x44A4: |
||
1030 | case 0x44A8: |
||
1031 | case 0x44AC: |
||
1032 | case 0x44B0: |
||
1033 | case 0x44B4: |
||
1034 | case 0x44B8: |
||
1035 | case 0x44BC: |
||
1036 | /* TX_FORMAT0_[0-15] */ |
||
1037 | i = (reg - 0x4480) >> 2; |
||
1221 | serge | 1038 | tmp = idx_value & 0x7FF; |
1120 | serge | 1039 | track->textures[i].width = tmp + 1; |
1221 | serge | 1040 | tmp = (idx_value >> 11) & 0x7FF; |
1120 | serge | 1041 | track->textures[i].height = tmp + 1; |
1221 | serge | 1042 | tmp = (idx_value >> 26) & 0xF; |
1120 | serge | 1043 | track->textures[i].num_levels = tmp; |
1221 | serge | 1044 | tmp = idx_value & (1 << 31); |
1120 | serge | 1045 | track->textures[i].use_pitch = !!tmp; |
1221 | serge | 1046 | tmp = (idx_value >> 22) & 0xF; |
1120 | serge | 1047 | track->textures[i].txdepth = tmp; |
1963 | serge | 1048 | track->tex_dirty = true; |
1120 | serge | 1049 | break; |
1179 | serge | 1050 | case R300_ZB_ZPASS_ADDR: |
3764 | Serge | 1051 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1179 | serge | 1052 | if (r) { |
1053 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1054 | idx, reg); |
||
3764 | Serge | 1055 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 1056 | return r; |
1057 | } |
||
1221 | serge | 1058 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1179 | serge | 1059 | break; |
1403 | serge | 1060 | case 0x4e0c: |
1061 | /* RB3D_COLOR_CHANNEL_MASK */ |
||
1062 | track->color_channel_mask = idx_value; |
||
1963 | serge | 1063 | track->cb_dirty = true; |
1403 | serge | 1064 | break; |
1963 | serge | 1065 | case 0x43a4: |
1066 | /* SC_HYPERZ_EN */ |
||
1067 | /* r300c emits this register - we need to disable hyperz for it |
||
1068 | * without complaining */ |
||
1069 | if (p->rdev->hyperz_filp != p->filp) { |
||
1070 | if (idx_value & 0x1) |
||
1071 | ib[idx] = idx_value & ~1; |
||
1072 | } |
||
1073 | break; |
||
1074 | case 0x4f1c: |
||
1403 | serge | 1075 | /* ZB_BW_CNTL */ |
1963 | serge | 1076 | track->zb_cb_clear = !!(idx_value & (1 << 5)); |
1077 | track->cb_dirty = true; |
||
1078 | track->zb_dirty = true; |
||
1079 | if (p->rdev->hyperz_filp != p->filp) { |
||
1080 | if (idx_value & (R300_HIZ_ENABLE | |
||
1081 | R300_RD_COMP_ENABLE | |
||
1082 | R300_WR_COMP_ENABLE | |
||
1083 | R300_FAST_FILL_ENABLE)) |
||
1084 | goto fail; |
||
1085 | } |
||
1403 | serge | 1086 | break; |
1087 | case 0x4e04: |
||
1088 | /* RB3D_BLENDCNTL */ |
||
1089 | track->blend_read_enable = !!(idx_value & (1 << 2)); |
||
1963 | serge | 1090 | track->cb_dirty = true; |
1403 | serge | 1091 | break; |
1963 | serge | 1092 | case R300_RB3D_AARESOLVE_OFFSET: |
3764 | Serge | 1093 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1963 | serge | 1094 | if (r) { |
1095 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1096 | idx, reg); |
||
3764 | Serge | 1097 | radeon_cs_dump_packet(p, pkt); |
1963 | serge | 1098 | return r; |
1099 | } |
||
1100 | track->aa.robj = reloc->robj; |
||
1101 | track->aa.offset = idx_value; |
||
1102 | track->aa_dirty = true; |
||
1103 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
||
1104 | break; |
||
1105 | case R300_RB3D_AARESOLVE_PITCH: |
||
1106 | track->aa.pitch = idx_value & 0x3FFE; |
||
1107 | track->aa_dirty = true; |
||
1108 | break; |
||
1109 | case R300_RB3D_AARESOLVE_CTL: |
||
1110 | track->aaresolve = idx_value & 0x1; |
||
1111 | track->aa_dirty = true; |
||
1112 | break; |
||
1113 | case 0x4f30: /* ZB_MASK_OFFSET */ |
||
1114 | case 0x4f34: /* ZB_ZMASK_PITCH */ |
||
1115 | case 0x4f44: /* ZB_HIZ_OFFSET */ |
||
1116 | case 0x4f54: /* ZB_HIZ_PITCH */ |
||
1117 | if (idx_value && (p->rdev->hyperz_filp != p->filp)) |
||
1118 | goto fail; |
||
1119 | break; |
||
1120 | case 0x4028: |
||
1121 | if (idx_value && (p->rdev->hyperz_filp != p->filp)) |
||
1122 | goto fail; |
||
1123 | /* GB_Z_PEQ_CONFIG */ |
||
1124 | if (p->rdev->family >= CHIP_RV350) |
||
1125 | break; |
||
1126 | goto fail; |
||
1127 | break; |
||
1179 | serge | 1128 | case 0x4be8: |
1129 | /* valid register only on RV530 */ |
||
1130 | if (p->rdev->family == CHIP_RV530) |
||
1131 | break; |
||
1132 | /* fallthrough do not move */ |
||
1120 | serge | 1133 | default: |
1963 | serge | 1134 | goto fail; |
1120 | serge | 1135 | } |
1136 | return 0; |
||
1963 | serge | 1137 | fail: |
1138 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n", |
||
1139 | reg, idx, idx_value); |
||
1140 | return -EINVAL; |
||
1120 | serge | 1141 | } |
1142 | |||
1143 | static int r300_packet3_check(struct radeon_cs_parser *p, |
||
1144 | struct radeon_cs_packet *pkt) |
||
1145 | { |
||
1146 | struct radeon_cs_reloc *reloc; |
||
1179 | serge | 1147 | struct r100_cs_track *track; |
1120 | serge | 1148 | volatile uint32_t *ib; |
1149 | unsigned idx; |
||
1150 | int r; |
||
1151 | |||
2997 | Serge | 1152 | ib = p->ib.ptr; |
1120 | serge | 1153 | idx = pkt->idx + 1; |
1179 | serge | 1154 | track = (struct r100_cs_track *)p->track; |
1120 | serge | 1155 | switch(pkt->opcode) { |
1156 | case PACKET3_3D_LOAD_VBPNTR: |
||
1221 | serge | 1157 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
1158 | if (r) |
||
1120 | serge | 1159 | return r; |
1160 | break; |
||
1161 | case PACKET3_INDX_BUFFER: |
||
3764 | Serge | 1162 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1120 | serge | 1163 | if (r) { |
1164 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
||
3764 | Serge | 1165 | radeon_cs_dump_packet(p, pkt); |
1120 | serge | 1166 | return r; |
1167 | } |
||
1221 | serge | 1168 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); |
1120 | serge | 1169 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1170 | if (r) { |
||
1171 | return r; |
||
1172 | } |
||
1173 | break; |
||
1174 | /* Draw packet */ |
||
1175 | case PACKET3_3D_DRAW_IMMD: |
||
1176 | /* Number of dwords is vtx_size * (num_vertices - 1) |
||
1177 | * PRIM_WALK must be equal to 3 vertex data in embedded |
||
1178 | * in cmd stream */ |
||
1221 | serge | 1179 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
1120 | serge | 1180 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1181 | return -EINVAL; |
||
1182 | } |
||
1221 | serge | 1183 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1120 | serge | 1184 | track->immd_dwords = pkt->count - 1; |
1179 | serge | 1185 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1186 | if (r) { |
1187 | return r; |
||
1188 | } |
||
1189 | break; |
||
1190 | case PACKET3_3D_DRAW_IMMD_2: |
||
1191 | /* Number of dwords is vtx_size * (num_vertices - 1) |
||
1192 | * PRIM_WALK must be equal to 3 vertex data in embedded |
||
1193 | * in cmd stream */ |
||
1221 | serge | 1194 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
1120 | serge | 1195 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1196 | return -EINVAL; |
||
1197 | } |
||
1221 | serge | 1198 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1120 | serge | 1199 | track->immd_dwords = pkt->count; |
1179 | serge | 1200 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1201 | if (r) { |
1202 | return r; |
||
1203 | } |
||
1204 | break; |
||
1205 | case PACKET3_3D_DRAW_VBUF: |
||
1221 | serge | 1206 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1179 | serge | 1207 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1208 | if (r) { |
1209 | return r; |
||
1210 | } |
||
1211 | break; |
||
1212 | case PACKET3_3D_DRAW_VBUF_2: |
||
1221 | serge | 1213 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1179 | serge | 1214 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1215 | if (r) { |
1216 | return r; |
||
1217 | } |
||
1218 | break; |
||
1219 | case PACKET3_3D_DRAW_INDX: |
||
1221 | serge | 1220 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1179 | serge | 1221 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1222 | if (r) { |
1223 | return r; |
||
1224 | } |
||
1225 | break; |
||
1226 | case PACKET3_3D_DRAW_INDX_2: |
||
1221 | serge | 1227 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1179 | serge | 1228 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1229 | if (r) { |
1230 | return r; |
||
1231 | } |
||
1232 | break; |
||
1963 | serge | 1233 | case PACKET3_3D_CLEAR_HIZ: |
1234 | case PACKET3_3D_CLEAR_ZMASK: |
||
1235 | if (p->rdev->hyperz_filp != p->filp) |
||
1236 | return -EINVAL; |
||
1237 | break; |
||
1238 | case PACKET3_3D_CLEAR_CMASK: |
||
1239 | if (p->rdev->cmask_filp != p->filp) |
||
1240 | return -EINVAL; |
||
1241 | break; |
||
1120 | serge | 1242 | case PACKET3_NOP: |
1243 | break; |
||
1244 | default: |
||
1245 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); |
||
1246 | return -EINVAL; |
||
1247 | } |
||
1248 | return 0; |
||
1249 | } |
||
1250 | |||
1251 | int r300_cs_parse(struct radeon_cs_parser *p) |
||
1252 | { |
||
1253 | struct radeon_cs_packet pkt; |
||
1179 | serge | 1254 | struct r100_cs_track *track; |
1120 | serge | 1255 | int r; |
1256 | |||
1179 | serge | 1257 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
1963 | serge | 1258 | if (track == NULL) |
1259 | return -ENOMEM; |
||
1179 | serge | 1260 | r100_cs_track_clear(p->rdev, track); |
1261 | p->track = track; |
||
1120 | serge | 1262 | do { |
3764 | Serge | 1263 | r = radeon_cs_packet_parse(p, &pkt, p->idx); |
1120 | serge | 1264 | if (r) { |
1265 | return r; |
||
1266 | } |
||
1267 | p->idx += pkt.count + 2; |
||
1268 | switch (pkt.type) { |
||
3764 | Serge | 1269 | case RADEON_PACKET_TYPE0: |
1120 | serge | 1270 | r = r100_cs_parse_packet0(p, &pkt, |
1271 | p->rdev->config.r300.reg_safe_bm, |
||
1272 | p->rdev->config.r300.reg_safe_bm_size, |
||
1273 | &r300_packet0_check); |
||
1274 | break; |
||
3764 | Serge | 1275 | case RADEON_PACKET_TYPE2: |
1120 | serge | 1276 | break; |
3764 | Serge | 1277 | case RADEON_PACKET_TYPE3: |
1120 | serge | 1278 | r = r300_packet3_check(p, &pkt); |
1279 | break; |
||
1280 | default: |
||
1281 | DRM_ERROR("Unknown packet type %d !\n", pkt.type); |
||
1282 | return -EINVAL; |
||
1283 | } |
||
1284 | if (r) { |
||
1285 | return r; |
||
1286 | } |
||
1287 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
||
1288 | return 0; |
||
1289 | } |
||
1128 | serge | 1290 | #endif |
1291 | |||
1179 | serge | 1292 | |
1293 | void r300_set_reg_safe(struct radeon_device *rdev) |
||
1120 | serge | 1294 | { |
1295 | rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; |
||
1296 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); |
||
1179 | serge | 1297 | } |
1298 | |||
1299 | void r300_mc_program(struct radeon_device *rdev) |
||
1300 | { |
||
1301 | struct r100_mc_save save; |
||
1302 | int r; |
||
1120 | serge | 1303 | |
1179 | serge | 1304 | r = r100_debugfs_mc_info_init(rdev); |
1305 | if (r) { |
||
1306 | dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); |
||
1307 | } |
||
1308 | |||
1309 | /* Stops all mc clients */ |
||
1310 | r100_mc_stop(rdev, &save); |
||
1311 | if (rdev->flags & RADEON_IS_AGP) { |
||
1312 | WREG32(R_00014C_MC_AGP_LOCATION, |
||
1313 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
||
1314 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
||
1315 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
||
1316 | WREG32(R_00015C_AGP_BASE_2, |
||
1317 | upper_32_bits(rdev->mc.agp_base) & 0xff); |
||
1318 | } else { |
||
1319 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); |
||
1320 | WREG32(R_000170_AGP_BASE, 0); |
||
1321 | WREG32(R_00015C_AGP_BASE_2, 0); |
||
1322 | } |
||
1323 | /* Wait for mc idle */ |
||
1324 | if (r300_mc_wait_for_idle(rdev)) |
||
1325 | DRM_INFO("Failed to wait MC idle before programming MC.\n"); |
||
1326 | /* Program MC, should be a 32bits limited address space */ |
||
1327 | WREG32(R_000148_MC_FB_LOCATION, |
||
1328 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
||
1329 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
||
1330 | r100_mc_resume(rdev, &save); |
||
1331 | } |
||
1221 | serge | 1332 | |
1333 | void r300_clock_startup(struct radeon_device *rdev) |
||
1334 | { |
||
1335 | u32 tmp; |
||
1336 | |||
1337 | if (radeon_dynclks != -1 && radeon_dynclks) |
||
1338 | radeon_legacy_set_clock_gating(rdev, 1); |
||
1339 | /* We need to force on some of the block */ |
||
1340 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); |
||
1341 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
||
1342 | if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) |
||
1343 | tmp |= S_00000D_FORCE_VAP(1); |
||
1344 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); |
||
1345 | } |
||
1346 | |||
1347 | static int r300_startup(struct radeon_device *rdev) |
||
1348 | { |
||
1349 | int r; |
||
1350 | |||
1321 | serge | 1351 | /* set common regs */ |
1352 | r100_set_common_regs(rdev); |
||
1353 | /* program mc */ |
||
1221 | serge | 1354 | r300_mc_program(rdev); |
1355 | /* Resume clock */ |
||
1356 | r300_clock_startup(rdev); |
||
1357 | /* Initialize GPU configuration (# pipes, ...) */ |
||
1358 | r300_gpu_init(rdev); |
||
1359 | /* Initialize GART (initialize after TTM so we can allocate |
||
1360 | * memory through TTM but finalize after TTM) */ |
||
1361 | if (rdev->flags & RADEON_IS_PCIE) { |
||
1362 | r = rv370_pcie_gart_enable(rdev); |
||
1363 | if (r) |
||
1364 | return r; |
||
1365 | } |
||
1321 | serge | 1366 | |
1367 | if (rdev->family == CHIP_R300 || |
||
1368 | rdev->family == CHIP_R350 || |
||
1369 | rdev->family == CHIP_RV350) |
||
1370 | r100_enable_bm(rdev); |
||
1371 | |||
1221 | serge | 1372 | if (rdev->flags & RADEON_IS_PCI) { |
1373 | r = r100_pci_gart_enable(rdev); |
||
1374 | if (r) |
||
1375 | return r; |
||
1376 | } |
||
1963 | serge | 1377 | |
2005 | serge | 1378 | /* allocate wb buffer */ |
1379 | r = radeon_wb_init(rdev); |
||
1380 | if (r) |
||
1381 | return r; |
||
1963 | serge | 1382 | |
3120 | serge | 1383 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
1384 | if (r) { |
||
1385 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
||
1386 | return r; |
||
1387 | } |
||
1388 | |||
1221 | serge | 1389 | /* Enable IRQ */ |
3764 | Serge | 1390 | if (!rdev->irq.installed) { |
1391 | r = radeon_irq_kms_init(rdev); |
||
1392 | if (r) |
||
1393 | return r; |
||
1394 | } |
||
1395 | |||
2005 | serge | 1396 | r100_irq_set(rdev); |
1403 | serge | 1397 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1221 | serge | 1398 | /* 1M ring buffer */ |
1412 | serge | 1399 | r = r100_cp_init(rdev, 1024 * 1024); |
1400 | if (r) { |
||
1963 | serge | 1401 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
1412 | serge | 1402 | return r; |
1403 | } |
||
2997 | Serge | 1404 | |
1405 | r = radeon_ib_pool_init(rdev); |
||
2005 | serge | 1406 | if (r) { |
2997 | Serge | 1407 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
2005 | serge | 1408 | return r; |
1409 | } |
||
2997 | Serge | 1410 | |
1221 | serge | 1411 | return 0; |
1412 | } |
||
1413 | |||
1414 | |||
1415 | |||
1416 | |||
1417 | |||
1418 | int r300_init(struct radeon_device *rdev) |
||
1419 | { |
||
1420 | int r; |
||
1421 | |||
1422 | /* Disable VGA */ |
||
1423 | r100_vga_render_disable(rdev); |
||
1424 | /* Initialize scratch registers */ |
||
1425 | radeon_scratch_init(rdev); |
||
1426 | /* Initialize surface registers */ |
||
1427 | radeon_surface_init(rdev); |
||
1428 | /* TODO: disable VGA need to use VGA request */ |
||
1963 | serge | 1429 | /* restore some register to sane defaults */ |
1430 | r100_restore_sanity(rdev); |
||
1221 | serge | 1431 | /* BIOS*/ |
1432 | if (!radeon_get_bios(rdev)) { |
||
1433 | if (ASIC_IS_AVIVO(rdev)) |
||
1434 | return -EINVAL; |
||
1435 | } |
||
1436 | if (rdev->is_atom_bios) { |
||
1437 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); |
||
1438 | return -EINVAL; |
||
1439 | } else { |
||
1440 | r = radeon_combios_init(rdev); |
||
1441 | if (r) |
||
1442 | return r; |
||
1443 | } |
||
1444 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
1963 | serge | 1445 | if (radeon_asic_reset(rdev)) { |
1221 | serge | 1446 | dev_warn(rdev->dev, |
1447 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
||
1448 | RREG32(R_000E40_RBBM_STATUS), |
||
1449 | RREG32(R_0007C0_CP_STAT)); |
||
1450 | } |
||
1451 | /* check if cards are posted or not */ |
||
1321 | serge | 1452 | if (radeon_boot_test_post_card(rdev) == false) |
1453 | return -EINVAL; |
||
1221 | serge | 1454 | /* Set asic errata */ |
1455 | r300_errata(rdev); |
||
1456 | /* Initialize clocks */ |
||
1457 | radeon_get_clock_info(rdev->ddev); |
||
1430 | serge | 1458 | /* initialize AGP */ |
1459 | if (rdev->flags & RADEON_IS_AGP) { |
||
1460 | r = radeon_agp_init(rdev); |
||
1461 | if (r) { |
||
1462 | radeon_agp_disable(rdev); |
||
1463 | } |
||
1464 | } |
||
1465 | /* initialize memory controller */ |
||
1466 | r300_mc_init(rdev); |
||
1221 | serge | 1467 | /* Fence driver */ |
2005 | serge | 1468 | r = radeon_fence_driver_init(rdev); |
1469 | if (r) |
||
1470 | return r; |
||
1221 | serge | 1471 | /* Memory manager */ |
1404 | serge | 1472 | r = radeon_bo_init(rdev); |
1221 | serge | 1473 | if (r) |
1474 | return r; |
||
1475 | if (rdev->flags & RADEON_IS_PCIE) { |
||
1476 | r = rv370_pcie_gart_init(rdev); |
||
1477 | if (r) |
||
1478 | return r; |
||
1479 | } |
||
1480 | if (rdev->flags & RADEON_IS_PCI) { |
||
1481 | r = r100_pci_gart_init(rdev); |
||
1482 | if (r) |
||
1483 | return r; |
||
1484 | } |
||
1485 | r300_set_reg_safe(rdev); |
||
2997 | Serge | 1486 | |
1221 | serge | 1487 | rdev->accel_working = true; |
1488 | r = r300_startup(rdev); |
||
1489 | if (r) { |
||
1490 | /* Somethings want wront with the accel init stop accel */ |
||
1491 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
||
1492 | if (rdev->flags & RADEON_IS_PCIE) |
||
1493 | rv370_pcie_gart_fini(rdev); |
||
1494 | if (rdev->flags & RADEON_IS_PCI) |
||
1495 | r100_pci_gart_fini(rdev); |
||
1496 | rdev->accel_working = false; |
||
1497 | } |
||
1498 | return 0; |
||
1499 | }>><>><>><>><>><>><>><>>><>>><>>><>><>>>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>> |