WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r300.c

Rev	Author	Line No.	Line
1120	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1179	serge	28	#include
1125	serge	29	#include "drmP.h"
		30	#include "drm.h"
1120	serge	31	#include "radeon_reg.h"
		32	#include "radeon.h"
1179	serge	33	#include "radeon_drm.h"
1120	serge	34
1179	serge	35	#include "r300d.h"
1221	serge	36	#include "rv350d.h"
1179	serge	37	#include "r300_reg_safe.h"
		38
1403	serge	39	/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
		40	*
		41	* GPU Errata:
		42	* - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
		43	* using MMIO to flush host path read cache, this lead to HARDLOCKUP.
		44	* However, scheduling such write to the ring seems harmless, i suspect
		45	* the CP read collide with the flush somehow, or maybe the MC, hard to
		46	* tell. (Jerome Glisse)
		47	*/
1120	serge	48
		49	/*
		50	* rv370,rv380 PCIE GART
		51	*/
1221	serge	52	static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
		53
1120	serge	54	void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
		55	{
		56	uint32_t tmp;
		57	int i;
		58
		59	/* Workaround HW bug do flush 2 times */
		60	for (i = 0; i < 2; i++) {
		61	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		62	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp \| RADEON_PCIE_TX_GART_INVALIDATE_TLB);
		63	(void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		64	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
1179	serge	65	}
1120	serge	66	mb();
1179	serge	67	}
		68
		69	int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
		70	{
		71	void __iomem ptr = (void )rdev->gart.table.vram.ptr;
		72
		73	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
		74	return -EINVAL;
1120	serge	75	}
1179	serge	76	addr = (lower_32_bits(addr) >> 8) \|
		77	((upper_32_bits(addr) & 0xff) << 24) \|
		78	0xc;
		79	/* on x86 we want this to be CPU endian, on powerpc
		80	* on powerpc without HW swappers, it'll get swapped on way
		81	* into VRAM - so no need for cpu_to_le32 on VRAM tables */
		82	writel(addr, ((void __iomem )ptr) + (i 4));
		83	return 0;
1120	serge	84	}
		85
1179	serge	86	int rv370_pcie_gart_init(struct radeon_device *rdev)
1120	serge	87	{
		88	int r;
		89
1179	serge	90	if (rdev->gart.table.vram.robj) {
		91	WARN(1, "RV370 PCIE GART already initialized.\n");
		92	return 0;
		93	}
1120	serge	94	/* Initialize common gart structure */
		95	r = radeon_gart_init(rdev);
1179	serge	96	if (r)
1120	serge	97	return r;
1129	serge	98	r = rv370_debugfs_pcie_gart_info_init(rdev);
1179	serge	99	if (r)
1129	serge	100	DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
1179	serge	101	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
		102	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
		103	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
		104	return radeon_gart_table_vram_alloc(rdev);
		105	}
		106
		107	int rv370_pcie_gart_enable(struct radeon_device *rdev)
		108	{
		109	uint32_t table_addr;
		110	uint32_t tmp;
		111	int r;
		112
		113	if (rdev->gart.table.vram.robj == NULL) {
		114	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
		115	return -EINVAL;
1129	serge	116	}
1179	serge	117	r = radeon_gart_table_vram_pin(rdev);
		118	if (r)
1120	serge	119	return r;
		120	/* discard memory request outside of configured range */
		121	tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		122	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
		123	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
1268	serge	124	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - RADEON_GPU_PAGE_SIZE;
1120	serge	125	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
		126	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
		127	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
		128	table_addr = rdev->gart.table_addr;
		129	WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
		130	/* FIXME: setup default page */
		131	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location);
		132	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
		133	/* Clear error */
		134	WREG32_PCIE(0x18, 0);
		135	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		136	tmp \|= RADEON_PCIE_TX_GART_EN;
		137	tmp \|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		138	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
		139	rv370_pcie_gart_tlb_flush(rdev);
		140	DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
1179	serge	141	(unsigned)(rdev->mc.gtt_size >> 20), table_addr);
1120	serge	142	rdev->gart.ready = true;
		143	return 0;
		144	}
		145
		146	void rv370_pcie_gart_disable(struct radeon_device *rdev)
		147	{
1321	serge	148	u32 tmp;
		149	int r;
1120	serge	150
		151	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		152	tmp \|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		153	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
		154	if (rdev->gart.table.vram.robj) {
1404	serge	155	r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
		156	if (likely(r == 0)) {
		157	radeon_bo_kunmap(rdev->gart.table.vram.robj);
		158	radeon_bo_unpin(rdev->gart.table.vram.robj);
		159	radeon_bo_unreserve(rdev->gart.table.vram.robj);
		160	}
1120	serge	161	}
		162	}
		163
1179	serge	164	void rv370_pcie_gart_fini(struct radeon_device *rdev)
1120	serge	165	{
		166	rv370_pcie_gart_disable(rdev);
1179	serge	167	radeon_gart_table_vram_free(rdev);
		168	radeon_gart_fini(rdev);
1120	serge	169	}
		170
		171	void r300_fence_ring_emit(struct radeon_device *rdev,
		172	struct radeon_fence *fence)
		173	{
		174	/* Who ever call radeon_fence_emit should call ring_lock and ask
		175	* for enough space (today caller are ib schedule and buffer move) */
		176	/* Write SC register so SC & US assert idle */
		177	radeon_ring_write(rdev, PACKET0(0x43E0, 0));
		178	radeon_ring_write(rdev, 0);
		179	radeon_ring_write(rdev, PACKET0(0x43E4, 0));
		180	radeon_ring_write(rdev, 0);
		181	/* Flush 3D cache */
		182	radeon_ring_write(rdev, PACKET0(0x4E4C, 0));
		183	radeon_ring_write(rdev, (2 << 0));
		184	radeon_ring_write(rdev, PACKET0(0x4F18, 0));
		185	radeon_ring_write(rdev, (1 << 0));
		186	/* Wait until IDLE & CLEAN */
		187	radeon_ring_write(rdev, PACKET0(0x1720, 0));
		188	radeon_ring_write(rdev, (1 << 17) \| (1 << 16) \| (1 << 9));
1403	serge	189	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		190	radeon_ring_write(rdev, rdev->config.r300.hdp_cntl \|
		191	RADEON_HDP_READ_BUFFER_INVALIDATE);
		192	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		193	radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
1120	serge	194	/* Emit fence sequence & fire IRQ */
		195	radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
		196	radeon_ring_write(rdev, fence->seq);
		197	radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
		198	radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
		199	}
		200
		201
1128	serge	202	#if 0
		203
1221	serge	204
1120	serge	205	int r300_copy_dma(struct radeon_device *rdev,
		206	uint64_t src_offset,
		207	uint64_t dst_offset,
		208	unsigned num_pages,
		209	struct radeon_fence *fence)
		210	{
		211	uint32_t size;
		212	uint32_t cur_size;
		213	int i, num_loops;
		214	int r = 0;
		215
		216	/* radeon pitch is /64 */
		217	size = num_pages << PAGE_SHIFT;
		218	num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
		219	r = radeon_ring_lock(rdev, num_loops * 4 + 64);
		220	if (r) {
		221	DRM_ERROR("radeon: moving bo (%d).\n", r);
		222	return r;
		223	}
		224	/* Must wait for 2D idle & clean before DMA or hangs might happen */
		225	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 ));
		226	radeon_ring_write(rdev, (1 << 16));
		227	for (i = 0; i < num_loops; i++) {
		228	cur_size = size;
		229	if (cur_size > 0x1FFFFF) {
		230	cur_size = 0x1FFFFF;
		231	}
		232	size -= cur_size;
		233	radeon_ring_write(rdev, PACKET0(0x720, 2));
		234	radeon_ring_write(rdev, src_offset);
		235	radeon_ring_write(rdev, dst_offset);
		236	radeon_ring_write(rdev, cur_size \| (1 << 31) \| (1 << 30));
		237	src_offset += cur_size;
		238	dst_offset += cur_size;
		239	}
		240	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		241	radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
		242	if (fence) {
		243	r = radeon_fence_emit(rdev, fence);
		244	}
		245	radeon_ring_unlock_commit(rdev);
		246	return r;
		247	}
		248
1128	serge	249	#endif
		250
1120	serge	251	void r300_ring_start(struct radeon_device *rdev)
		252	{
		253	unsigned gb_tile_config;
		254	int r;
		255
		256	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
		257	gb_tile_config = (R300_ENABLE_TILING \| R300_TILE_SIZE_16);
		258	switch(rdev->num_gb_pipes) {
		259	case 2:
		260	gb_tile_config \|= R300_PIPE_COUNT_R300;
		261	break;
		262	case 3:
		263	gb_tile_config \|= R300_PIPE_COUNT_R420_3P;
		264	break;
		265	case 4:
		266	gb_tile_config \|= R300_PIPE_COUNT_R420;
		267	break;
		268	case 1:
		269	default:
		270	gb_tile_config \|= R300_PIPE_COUNT_RV350;
		271	break;
		272	}
		273
		274	r = radeon_ring_lock(rdev, 64);
		275	if (r) {
		276	return;
		277	}
		278	radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
		279	radeon_ring_write(rdev,
		280	RADEON_ISYNC_ANY2D_IDLE3D \|
		281	RADEON_ISYNC_ANY3D_IDLE2D \|
		282	RADEON_ISYNC_WAIT_IDLEGUI \|
		283	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
		284	radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
		285	radeon_ring_write(rdev, gb_tile_config);
		286	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		287	radeon_ring_write(rdev,
		288	RADEON_WAIT_2D_IDLECLEAN \|
		289	RADEON_WAIT_3D_IDLECLEAN);
		290	radeon_ring_write(rdev, PACKET0(0x170C, 0));
		291	radeon_ring_write(rdev, 1 << 31);
		292	radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
		293	radeon_ring_write(rdev, 0);
		294	radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
		295	radeon_ring_write(rdev, 0);
		296	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
		297	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH \| R300_RB3D_DC_FREE);
		298	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
		299	radeon_ring_write(rdev, R300_ZC_FLUSH \| R300_ZC_FREE);
		300	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		301	radeon_ring_write(rdev,
		302	RADEON_WAIT_2D_IDLECLEAN \|
		303	RADEON_WAIT_3D_IDLECLEAN);
		304	radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
		305	radeon_ring_write(rdev, 0);
		306	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
		307	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH \| R300_RB3D_DC_FREE);
		308	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
		309	radeon_ring_write(rdev, R300_ZC_FLUSH \| R300_ZC_FREE);
		310	radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
		311	radeon_ring_write(rdev,
		312	((6 << R300_MS_X0_SHIFT) \|
		313	(6 << R300_MS_Y0_SHIFT) \|
		314	(6 << R300_MS_X1_SHIFT) \|
		315	(6 << R300_MS_Y1_SHIFT) \|
		316	(6 << R300_MS_X2_SHIFT) \|
		317	(6 << R300_MS_Y2_SHIFT) \|
		318	(6 << R300_MSBD0_Y_SHIFT) \|
		319	(6 << R300_MSBD0_X_SHIFT)));
		320	radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
		321	radeon_ring_write(rdev,
		322	((6 << R300_MS_X3_SHIFT) \|
		323	(6 << R300_MS_Y3_SHIFT) \|
		324	(6 << R300_MS_X4_SHIFT) \|
		325	(6 << R300_MS_Y4_SHIFT) \|
		326	(6 << R300_MS_X5_SHIFT) \|
		327	(6 << R300_MS_Y5_SHIFT) \|
		328	(6 << R300_MSBD1_SHIFT)));
		329	radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
		330	radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL \| R300_GA_FASTSYNC_CNTL);
		331	radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
		332	radeon_ring_write(rdev,
		333	R300_FRONT_PTYPE_TRIANGE \| R300_BACK_PTYPE_TRIANGE);
		334	radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
		335	radeon_ring_write(rdev,
		336	R300_GEOMETRY_ROUND_NEAREST \|
		337	R300_COLOR_ROUND_NEAREST);
		338	radeon_ring_unlock_commit(rdev);
		339	}
		340
		341	void r300_errata(struct radeon_device *rdev)
		342	{
		343	rdev->pll_errata = 0;
		344
		345	if (rdev->family == CHIP_R300 &&
		346	(RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
		347	rdev->pll_errata \|= CHIP_ERRATA_R300_CG;
		348	}
		349	}
		350
		351	int r300_mc_wait_for_idle(struct radeon_device *rdev)
		352	{
		353	unsigned i;
		354	uint32_t tmp;
		355
		356	for (i = 0; i < rdev->usec_timeout; i++) {
		357	/* read MC_STATUS */
		358	tmp = RREG32(0x0150);
		359	if (tmp & (1 << 4)) {
		360	return 0;
		361	}
		362	DRM_UDELAY(1);
		363	}
		364	return -1;
		365	}
		366
		367	void r300_gpu_init(struct radeon_device *rdev)
		368	{
		369	uint32_t gb_tile_config, tmp;
		370
		371	r100_hdp_reset(rdev);
		372	/* FIXME: rv380 one pipes ? */
		373	if ((rdev->family == CHIP_R300) \|\| (rdev->family == CHIP_R350)) {
		374	/* r300,r350 */
		375	rdev->num_gb_pipes = 2;
		376	} else {
		377	/* rv350,rv370,rv380 */
		378	rdev->num_gb_pipes = 1;
		379	}
1179	serge	380	rdev->num_z_pipes = 1;
1120	serge	381	gb_tile_config = (R300_ENABLE_TILING \| R300_TILE_SIZE_16);
		382	switch (rdev->num_gb_pipes) {
		383	case 2:
		384	gb_tile_config \|= R300_PIPE_COUNT_R300;
		385	break;
		386	case 3:
		387	gb_tile_config \|= R300_PIPE_COUNT_R420_3P;
		388	break;
		389	case 4:
		390	gb_tile_config \|= R300_PIPE_COUNT_R420;
		391	break;
		392	default:
		393	case 1:
		394	gb_tile_config \|= R300_PIPE_COUNT_RV350;
		395	break;
		396	}
		397	WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
		398
		399	if (r100_gui_wait_for_idle(rdev)) {
		400	printk(KERN_WARNING "Failed to wait GUI idle while "
		401	"programming pipes. Bad things might happen.\n");
		402	}
		403
		404	tmp = RREG32(0x170C);
		405	WREG32(0x170C, tmp \| (1 << 31));
		406
		407	WREG32(R300_RB2D_DSTCACHE_MODE,
		408	R300_DC_AUTOFLUSH_ENABLE \|
		409	R300_DC_DC_DISABLE_IGNORE_PE);
		410
		411	if (r100_gui_wait_for_idle(rdev)) {
		412	printk(KERN_WARNING "Failed to wait GUI idle while "
		413	"programming pipes. Bad things might happen.\n");
		414	}
		415	if (r300_mc_wait_for_idle(rdev)) {
		416	printk(KERN_WARNING "Failed to wait MC idle while "
		417	"programming pipes. Bad things might happen.\n");
		418	}
1179	serge	419	DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
		420	rdev->num_gb_pipes, rdev->num_z_pipes);
1120	serge	421	}
		422
		423	int r300_ga_reset(struct radeon_device *rdev)
		424	{
		425	uint32_t tmp;
		426	bool reinit_cp;
		427	int i;
		428
		429	reinit_cp = rdev->cp.ready;
		430	rdev->cp.ready = false;
		431	for (i = 0; i < rdev->usec_timeout; i++) {
		432	WREG32(RADEON_CP_CSQ_MODE, 0);
		433	WREG32(RADEON_CP_CSQ_CNTL, 0);
		434	WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
		435	(void)RREG32(RADEON_RBBM_SOFT_RESET);
		436	udelay(200);
		437	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		438	/* Wait to prevent race in RBBM_STATUS */
		439	mdelay(1);
		440	tmp = RREG32(RADEON_RBBM_STATUS);
		441	if (tmp & ((1 << 20) \| (1 << 26))) {
		442	DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
		443	/* GA still busy soft reset it */
		444	WREG32(0x429C, 0x200);
		445	WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
		446	WREG32(0x43E0, 0);
		447	WREG32(0x43E4, 0);
		448	WREG32(0x24AC, 0);
		449	}
		450	/* Wait to prevent race in RBBM_STATUS */
		451	mdelay(1);
		452	tmp = RREG32(RADEON_RBBM_STATUS);
		453	if (!(tmp & ((1 << 20) \| (1 << 26)))) {
		454	break;
		455	}
		456	}
		457	for (i = 0; i < rdev->usec_timeout; i++) {
		458	tmp = RREG32(RADEON_RBBM_STATUS);
		459	if (!(tmp & ((1 << 20) \| (1 << 26)))) {
		460	DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
		461	tmp);
		462	if (reinit_cp) {
		463	return r100_cp_init(rdev, rdev->cp.ring_size);
		464	}
		465	return 0;
		466	}
		467	DRM_UDELAY(1);
		468	}
		469	tmp = RREG32(RADEON_RBBM_STATUS);
		470	DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
		471	return -1;
		472	}
		473
		474	int r300_gpu_reset(struct radeon_device *rdev)
		475	{
		476	uint32_t status;
		477
		478	/* reset order likely matter */
		479	status = RREG32(RADEON_RBBM_STATUS);
		480	/* reset HDP */
		481	r100_hdp_reset(rdev);
		482	/* reset rb2d */
		483	if (status & ((1 << 17) \| (1 << 18) \| (1 << 27))) {
		484	r100_rb2d_reset(rdev);
		485	}
		486	/* reset GA */
		487	if (status & ((1 << 20) \| (1 << 26))) {
		488	r300_ga_reset(rdev);
		489	}
		490	/* reset CP */
		491	status = RREG32(RADEON_RBBM_STATUS);
		492	if (status & (1 << 16)) {
		493	r100_cp_reset(rdev);
		494	}
		495	/* Check if GPU is idle */
		496	status = RREG32(RADEON_RBBM_STATUS);
		497	if (status & (1 << 31)) {
		498	DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
		499	return -1;
		500	}
		501	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
		502	return 0;
		503	}
		504
		505
		506	/*
		507	* r300,r350,rv350,rv380 VRAM info
		508	*/
		509	void r300_vram_info(struct radeon_device *rdev)
		510	{
		511	uint32_t tmp;
		512
		513	/* DDR for all card after R300 & IGP */
		514	rdev->mc.vram_is_ddr = true;
1404	serge	515
1120	serge	516	tmp = RREG32(RADEON_MEM_CNTL);
1404	serge	517	tmp &= R300_MEM_NUM_CHANNELS_MASK;
		518	switch (tmp) {
		519	case 0: rdev->mc.vram_width = 64; break;
		520	case 1: rdev->mc.vram_width = 128; break;
		521	case 2: rdev->mc.vram_width = 256; break;
		522	default: rdev->mc.vram_width = 128; break;
1120	serge	523	}
		524
1179	serge	525	r100_vram_init_sizes(rdev);
1120	serge	526	}
		527
		528	void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
		529	{
		530	uint32_t link_width_cntl, mask;
		531
		532	if (rdev->flags & RADEON_IS_IGP)
		533	return;
		534
		535	if (!(rdev->flags & RADEON_IS_PCIE))
		536	return;
		537
		538	/* FIXME wait for idle */
		539
		540	switch (lanes) {
		541	case 0:
		542	mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
		543	break;
		544	case 1:
		545	mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
		546	break;
		547	case 2:
		548	mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
		549	break;
		550	case 4:
		551	mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
		552	break;
		553	case 8:
		554	mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
		555	break;
		556	case 12:
		557	mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
		558	break;
		559	case 16:
		560	default:
		561	mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
		562	break;
		563	}
		564
		565	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		566
		567	if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
		568	(mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
		569	return;
		570
		571	link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK \|
		572	RADEON_PCIE_LC_RECONFIG_NOW \|
		573	RADEON_PCIE_LC_RECONFIG_LATER \|
		574	RADEON_PCIE_LC_SHORT_RECONFIG_EN);
		575	link_width_cntl \|= mask;
		576	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
		577	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl \|
		578	RADEON_PCIE_LC_RECONFIG_NOW));
		579
		580	/* wait for lane set to complete */
		581	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		582	while (link_width_cntl == 0xffffffff)
		583	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		584
		585	}
		586
		587	#if defined(CONFIG_DEBUG_FS)
		588	static int rv370_debugfs_pcie_gart_info(struct seq_file m, void data)
		589	{
		590	struct drm_info_node node = (struct drm_info_node ) m->private;
		591	struct drm_device *dev = node->minor->dev;
		592	struct radeon_device *rdev = dev->dev_private;
		593	uint32_t tmp;
		594
		595	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		596	seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
		597	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
		598	seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
		599	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
		600	seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
		601	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
		602	seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
		603	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
		604	seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
		605	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
		606	seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
		607	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
		608	seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
		609	return 0;
		610	}
		611
		612	static struct drm_info_list rv370_pcie_gart_info_list[] = {
		613	{"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
		614	};
		615	#endif
		616
1221	serge	617	static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
1120	serge	618	{
		619	#if defined(CONFIG_DEBUG_FS)
		620	return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
		621	#else
		622	return 0;
		623	#endif
		624	}
		625
		626
1128	serge	627	#if 0
1221	serge	628
1120	serge	629	static int r300_packet0_check(struct radeon_cs_parser *p,
		630	struct radeon_cs_packet *pkt,
		631	unsigned idx, unsigned reg)
		632	{
		633	struct radeon_cs_reloc *reloc;
1179	serge	634	struct r100_cs_track *track;
1120	serge	635	volatile uint32_t *ib;
1179	serge	636	uint32_t tmp, tile_flags = 0;
1120	serge	637	unsigned i;
		638	int r;
1221	serge	639	u32 idx_value;
1120	serge	640
		641	ib = p->ib->ptr;
1179	serge	642	track = (struct r100_cs_track *)p->track;
1221	serge	643	idx_value = radeon_get_ib_value(p, idx);
		644
1120	serge	645	switch(reg) {
1179	serge	646	case AVIVO_D1MODE_VLINE_START_END:
		647	case RADEON_CRTC_GUI_TRIG_VLINE:
		648	r = r100_cs_packet_parse_vline(p);
1120	serge	649	if (r) {
		650	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		651	idx, reg);
		652	r100_cs_dump_packet(p, pkt);
		653	return r;
		654	}
		655	break;
1179	serge	656	case RADEON_DST_PITCH_OFFSET:
		657	case RADEON_SRC_PITCH_OFFSET:
		658	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		659	if (r)
		660	return r;
		661	break;
1120	serge	662	case R300_RB3D_COLOROFFSET0:
		663	case R300_RB3D_COLOROFFSET1:
		664	case R300_RB3D_COLOROFFSET2:
		665	case R300_RB3D_COLOROFFSET3:
		666	i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
		667	r = r100_cs_packet_next_reloc(p, &reloc);
		668	if (r) {
		669	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		670	idx, reg);
		671	r100_cs_dump_packet(p, pkt);
		672	return r;
		673	}
		674	track->cb[i].robj = reloc->robj;
1221	serge	675	track->cb[i].offset = idx_value;
		676	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1120	serge	677	break;
		678	case R300_ZB_DEPTHOFFSET:
		679	r = r100_cs_packet_next_reloc(p, &reloc);
		680	if (r) {
		681	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		682	idx, reg);
		683	r100_cs_dump_packet(p, pkt);
		684	return r;
		685	}
		686	track->zb.robj = reloc->robj;
1221	serge	687	track->zb.offset = idx_value;
		688	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1120	serge	689	break;
		690	case R300_TX_OFFSET_0:
		691	case R300_TX_OFFSET_0+4:
		692	case R300_TX_OFFSET_0+8:
		693	case R300_TX_OFFSET_0+12:
		694	case R300_TX_OFFSET_0+16:
		695	case R300_TX_OFFSET_0+20:
		696	case R300_TX_OFFSET_0+24:
		697	case R300_TX_OFFSET_0+28:
		698	case R300_TX_OFFSET_0+32:
		699	case R300_TX_OFFSET_0+36:
		700	case R300_TX_OFFSET_0+40:
		701	case R300_TX_OFFSET_0+44:
		702	case R300_TX_OFFSET_0+48:
		703	case R300_TX_OFFSET_0+52:
		704	case R300_TX_OFFSET_0+56:
		705	case R300_TX_OFFSET_0+60:
		706	i = (reg - R300_TX_OFFSET_0) >> 2;
		707	r = r100_cs_packet_next_reloc(p, &reloc);
		708	if (r) {
		709	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		710	idx, reg);
		711	r100_cs_dump_packet(p, pkt);
		712	return r;
		713	}
1403	serge	714
		715	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		716	tile_flags \|= R300_TXO_MACRO_TILE;
		717	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		718	tile_flags \|= R300_TXO_MICRO_TILE;
		719
		720	tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
		721	tmp \|= tile_flags;
		722	ib[idx] = tmp;
1120	serge	723	track->textures[i].robj = reloc->robj;
		724	break;
		725	/* Tracked registers */
		726	case 0x2084:
		727	/* VAP_VF_CNTL */
1221	serge	728	track->vap_vf_cntl = idx_value;
1120	serge	729	break;
		730	case 0x20B4:
		731	/* VAP_VTX_SIZE */
1221	serge	732	track->vtx_size = idx_value & 0x7F;
1120	serge	733	break;
		734	case 0x2134:
		735	/* VAP_VF_MAX_VTX_INDX */
1221	serge	736	track->max_indx = idx_value & 0x00FFFFFFUL;
1120	serge	737	break;
		738	case 0x43E4:
		739	/* SC_SCISSOR1 */
1221	serge	740	track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
1120	serge	741	if (p->rdev->family < CHIP_RV515) {
		742	track->maxy -= 1440;
		743	}
		744	break;
		745	case 0x4E00:
		746	/* RB3D_CCTL */
1221	serge	747	track->num_cb = ((idx_value >> 5) & 0x3) + 1;
1120	serge	748	break;
		749	case 0x4E38:
		750	case 0x4E3C:
		751	case 0x4E40:
		752	case 0x4E44:
		753	/* RB3D_COLORPITCH0 */
		754	/* RB3D_COLORPITCH1 */
		755	/* RB3D_COLORPITCH2 */
		756	/* RB3D_COLORPITCH3 */
1179	serge	757	r = r100_cs_packet_next_reloc(p, &reloc);
		758	if (r) {
		759	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		760	idx, reg);
		761	r100_cs_dump_packet(p, pkt);
		762	return r;
		763	}
		764
		765	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		766	tile_flags \|= R300_COLOR_TILE_ENABLE;
		767	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		768	tile_flags \|= R300_COLOR_MICROTILE_ENABLE;
		769
1221	serge	770	tmp = idx_value & ~(0x7 << 16);
1179	serge	771	tmp \|= tile_flags;
		772	ib[idx] = tmp;
		773
1120	serge	774	i = (reg - 0x4E38) >> 2;
1221	serge	775	track->cb[i].pitch = idx_value & 0x3FFE;
		776	switch (((idx_value >> 21) & 0xF)) {
1120	serge	777	case 9:
		778	case 11:
		779	case 12:
		780	track->cb[i].cpp = 1;
		781	break;
		782	case 3:
		783	case 4:
		784	case 13:
		785	case 15:
		786	track->cb[i].cpp = 2;
		787	break;
		788	case 6:
		789	track->cb[i].cpp = 4;
		790	break;
		791	case 10:
		792	track->cb[i].cpp = 8;
		793	break;
		794	case 7:
		795	track->cb[i].cpp = 16;
		796	break;
		797	default:
		798	DRM_ERROR("Invalid color buffer format (%d) !\n",
1221	serge	799	((idx_value >> 21) & 0xF));
1120	serge	800	return -EINVAL;
		801	}
		802	break;
		803	case 0x4F00:
		804	/* ZB_CNTL */
1221	serge	805	if (idx_value & 2) {
1120	serge	806	track->z_enabled = true;
		807	} else {
		808	track->z_enabled = false;
		809	}
		810	break;
		811	case 0x4F10:
		812	/* ZB_FORMAT */
1221	serge	813	switch ((idx_value & 0xF)) {
1120	serge	814	case 0:
		815	case 1:
		816	track->zb.cpp = 2;
		817	break;
		818	case 2:
		819	track->zb.cpp = 4;
		820	break;
		821	default:
		822	DRM_ERROR("Invalid z buffer format (%d) !\n",
1221	serge	823	(idx_value & 0xF));
1120	serge	824	return -EINVAL;
		825	}
		826	break;
		827	case 0x4F24:
		828	/* ZB_DEPTHPITCH */
1179	serge	829	r = r100_cs_packet_next_reloc(p, &reloc);
		830	if (r) {
		831	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		832	idx, reg);
		833	r100_cs_dump_packet(p, pkt);
		834	return r;
		835	}
		836
		837	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		838	tile_flags \|= R300_DEPTHMACROTILE_ENABLE;
		839	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		840	tile_flags \|= R300_DEPTHMICROTILE_TILED;;
		841
1221	serge	842	tmp = idx_value & ~(0x7 << 16);
1179	serge	843	tmp \|= tile_flags;
		844	ib[idx] = tmp;
		845
1221	serge	846	track->zb.pitch = idx_value & 0x3FFC;
1120	serge	847	break;
		848	case 0x4104:
		849	for (i = 0; i < 16; i++) {
		850	bool enabled;
		851
1221	serge	852	enabled = !!(idx_value & (1 << i));
1120	serge	853	track->textures[i].enabled = enabled;
		854	}
		855	break;
		856	case 0x44C0:
		857	case 0x44C4:
		858	case 0x44C8:
		859	case 0x44CC:
		860	case 0x44D0:
		861	case 0x44D4:
		862	case 0x44D8:
		863	case 0x44DC:
		864	case 0x44E0:
		865	case 0x44E4:
		866	case 0x44E8:
		867	case 0x44EC:
		868	case 0x44F0:
		869	case 0x44F4:
		870	case 0x44F8:
		871	case 0x44FC:
		872	/* TX_FORMAT1_[0-15] */
		873	i = (reg - 0x44C0) >> 2;
1221	serge	874	tmp = (idx_value >> 25) & 0x3;
1120	serge	875	track->textures[i].tex_coord_type = tmp;
1221	serge	876	switch ((idx_value & 0x1F)) {
1179	serge	877	case R300_TX_FORMAT_X8:
		878	case R300_TX_FORMAT_Y4X4:
		879	case R300_TX_FORMAT_Z3Y3X2:
1120	serge	880	track->textures[i].cpp = 1;
		881	break;
1179	serge	882	case R300_TX_FORMAT_X16:
		883	case R300_TX_FORMAT_Y8X8:
		884	case R300_TX_FORMAT_Z5Y6X5:
		885	case R300_TX_FORMAT_Z6Y5X5:
		886	case R300_TX_FORMAT_W4Z4Y4X4:
		887	case R300_TX_FORMAT_W1Z5Y5X5:
		888	case R300_TX_FORMAT_D3DMFT_CxV8U8:
		889	case R300_TX_FORMAT_B8G8_B8G8:
		890	case R300_TX_FORMAT_G8R8_G8B8:
1120	serge	891	track->textures[i].cpp = 2;
		892	break;
1179	serge	893	case R300_TX_FORMAT_Y16X16:
		894	case R300_TX_FORMAT_Z11Y11X10:
		895	case R300_TX_FORMAT_Z10Y11X11:
		896	case R300_TX_FORMAT_W8Z8Y8X8:
		897	case R300_TX_FORMAT_W2Z10Y10X10:
		898	case 0x17:
		899	case R300_TX_FORMAT_FL_I32:
		900	case 0x1e:
1120	serge	901	track->textures[i].cpp = 4;
		902	break;
1179	serge	903	case R300_TX_FORMAT_W16Z16Y16X16:
		904	case R300_TX_FORMAT_FL_R16G16B16A16:
		905	case R300_TX_FORMAT_FL_I32A32:
1120	serge	906	track->textures[i].cpp = 8;
		907	break;
1179	serge	908	case R300_TX_FORMAT_FL_R32G32B32A32:
1120	serge	909	track->textures[i].cpp = 16;
		910	break;
1403	serge	911	case R300_TX_FORMAT_DXT1:
		912	track->textures[i].cpp = 1;
		913	track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
		914	break;
		915	case R300_TX_FORMAT_ATI2N:
		916	if (p->rdev->family < CHIP_R420) {
		917	DRM_ERROR("Invalid texture format %u\n",
		918	(idx_value & 0x1F));
		919	return -EINVAL;
		920	}
		921	/* The same rules apply as for DXT3/5. */
		922	/* Pass through. */
		923	case R300_TX_FORMAT_DXT3:
		924	case R300_TX_FORMAT_DXT5:
		925	track->textures[i].cpp = 1;
		926	track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
		927	break;
1120	serge	928	default:
		929	DRM_ERROR("Invalid texture format %u\n",
1221	serge	930	(idx_value & 0x1F));
1120	serge	931	return -EINVAL;
		932	break;
		933	}
		934	break;
		935	case 0x4400:
		936	case 0x4404:
		937	case 0x4408:
		938	case 0x440C:
		939	case 0x4410:
		940	case 0x4414:
		941	case 0x4418:
		942	case 0x441C:
		943	case 0x4420:
		944	case 0x4424:
		945	case 0x4428:
		946	case 0x442C:
		947	case 0x4430:
		948	case 0x4434:
		949	case 0x4438:
		950	case 0x443C:
		951	/* TX_FILTER0_[0-15] */
		952	i = (reg - 0x4400) >> 2;
1221	serge	953	tmp = idx_value & 0x7;
1120	serge	954	if (tmp == 2 \|\| tmp == 4 \|\| tmp == 6) {
		955	track->textures[i].roundup_w = false;
		956	}
1221	serge	957	tmp = (idx_value >> 3) & 0x7;
1120	serge	958	if (tmp == 2 \|\| tmp == 4 \|\| tmp == 6) {
		959	track->textures[i].roundup_h = false;
		960	}
		961	break;
		962	case 0x4500:
		963	case 0x4504:
		964	case 0x4508:
		965	case 0x450C:
		966	case 0x4510:
		967	case 0x4514:
		968	case 0x4518:
		969	case 0x451C:
		970	case 0x4520:
		971	case 0x4524:
		972	case 0x4528:
		973	case 0x452C:
		974	case 0x4530:
		975	case 0x4534:
		976	case 0x4538:
		977	case 0x453C:
		978	/* TX_FORMAT2_[0-15] */
		979	i = (reg - 0x4500) >> 2;
1221	serge	980	tmp = idx_value & 0x3FFF;
1120	serge	981	track->textures[i].pitch = tmp + 1;
		982	if (p->rdev->family >= CHIP_RV515) {
1221	serge	983	tmp = ((idx_value >> 15) & 1) << 11;
1120	serge	984	track->textures[i].width_11 = tmp;
1221	serge	985	tmp = ((idx_value >> 16) & 1) << 11;
1120	serge	986	track->textures[i].height_11 = tmp;
1403	serge	987
		988	/* ATI1N */
		989	if (idx_value & (1 << 14)) {
		990	/* The same rules apply as for DXT1. */
		991	track->textures[i].compress_format =
		992	R100_TRACK_COMP_DXT1;
		993	}
		994	} else if (idx_value & (1 << 14)) {
		995	DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
		996	return -EINVAL;
1120	serge	997	}
		998	break;
		999	case 0x4480:
		1000	case 0x4484:
		1001	case 0x4488:
		1002	case 0x448C:
		1003	case 0x4490:
		1004	case 0x4494:
		1005	case 0x4498:
		1006	case 0x449C:
		1007	case 0x44A0:
		1008	case 0x44A4:
		1009	case 0x44A8:
		1010	case 0x44AC:
		1011	case 0x44B0:
		1012	case 0x44B4:
		1013	case 0x44B8:
		1014	case 0x44BC:
		1015	/* TX_FORMAT0_[0-15] */
		1016	i = (reg - 0x4480) >> 2;
1221	serge	1017	tmp = idx_value & 0x7FF;
1120	serge	1018	track->textures[i].width = tmp + 1;
1221	serge	1019	tmp = (idx_value >> 11) & 0x7FF;
1120	serge	1020	track->textures[i].height = tmp + 1;
1221	serge	1021	tmp = (idx_value >> 26) & 0xF;
1120	serge	1022	track->textures[i].num_levels = tmp;
1221	serge	1023	tmp = idx_value & (1 << 31);
1120	serge	1024	track->textures[i].use_pitch = !!tmp;
1221	serge	1025	tmp = (idx_value >> 22) & 0xF;
1120	serge	1026	track->textures[i].txdepth = tmp;
		1027	break;
1179	serge	1028	case R300_ZB_ZPASS_ADDR:
		1029	r = r100_cs_packet_next_reloc(p, &reloc);
		1030	if (r) {
		1031	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1032	idx, reg);
		1033	r100_cs_dump_packet(p, pkt);
		1034	return r;
		1035	}
1221	serge	1036	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1037	break;
1403	serge	1038	case 0x4e0c:
		1039	/* RB3D_COLOR_CHANNEL_MASK */
		1040	track->color_channel_mask = idx_value;
		1041	break;
		1042	case 0x4d1c:
		1043	/* ZB_BW_CNTL */
		1044	track->fastfill = !!(idx_value & (1 << 2));
		1045	break;
		1046	case 0x4e04:
		1047	/* RB3D_BLENDCNTL */
		1048	track->blend_read_enable = !!(idx_value & (1 << 2));
		1049	break;
1179	serge	1050	case 0x4be8:
		1051	/* valid register only on RV530 */
		1052	if (p->rdev->family == CHIP_RV530)
		1053	break;
		1054	/* fallthrough do not move */
1120	serge	1055	default:
		1056	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
		1057	reg, idx);
		1058	return -EINVAL;
		1059	}
		1060	return 0;
		1061	}
		1062
		1063	static int r300_packet3_check(struct radeon_cs_parser *p,
		1064	struct radeon_cs_packet *pkt)
		1065	{
		1066	struct radeon_cs_reloc *reloc;
1179	serge	1067	struct r100_cs_track *track;
1120	serge	1068	volatile uint32_t *ib;
		1069	unsigned idx;
		1070	int r;
		1071
		1072	ib = p->ib->ptr;
		1073	idx = pkt->idx + 1;
1179	serge	1074	track = (struct r100_cs_track *)p->track;
1120	serge	1075	switch(pkt->opcode) {
		1076	case PACKET3_3D_LOAD_VBPNTR:
1221	serge	1077	r = r100_packet3_load_vbpntr(p, pkt, idx);
		1078	if (r)
1120	serge	1079	return r;
		1080	break;
		1081	case PACKET3_INDX_BUFFER:
		1082	r = r100_cs_packet_next_reloc(p, &reloc);
		1083	if (r) {
		1084	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1085	r100_cs_dump_packet(p, pkt);
		1086	return r;
		1087	}
1221	serge	1088	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1120	serge	1089	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		1090	if (r) {
		1091	return r;
		1092	}
		1093	break;
		1094	/* Draw packet */
		1095	case PACKET3_3D_DRAW_IMMD:
		1096	/* Number of dwords is vtx_size * (num_vertices - 1)
		1097	* PRIM_WALK must be equal to 3 vertex data in embedded
		1098	* in cmd stream */
1221	serge	1099	if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1120	serge	1100	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1101	return -EINVAL;
		1102	}
1221	serge	1103	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1120	serge	1104	track->immd_dwords = pkt->count - 1;
1179	serge	1105	r = r100_cs_track_check(p->rdev, track);
1120	serge	1106	if (r) {
		1107	return r;
		1108	}
		1109	break;
		1110	case PACKET3_3D_DRAW_IMMD_2:
		1111	/* Number of dwords is vtx_size * (num_vertices - 1)
		1112	* PRIM_WALK must be equal to 3 vertex data in embedded
		1113	* in cmd stream */
1221	serge	1114	if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1120	serge	1115	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1116	return -EINVAL;
		1117	}
1221	serge	1118	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1120	serge	1119	track->immd_dwords = pkt->count;
1179	serge	1120	r = r100_cs_track_check(p->rdev, track);
1120	serge	1121	if (r) {
		1122	return r;
		1123	}
		1124	break;
		1125	case PACKET3_3D_DRAW_VBUF:
1221	serge	1126	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1127	r = r100_cs_track_check(p->rdev, track);
1120	serge	1128	if (r) {
		1129	return r;
		1130	}
		1131	break;
		1132	case PACKET3_3D_DRAW_VBUF_2:
1221	serge	1133	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1134	r = r100_cs_track_check(p->rdev, track);
1120	serge	1135	if (r) {
		1136	return r;
		1137	}
		1138	break;
		1139	case PACKET3_3D_DRAW_INDX:
1221	serge	1140	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1141	r = r100_cs_track_check(p->rdev, track);
1120	serge	1142	if (r) {
		1143	return r;
		1144	}
		1145	break;
		1146	case PACKET3_3D_DRAW_INDX_2:
1221	serge	1147	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1148	r = r100_cs_track_check(p->rdev, track);
1120	serge	1149	if (r) {
		1150	return r;
		1151	}
		1152	break;
		1153	case PACKET3_NOP:
		1154	break;
		1155	default:
		1156	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		1157	return -EINVAL;
		1158	}
		1159	return 0;
		1160	}
		1161
		1162	int r300_cs_parse(struct radeon_cs_parser *p)
		1163	{
		1164	struct radeon_cs_packet pkt;
1179	serge	1165	struct r100_cs_track *track;
1120	serge	1166	int r;
		1167
1179	serge	1168	track = kzalloc(sizeof(*track), GFP_KERNEL);
		1169	r100_cs_track_clear(p->rdev, track);
		1170	p->track = track;
1120	serge	1171	do {
		1172	r = r100_cs_packet_parse(p, &pkt, p->idx);
		1173	if (r) {
		1174	return r;
		1175	}
		1176	p->idx += pkt.count + 2;
		1177	switch (pkt.type) {
		1178	case PACKET_TYPE0:
		1179	r = r100_cs_parse_packet0(p, &pkt,
		1180	p->rdev->config.r300.reg_safe_bm,
		1181	p->rdev->config.r300.reg_safe_bm_size,
		1182	&r300_packet0_check);
		1183	break;
		1184	case PACKET_TYPE2:
		1185	break;
		1186	case PACKET_TYPE3:
		1187	r = r300_packet3_check(p, &pkt);
		1188	break;
		1189	default:
		1190	DRM_ERROR("Unknown packet type %d !\n", pkt.type);
		1191	return -EINVAL;
		1192	}
		1193	if (r) {
		1194	return r;
		1195	}
		1196	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
		1197	return 0;
		1198	}
1128	serge	1199	#endif
		1200
1179	serge	1201
		1202	void r300_set_reg_safe(struct radeon_device *rdev)
1120	serge	1203	{
		1204	rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
		1205	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1179	serge	1206	}
		1207
		1208	void r300_mc_program(struct radeon_device *rdev)
		1209	{
		1210	struct r100_mc_save save;
		1211	int r;
1120	serge	1212
1179	serge	1213	r = r100_debugfs_mc_info_init(rdev);
		1214	if (r) {
		1215	dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		1216	}
		1217
		1218	/* Stops all mc clients */
		1219	r100_mc_stop(rdev, &save);
		1220	if (rdev->flags & RADEON_IS_AGP) {
		1221	WREG32(R_00014C_MC_AGP_LOCATION,
		1222	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		1223	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		1224	WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		1225	WREG32(R_00015C_AGP_BASE_2,
		1226	upper_32_bits(rdev->mc.agp_base) & 0xff);
		1227	} else {
		1228	WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		1229	WREG32(R_000170_AGP_BASE, 0);
		1230	WREG32(R_00015C_AGP_BASE_2, 0);
		1231	}
		1232	/* Wait for mc idle */
		1233	if (r300_mc_wait_for_idle(rdev))
		1234	DRM_INFO("Failed to wait MC idle before programming MC.\n");
		1235	/* Program MC, should be a 32bits limited address space */
		1236	WREG32(R_000148_MC_FB_LOCATION,
		1237	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		1238	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		1239	r100_mc_resume(rdev, &save);
		1240	}
1221	serge	1241
		1242	void r300_clock_startup(struct radeon_device *rdev)
		1243	{
		1244	u32 tmp;
		1245
		1246	if (radeon_dynclks != -1 && radeon_dynclks)
		1247	radeon_legacy_set_clock_gating(rdev, 1);
		1248	/* We need to force on some of the block */
		1249	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
		1250	tmp \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		1251	if ((rdev->family == CHIP_RV350) \|\| (rdev->family == CHIP_RV380))
		1252	tmp \|= S_00000D_FORCE_VAP(1);
		1253	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
		1254	}
		1255
		1256	static int r300_startup(struct radeon_device *rdev)
		1257	{
		1258	int r;
		1259
1321	serge	1260	/* set common regs */
		1261	r100_set_common_regs(rdev);
		1262	/* program mc */
1221	serge	1263	r300_mc_program(rdev);
		1264	/* Resume clock */
		1265	r300_clock_startup(rdev);
		1266	/* Initialize GPU configuration (# pipes, ...) */
		1267	r300_gpu_init(rdev);
		1268	/* Initialize GART (initialize after TTM so we can allocate
		1269	* memory through TTM but finalize after TTM) */
		1270	if (rdev->flags & RADEON_IS_PCIE) {
		1271	r = rv370_pcie_gart_enable(rdev);
		1272	if (r)
		1273	return r;
		1274	}
1321	serge	1275
		1276	if (rdev->family == CHIP_R300 \|\|
		1277	rdev->family == CHIP_R350 \|\|
		1278	rdev->family == CHIP_RV350)
		1279	r100_enable_bm(rdev);
		1280
1221	serge	1281	if (rdev->flags & RADEON_IS_PCI) {
		1282	r = r100_pci_gart_enable(rdev);
		1283	if (r)
		1284	return r;
		1285	}
		1286	/* Enable IRQ */
		1287	// r100_irq_set(rdev);
1403	serge	1288	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1221	serge	1289	/* 1M ring buffer */
1412	serge	1290	r = r100_cp_init(rdev, 1024 * 1024);
		1291	if (r) {
		1292	dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
		1293	return r;
		1294	}
1221	serge	1295	// r = r100_wb_init(rdev);
		1296	// if (r)
		1297	// dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
		1298	// r = r100_ib_init(rdev);
		1299	// if (r) {
		1300	// dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
		1301	// return r;
		1302	// }
		1303	return 0;
		1304	}
		1305
		1306
		1307
		1308
		1309
		1310	int r300_init(struct radeon_device *rdev)
		1311	{
		1312	int r;
		1313
		1314	/* Disable VGA */
		1315	r100_vga_render_disable(rdev);
		1316	/* Initialize scratch registers */
		1317	radeon_scratch_init(rdev);
		1318	/* Initialize surface registers */
		1319	radeon_surface_init(rdev);
		1320	/* TODO: disable VGA need to use VGA request */
		1321	/* BIOS*/
		1322	if (!radeon_get_bios(rdev)) {
		1323	if (ASIC_IS_AVIVO(rdev))
		1324	return -EINVAL;
		1325	}
		1326	if (rdev->is_atom_bios) {
		1327	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		1328	return -EINVAL;
		1329	} else {
		1330	r = radeon_combios_init(rdev);
		1331	if (r)
		1332	return r;
		1333	}
		1334	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
		1335	if (radeon_gpu_reset(rdev)) {
		1336	dev_warn(rdev->dev,
		1337	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		1338	RREG32(R_000E40_RBBM_STATUS),
		1339	RREG32(R_0007C0_CP_STAT));
		1340	}
		1341	/* check if cards are posted or not */
1321	serge	1342	if (radeon_boot_test_post_card(rdev) == false)
		1343	return -EINVAL;
1221	serge	1344	/* Set asic errata */
		1345	r300_errata(rdev);
		1346	/* Initialize clocks */
		1347	radeon_get_clock_info(rdev->ddev);
1403	serge	1348	/* Initialize power management */
		1349	radeon_pm_init(rdev);
1221	serge	1350	/* Get vram informations */
		1351	r300_vram_info(rdev);
		1352	/* Initialize memory controller (also test AGP) */
		1353	r = r420_mc_init(rdev);
1246	serge	1354	dbgprintf("mc vram location %x\n", rdev->mc.vram_location);
1221	serge	1355	if (r)
		1356	return r;
		1357	/* Fence driver */
		1358	// r = radeon_fence_driver_init(rdev);
		1359	// if (r)
		1360	// return r;
		1361	// r = radeon_irq_kms_init(rdev);
		1362	// if (r)
		1363	// return r;
		1364	/* Memory manager */
1404	serge	1365	r = radeon_bo_init(rdev);
1221	serge	1366	if (r)
		1367	return r;
		1368	if (rdev->flags & RADEON_IS_PCIE) {
		1369	r = rv370_pcie_gart_init(rdev);
		1370	if (r)
		1371	return r;
		1372	}
		1373	if (rdev->flags & RADEON_IS_PCI) {
		1374	r = r100_pci_gart_init(rdev);
		1375	if (r)
		1376	return r;
		1377	}
		1378	r300_set_reg_safe(rdev);
		1379	rdev->accel_working = true;
		1380	r = r300_startup(rdev);
		1381	if (r) {
		1382	/* Somethings want wront with the accel init stop accel */
		1383	dev_err(rdev->dev, "Disabling GPU acceleration\n");
		1384	// r300_suspend(rdev);
		1385	// r100_cp_fini(rdev);
		1386	// r100_wb_fini(rdev);
		1387	// r100_ib_fini(rdev);
		1388	if (rdev->flags & RADEON_IS_PCIE)
		1389	rv370_pcie_gart_fini(rdev);
		1390	if (rdev->flags & RADEON_IS_PCI)
		1391	r100_pci_gart_fini(rdev);
1404	serge	1392	// radeon_agp_fini(rdev);
1221	serge	1393	rdev->accel_working = false;
		1394	}
		1395	return 0;
		1396	}

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(root)/drivers/video/drm/radeon/r300.c – Rev 1412