WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r300.c

Rev	Author	Line No.	Line
1120	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1179	serge	28	#include
1125	serge	29	#include "drmP.h"
		30	#include "drm.h"
1120	serge	31	#include "radeon_reg.h"
		32	#include "radeon.h"
1179	serge	33	#include "radeon_drm.h"
1120	serge	34
1179	serge	35	#include "r300d.h"
1221	serge	36	#include "rv350d.h"
1179	serge	37	#include "r300_reg_safe.h"
		38
1403	serge	39	/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
		40	*
		41	* GPU Errata:
		42	* - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
		43	* using MMIO to flush host path read cache, this lead to HARDLOCKUP.
		44	* However, scheduling such write to the ring seems harmless, i suspect
		45	* the CP read collide with the flush somehow, or maybe the MC, hard to
		46	* tell. (Jerome Glisse)
		47	*/
1120	serge	48
		49	/*
		50	* rv370,rv380 PCIE GART
		51	*/
1221	serge	52	static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
		53
1120	serge	54	void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
		55	{
		56	uint32_t tmp;
		57	int i;
		58
		59	/* Workaround HW bug do flush 2 times */
		60	for (i = 0; i < 2; i++) {
		61	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		62	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp \| RADEON_PCIE_TX_GART_INVALIDATE_TLB);
		63	(void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		64	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
1179	serge	65	}
1120	serge	66	mb();
1179	serge	67	}
		68
		69	int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
		70	{
		71	void __iomem ptr = (void )rdev->gart.table.vram.ptr;
		72
		73	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
		74	return -EINVAL;
1120	serge	75	}
1179	serge	76	addr = (lower_32_bits(addr) >> 8) \|
		77	((upper_32_bits(addr) & 0xff) << 24) \|
		78	0xc;
		79	/* on x86 we want this to be CPU endian, on powerpc
		80	* on powerpc without HW swappers, it'll get swapped on way
		81	* into VRAM - so no need for cpu_to_le32 on VRAM tables */
		82	writel(addr, ((void __iomem )ptr) + (i 4));
		83	return 0;
1120	serge	84	}
		85
1179	serge	86	int rv370_pcie_gart_init(struct radeon_device *rdev)
1120	serge	87	{
		88	int r;
		89
1179	serge	90	if (rdev->gart.table.vram.robj) {
		91	WARN(1, "RV370 PCIE GART already initialized.\n");
		92	return 0;
		93	}
1120	serge	94	/* Initialize common gart structure */
		95	r = radeon_gart_init(rdev);
1179	serge	96	if (r)
1120	serge	97	return r;
1129	serge	98	r = rv370_debugfs_pcie_gart_info_init(rdev);
1179	serge	99	if (r)
1129	serge	100	DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
1179	serge	101	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
		102	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
		103	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
		104	return radeon_gart_table_vram_alloc(rdev);
		105	}
		106
		107	int rv370_pcie_gart_enable(struct radeon_device *rdev)
		108	{
		109	uint32_t table_addr;
		110	uint32_t tmp;
		111	int r;
		112
		113	if (rdev->gart.table.vram.robj == NULL) {
		114	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
		115	return -EINVAL;
1129	serge	116	}
1179	serge	117	r = radeon_gart_table_vram_pin(rdev);
		118	if (r)
1120	serge	119	return r;
		120	/* discard memory request outside of configured range */
		121	tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		122	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
		123	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
1268	serge	124	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - RADEON_GPU_PAGE_SIZE;
1120	serge	125	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
		126	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
		127	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
		128	table_addr = rdev->gart.table_addr;
		129	WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
		130	/* FIXME: setup default page */
		131	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location);
		132	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
		133	/* Clear error */
		134	WREG32_PCIE(0x18, 0);
		135	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		136	tmp \|= RADEON_PCIE_TX_GART_EN;
		137	tmp \|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		138	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
		139	rv370_pcie_gart_tlb_flush(rdev);
		140	DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
1179	serge	141	(unsigned)(rdev->mc.gtt_size >> 20), table_addr);
1120	serge	142	rdev->gart.ready = true;
		143	return 0;
		144	}
		145
		146	void rv370_pcie_gart_disable(struct radeon_device *rdev)
		147	{
1321	serge	148	u32 tmp;
		149	int r;
1120	serge	150
		151	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		152	tmp \|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		153	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
		154	if (rdev->gart.table.vram.robj) {
		155	// radeon_object_kunmap(rdev->gart.table.vram.robj);
		156	// radeon_object_unpin(rdev->gart.table.vram.robj);
		157	}
		158	}
		159
1179	serge	160	void rv370_pcie_gart_fini(struct radeon_device *rdev)
1120	serge	161	{
		162	rv370_pcie_gart_disable(rdev);
1179	serge	163	radeon_gart_table_vram_free(rdev);
		164	radeon_gart_fini(rdev);
1120	serge	165	}
		166
		167	void r300_fence_ring_emit(struct radeon_device *rdev,
		168	struct radeon_fence *fence)
		169	{
		170	/* Who ever call radeon_fence_emit should call ring_lock and ask
		171	* for enough space (today caller are ib schedule and buffer move) */
		172	/* Write SC register so SC & US assert idle */
		173	radeon_ring_write(rdev, PACKET0(0x43E0, 0));
		174	radeon_ring_write(rdev, 0);
		175	radeon_ring_write(rdev, PACKET0(0x43E4, 0));
		176	radeon_ring_write(rdev, 0);
		177	/* Flush 3D cache */
		178	radeon_ring_write(rdev, PACKET0(0x4E4C, 0));
		179	radeon_ring_write(rdev, (2 << 0));
		180	radeon_ring_write(rdev, PACKET0(0x4F18, 0));
		181	radeon_ring_write(rdev, (1 << 0));
		182	/* Wait until IDLE & CLEAN */
		183	radeon_ring_write(rdev, PACKET0(0x1720, 0));
		184	radeon_ring_write(rdev, (1 << 17) \| (1 << 16) \| (1 << 9));
1403	serge	185	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		186	radeon_ring_write(rdev, rdev->config.r300.hdp_cntl \|
		187	RADEON_HDP_READ_BUFFER_INVALIDATE);
		188	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		189	radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
1120	serge	190	/* Emit fence sequence & fire IRQ */
		191	radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
		192	radeon_ring_write(rdev, fence->seq);
		193	radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
		194	radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
		195	}
		196
		197
1128	serge	198	#if 0
		199
1221	serge	200
1120	serge	201	int r300_copy_dma(struct radeon_device *rdev,
		202	uint64_t src_offset,
		203	uint64_t dst_offset,
		204	unsigned num_pages,
		205	struct radeon_fence *fence)
		206	{
		207	uint32_t size;
		208	uint32_t cur_size;
		209	int i, num_loops;
		210	int r = 0;
		211
		212	/* radeon pitch is /64 */
		213	size = num_pages << PAGE_SHIFT;
		214	num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
		215	r = radeon_ring_lock(rdev, num_loops * 4 + 64);
		216	if (r) {
		217	DRM_ERROR("radeon: moving bo (%d).\n", r);
		218	return r;
		219	}
		220	/* Must wait for 2D idle & clean before DMA or hangs might happen */
		221	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 ));
		222	radeon_ring_write(rdev, (1 << 16));
		223	for (i = 0; i < num_loops; i++) {
		224	cur_size = size;
		225	if (cur_size > 0x1FFFFF) {
		226	cur_size = 0x1FFFFF;
		227	}
		228	size -= cur_size;
		229	radeon_ring_write(rdev, PACKET0(0x720, 2));
		230	radeon_ring_write(rdev, src_offset);
		231	radeon_ring_write(rdev, dst_offset);
		232	radeon_ring_write(rdev, cur_size \| (1 << 31) \| (1 << 30));
		233	src_offset += cur_size;
		234	dst_offset += cur_size;
		235	}
		236	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		237	radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
		238	if (fence) {
		239	r = radeon_fence_emit(rdev, fence);
		240	}
		241	radeon_ring_unlock_commit(rdev);
		242	return r;
		243	}
		244
1128	serge	245	#endif
		246
1120	serge	247	void r300_ring_start(struct radeon_device *rdev)
		248	{
		249	unsigned gb_tile_config;
		250	int r;
		251
		252	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
		253	gb_tile_config = (R300_ENABLE_TILING \| R300_TILE_SIZE_16);
		254	switch(rdev->num_gb_pipes) {
		255	case 2:
		256	gb_tile_config \|= R300_PIPE_COUNT_R300;
		257	break;
		258	case 3:
		259	gb_tile_config \|= R300_PIPE_COUNT_R420_3P;
		260	break;
		261	case 4:
		262	gb_tile_config \|= R300_PIPE_COUNT_R420;
		263	break;
		264	case 1:
		265	default:
		266	gb_tile_config \|= R300_PIPE_COUNT_RV350;
		267	break;
		268	}
		269
		270	r = radeon_ring_lock(rdev, 64);
		271	if (r) {
		272	return;
		273	}
		274	radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
		275	radeon_ring_write(rdev,
		276	RADEON_ISYNC_ANY2D_IDLE3D \|
		277	RADEON_ISYNC_ANY3D_IDLE2D \|
		278	RADEON_ISYNC_WAIT_IDLEGUI \|
		279	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
		280	radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
		281	radeon_ring_write(rdev, gb_tile_config);
		282	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		283	radeon_ring_write(rdev,
		284	RADEON_WAIT_2D_IDLECLEAN \|
		285	RADEON_WAIT_3D_IDLECLEAN);
		286	radeon_ring_write(rdev, PACKET0(0x170C, 0));
		287	radeon_ring_write(rdev, 1 << 31);
		288	radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
		289	radeon_ring_write(rdev, 0);
		290	radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
		291	radeon_ring_write(rdev, 0);
		292	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
		293	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH \| R300_RB3D_DC_FREE);
		294	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
		295	radeon_ring_write(rdev, R300_ZC_FLUSH \| R300_ZC_FREE);
		296	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		297	radeon_ring_write(rdev,
		298	RADEON_WAIT_2D_IDLECLEAN \|
		299	RADEON_WAIT_3D_IDLECLEAN);
		300	radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
		301	radeon_ring_write(rdev, 0);
		302	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
		303	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH \| R300_RB3D_DC_FREE);
		304	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
		305	radeon_ring_write(rdev, R300_ZC_FLUSH \| R300_ZC_FREE);
		306	radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
		307	radeon_ring_write(rdev,
		308	((6 << R300_MS_X0_SHIFT) \|
		309	(6 << R300_MS_Y0_SHIFT) \|
		310	(6 << R300_MS_X1_SHIFT) \|
		311	(6 << R300_MS_Y1_SHIFT) \|
		312	(6 << R300_MS_X2_SHIFT) \|
		313	(6 << R300_MS_Y2_SHIFT) \|
		314	(6 << R300_MSBD0_Y_SHIFT) \|
		315	(6 << R300_MSBD0_X_SHIFT)));
		316	radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
		317	radeon_ring_write(rdev,
		318	((6 << R300_MS_X3_SHIFT) \|
		319	(6 << R300_MS_Y3_SHIFT) \|
		320	(6 << R300_MS_X4_SHIFT) \|
		321	(6 << R300_MS_Y4_SHIFT) \|
		322	(6 << R300_MS_X5_SHIFT) \|
		323	(6 << R300_MS_Y5_SHIFT) \|
		324	(6 << R300_MSBD1_SHIFT)));
		325	radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
		326	radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL \| R300_GA_FASTSYNC_CNTL);
		327	radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
		328	radeon_ring_write(rdev,
		329	R300_FRONT_PTYPE_TRIANGE \| R300_BACK_PTYPE_TRIANGE);
		330	radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
		331	radeon_ring_write(rdev,
		332	R300_GEOMETRY_ROUND_NEAREST \|
		333	R300_COLOR_ROUND_NEAREST);
		334	radeon_ring_unlock_commit(rdev);
		335	}
		336
		337	void r300_errata(struct radeon_device *rdev)
		338	{
		339	rdev->pll_errata = 0;
		340
		341	if (rdev->family == CHIP_R300 &&
		342	(RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
		343	rdev->pll_errata \|= CHIP_ERRATA_R300_CG;
		344	}
		345	}
		346
		347	int r300_mc_wait_for_idle(struct radeon_device *rdev)
		348	{
		349	unsigned i;
		350	uint32_t tmp;
		351
		352	for (i = 0; i < rdev->usec_timeout; i++) {
		353	/* read MC_STATUS */
		354	tmp = RREG32(0x0150);
		355	if (tmp & (1 << 4)) {
		356	return 0;
		357	}
		358	DRM_UDELAY(1);
		359	}
		360	return -1;
		361	}
		362
		363	void r300_gpu_init(struct radeon_device *rdev)
		364	{
		365	uint32_t gb_tile_config, tmp;
		366
		367	r100_hdp_reset(rdev);
		368	/* FIXME: rv380 one pipes ? */
		369	if ((rdev->family == CHIP_R300) \|\| (rdev->family == CHIP_R350)) {
		370	/* r300,r350 */
		371	rdev->num_gb_pipes = 2;
		372	} else {
		373	/* rv350,rv370,rv380 */
		374	rdev->num_gb_pipes = 1;
		375	}
1179	serge	376	rdev->num_z_pipes = 1;
1120	serge	377	gb_tile_config = (R300_ENABLE_TILING \| R300_TILE_SIZE_16);
		378	switch (rdev->num_gb_pipes) {
		379	case 2:
		380	gb_tile_config \|= R300_PIPE_COUNT_R300;
		381	break;
		382	case 3:
		383	gb_tile_config \|= R300_PIPE_COUNT_R420_3P;
		384	break;
		385	case 4:
		386	gb_tile_config \|= R300_PIPE_COUNT_R420;
		387	break;
		388	default:
		389	case 1:
		390	gb_tile_config \|= R300_PIPE_COUNT_RV350;
		391	break;
		392	}
		393	WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
		394
		395	if (r100_gui_wait_for_idle(rdev)) {
		396	printk(KERN_WARNING "Failed to wait GUI idle while "
		397	"programming pipes. Bad things might happen.\n");
		398	}
		399
		400	tmp = RREG32(0x170C);
		401	WREG32(0x170C, tmp \| (1 << 31));
		402
		403	WREG32(R300_RB2D_DSTCACHE_MODE,
		404	R300_DC_AUTOFLUSH_ENABLE \|
		405	R300_DC_DC_DISABLE_IGNORE_PE);
		406
		407	if (r100_gui_wait_for_idle(rdev)) {
		408	printk(KERN_WARNING "Failed to wait GUI idle while "
		409	"programming pipes. Bad things might happen.\n");
		410	}
		411	if (r300_mc_wait_for_idle(rdev)) {
		412	printk(KERN_WARNING "Failed to wait MC idle while "
		413	"programming pipes. Bad things might happen.\n");
		414	}
1179	serge	415	DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
		416	rdev->num_gb_pipes, rdev->num_z_pipes);
1120	serge	417	}
		418
		419	int r300_ga_reset(struct radeon_device *rdev)
		420	{
		421	uint32_t tmp;
		422	bool reinit_cp;
		423	int i;
		424
		425	reinit_cp = rdev->cp.ready;
		426	rdev->cp.ready = false;
		427	for (i = 0; i < rdev->usec_timeout; i++) {
		428	WREG32(RADEON_CP_CSQ_MODE, 0);
		429	WREG32(RADEON_CP_CSQ_CNTL, 0);
		430	WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
		431	(void)RREG32(RADEON_RBBM_SOFT_RESET);
		432	udelay(200);
		433	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		434	/* Wait to prevent race in RBBM_STATUS */
		435	mdelay(1);
		436	tmp = RREG32(RADEON_RBBM_STATUS);
		437	if (tmp & ((1 << 20) \| (1 << 26))) {
		438	DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
		439	/* GA still busy soft reset it */
		440	WREG32(0x429C, 0x200);
		441	WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
		442	WREG32(0x43E0, 0);
		443	WREG32(0x43E4, 0);
		444	WREG32(0x24AC, 0);
		445	}
		446	/* Wait to prevent race in RBBM_STATUS */
		447	mdelay(1);
		448	tmp = RREG32(RADEON_RBBM_STATUS);
		449	if (!(tmp & ((1 << 20) \| (1 << 26)))) {
		450	break;
		451	}
		452	}
		453	for (i = 0; i < rdev->usec_timeout; i++) {
		454	tmp = RREG32(RADEON_RBBM_STATUS);
		455	if (!(tmp & ((1 << 20) \| (1 << 26)))) {
		456	DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
		457	tmp);
		458	if (reinit_cp) {
		459	return r100_cp_init(rdev, rdev->cp.ring_size);
		460	}
		461	return 0;
		462	}
		463	DRM_UDELAY(1);
		464	}
		465	tmp = RREG32(RADEON_RBBM_STATUS);
		466	DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
		467	return -1;
		468	}
		469
		470	int r300_gpu_reset(struct radeon_device *rdev)
		471	{
		472	uint32_t status;
		473
		474	/* reset order likely matter */
		475	status = RREG32(RADEON_RBBM_STATUS);
		476	/* reset HDP */
		477	r100_hdp_reset(rdev);
		478	/* reset rb2d */
		479	if (status & ((1 << 17) \| (1 << 18) \| (1 << 27))) {
		480	r100_rb2d_reset(rdev);
		481	}
		482	/* reset GA */
		483	if (status & ((1 << 20) \| (1 << 26))) {
		484	r300_ga_reset(rdev);
		485	}
		486	/* reset CP */
		487	status = RREG32(RADEON_RBBM_STATUS);
		488	if (status & (1 << 16)) {
		489	r100_cp_reset(rdev);
		490	}
		491	/* Check if GPU is idle */
		492	status = RREG32(RADEON_RBBM_STATUS);
		493	if (status & (1 << 31)) {
		494	DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
		495	return -1;
		496	}
		497	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
		498	return 0;
		499	}
		500
		501
		502	/*
		503	* r300,r350,rv350,rv380 VRAM info
		504	*/
		505	void r300_vram_info(struct radeon_device *rdev)
		506	{
		507	uint32_t tmp;
		508
		509	/* DDR for all card after R300 & IGP */
		510	rdev->mc.vram_is_ddr = true;
		511	tmp = RREG32(RADEON_MEM_CNTL);
		512	if (tmp & R300_MEM_NUM_CHANNELS_MASK) {
		513	rdev->mc.vram_width = 128;
		514	} else {
		515	rdev->mc.vram_width = 64;
		516	}
		517
1179	serge	518	r100_vram_init_sizes(rdev);
1120	serge	519	}
		520
		521	void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
		522	{
		523	uint32_t link_width_cntl, mask;
		524
		525	if (rdev->flags & RADEON_IS_IGP)
		526	return;
		527
		528	if (!(rdev->flags & RADEON_IS_PCIE))
		529	return;
		530
		531	/* FIXME wait for idle */
		532
		533	switch (lanes) {
		534	case 0:
		535	mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
		536	break;
		537	case 1:
		538	mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
		539	break;
		540	case 2:
		541	mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
		542	break;
		543	case 4:
		544	mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
		545	break;
		546	case 8:
		547	mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
		548	break;
		549	case 12:
		550	mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
		551	break;
		552	case 16:
		553	default:
		554	mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
		555	break;
		556	}
		557
		558	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		559
		560	if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
		561	(mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
		562	return;
		563
		564	link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK \|
		565	RADEON_PCIE_LC_RECONFIG_NOW \|
		566	RADEON_PCIE_LC_RECONFIG_LATER \|
		567	RADEON_PCIE_LC_SHORT_RECONFIG_EN);
		568	link_width_cntl \|= mask;
		569	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
		570	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl \|
		571	RADEON_PCIE_LC_RECONFIG_NOW));
		572
		573	/* wait for lane set to complete */
		574	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		575	while (link_width_cntl == 0xffffffff)
		576	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		577
		578	}
		579
		580	#if defined(CONFIG_DEBUG_FS)
		581	static int rv370_debugfs_pcie_gart_info(struct seq_file m, void data)
		582	{
		583	struct drm_info_node node = (struct drm_info_node ) m->private;
		584	struct drm_device *dev = node->minor->dev;
		585	struct radeon_device *rdev = dev->dev_private;
		586	uint32_t tmp;
		587
		588	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		589	seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
		590	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
		591	seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
		592	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
		593	seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
		594	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
		595	seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
		596	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
		597	seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
		598	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
		599	seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
		600	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
		601	seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
		602	return 0;
		603	}
		604
		605	static struct drm_info_list rv370_pcie_gart_info_list[] = {
		606	{"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
		607	};
		608	#endif
		609
1221	serge	610	static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
1120	serge	611	{
		612	#if defined(CONFIG_DEBUG_FS)
		613	return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
		614	#else
		615	return 0;
		616	#endif
		617	}
		618
		619
1128	serge	620	#if 0
1221	serge	621
1120	serge	622	static int r300_packet0_check(struct radeon_cs_parser *p,
		623	struct radeon_cs_packet *pkt,
		624	unsigned idx, unsigned reg)
		625	{
		626	struct radeon_cs_reloc *reloc;
1179	serge	627	struct r100_cs_track *track;
1120	serge	628	volatile uint32_t *ib;
1179	serge	629	uint32_t tmp, tile_flags = 0;
1120	serge	630	unsigned i;
		631	int r;
1221	serge	632	u32 idx_value;
1120	serge	633
		634	ib = p->ib->ptr;
1179	serge	635	track = (struct r100_cs_track *)p->track;
1221	serge	636	idx_value = radeon_get_ib_value(p, idx);
		637
1120	serge	638	switch(reg) {
1179	serge	639	case AVIVO_D1MODE_VLINE_START_END:
		640	case RADEON_CRTC_GUI_TRIG_VLINE:
		641	r = r100_cs_packet_parse_vline(p);
1120	serge	642	if (r) {
		643	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		644	idx, reg);
		645	r100_cs_dump_packet(p, pkt);
		646	return r;
		647	}
		648	break;
1179	serge	649	case RADEON_DST_PITCH_OFFSET:
		650	case RADEON_SRC_PITCH_OFFSET:
		651	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		652	if (r)
		653	return r;
		654	break;
1120	serge	655	case R300_RB3D_COLOROFFSET0:
		656	case R300_RB3D_COLOROFFSET1:
		657	case R300_RB3D_COLOROFFSET2:
		658	case R300_RB3D_COLOROFFSET3:
		659	i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
		660	r = r100_cs_packet_next_reloc(p, &reloc);
		661	if (r) {
		662	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		663	idx, reg);
		664	r100_cs_dump_packet(p, pkt);
		665	return r;
		666	}
		667	track->cb[i].robj = reloc->robj;
1221	serge	668	track->cb[i].offset = idx_value;
		669	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1120	serge	670	break;
		671	case R300_ZB_DEPTHOFFSET:
		672	r = r100_cs_packet_next_reloc(p, &reloc);
		673	if (r) {
		674	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		675	idx, reg);
		676	r100_cs_dump_packet(p, pkt);
		677	return r;
		678	}
		679	track->zb.robj = reloc->robj;
1221	serge	680	track->zb.offset = idx_value;
		681	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1120	serge	682	break;
		683	case R300_TX_OFFSET_0:
		684	case R300_TX_OFFSET_0+4:
		685	case R300_TX_OFFSET_0+8:
		686	case R300_TX_OFFSET_0+12:
		687	case R300_TX_OFFSET_0+16:
		688	case R300_TX_OFFSET_0+20:
		689	case R300_TX_OFFSET_0+24:
		690	case R300_TX_OFFSET_0+28:
		691	case R300_TX_OFFSET_0+32:
		692	case R300_TX_OFFSET_0+36:
		693	case R300_TX_OFFSET_0+40:
		694	case R300_TX_OFFSET_0+44:
		695	case R300_TX_OFFSET_0+48:
		696	case R300_TX_OFFSET_0+52:
		697	case R300_TX_OFFSET_0+56:
		698	case R300_TX_OFFSET_0+60:
		699	i = (reg - R300_TX_OFFSET_0) >> 2;
		700	r = r100_cs_packet_next_reloc(p, &reloc);
		701	if (r) {
		702	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		703	idx, reg);
		704	r100_cs_dump_packet(p, pkt);
		705	return r;
		706	}
1403	serge	707
		708	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		709	tile_flags \|= R300_TXO_MACRO_TILE;
		710	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		711	tile_flags \|= R300_TXO_MICRO_TILE;
		712
		713	tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
		714	tmp \|= tile_flags;
		715	ib[idx] = tmp;
1120	serge	716	track->textures[i].robj = reloc->robj;
		717	break;
		718	/* Tracked registers */
		719	case 0x2084:
		720	/* VAP_VF_CNTL */
1221	serge	721	track->vap_vf_cntl = idx_value;
1120	serge	722	break;
		723	case 0x20B4:
		724	/* VAP_VTX_SIZE */
1221	serge	725	track->vtx_size = idx_value & 0x7F;
1120	serge	726	break;
		727	case 0x2134:
		728	/* VAP_VF_MAX_VTX_INDX */
1221	serge	729	track->max_indx = idx_value & 0x00FFFFFFUL;
1120	serge	730	break;
		731	case 0x43E4:
		732	/* SC_SCISSOR1 */
1221	serge	733	track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
1120	serge	734	if (p->rdev->family < CHIP_RV515) {
		735	track->maxy -= 1440;
		736	}
		737	break;
		738	case 0x4E00:
		739	/* RB3D_CCTL */
1221	serge	740	track->num_cb = ((idx_value >> 5) & 0x3) + 1;
1120	serge	741	break;
		742	case 0x4E38:
		743	case 0x4E3C:
		744	case 0x4E40:
		745	case 0x4E44:
		746	/* RB3D_COLORPITCH0 */
		747	/* RB3D_COLORPITCH1 */
		748	/* RB3D_COLORPITCH2 */
		749	/* RB3D_COLORPITCH3 */
1179	serge	750	r = r100_cs_packet_next_reloc(p, &reloc);
		751	if (r) {
		752	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		753	idx, reg);
		754	r100_cs_dump_packet(p, pkt);
		755	return r;
		756	}
		757
		758	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		759	tile_flags \|= R300_COLOR_TILE_ENABLE;
		760	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		761	tile_flags \|= R300_COLOR_MICROTILE_ENABLE;
		762
1221	serge	763	tmp = idx_value & ~(0x7 << 16);
1179	serge	764	tmp \|= tile_flags;
		765	ib[idx] = tmp;
		766
1120	serge	767	i = (reg - 0x4E38) >> 2;
1221	serge	768	track->cb[i].pitch = idx_value & 0x3FFE;
		769	switch (((idx_value >> 21) & 0xF)) {
1120	serge	770	case 9:
		771	case 11:
		772	case 12:
		773	track->cb[i].cpp = 1;
		774	break;
		775	case 3:
		776	case 4:
		777	case 13:
		778	case 15:
		779	track->cb[i].cpp = 2;
		780	break;
		781	case 6:
		782	track->cb[i].cpp = 4;
		783	break;
		784	case 10:
		785	track->cb[i].cpp = 8;
		786	break;
		787	case 7:
		788	track->cb[i].cpp = 16;
		789	break;
		790	default:
		791	DRM_ERROR("Invalid color buffer format (%d) !\n",
1221	serge	792	((idx_value >> 21) & 0xF));
1120	serge	793	return -EINVAL;
		794	}
		795	break;
		796	case 0x4F00:
		797	/* ZB_CNTL */
1221	serge	798	if (idx_value & 2) {
1120	serge	799	track->z_enabled = true;
		800	} else {
		801	track->z_enabled = false;
		802	}
		803	break;
		804	case 0x4F10:
		805	/* ZB_FORMAT */
1221	serge	806	switch ((idx_value & 0xF)) {
1120	serge	807	case 0:
		808	case 1:
		809	track->zb.cpp = 2;
		810	break;
		811	case 2:
		812	track->zb.cpp = 4;
		813	break;
		814	default:
		815	DRM_ERROR("Invalid z buffer format (%d) !\n",
1221	serge	816	(idx_value & 0xF));
1120	serge	817	return -EINVAL;
		818	}
		819	break;
		820	case 0x4F24:
		821	/* ZB_DEPTHPITCH */
1179	serge	822	r = r100_cs_packet_next_reloc(p, &reloc);
		823	if (r) {
		824	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		825	idx, reg);
		826	r100_cs_dump_packet(p, pkt);
		827	return r;
		828	}
		829
		830	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		831	tile_flags \|= R300_DEPTHMACROTILE_ENABLE;
		832	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		833	tile_flags \|= R300_DEPTHMICROTILE_TILED;;
		834
1221	serge	835	tmp = idx_value & ~(0x7 << 16);
1179	serge	836	tmp \|= tile_flags;
		837	ib[idx] = tmp;
		838
1221	serge	839	track->zb.pitch = idx_value & 0x3FFC;
1120	serge	840	break;
		841	case 0x4104:
		842	for (i = 0; i < 16; i++) {
		843	bool enabled;
		844
1221	serge	845	enabled = !!(idx_value & (1 << i));
1120	serge	846	track->textures[i].enabled = enabled;
		847	}
		848	break;
		849	case 0x44C0:
		850	case 0x44C4:
		851	case 0x44C8:
		852	case 0x44CC:
		853	case 0x44D0:
		854	case 0x44D4:
		855	case 0x44D8:
		856	case 0x44DC:
		857	case 0x44E0:
		858	case 0x44E4:
		859	case 0x44E8:
		860	case 0x44EC:
		861	case 0x44F0:
		862	case 0x44F4:
		863	case 0x44F8:
		864	case 0x44FC:
		865	/* TX_FORMAT1_[0-15] */
		866	i = (reg - 0x44C0) >> 2;
1221	serge	867	tmp = (idx_value >> 25) & 0x3;
1120	serge	868	track->textures[i].tex_coord_type = tmp;
1221	serge	869	switch ((idx_value & 0x1F)) {
1179	serge	870	case R300_TX_FORMAT_X8:
		871	case R300_TX_FORMAT_Y4X4:
		872	case R300_TX_FORMAT_Z3Y3X2:
1120	serge	873	track->textures[i].cpp = 1;
		874	break;
1179	serge	875	case R300_TX_FORMAT_X16:
		876	case R300_TX_FORMAT_Y8X8:
		877	case R300_TX_FORMAT_Z5Y6X5:
		878	case R300_TX_FORMAT_Z6Y5X5:
		879	case R300_TX_FORMAT_W4Z4Y4X4:
		880	case R300_TX_FORMAT_W1Z5Y5X5:
		881	case R300_TX_FORMAT_D3DMFT_CxV8U8:
		882	case R300_TX_FORMAT_B8G8_B8G8:
		883	case R300_TX_FORMAT_G8R8_G8B8:
1120	serge	884	track->textures[i].cpp = 2;
		885	break;
1179	serge	886	case R300_TX_FORMAT_Y16X16:
		887	case R300_TX_FORMAT_Z11Y11X10:
		888	case R300_TX_FORMAT_Z10Y11X11:
		889	case R300_TX_FORMAT_W8Z8Y8X8:
		890	case R300_TX_FORMAT_W2Z10Y10X10:
		891	case 0x17:
		892	case R300_TX_FORMAT_FL_I32:
		893	case 0x1e:
1120	serge	894	track->textures[i].cpp = 4;
		895	break;
1179	serge	896	case R300_TX_FORMAT_W16Z16Y16X16:
		897	case R300_TX_FORMAT_FL_R16G16B16A16:
		898	case R300_TX_FORMAT_FL_I32A32:
1120	serge	899	track->textures[i].cpp = 8;
		900	break;
1179	serge	901	case R300_TX_FORMAT_FL_R32G32B32A32:
1120	serge	902	track->textures[i].cpp = 16;
		903	break;
1403	serge	904	case R300_TX_FORMAT_DXT1:
		905	track->textures[i].cpp = 1;
		906	track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
		907	break;
		908	case R300_TX_FORMAT_ATI2N:
		909	if (p->rdev->family < CHIP_R420) {
		910	DRM_ERROR("Invalid texture format %u\n",
		911	(idx_value & 0x1F));
		912	return -EINVAL;
		913	}
		914	/* The same rules apply as for DXT3/5. */
		915	/* Pass through. */
		916	case R300_TX_FORMAT_DXT3:
		917	case R300_TX_FORMAT_DXT5:
		918	track->textures[i].cpp = 1;
		919	track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
		920	break;
1120	serge	921	default:
		922	DRM_ERROR("Invalid texture format %u\n",
1221	serge	923	(idx_value & 0x1F));
1120	serge	924	return -EINVAL;
		925	break;
		926	}
		927	break;
		928	case 0x4400:
		929	case 0x4404:
		930	case 0x4408:
		931	case 0x440C:
		932	case 0x4410:
		933	case 0x4414:
		934	case 0x4418:
		935	case 0x441C:
		936	case 0x4420:
		937	case 0x4424:
		938	case 0x4428:
		939	case 0x442C:
		940	case 0x4430:
		941	case 0x4434:
		942	case 0x4438:
		943	case 0x443C:
		944	/* TX_FILTER0_[0-15] */
		945	i = (reg - 0x4400) >> 2;
1221	serge	946	tmp = idx_value & 0x7;
1120	serge	947	if (tmp == 2 \|\| tmp == 4 \|\| tmp == 6) {
		948	track->textures[i].roundup_w = false;
		949	}
1221	serge	950	tmp = (idx_value >> 3) & 0x7;
1120	serge	951	if (tmp == 2 \|\| tmp == 4 \|\| tmp == 6) {
		952	track->textures[i].roundup_h = false;
		953	}
		954	break;
		955	case 0x4500:
		956	case 0x4504:
		957	case 0x4508:
		958	case 0x450C:
		959	case 0x4510:
		960	case 0x4514:
		961	case 0x4518:
		962	case 0x451C:
		963	case 0x4520:
		964	case 0x4524:
		965	case 0x4528:
		966	case 0x452C:
		967	case 0x4530:
		968	case 0x4534:
		969	case 0x4538:
		970	case 0x453C:
		971	/* TX_FORMAT2_[0-15] */
		972	i = (reg - 0x4500) >> 2;
1221	serge	973	tmp = idx_value & 0x3FFF;
1120	serge	974	track->textures[i].pitch = tmp + 1;
		975	if (p->rdev->family >= CHIP_RV515) {
1221	serge	976	tmp = ((idx_value >> 15) & 1) << 11;
1120	serge	977	track->textures[i].width_11 = tmp;
1221	serge	978	tmp = ((idx_value >> 16) & 1) << 11;
1120	serge	979	track->textures[i].height_11 = tmp;
1403	serge	980
		981	/* ATI1N */
		982	if (idx_value & (1 << 14)) {
		983	/* The same rules apply as for DXT1. */
		984	track->textures[i].compress_format =
		985	R100_TRACK_COMP_DXT1;
		986	}
		987	} else if (idx_value & (1 << 14)) {
		988	DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
		989	return -EINVAL;
1120	serge	990	}
		991	break;
		992	case 0x4480:
		993	case 0x4484:
		994	case 0x4488:
		995	case 0x448C:
		996	case 0x4490:
		997	case 0x4494:
		998	case 0x4498:
		999	case 0x449C:
		1000	case 0x44A0:
		1001	case 0x44A4:
		1002	case 0x44A8:
		1003	case 0x44AC:
		1004	case 0x44B0:
		1005	case 0x44B4:
		1006	case 0x44B8:
		1007	case 0x44BC:
		1008	/* TX_FORMAT0_[0-15] */
		1009	i = (reg - 0x4480) >> 2;
1221	serge	1010	tmp = idx_value & 0x7FF;
1120	serge	1011	track->textures[i].width = tmp + 1;
1221	serge	1012	tmp = (idx_value >> 11) & 0x7FF;
1120	serge	1013	track->textures[i].height = tmp + 1;
1221	serge	1014	tmp = (idx_value >> 26) & 0xF;
1120	serge	1015	track->textures[i].num_levels = tmp;
1221	serge	1016	tmp = idx_value & (1 << 31);
1120	serge	1017	track->textures[i].use_pitch = !!tmp;
1221	serge	1018	tmp = (idx_value >> 22) & 0xF;
1120	serge	1019	track->textures[i].txdepth = tmp;
		1020	break;
1179	serge	1021	case R300_ZB_ZPASS_ADDR:
		1022	r = r100_cs_packet_next_reloc(p, &reloc);
		1023	if (r) {
		1024	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1025	idx, reg);
		1026	r100_cs_dump_packet(p, pkt);
		1027	return r;
		1028	}
1221	serge	1029	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1030	break;
1403	serge	1031	case 0x4e0c:
		1032	/* RB3D_COLOR_CHANNEL_MASK */
		1033	track->color_channel_mask = idx_value;
		1034	break;
		1035	case 0x4d1c:
		1036	/* ZB_BW_CNTL */
		1037	track->fastfill = !!(idx_value & (1 << 2));
		1038	break;
		1039	case 0x4e04:
		1040	/* RB3D_BLENDCNTL */
		1041	track->blend_read_enable = !!(idx_value & (1 << 2));
		1042	break;
1179	serge	1043	case 0x4be8:
		1044	/* valid register only on RV530 */
		1045	if (p->rdev->family == CHIP_RV530)
		1046	break;
		1047	/* fallthrough do not move */
1120	serge	1048	default:
		1049	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
		1050	reg, idx);
		1051	return -EINVAL;
		1052	}
		1053	return 0;
		1054	}
		1055
		1056	static int r300_packet3_check(struct radeon_cs_parser *p,
		1057	struct radeon_cs_packet *pkt)
		1058	{
		1059	struct radeon_cs_reloc *reloc;
1179	serge	1060	struct r100_cs_track *track;
1120	serge	1061	volatile uint32_t *ib;
		1062	unsigned idx;
		1063	int r;
		1064
		1065	ib = p->ib->ptr;
		1066	idx = pkt->idx + 1;
1179	serge	1067	track = (struct r100_cs_track *)p->track;
1120	serge	1068	switch(pkt->opcode) {
		1069	case PACKET3_3D_LOAD_VBPNTR:
1221	serge	1070	r = r100_packet3_load_vbpntr(p, pkt, idx);
		1071	if (r)
1120	serge	1072	return r;
		1073	break;
		1074	case PACKET3_INDX_BUFFER:
		1075	r = r100_cs_packet_next_reloc(p, &reloc);
		1076	if (r) {
		1077	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1078	r100_cs_dump_packet(p, pkt);
		1079	return r;
		1080	}
1221	serge	1081	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1120	serge	1082	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		1083	if (r) {
		1084	return r;
		1085	}
		1086	break;
		1087	/* Draw packet */
		1088	case PACKET3_3D_DRAW_IMMD:
		1089	/* Number of dwords is vtx_size * (num_vertices - 1)
		1090	* PRIM_WALK must be equal to 3 vertex data in embedded
		1091	* in cmd stream */
1221	serge	1092	if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1120	serge	1093	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1094	return -EINVAL;
		1095	}
1221	serge	1096	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1120	serge	1097	track->immd_dwords = pkt->count - 1;
1179	serge	1098	r = r100_cs_track_check(p->rdev, track);
1120	serge	1099	if (r) {
		1100	return r;
		1101	}
		1102	break;
		1103	case PACKET3_3D_DRAW_IMMD_2:
		1104	/* Number of dwords is vtx_size * (num_vertices - 1)
		1105	* PRIM_WALK must be equal to 3 vertex data in embedded
		1106	* in cmd stream */
1221	serge	1107	if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1120	serge	1108	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1109	return -EINVAL;
		1110	}
1221	serge	1111	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1120	serge	1112	track->immd_dwords = pkt->count;
1179	serge	1113	r = r100_cs_track_check(p->rdev, track);
1120	serge	1114	if (r) {
		1115	return r;
		1116	}
		1117	break;
		1118	case PACKET3_3D_DRAW_VBUF:
1221	serge	1119	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1120	r = r100_cs_track_check(p->rdev, track);
1120	serge	1121	if (r) {
		1122	return r;
		1123	}
		1124	break;
		1125	case PACKET3_3D_DRAW_VBUF_2:
1221	serge	1126	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1127	r = r100_cs_track_check(p->rdev, track);
1120	serge	1128	if (r) {
		1129	return r;
		1130	}
		1131	break;
		1132	case PACKET3_3D_DRAW_INDX:
1221	serge	1133	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1134	r = r100_cs_track_check(p->rdev, track);
1120	serge	1135	if (r) {
		1136	return r;
		1137	}
		1138	break;
		1139	case PACKET3_3D_DRAW_INDX_2:
1221	serge	1140	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1141	r = r100_cs_track_check(p->rdev, track);
1120	serge	1142	if (r) {
		1143	return r;
		1144	}
		1145	break;
		1146	case PACKET3_NOP:
		1147	break;
		1148	default:
		1149	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		1150	return -EINVAL;
		1151	}
		1152	return 0;
		1153	}
		1154
		1155	int r300_cs_parse(struct radeon_cs_parser *p)
		1156	{
		1157	struct radeon_cs_packet pkt;
1179	serge	1158	struct r100_cs_track *track;
1120	serge	1159	int r;
		1160
1179	serge	1161	track = kzalloc(sizeof(*track), GFP_KERNEL);
		1162	r100_cs_track_clear(p->rdev, track);
		1163	p->track = track;
1120	serge	1164	do {
		1165	r = r100_cs_packet_parse(p, &pkt, p->idx);
		1166	if (r) {
		1167	return r;
		1168	}
		1169	p->idx += pkt.count + 2;
		1170	switch (pkt.type) {
		1171	case PACKET_TYPE0:
		1172	r = r100_cs_parse_packet0(p, &pkt,
		1173	p->rdev->config.r300.reg_safe_bm,
		1174	p->rdev->config.r300.reg_safe_bm_size,
		1175	&r300_packet0_check);
		1176	break;
		1177	case PACKET_TYPE2:
		1178	break;
		1179	case PACKET_TYPE3:
		1180	r = r300_packet3_check(p, &pkt);
		1181	break;
		1182	default:
		1183	DRM_ERROR("Unknown packet type %d !\n", pkt.type);
		1184	return -EINVAL;
		1185	}
		1186	if (r) {
		1187	return r;
		1188	}
		1189	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
		1190	return 0;
		1191	}
1128	serge	1192	#endif
		1193
1179	serge	1194
		1195	void r300_set_reg_safe(struct radeon_device *rdev)
1120	serge	1196	{
		1197	rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
		1198	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1179	serge	1199	}
		1200
		1201	void r300_mc_program(struct radeon_device *rdev)
		1202	{
		1203	struct r100_mc_save save;
		1204	int r;
1120	serge	1205
1179	serge	1206	r = r100_debugfs_mc_info_init(rdev);
		1207	if (r) {
		1208	dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		1209	}
		1210
		1211	/* Stops all mc clients */
		1212	r100_mc_stop(rdev, &save);
		1213	if (rdev->flags & RADEON_IS_AGP) {
		1214	WREG32(R_00014C_MC_AGP_LOCATION,
		1215	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		1216	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		1217	WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		1218	WREG32(R_00015C_AGP_BASE_2,
		1219	upper_32_bits(rdev->mc.agp_base) & 0xff);
		1220	} else {
		1221	WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		1222	WREG32(R_000170_AGP_BASE, 0);
		1223	WREG32(R_00015C_AGP_BASE_2, 0);
		1224	}
		1225	/* Wait for mc idle */
		1226	if (r300_mc_wait_for_idle(rdev))
		1227	DRM_INFO("Failed to wait MC idle before programming MC.\n");
		1228	/* Program MC, should be a 32bits limited address space */
		1229	WREG32(R_000148_MC_FB_LOCATION,
		1230	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		1231	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		1232	r100_mc_resume(rdev, &save);
		1233	}
1221	serge	1234
		1235	void r300_clock_startup(struct radeon_device *rdev)
		1236	{
		1237	u32 tmp;
		1238
		1239	if (radeon_dynclks != -1 && radeon_dynclks)
		1240	radeon_legacy_set_clock_gating(rdev, 1);
		1241	/* We need to force on some of the block */
		1242	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
		1243	tmp \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		1244	if ((rdev->family == CHIP_RV350) \|\| (rdev->family == CHIP_RV380))
		1245	tmp \|= S_00000D_FORCE_VAP(1);
		1246	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
		1247	}
		1248
		1249	static int r300_startup(struct radeon_device *rdev)
		1250	{
		1251	int r;
		1252
1321	serge	1253	/* set common regs */
		1254	r100_set_common_regs(rdev);
		1255	/* program mc */
1221	serge	1256	r300_mc_program(rdev);
		1257	/* Resume clock */
		1258	r300_clock_startup(rdev);
		1259	/* Initialize GPU configuration (# pipes, ...) */
		1260	r300_gpu_init(rdev);
		1261	/* Initialize GART (initialize after TTM so we can allocate
		1262	* memory through TTM but finalize after TTM) */
		1263	if (rdev->flags & RADEON_IS_PCIE) {
		1264	r = rv370_pcie_gart_enable(rdev);
		1265	if (r)
		1266	return r;
		1267	}
1321	serge	1268
		1269	if (rdev->family == CHIP_R300 \|\|
		1270	rdev->family == CHIP_R350 \|\|
		1271	rdev->family == CHIP_RV350)
		1272	r100_enable_bm(rdev);
		1273
1221	serge	1274	if (rdev->flags & RADEON_IS_PCI) {
		1275	r = r100_pci_gart_enable(rdev);
		1276	if (r)
		1277	return r;
		1278	}
		1279	/* Enable IRQ */
		1280	// r100_irq_set(rdev);
1403	serge	1281	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1221	serge	1282	/* 1M ring buffer */
		1283	// r = r100_cp_init(rdev, 1024 * 1024);
		1284	// if (r) {
		1285	// dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
		1286	// return r;
		1287	// }
		1288	// r = r100_wb_init(rdev);
		1289	// if (r)
		1290	// dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
		1291	// r = r100_ib_init(rdev);
		1292	// if (r) {
		1293	// dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
		1294	// return r;
		1295	// }
		1296	return 0;
		1297	}
		1298
		1299
		1300
		1301
		1302
		1303	int r300_init(struct radeon_device *rdev)
		1304	{
		1305	int r;
		1306
		1307	/* Disable VGA */
		1308	r100_vga_render_disable(rdev);
		1309	/* Initialize scratch registers */
		1310	radeon_scratch_init(rdev);
		1311	/* Initialize surface registers */
		1312	radeon_surface_init(rdev);
		1313	/* TODO: disable VGA need to use VGA request */
		1314	/* BIOS*/
		1315	if (!radeon_get_bios(rdev)) {
		1316	if (ASIC_IS_AVIVO(rdev))
		1317	return -EINVAL;
		1318	}
		1319	if (rdev->is_atom_bios) {
		1320	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		1321	return -EINVAL;
		1322	} else {
		1323	r = radeon_combios_init(rdev);
		1324	if (r)
		1325	return r;
		1326	}
		1327	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
		1328	if (radeon_gpu_reset(rdev)) {
		1329	dev_warn(rdev->dev,
		1330	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		1331	RREG32(R_000E40_RBBM_STATUS),
		1332	RREG32(R_0007C0_CP_STAT));
		1333	}
		1334	/* check if cards are posted or not */
1321	serge	1335	if (radeon_boot_test_post_card(rdev) == false)
		1336	return -EINVAL;
1221	serge	1337	/* Set asic errata */
		1338	r300_errata(rdev);
		1339	/* Initialize clocks */
		1340	radeon_get_clock_info(rdev->ddev);
1403	serge	1341	/* Initialize power management */
		1342	radeon_pm_init(rdev);
1221	serge	1343	/* Get vram informations */
		1344	r300_vram_info(rdev);
		1345	/* Initialize memory controller (also test AGP) */
		1346	r = r420_mc_init(rdev);
1246	serge	1347	dbgprintf("mc vram location %x\n", rdev->mc.vram_location);
1221	serge	1348	if (r)
		1349	return r;
		1350	/* Fence driver */
		1351	// r = radeon_fence_driver_init(rdev);
		1352	// if (r)
		1353	// return r;
		1354	// r = radeon_irq_kms_init(rdev);
		1355	// if (r)
		1356	// return r;
		1357	/* Memory manager */
		1358	r = radeon_object_init(rdev);
		1359	if (r)
		1360	return r;
		1361	if (rdev->flags & RADEON_IS_PCIE) {
		1362	r = rv370_pcie_gart_init(rdev);
		1363	if (r)
		1364	return r;
		1365	}
		1366	if (rdev->flags & RADEON_IS_PCI) {
		1367	r = r100_pci_gart_init(rdev);
		1368	if (r)
		1369	return r;
		1370	}
		1371	r300_set_reg_safe(rdev);
		1372	rdev->accel_working = true;
		1373	r = r300_startup(rdev);
		1374	if (r) {
		1375	/* Somethings want wront with the accel init stop accel */
		1376	dev_err(rdev->dev, "Disabling GPU acceleration\n");
		1377	// r300_suspend(rdev);
		1378	// r100_cp_fini(rdev);
		1379	// r100_wb_fini(rdev);
		1380	// r100_ib_fini(rdev);
		1381	if (rdev->flags & RADEON_IS_PCIE)
		1382	rv370_pcie_gart_fini(rdev);
		1383	if (rdev->flags & RADEON_IS_PCI)
		1384	r100_pci_gart_fini(rdev);
		1385	// radeon_irq_kms_fini(rdev);
		1386	rdev->accel_working = false;
		1387	}
		1388	return 0;
		1389	}

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(root)/drivers/video/drm/radeon/r300.c – Rev 1403