WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r300.c

Rev	Author	Line No.	Line
1120	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1179	serge	28	#include
1125	serge	29	#include "drmP.h"
		30	#include "drm.h"
1120	serge	31	#include "radeon_reg.h"
		32	#include "radeon.h"
1179	serge	33	#include "radeon_drm.h"
1120	serge	34
1179	serge	35	#include "r300d.h"
1221	serge	36	#include "rv350d.h"
1179	serge	37	#include "r300_reg_safe.h"
		38
1221	serge	39	/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */
1120	serge	40
		41	/*
		42	* rv370,rv380 PCIE GART
		43	*/
1221	serge	44	static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
		45
1120	serge	46	void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
		47	{
		48	uint32_t tmp;
		49	int i;
		50
		51	/* Workaround HW bug do flush 2 times */
		52	for (i = 0; i < 2; i++) {
		53	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		54	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp \| RADEON_PCIE_TX_GART_INVALIDATE_TLB);
		55	(void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		56	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
1179	serge	57	}
1120	serge	58	mb();
1179	serge	59	}
		60
		61	int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
		62	{
		63	void __iomem ptr = (void )rdev->gart.table.vram.ptr;
		64
		65	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
		66	return -EINVAL;
1120	serge	67	}
1179	serge	68	addr = (lower_32_bits(addr) >> 8) \|
		69	((upper_32_bits(addr) & 0xff) << 24) \|
		70	0xc;
		71	/* on x86 we want this to be CPU endian, on powerpc
		72	* on powerpc without HW swappers, it'll get swapped on way
		73	* into VRAM - so no need for cpu_to_le32 on VRAM tables */
		74	writel(addr, ((void __iomem )ptr) + (i 4));
		75	return 0;
1120	serge	76	}
		77
1179	serge	78	int rv370_pcie_gart_init(struct radeon_device *rdev)
1120	serge	79	{
		80	int r;
		81
1179	serge	82	if (rdev->gart.table.vram.robj) {
		83	WARN(1, "RV370 PCIE GART already initialized.\n");
		84	return 0;
		85	}
1120	serge	86	/* Initialize common gart structure */
		87	r = radeon_gart_init(rdev);
1179	serge	88	if (r)
1120	serge	89	return r;
1129	serge	90	r = rv370_debugfs_pcie_gart_info_init(rdev);
1179	serge	91	if (r)
1129	serge	92	DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
1179	serge	93	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
		94	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
		95	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
		96	return radeon_gart_table_vram_alloc(rdev);
		97	}
		98
		99	int rv370_pcie_gart_enable(struct radeon_device *rdev)
		100	{
		101	uint32_t table_addr;
		102	uint32_t tmp;
		103	int r;
		104
		105	if (rdev->gart.table.vram.robj == NULL) {
		106	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
		107	return -EINVAL;
1129	serge	108	}
1179	serge	109	r = radeon_gart_table_vram_pin(rdev);
		110	if (r)
1120	serge	111	return r;
		112	/* discard memory request outside of configured range */
		113	tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		114	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
		115	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
1268	serge	116	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - RADEON_GPU_PAGE_SIZE;
1120	serge	117	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
		118	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
		119	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
		120	table_addr = rdev->gart.table_addr;
		121	WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
		122	/* FIXME: setup default page */
		123	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location);
		124	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
		125	/* Clear error */
		126	WREG32_PCIE(0x18, 0);
		127	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		128	tmp \|= RADEON_PCIE_TX_GART_EN;
		129	tmp \|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		130	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
		131	rv370_pcie_gart_tlb_flush(rdev);
		132	DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
1179	serge	133	(unsigned)(rdev->mc.gtt_size >> 20), table_addr);
1120	serge	134	rdev->gart.ready = true;
		135	return 0;
		136	}
		137
		138	void rv370_pcie_gart_disable(struct radeon_device *rdev)
		139	{
1321	serge	140	u32 tmp;
		141	int r;
1120	serge	142
		143	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		144	tmp \|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		145	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
		146	if (rdev->gart.table.vram.robj) {
		147	// radeon_object_kunmap(rdev->gart.table.vram.robj);
		148	// radeon_object_unpin(rdev->gart.table.vram.robj);
		149	}
		150	}
		151
1179	serge	152	void rv370_pcie_gart_fini(struct radeon_device *rdev)
1120	serge	153	{
		154	rv370_pcie_gart_disable(rdev);
1179	serge	155	radeon_gart_table_vram_free(rdev);
		156	radeon_gart_fini(rdev);
1120	serge	157	}
		158
		159	void r300_fence_ring_emit(struct radeon_device *rdev,
		160	struct radeon_fence *fence)
		161	{
		162	/* Who ever call radeon_fence_emit should call ring_lock and ask
		163	* for enough space (today caller are ib schedule and buffer move) */
		164	/* Write SC register so SC & US assert idle */
		165	radeon_ring_write(rdev, PACKET0(0x43E0, 0));
		166	radeon_ring_write(rdev, 0);
		167	radeon_ring_write(rdev, PACKET0(0x43E4, 0));
		168	radeon_ring_write(rdev, 0);
		169	/* Flush 3D cache */
		170	radeon_ring_write(rdev, PACKET0(0x4E4C, 0));
		171	radeon_ring_write(rdev, (2 << 0));
		172	radeon_ring_write(rdev, PACKET0(0x4F18, 0));
		173	radeon_ring_write(rdev, (1 << 0));
		174	/* Wait until IDLE & CLEAN */
		175	radeon_ring_write(rdev, PACKET0(0x1720, 0));
		176	radeon_ring_write(rdev, (1 << 17) \| (1 << 16) \| (1 << 9));
		177	/* Emit fence sequence & fire IRQ */
		178	radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
		179	radeon_ring_write(rdev, fence->seq);
		180	radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
		181	radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
		182	}
		183
		184
1128	serge	185	#if 0
		186
1221	serge	187
1120	serge	188	int r300_copy_dma(struct radeon_device *rdev,
		189	uint64_t src_offset,
		190	uint64_t dst_offset,
		191	unsigned num_pages,
		192	struct radeon_fence *fence)
		193	{
		194	uint32_t size;
		195	uint32_t cur_size;
		196	int i, num_loops;
		197	int r = 0;
		198
		199	/* radeon pitch is /64 */
		200	size = num_pages << PAGE_SHIFT;
		201	num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
		202	r = radeon_ring_lock(rdev, num_loops * 4 + 64);
		203	if (r) {
		204	DRM_ERROR("radeon: moving bo (%d).\n", r);
		205	return r;
		206	}
		207	/* Must wait for 2D idle & clean before DMA or hangs might happen */
		208	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 ));
		209	radeon_ring_write(rdev, (1 << 16));
		210	for (i = 0; i < num_loops; i++) {
		211	cur_size = size;
		212	if (cur_size > 0x1FFFFF) {
		213	cur_size = 0x1FFFFF;
		214	}
		215	size -= cur_size;
		216	radeon_ring_write(rdev, PACKET0(0x720, 2));
		217	radeon_ring_write(rdev, src_offset);
		218	radeon_ring_write(rdev, dst_offset);
		219	radeon_ring_write(rdev, cur_size \| (1 << 31) \| (1 << 30));
		220	src_offset += cur_size;
		221	dst_offset += cur_size;
		222	}
		223	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		224	radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
		225	if (fence) {
		226	r = radeon_fence_emit(rdev, fence);
		227	}
		228	radeon_ring_unlock_commit(rdev);
		229	return r;
		230	}
		231
1128	serge	232	#endif
		233
1120	serge	234	void r300_ring_start(struct radeon_device *rdev)
		235	{
		236	unsigned gb_tile_config;
		237	int r;
		238
		239	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
		240	gb_tile_config = (R300_ENABLE_TILING \| R300_TILE_SIZE_16);
		241	switch(rdev->num_gb_pipes) {
		242	case 2:
		243	gb_tile_config \|= R300_PIPE_COUNT_R300;
		244	break;
		245	case 3:
		246	gb_tile_config \|= R300_PIPE_COUNT_R420_3P;
		247	break;
		248	case 4:
		249	gb_tile_config \|= R300_PIPE_COUNT_R420;
		250	break;
		251	case 1:
		252	default:
		253	gb_tile_config \|= R300_PIPE_COUNT_RV350;
		254	break;
		255	}
		256
		257	r = radeon_ring_lock(rdev, 64);
		258	if (r) {
		259	return;
		260	}
		261	radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
		262	radeon_ring_write(rdev,
		263	RADEON_ISYNC_ANY2D_IDLE3D \|
		264	RADEON_ISYNC_ANY3D_IDLE2D \|
		265	RADEON_ISYNC_WAIT_IDLEGUI \|
		266	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
		267	radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
		268	radeon_ring_write(rdev, gb_tile_config);
		269	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		270	radeon_ring_write(rdev,
		271	RADEON_WAIT_2D_IDLECLEAN \|
		272	RADEON_WAIT_3D_IDLECLEAN);
		273	radeon_ring_write(rdev, PACKET0(0x170C, 0));
		274	radeon_ring_write(rdev, 1 << 31);
		275	radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
		276	radeon_ring_write(rdev, 0);
		277	radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
		278	radeon_ring_write(rdev, 0);
		279	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
		280	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH \| R300_RB3D_DC_FREE);
		281	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
		282	radeon_ring_write(rdev, R300_ZC_FLUSH \| R300_ZC_FREE);
		283	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		284	radeon_ring_write(rdev,
		285	RADEON_WAIT_2D_IDLECLEAN \|
		286	RADEON_WAIT_3D_IDLECLEAN);
		287	radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
		288	radeon_ring_write(rdev, 0);
		289	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
		290	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH \| R300_RB3D_DC_FREE);
		291	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
		292	radeon_ring_write(rdev, R300_ZC_FLUSH \| R300_ZC_FREE);
		293	radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
		294	radeon_ring_write(rdev,
		295	((6 << R300_MS_X0_SHIFT) \|
		296	(6 << R300_MS_Y0_SHIFT) \|
		297	(6 << R300_MS_X1_SHIFT) \|
		298	(6 << R300_MS_Y1_SHIFT) \|
		299	(6 << R300_MS_X2_SHIFT) \|
		300	(6 << R300_MS_Y2_SHIFT) \|
		301	(6 << R300_MSBD0_Y_SHIFT) \|
		302	(6 << R300_MSBD0_X_SHIFT)));
		303	radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
		304	radeon_ring_write(rdev,
		305	((6 << R300_MS_X3_SHIFT) \|
		306	(6 << R300_MS_Y3_SHIFT) \|
		307	(6 << R300_MS_X4_SHIFT) \|
		308	(6 << R300_MS_Y4_SHIFT) \|
		309	(6 << R300_MS_X5_SHIFT) \|
		310	(6 << R300_MS_Y5_SHIFT) \|
		311	(6 << R300_MSBD1_SHIFT)));
		312	radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
		313	radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL \| R300_GA_FASTSYNC_CNTL);
		314	radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
		315	radeon_ring_write(rdev,
		316	R300_FRONT_PTYPE_TRIANGE \| R300_BACK_PTYPE_TRIANGE);
		317	radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
		318	radeon_ring_write(rdev,
		319	R300_GEOMETRY_ROUND_NEAREST \|
		320	R300_COLOR_ROUND_NEAREST);
		321	radeon_ring_unlock_commit(rdev);
		322	}
		323
		324	void r300_errata(struct radeon_device *rdev)
		325	{
		326	rdev->pll_errata = 0;
		327
		328	if (rdev->family == CHIP_R300 &&
		329	(RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
		330	rdev->pll_errata \|= CHIP_ERRATA_R300_CG;
		331	}
		332	}
		333
		334	int r300_mc_wait_for_idle(struct radeon_device *rdev)
		335	{
		336	unsigned i;
		337	uint32_t tmp;
		338
		339	for (i = 0; i < rdev->usec_timeout; i++) {
		340	/* read MC_STATUS */
		341	tmp = RREG32(0x0150);
		342	if (tmp & (1 << 4)) {
		343	return 0;
		344	}
		345	DRM_UDELAY(1);
		346	}
		347	return -1;
		348	}
		349
		350	void r300_gpu_init(struct radeon_device *rdev)
		351	{
		352	uint32_t gb_tile_config, tmp;
		353
		354	r100_hdp_reset(rdev);
		355	/* FIXME: rv380 one pipes ? */
		356	if ((rdev->family == CHIP_R300) \|\| (rdev->family == CHIP_R350)) {
		357	/* r300,r350 */
		358	rdev->num_gb_pipes = 2;
		359	} else {
		360	/* rv350,rv370,rv380 */
		361	rdev->num_gb_pipes = 1;
		362	}
1179	serge	363	rdev->num_z_pipes = 1;
1120	serge	364	gb_tile_config = (R300_ENABLE_TILING \| R300_TILE_SIZE_16);
		365	switch (rdev->num_gb_pipes) {
		366	case 2:
		367	gb_tile_config \|= R300_PIPE_COUNT_R300;
		368	break;
		369	case 3:
		370	gb_tile_config \|= R300_PIPE_COUNT_R420_3P;
		371	break;
		372	case 4:
		373	gb_tile_config \|= R300_PIPE_COUNT_R420;
		374	break;
		375	default:
		376	case 1:
		377	gb_tile_config \|= R300_PIPE_COUNT_RV350;
		378	break;
		379	}
		380	WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
		381
		382	if (r100_gui_wait_for_idle(rdev)) {
		383	printk(KERN_WARNING "Failed to wait GUI idle while "
		384	"programming pipes. Bad things might happen.\n");
		385	}
		386
		387	tmp = RREG32(0x170C);
		388	WREG32(0x170C, tmp \| (1 << 31));
		389
		390	WREG32(R300_RB2D_DSTCACHE_MODE,
		391	R300_DC_AUTOFLUSH_ENABLE \|
		392	R300_DC_DC_DISABLE_IGNORE_PE);
		393
		394	if (r100_gui_wait_for_idle(rdev)) {
		395	printk(KERN_WARNING "Failed to wait GUI idle while "
		396	"programming pipes. Bad things might happen.\n");
		397	}
		398	if (r300_mc_wait_for_idle(rdev)) {
		399	printk(KERN_WARNING "Failed to wait MC idle while "
		400	"programming pipes. Bad things might happen.\n");
		401	}
1179	serge	402	DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
		403	rdev->num_gb_pipes, rdev->num_z_pipes);
1120	serge	404	}
		405
		406	int r300_ga_reset(struct radeon_device *rdev)
		407	{
		408	uint32_t tmp;
		409	bool reinit_cp;
		410	int i;
		411
		412	reinit_cp = rdev->cp.ready;
		413	rdev->cp.ready = false;
		414	for (i = 0; i < rdev->usec_timeout; i++) {
		415	WREG32(RADEON_CP_CSQ_MODE, 0);
		416	WREG32(RADEON_CP_CSQ_CNTL, 0);
		417	WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
		418	(void)RREG32(RADEON_RBBM_SOFT_RESET);
		419	udelay(200);
		420	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		421	/* Wait to prevent race in RBBM_STATUS */
		422	mdelay(1);
		423	tmp = RREG32(RADEON_RBBM_STATUS);
		424	if (tmp & ((1 << 20) \| (1 << 26))) {
		425	DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
		426	/* GA still busy soft reset it */
		427	WREG32(0x429C, 0x200);
		428	WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
		429	WREG32(0x43E0, 0);
		430	WREG32(0x43E4, 0);
		431	WREG32(0x24AC, 0);
		432	}
		433	/* Wait to prevent race in RBBM_STATUS */
		434	mdelay(1);
		435	tmp = RREG32(RADEON_RBBM_STATUS);
		436	if (!(tmp & ((1 << 20) \| (1 << 26)))) {
		437	break;
		438	}
		439	}
		440	for (i = 0; i < rdev->usec_timeout; i++) {
		441	tmp = RREG32(RADEON_RBBM_STATUS);
		442	if (!(tmp & ((1 << 20) \| (1 << 26)))) {
		443	DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
		444	tmp);
		445	if (reinit_cp) {
		446	return r100_cp_init(rdev, rdev->cp.ring_size);
		447	}
		448	return 0;
		449	}
		450	DRM_UDELAY(1);
		451	}
		452	tmp = RREG32(RADEON_RBBM_STATUS);
		453	DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
		454	return -1;
		455	}
		456
		457	int r300_gpu_reset(struct radeon_device *rdev)
		458	{
		459	uint32_t status;
		460
		461	/* reset order likely matter */
		462	status = RREG32(RADEON_RBBM_STATUS);
		463	/* reset HDP */
		464	r100_hdp_reset(rdev);
		465	/* reset rb2d */
		466	if (status & ((1 << 17) \| (1 << 18) \| (1 << 27))) {
		467	r100_rb2d_reset(rdev);
		468	}
		469	/* reset GA */
		470	if (status & ((1 << 20) \| (1 << 26))) {
		471	r300_ga_reset(rdev);
		472	}
		473	/* reset CP */
		474	status = RREG32(RADEON_RBBM_STATUS);
		475	if (status & (1 << 16)) {
		476	r100_cp_reset(rdev);
		477	}
		478	/* Check if GPU is idle */
		479	status = RREG32(RADEON_RBBM_STATUS);
		480	if (status & (1 << 31)) {
		481	DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
		482	return -1;
		483	}
		484	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
		485	return 0;
		486	}
		487
		488
		489	/*
		490	* r300,r350,rv350,rv380 VRAM info
		491	*/
		492	void r300_vram_info(struct radeon_device *rdev)
		493	{
		494	uint32_t tmp;
		495
		496	/* DDR for all card after R300 & IGP */
		497	rdev->mc.vram_is_ddr = true;
		498	tmp = RREG32(RADEON_MEM_CNTL);
		499	if (tmp & R300_MEM_NUM_CHANNELS_MASK) {
		500	rdev->mc.vram_width = 128;
		501	} else {
		502	rdev->mc.vram_width = 64;
		503	}
		504
1179	serge	505	r100_vram_init_sizes(rdev);
1120	serge	506	}
		507
		508	void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
		509	{
		510	uint32_t link_width_cntl, mask;
		511
		512	if (rdev->flags & RADEON_IS_IGP)
		513	return;
		514
		515	if (!(rdev->flags & RADEON_IS_PCIE))
		516	return;
		517
		518	/* FIXME wait for idle */
		519
		520	switch (lanes) {
		521	case 0:
		522	mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
		523	break;
		524	case 1:
		525	mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
		526	break;
		527	case 2:
		528	mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
		529	break;
		530	case 4:
		531	mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
		532	break;
		533	case 8:
		534	mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
		535	break;
		536	case 12:
		537	mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
		538	break;
		539	case 16:
		540	default:
		541	mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
		542	break;
		543	}
		544
		545	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		546
		547	if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
		548	(mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
		549	return;
		550
		551	link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK \|
		552	RADEON_PCIE_LC_RECONFIG_NOW \|
		553	RADEON_PCIE_LC_RECONFIG_LATER \|
		554	RADEON_PCIE_LC_SHORT_RECONFIG_EN);
		555	link_width_cntl \|= mask;
		556	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
		557	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl \|
		558	RADEON_PCIE_LC_RECONFIG_NOW));
		559
		560	/* wait for lane set to complete */
		561	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		562	while (link_width_cntl == 0xffffffff)
		563	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		564
		565	}
		566
		567	#if defined(CONFIG_DEBUG_FS)
		568	static int rv370_debugfs_pcie_gart_info(struct seq_file m, void data)
		569	{
		570	struct drm_info_node node = (struct drm_info_node ) m->private;
		571	struct drm_device *dev = node->minor->dev;
		572	struct radeon_device *rdev = dev->dev_private;
		573	uint32_t tmp;
		574
		575	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		576	seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
		577	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
		578	seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
		579	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
		580	seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
		581	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
		582	seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
		583	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
		584	seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
		585	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
		586	seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
		587	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
		588	seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
		589	return 0;
		590	}
		591
		592	static struct drm_info_list rv370_pcie_gart_info_list[] = {
		593	{"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
		594	};
		595	#endif
		596
1221	serge	597	static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
1120	serge	598	{
		599	#if defined(CONFIG_DEBUG_FS)
		600	return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
		601	#else
		602	return 0;
		603	#endif
		604	}
		605
		606
1128	serge	607	#if 0
1221	serge	608
1120	serge	609	static int r300_packet0_check(struct radeon_cs_parser *p,
		610	struct radeon_cs_packet *pkt,
		611	unsigned idx, unsigned reg)
		612	{
		613	struct radeon_cs_reloc *reloc;
1179	serge	614	struct r100_cs_track *track;
1120	serge	615	volatile uint32_t *ib;
1179	serge	616	uint32_t tmp, tile_flags = 0;
1120	serge	617	unsigned i;
		618	int r;
1221	serge	619	u32 idx_value;
1120	serge	620
		621	ib = p->ib->ptr;
1179	serge	622	track = (struct r100_cs_track *)p->track;
1221	serge	623	idx_value = radeon_get_ib_value(p, idx);
		624
1120	serge	625	switch(reg) {
1179	serge	626	case AVIVO_D1MODE_VLINE_START_END:
		627	case RADEON_CRTC_GUI_TRIG_VLINE:
		628	r = r100_cs_packet_parse_vline(p);
1120	serge	629	if (r) {
		630	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		631	idx, reg);
		632	r100_cs_dump_packet(p, pkt);
		633	return r;
		634	}
		635	break;
1179	serge	636	case RADEON_DST_PITCH_OFFSET:
		637	case RADEON_SRC_PITCH_OFFSET:
		638	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		639	if (r)
		640	return r;
		641	break;
1120	serge	642	case R300_RB3D_COLOROFFSET0:
		643	case R300_RB3D_COLOROFFSET1:
		644	case R300_RB3D_COLOROFFSET2:
		645	case R300_RB3D_COLOROFFSET3:
		646	i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
		647	r = r100_cs_packet_next_reloc(p, &reloc);
		648	if (r) {
		649	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		650	idx, reg);
		651	r100_cs_dump_packet(p, pkt);
		652	return r;
		653	}
		654	track->cb[i].robj = reloc->robj;
1221	serge	655	track->cb[i].offset = idx_value;
		656	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1120	serge	657	break;
		658	case R300_ZB_DEPTHOFFSET:
		659	r = r100_cs_packet_next_reloc(p, &reloc);
		660	if (r) {
		661	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		662	idx, reg);
		663	r100_cs_dump_packet(p, pkt);
		664	return r;
		665	}
		666	track->zb.robj = reloc->robj;
1221	serge	667	track->zb.offset = idx_value;
		668	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1120	serge	669	break;
		670	case R300_TX_OFFSET_0:
		671	case R300_TX_OFFSET_0+4:
		672	case R300_TX_OFFSET_0+8:
		673	case R300_TX_OFFSET_0+12:
		674	case R300_TX_OFFSET_0+16:
		675	case R300_TX_OFFSET_0+20:
		676	case R300_TX_OFFSET_0+24:
		677	case R300_TX_OFFSET_0+28:
		678	case R300_TX_OFFSET_0+32:
		679	case R300_TX_OFFSET_0+36:
		680	case R300_TX_OFFSET_0+40:
		681	case R300_TX_OFFSET_0+44:
		682	case R300_TX_OFFSET_0+48:
		683	case R300_TX_OFFSET_0+52:
		684	case R300_TX_OFFSET_0+56:
		685	case R300_TX_OFFSET_0+60:
		686	i = (reg - R300_TX_OFFSET_0) >> 2;
		687	r = r100_cs_packet_next_reloc(p, &reloc);
		688	if (r) {
		689	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		690	idx, reg);
		691	r100_cs_dump_packet(p, pkt);
		692	return r;
		693	}
1221	serge	694	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1120	serge	695	track->textures[i].robj = reloc->robj;
		696	break;
		697	/* Tracked registers */
		698	case 0x2084:
		699	/* VAP_VF_CNTL */
1221	serge	700	track->vap_vf_cntl = idx_value;
1120	serge	701	break;
		702	case 0x20B4:
		703	/* VAP_VTX_SIZE */
1221	serge	704	track->vtx_size = idx_value & 0x7F;
1120	serge	705	break;
		706	case 0x2134:
		707	/* VAP_VF_MAX_VTX_INDX */
1221	serge	708	track->max_indx = idx_value & 0x00FFFFFFUL;
1120	serge	709	break;
		710	case 0x43E4:
		711	/* SC_SCISSOR1 */
1221	serge	712	track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
1120	serge	713	if (p->rdev->family < CHIP_RV515) {
		714	track->maxy -= 1440;
		715	}
		716	break;
		717	case 0x4E00:
		718	/* RB3D_CCTL */
1221	serge	719	track->num_cb = ((idx_value >> 5) & 0x3) + 1;
1120	serge	720	break;
		721	case 0x4E38:
		722	case 0x4E3C:
		723	case 0x4E40:
		724	case 0x4E44:
		725	/* RB3D_COLORPITCH0 */
		726	/* RB3D_COLORPITCH1 */
		727	/* RB3D_COLORPITCH2 */
		728	/* RB3D_COLORPITCH3 */
1179	serge	729	r = r100_cs_packet_next_reloc(p, &reloc);
		730	if (r) {
		731	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		732	idx, reg);
		733	r100_cs_dump_packet(p, pkt);
		734	return r;
		735	}
		736
		737	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		738	tile_flags \|= R300_COLOR_TILE_ENABLE;
		739	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		740	tile_flags \|= R300_COLOR_MICROTILE_ENABLE;
		741
1221	serge	742	tmp = idx_value & ~(0x7 << 16);
1179	serge	743	tmp \|= tile_flags;
		744	ib[idx] = tmp;
		745
1120	serge	746	i = (reg - 0x4E38) >> 2;
1221	serge	747	track->cb[i].pitch = idx_value & 0x3FFE;
		748	switch (((idx_value >> 21) & 0xF)) {
1120	serge	749	case 9:
		750	case 11:
		751	case 12:
		752	track->cb[i].cpp = 1;
		753	break;
		754	case 3:
		755	case 4:
		756	case 13:
		757	case 15:
		758	track->cb[i].cpp = 2;
		759	break;
		760	case 6:
		761	track->cb[i].cpp = 4;
		762	break;
		763	case 10:
		764	track->cb[i].cpp = 8;
		765	break;
		766	case 7:
		767	track->cb[i].cpp = 16;
		768	break;
		769	default:
		770	DRM_ERROR("Invalid color buffer format (%d) !\n",
1221	serge	771	((idx_value >> 21) & 0xF));
1120	serge	772	return -EINVAL;
		773	}
		774	break;
		775	case 0x4F00:
		776	/* ZB_CNTL */
1221	serge	777	if (idx_value & 2) {
1120	serge	778	track->z_enabled = true;
		779	} else {
		780	track->z_enabled = false;
		781	}
		782	break;
		783	case 0x4F10:
		784	/* ZB_FORMAT */
1221	serge	785	switch ((idx_value & 0xF)) {
1120	serge	786	case 0:
		787	case 1:
		788	track->zb.cpp = 2;
		789	break;
		790	case 2:
		791	track->zb.cpp = 4;
		792	break;
		793	default:
		794	DRM_ERROR("Invalid z buffer format (%d) !\n",
1221	serge	795	(idx_value & 0xF));
1120	serge	796	return -EINVAL;
		797	}
		798	break;
		799	case 0x4F24:
		800	/* ZB_DEPTHPITCH */
1179	serge	801	r = r100_cs_packet_next_reloc(p, &reloc);
		802	if (r) {
		803	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		804	idx, reg);
		805	r100_cs_dump_packet(p, pkt);
		806	return r;
		807	}
		808
		809	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		810	tile_flags \|= R300_DEPTHMACROTILE_ENABLE;
		811	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		812	tile_flags \|= R300_DEPTHMICROTILE_TILED;;
		813
1221	serge	814	tmp = idx_value & ~(0x7 << 16);
1179	serge	815	tmp \|= tile_flags;
		816	ib[idx] = tmp;
		817
1221	serge	818	track->zb.pitch = idx_value & 0x3FFC;
1120	serge	819	break;
		820	case 0x4104:
		821	for (i = 0; i < 16; i++) {
		822	bool enabled;
		823
1221	serge	824	enabled = !!(idx_value & (1 << i));
1120	serge	825	track->textures[i].enabled = enabled;
		826	}
		827	break;
		828	case 0x44C0:
		829	case 0x44C4:
		830	case 0x44C8:
		831	case 0x44CC:
		832	case 0x44D0:
		833	case 0x44D4:
		834	case 0x44D8:
		835	case 0x44DC:
		836	case 0x44E0:
		837	case 0x44E4:
		838	case 0x44E8:
		839	case 0x44EC:
		840	case 0x44F0:
		841	case 0x44F4:
		842	case 0x44F8:
		843	case 0x44FC:
		844	/* TX_FORMAT1_[0-15] */
		845	i = (reg - 0x44C0) >> 2;
1221	serge	846	tmp = (idx_value >> 25) & 0x3;
1120	serge	847	track->textures[i].tex_coord_type = tmp;
1221	serge	848	switch ((idx_value & 0x1F)) {
1179	serge	849	case R300_TX_FORMAT_X8:
		850	case R300_TX_FORMAT_Y4X4:
		851	case R300_TX_FORMAT_Z3Y3X2:
1120	serge	852	track->textures[i].cpp = 1;
		853	break;
1179	serge	854	case R300_TX_FORMAT_X16:
		855	case R300_TX_FORMAT_Y8X8:
		856	case R300_TX_FORMAT_Z5Y6X5:
		857	case R300_TX_FORMAT_Z6Y5X5:
		858	case R300_TX_FORMAT_W4Z4Y4X4:
		859	case R300_TX_FORMAT_W1Z5Y5X5:
		860	case R300_TX_FORMAT_DXT1:
		861	case R300_TX_FORMAT_D3DMFT_CxV8U8:
		862	case R300_TX_FORMAT_B8G8_B8G8:
		863	case R300_TX_FORMAT_G8R8_G8B8:
1120	serge	864	track->textures[i].cpp = 2;
		865	break;
1179	serge	866	case R300_TX_FORMAT_Y16X16:
		867	case R300_TX_FORMAT_Z11Y11X10:
		868	case R300_TX_FORMAT_Z10Y11X11:
		869	case R300_TX_FORMAT_W8Z8Y8X8:
		870	case R300_TX_FORMAT_W2Z10Y10X10:
		871	case 0x17:
		872	case R300_TX_FORMAT_FL_I32:
		873	case 0x1e:
		874	case R300_TX_FORMAT_DXT3:
		875	case R300_TX_FORMAT_DXT5:
1120	serge	876	track->textures[i].cpp = 4;
		877	break;
1179	serge	878	case R300_TX_FORMAT_W16Z16Y16X16:
		879	case R300_TX_FORMAT_FL_R16G16B16A16:
		880	case R300_TX_FORMAT_FL_I32A32:
1120	serge	881	track->textures[i].cpp = 8;
		882	break;
1179	serge	883	case R300_TX_FORMAT_FL_R32G32B32A32:
1120	serge	884	track->textures[i].cpp = 16;
		885	break;
		886	default:
		887	DRM_ERROR("Invalid texture format %u\n",
1221	serge	888	(idx_value & 0x1F));
1120	serge	889	return -EINVAL;
		890	break;
		891	}
		892	break;
		893	case 0x4400:
		894	case 0x4404:
		895	case 0x4408:
		896	case 0x440C:
		897	case 0x4410:
		898	case 0x4414:
		899	case 0x4418:
		900	case 0x441C:
		901	case 0x4420:
		902	case 0x4424:
		903	case 0x4428:
		904	case 0x442C:
		905	case 0x4430:
		906	case 0x4434:
		907	case 0x4438:
		908	case 0x443C:
		909	/* TX_FILTER0_[0-15] */
		910	i = (reg - 0x4400) >> 2;
1221	serge	911	tmp = idx_value & 0x7;
1120	serge	912	if (tmp == 2 \|\| tmp == 4 \|\| tmp == 6) {
		913	track->textures[i].roundup_w = false;
		914	}
1221	serge	915	tmp = (idx_value >> 3) & 0x7;
1120	serge	916	if (tmp == 2 \|\| tmp == 4 \|\| tmp == 6) {
		917	track->textures[i].roundup_h = false;
		918	}
		919	break;
		920	case 0x4500:
		921	case 0x4504:
		922	case 0x4508:
		923	case 0x450C:
		924	case 0x4510:
		925	case 0x4514:
		926	case 0x4518:
		927	case 0x451C:
		928	case 0x4520:
		929	case 0x4524:
		930	case 0x4528:
		931	case 0x452C:
		932	case 0x4530:
		933	case 0x4534:
		934	case 0x4538:
		935	case 0x453C:
		936	/* TX_FORMAT2_[0-15] */
		937	i = (reg - 0x4500) >> 2;
1221	serge	938	tmp = idx_value & 0x3FFF;
1120	serge	939	track->textures[i].pitch = tmp + 1;
		940	if (p->rdev->family >= CHIP_RV515) {
1221	serge	941	tmp = ((idx_value >> 15) & 1) << 11;
1120	serge	942	track->textures[i].width_11 = tmp;
1221	serge	943	tmp = ((idx_value >> 16) & 1) << 11;
1120	serge	944	track->textures[i].height_11 = tmp;
		945	}
		946	break;
		947	case 0x4480:
		948	case 0x4484:
		949	case 0x4488:
		950	case 0x448C:
		951	case 0x4490:
		952	case 0x4494:
		953	case 0x4498:
		954	case 0x449C:
		955	case 0x44A0:
		956	case 0x44A4:
		957	case 0x44A8:
		958	case 0x44AC:
		959	case 0x44B0:
		960	case 0x44B4:
		961	case 0x44B8:
		962	case 0x44BC:
		963	/* TX_FORMAT0_[0-15] */
		964	i = (reg - 0x4480) >> 2;
1221	serge	965	tmp = idx_value & 0x7FF;
1120	serge	966	track->textures[i].width = tmp + 1;
1221	serge	967	tmp = (idx_value >> 11) & 0x7FF;
1120	serge	968	track->textures[i].height = tmp + 1;
1221	serge	969	tmp = (idx_value >> 26) & 0xF;
1120	serge	970	track->textures[i].num_levels = tmp;
1221	serge	971	tmp = idx_value & (1 << 31);
1120	serge	972	track->textures[i].use_pitch = !!tmp;
1221	serge	973	tmp = (idx_value >> 22) & 0xF;
1120	serge	974	track->textures[i].txdepth = tmp;
		975	break;
1179	serge	976	case R300_ZB_ZPASS_ADDR:
		977	r = r100_cs_packet_next_reloc(p, &reloc);
		978	if (r) {
		979	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		980	idx, reg);
		981	r100_cs_dump_packet(p, pkt);
		982	return r;
		983	}
1221	serge	984	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	985	break;
		986	case 0x4be8:
		987	/* valid register only on RV530 */
		988	if (p->rdev->family == CHIP_RV530)
		989	break;
		990	/* fallthrough do not move */
1120	serge	991	default:
		992	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
		993	reg, idx);
		994	return -EINVAL;
		995	}
		996	return 0;
		997	}
		998
		999	static int r300_packet3_check(struct radeon_cs_parser *p,
		1000	struct radeon_cs_packet *pkt)
		1001	{
		1002	struct radeon_cs_reloc *reloc;
1179	serge	1003	struct r100_cs_track *track;
1120	serge	1004	volatile uint32_t *ib;
		1005	unsigned idx;
		1006	int r;
		1007
		1008	ib = p->ib->ptr;
		1009	idx = pkt->idx + 1;
1179	serge	1010	track = (struct r100_cs_track *)p->track;
1120	serge	1011	switch(pkt->opcode) {
		1012	case PACKET3_3D_LOAD_VBPNTR:
1221	serge	1013	r = r100_packet3_load_vbpntr(p, pkt, idx);
		1014	if (r)
1120	serge	1015	return r;
		1016	break;
		1017	case PACKET3_INDX_BUFFER:
		1018	r = r100_cs_packet_next_reloc(p, &reloc);
		1019	if (r) {
		1020	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1021	r100_cs_dump_packet(p, pkt);
		1022	return r;
		1023	}
1221	serge	1024	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1120	serge	1025	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		1026	if (r) {
		1027	return r;
		1028	}
		1029	break;
		1030	/* Draw packet */
		1031	case PACKET3_3D_DRAW_IMMD:
		1032	/* Number of dwords is vtx_size * (num_vertices - 1)
		1033	* PRIM_WALK must be equal to 3 vertex data in embedded
		1034	* in cmd stream */
1221	serge	1035	if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1120	serge	1036	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1037	return -EINVAL;
		1038	}
1221	serge	1039	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1120	serge	1040	track->immd_dwords = pkt->count - 1;
1179	serge	1041	r = r100_cs_track_check(p->rdev, track);
1120	serge	1042	if (r) {
		1043	return r;
		1044	}
		1045	break;
		1046	case PACKET3_3D_DRAW_IMMD_2:
		1047	/* Number of dwords is vtx_size * (num_vertices - 1)
		1048	* PRIM_WALK must be equal to 3 vertex data in embedded
		1049	* in cmd stream */
1221	serge	1050	if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1120	serge	1051	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1052	return -EINVAL;
		1053	}
1221	serge	1054	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1120	serge	1055	track->immd_dwords = pkt->count;
1179	serge	1056	r = r100_cs_track_check(p->rdev, track);
1120	serge	1057	if (r) {
		1058	return r;
		1059	}
		1060	break;
		1061	case PACKET3_3D_DRAW_VBUF:
1221	serge	1062	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1063	r = r100_cs_track_check(p->rdev, track);
1120	serge	1064	if (r) {
		1065	return r;
		1066	}
		1067	break;
		1068	case PACKET3_3D_DRAW_VBUF_2:
1221	serge	1069	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1070	r = r100_cs_track_check(p->rdev, track);
1120	serge	1071	if (r) {
		1072	return r;
		1073	}
		1074	break;
		1075	case PACKET3_3D_DRAW_INDX:
1221	serge	1076	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1077	r = r100_cs_track_check(p->rdev, track);
1120	serge	1078	if (r) {
		1079	return r;
		1080	}
		1081	break;
		1082	case PACKET3_3D_DRAW_INDX_2:
1221	serge	1083	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1084	r = r100_cs_track_check(p->rdev, track);
1120	serge	1085	if (r) {
		1086	return r;
		1087	}
		1088	break;
		1089	case PACKET3_NOP:
		1090	break;
		1091	default:
		1092	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		1093	return -EINVAL;
		1094	}
		1095	return 0;
		1096	}
		1097
		1098	int r300_cs_parse(struct radeon_cs_parser *p)
		1099	{
		1100	struct radeon_cs_packet pkt;
1179	serge	1101	struct r100_cs_track *track;
1120	serge	1102	int r;
		1103
1179	serge	1104	track = kzalloc(sizeof(*track), GFP_KERNEL);
		1105	r100_cs_track_clear(p->rdev, track);
		1106	p->track = track;
1120	serge	1107	do {
		1108	r = r100_cs_packet_parse(p, &pkt, p->idx);
		1109	if (r) {
		1110	return r;
		1111	}
		1112	p->idx += pkt.count + 2;
		1113	switch (pkt.type) {
		1114	case PACKET_TYPE0:
		1115	r = r100_cs_parse_packet0(p, &pkt,
		1116	p->rdev->config.r300.reg_safe_bm,
		1117	p->rdev->config.r300.reg_safe_bm_size,
		1118	&r300_packet0_check);
		1119	break;
		1120	case PACKET_TYPE2:
		1121	break;
		1122	case PACKET_TYPE3:
		1123	r = r300_packet3_check(p, &pkt);
		1124	break;
		1125	default:
		1126	DRM_ERROR("Unknown packet type %d !\n", pkt.type);
		1127	return -EINVAL;
		1128	}
		1129	if (r) {
		1130	return r;
		1131	}
		1132	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
		1133	return 0;
		1134	}
1128	serge	1135	#endif
		1136
1179	serge	1137
		1138	void r300_set_reg_safe(struct radeon_device *rdev)
1120	serge	1139	{
		1140	rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
		1141	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1179	serge	1142	}
		1143
		1144	void r300_mc_program(struct radeon_device *rdev)
		1145	{
		1146	struct r100_mc_save save;
		1147	int r;
1120	serge	1148
1179	serge	1149	r = r100_debugfs_mc_info_init(rdev);
		1150	if (r) {
		1151	dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		1152	}
		1153
		1154	/* Stops all mc clients */
		1155	r100_mc_stop(rdev, &save);
		1156	if (rdev->flags & RADEON_IS_AGP) {
		1157	WREG32(R_00014C_MC_AGP_LOCATION,
		1158	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		1159	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		1160	WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		1161	WREG32(R_00015C_AGP_BASE_2,
		1162	upper_32_bits(rdev->mc.agp_base) & 0xff);
		1163	} else {
		1164	WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		1165	WREG32(R_000170_AGP_BASE, 0);
		1166	WREG32(R_00015C_AGP_BASE_2, 0);
		1167	}
		1168	/* Wait for mc idle */
		1169	if (r300_mc_wait_for_idle(rdev))
		1170	DRM_INFO("Failed to wait MC idle before programming MC.\n");
		1171	/* Program MC, should be a 32bits limited address space */
		1172	WREG32(R_000148_MC_FB_LOCATION,
		1173	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		1174	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		1175	r100_mc_resume(rdev, &save);
		1176	}
1221	serge	1177
		1178	void r300_clock_startup(struct radeon_device *rdev)
		1179	{
		1180	u32 tmp;
		1181
		1182	if (radeon_dynclks != -1 && radeon_dynclks)
		1183	radeon_legacy_set_clock_gating(rdev, 1);
		1184	/* We need to force on some of the block */
		1185	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
		1186	tmp \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		1187	if ((rdev->family == CHIP_RV350) \|\| (rdev->family == CHIP_RV380))
		1188	tmp \|= S_00000D_FORCE_VAP(1);
		1189	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
		1190	}
		1191
		1192	static int r300_startup(struct radeon_device *rdev)
		1193	{
		1194	int r;
		1195
1321	serge	1196	/* set common regs */
		1197	r100_set_common_regs(rdev);
		1198	/* program mc */
1221	serge	1199	r300_mc_program(rdev);
		1200	/* Resume clock */
		1201	r300_clock_startup(rdev);
		1202	/* Initialize GPU configuration (# pipes, ...) */
		1203	r300_gpu_init(rdev);
		1204	/* Initialize GART (initialize after TTM so we can allocate
		1205	* memory through TTM but finalize after TTM) */
		1206	if (rdev->flags & RADEON_IS_PCIE) {
		1207	r = rv370_pcie_gart_enable(rdev);
		1208	if (r)
		1209	return r;
		1210	}
1321	serge	1211
		1212	if (rdev->family == CHIP_R300 \|\|
		1213	rdev->family == CHIP_R350 \|\|
		1214	rdev->family == CHIP_RV350)
		1215	r100_enable_bm(rdev);
		1216
1221	serge	1217	if (rdev->flags & RADEON_IS_PCI) {
		1218	r = r100_pci_gart_enable(rdev);
		1219	if (r)
		1220	return r;
		1221	}
		1222	/* Enable IRQ */
		1223	// r100_irq_set(rdev);
		1224	/* 1M ring buffer */
		1225	// r = r100_cp_init(rdev, 1024 * 1024);
		1226	// if (r) {
		1227	// dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
		1228	// return r;
		1229	// }
		1230	// r = r100_wb_init(rdev);
		1231	// if (r)
		1232	// dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
		1233	// r = r100_ib_init(rdev);
		1234	// if (r) {
		1235	// dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
		1236	// return r;
		1237	// }
		1238	return 0;
		1239	}
		1240
		1241
		1242
		1243
		1244
		1245	int r300_init(struct radeon_device *rdev)
		1246	{
		1247	int r;
		1248
		1249	/* Disable VGA */
		1250	r100_vga_render_disable(rdev);
		1251	/* Initialize scratch registers */
		1252	radeon_scratch_init(rdev);
		1253	/* Initialize surface registers */
		1254	radeon_surface_init(rdev);
		1255	/* TODO: disable VGA need to use VGA request */
		1256	/* BIOS*/
		1257	if (!radeon_get_bios(rdev)) {
		1258	if (ASIC_IS_AVIVO(rdev))
		1259	return -EINVAL;
		1260	}
		1261	if (rdev->is_atom_bios) {
		1262	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		1263	return -EINVAL;
		1264	} else {
		1265	r = radeon_combios_init(rdev);
		1266	if (r)
		1267	return r;
		1268	}
		1269	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
		1270	if (radeon_gpu_reset(rdev)) {
		1271	dev_warn(rdev->dev,
		1272	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		1273	RREG32(R_000E40_RBBM_STATUS),
		1274	RREG32(R_0007C0_CP_STAT));
		1275	}
		1276	/* check if cards are posted or not */
1321	serge	1277	if (radeon_boot_test_post_card(rdev) == false)
		1278	return -EINVAL;
1221	serge	1279	/* Set asic errata */
		1280	r300_errata(rdev);
		1281	/* Initialize clocks */
		1282	radeon_get_clock_info(rdev->ddev);
		1283	/* Get vram informations */
		1284	r300_vram_info(rdev);
		1285	/* Initialize memory controller (also test AGP) */
		1286	r = r420_mc_init(rdev);
1246	serge	1287	dbgprintf("mc vram location %x\n", rdev->mc.vram_location);
1221	serge	1288	if (r)
		1289	return r;
		1290	/* Fence driver */
		1291	// r = radeon_fence_driver_init(rdev);
		1292	// if (r)
		1293	// return r;
		1294	// r = radeon_irq_kms_init(rdev);
		1295	// if (r)
		1296	// return r;
		1297	/* Memory manager */
		1298	r = radeon_object_init(rdev);
		1299	if (r)
		1300	return r;
		1301	if (rdev->flags & RADEON_IS_PCIE) {
		1302	r = rv370_pcie_gart_init(rdev);
		1303	if (r)
		1304	return r;
		1305	}
		1306	if (rdev->flags & RADEON_IS_PCI) {
		1307	r = r100_pci_gart_init(rdev);
		1308	if (r)
		1309	return r;
		1310	}
		1311	r300_set_reg_safe(rdev);
		1312	rdev->accel_working = true;
		1313	r = r300_startup(rdev);
		1314	if (r) {
		1315	/* Somethings want wront with the accel init stop accel */
		1316	dev_err(rdev->dev, "Disabling GPU acceleration\n");
		1317	// r300_suspend(rdev);
		1318	// r100_cp_fini(rdev);
		1319	// r100_wb_fini(rdev);
		1320	// r100_ib_fini(rdev);
		1321	if (rdev->flags & RADEON_IS_PCIE)
		1322	rv370_pcie_gart_fini(rdev);
		1323	if (rdev->flags & RADEON_IS_PCI)
		1324	r100_pci_gart_fini(rdev);
		1325	// radeon_irq_kms_fini(rdev);
		1326	rdev->accel_working = false;
		1327	}
		1328	return 0;
		1329	}

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(root)/drivers/video/drm/radeon/r300.c – Rev 1321