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Rev | Author | Line No. | Line |
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1120 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1179 | serge | 28 | #include |
1125 | serge | 29 | #include "drmP.h" |
30 | #include "drm.h" |
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1120 | serge | 31 | #include "radeon_reg.h" |
32 | #include "radeon.h" |
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1179 | serge | 33 | #include "radeon_drm.h" |
1120 | serge | 34 | |
1179 | serge | 35 | #include "r300d.h" |
36 | |||
37 | #include "r300_reg_safe.h" |
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38 | |||
1120 | serge | 39 | /* r300,r350,rv350,rv370,rv380 depends on : */ |
40 | void r100_hdp_reset(struct radeon_device *rdev); |
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41 | int r100_cp_reset(struct radeon_device *rdev); |
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42 | int r100_rb2d_reset(struct radeon_device *rdev); |
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43 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
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44 | int r100_pci_gart_enable(struct radeon_device *rdev); |
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45 | void r100_mc_setup(struct radeon_device *rdev); |
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46 | void r100_mc_disable_clients(struct radeon_device *rdev); |
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47 | int r100_gui_wait_for_idle(struct radeon_device *rdev); |
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48 | int r100_cs_packet_parse(struct radeon_cs_parser *p, |
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49 | struct radeon_cs_packet *pkt, |
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50 | unsigned idx); |
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1179 | serge | 51 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); |
1120 | serge | 52 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
53 | struct radeon_cs_packet *pkt, |
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54 | const unsigned *auth, unsigned n, |
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55 | radeon_packet0_check_t check); |
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56 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
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57 | struct radeon_cs_packet *pkt, |
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58 | struct radeon_object *robj); |
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59 | |||
60 | /* This files gather functions specifics to: |
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61 | * r300,r350,rv350,rv370,rv380 |
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62 | * |
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63 | * Some of these functions might be used by newer ASICs. |
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64 | */ |
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65 | void r300_gpu_init(struct radeon_device *rdev); |
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66 | int r300_mc_wait_for_idle(struct radeon_device *rdev); |
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67 | int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
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68 | |||
69 | |||
70 | /* |
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71 | * rv370,rv380 PCIE GART |
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72 | */ |
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73 | void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) |
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74 | { |
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75 | uint32_t tmp; |
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76 | int i; |
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77 | |||
78 | /* Workaround HW bug do flush 2 times */ |
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79 | for (i = 0; i < 2; i++) { |
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80 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
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81 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); |
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82 | (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
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83 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
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1179 | serge | 84 | } |
1120 | serge | 85 | mb(); |
1179 | serge | 86 | } |
87 | |||
88 | int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
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89 | { |
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90 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
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91 | |||
92 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
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93 | return -EINVAL; |
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1120 | serge | 94 | } |
1179 | serge | 95 | addr = (lower_32_bits(addr) >> 8) | |
96 | ((upper_32_bits(addr) & 0xff) << 24) | |
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97 | 0xc; |
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98 | /* on x86 we want this to be CPU endian, on powerpc |
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99 | * on powerpc without HW swappers, it'll get swapped on way |
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100 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ |
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101 | writel(addr, ((void __iomem *)ptr) + (i * 4)); |
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102 | return 0; |
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1120 | serge | 103 | } |
104 | |||
1179 | serge | 105 | int rv370_pcie_gart_init(struct radeon_device *rdev) |
1120 | serge | 106 | { |
107 | int r; |
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108 | |||
1179 | serge | 109 | if (rdev->gart.table.vram.robj) { |
110 | WARN(1, "RV370 PCIE GART already initialized.\n"); |
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111 | return 0; |
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112 | } |
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1120 | serge | 113 | /* Initialize common gart structure */ |
114 | r = radeon_gart_init(rdev); |
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1179 | serge | 115 | if (r) |
1120 | serge | 116 | return r; |
1129 | serge | 117 | r = rv370_debugfs_pcie_gart_info_init(rdev); |
1179 | serge | 118 | if (r) |
1129 | serge | 119 | DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); |
1179 | serge | 120 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
121 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
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122 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
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123 | return radeon_gart_table_vram_alloc(rdev); |
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124 | } |
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125 | |||
126 | int rv370_pcie_gart_enable(struct radeon_device *rdev) |
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127 | { |
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128 | uint32_t table_addr; |
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129 | uint32_t tmp; |
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130 | int r; |
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131 | |||
132 | if (rdev->gart.table.vram.robj == NULL) { |
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133 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
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134 | return -EINVAL; |
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1129 | serge | 135 | } |
1179 | serge | 136 | r = radeon_gart_table_vram_pin(rdev); |
137 | if (r) |
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1120 | serge | 138 | return r; |
139 | /* discard memory request outside of configured range */ |
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140 | tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
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141 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
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142 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location); |
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143 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 4096; |
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144 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); |
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145 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); |
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146 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); |
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147 | table_addr = rdev->gart.table_addr; |
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148 | WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); |
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149 | /* FIXME: setup default page */ |
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150 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location); |
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151 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); |
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152 | /* Clear error */ |
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153 | WREG32_PCIE(0x18, 0); |
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154 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
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155 | tmp |= RADEON_PCIE_TX_GART_EN; |
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156 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
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157 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
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158 | rv370_pcie_gart_tlb_flush(rdev); |
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159 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n", |
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1179 | serge | 160 | (unsigned)(rdev->mc.gtt_size >> 20), table_addr); |
1120 | serge | 161 | rdev->gart.ready = true; |
162 | return 0; |
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163 | } |
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164 | |||
165 | void rv370_pcie_gart_disable(struct radeon_device *rdev) |
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166 | { |
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167 | uint32_t tmp; |
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168 | |||
169 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
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170 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
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171 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); |
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172 | if (rdev->gart.table.vram.robj) { |
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173 | // radeon_object_kunmap(rdev->gart.table.vram.robj); |
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174 | // radeon_object_unpin(rdev->gart.table.vram.robj); |
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175 | } |
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176 | } |
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177 | |||
1179 | serge | 178 | void rv370_pcie_gart_fini(struct radeon_device *rdev) |
1120 | serge | 179 | { |
180 | rv370_pcie_gart_disable(rdev); |
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1179 | serge | 181 | radeon_gart_table_vram_free(rdev); |
182 | radeon_gart_fini(rdev); |
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1120 | serge | 183 | } |
184 | |||
185 | /* |
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186 | * MC |
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187 | */ |
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188 | int r300_mc_init(struct radeon_device *rdev) |
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189 | { |
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190 | int r; |
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191 | |||
1129 | serge | 192 | if (r100_debugfs_rbbm_init(rdev)) { |
193 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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194 | } |
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1120 | serge | 195 | |
196 | r300_gpu_init(rdev); |
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197 | r100_pci_gart_disable(rdev); |
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198 | if (rdev->flags & RADEON_IS_PCIE) { |
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199 | rv370_pcie_gart_disable(rdev); |
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200 | } |
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201 | |||
202 | /* Setup GPU memory space */ |
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203 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
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204 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
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205 | r = radeon_mc_setup(rdev); |
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206 | if (r) { |
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207 | return r; |
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208 | } |
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209 | |||
210 | /* Program GPU memory space */ |
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211 | r100_mc_disable_clients(rdev); |
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212 | if (r300_mc_wait_for_idle(rdev)) { |
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213 | printk(KERN_WARNING "Failed to wait MC idle while " |
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214 | "programming pipes. Bad things might happen.\n"); |
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215 | } |
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216 | r100_mc_setup(rdev); |
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217 | return 0; |
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218 | } |
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219 | |||
220 | void r300_mc_fini(struct radeon_device *rdev) |
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221 | { |
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222 | } |
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223 | |||
224 | |||
225 | /* |
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226 | * Fence emission |
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227 | */ |
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228 | void r300_fence_ring_emit(struct radeon_device *rdev, |
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229 | struct radeon_fence *fence) |
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230 | { |
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231 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
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232 | * for enough space (today caller are ib schedule and buffer move) */ |
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233 | /* Write SC register so SC & US assert idle */ |
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234 | radeon_ring_write(rdev, PACKET0(0x43E0, 0)); |
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235 | radeon_ring_write(rdev, 0); |
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236 | radeon_ring_write(rdev, PACKET0(0x43E4, 0)); |
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237 | radeon_ring_write(rdev, 0); |
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238 | /* Flush 3D cache */ |
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239 | radeon_ring_write(rdev, PACKET0(0x4E4C, 0)); |
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240 | radeon_ring_write(rdev, (2 << 0)); |
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241 | radeon_ring_write(rdev, PACKET0(0x4F18, 0)); |
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242 | radeon_ring_write(rdev, (1 << 0)); |
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243 | /* Wait until IDLE & CLEAN */ |
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244 | radeon_ring_write(rdev, PACKET0(0x1720, 0)); |
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245 | radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9)); |
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246 | /* Emit fence sequence & fire IRQ */ |
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247 | radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); |
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248 | radeon_ring_write(rdev, fence->seq); |
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249 | radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
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250 | radeon_ring_write(rdev, RADEON_SW_INT_FIRE); |
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251 | } |
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252 | |||
253 | |||
1128 | serge | 254 | #if 0 |
255 | |||
1120 | serge | 256 | /* |
257 | * Global GPU functions |
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258 | */ |
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259 | int r300_copy_dma(struct radeon_device *rdev, |
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260 | uint64_t src_offset, |
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261 | uint64_t dst_offset, |
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262 | unsigned num_pages, |
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263 | struct radeon_fence *fence) |
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264 | { |
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265 | uint32_t size; |
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266 | uint32_t cur_size; |
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267 | int i, num_loops; |
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268 | int r = 0; |
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269 | |||
270 | /* radeon pitch is /64 */ |
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271 | size = num_pages << PAGE_SHIFT; |
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272 | num_loops = DIV_ROUND_UP(size, 0x1FFFFF); |
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273 | r = radeon_ring_lock(rdev, num_loops * 4 + 64); |
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274 | if (r) { |
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275 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
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276 | return r; |
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277 | } |
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278 | /* Must wait for 2D idle & clean before DMA or hangs might happen */ |
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279 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 )); |
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280 | radeon_ring_write(rdev, (1 << 16)); |
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281 | for (i = 0; i < num_loops; i++) { |
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282 | cur_size = size; |
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283 | if (cur_size > 0x1FFFFF) { |
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284 | cur_size = 0x1FFFFF; |
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285 | } |
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286 | size -= cur_size; |
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287 | radeon_ring_write(rdev, PACKET0(0x720, 2)); |
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288 | radeon_ring_write(rdev, src_offset); |
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289 | radeon_ring_write(rdev, dst_offset); |
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290 | radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30)); |
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291 | src_offset += cur_size; |
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292 | dst_offset += cur_size; |
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293 | } |
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294 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
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295 | radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE); |
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296 | if (fence) { |
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297 | r = radeon_fence_emit(rdev, fence); |
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298 | } |
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299 | radeon_ring_unlock_commit(rdev); |
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300 | return r; |
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301 | } |
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302 | |||
1128 | serge | 303 | #endif |
304 | |||
1120 | serge | 305 | void r300_ring_start(struct radeon_device *rdev) |
306 | { |
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307 | unsigned gb_tile_config; |
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308 | int r; |
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309 | |||
310 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
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311 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
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312 | switch(rdev->num_gb_pipes) { |
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313 | case 2: |
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314 | gb_tile_config |= R300_PIPE_COUNT_R300; |
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315 | break; |
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316 | case 3: |
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317 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
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318 | break; |
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319 | case 4: |
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320 | gb_tile_config |= R300_PIPE_COUNT_R420; |
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321 | break; |
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322 | case 1: |
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323 | default: |
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324 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
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325 | break; |
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326 | } |
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327 | |||
328 | r = radeon_ring_lock(rdev, 64); |
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329 | if (r) { |
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330 | return; |
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331 | } |
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332 | radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); |
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333 | radeon_ring_write(rdev, |
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334 | RADEON_ISYNC_ANY2D_IDLE3D | |
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335 | RADEON_ISYNC_ANY3D_IDLE2D | |
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336 | RADEON_ISYNC_WAIT_IDLEGUI | |
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337 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
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338 | radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); |
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339 | radeon_ring_write(rdev, gb_tile_config); |
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340 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
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341 | radeon_ring_write(rdev, |
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342 | RADEON_WAIT_2D_IDLECLEAN | |
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343 | RADEON_WAIT_3D_IDLECLEAN); |
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344 | radeon_ring_write(rdev, PACKET0(0x170C, 0)); |
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345 | radeon_ring_write(rdev, 1 << 31); |
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346 | radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); |
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347 | radeon_ring_write(rdev, 0); |
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348 | radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); |
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349 | radeon_ring_write(rdev, 0); |
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350 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
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351 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
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352 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
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353 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
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354 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
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355 | radeon_ring_write(rdev, |
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356 | RADEON_WAIT_2D_IDLECLEAN | |
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357 | RADEON_WAIT_3D_IDLECLEAN); |
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358 | radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); |
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359 | radeon_ring_write(rdev, 0); |
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360 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
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361 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
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362 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
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363 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
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364 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); |
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365 | radeon_ring_write(rdev, |
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366 | ((6 << R300_MS_X0_SHIFT) | |
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367 | (6 << R300_MS_Y0_SHIFT) | |
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368 | (6 << R300_MS_X1_SHIFT) | |
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369 | (6 << R300_MS_Y1_SHIFT) | |
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370 | (6 << R300_MS_X2_SHIFT) | |
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371 | (6 << R300_MS_Y2_SHIFT) | |
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372 | (6 << R300_MSBD0_Y_SHIFT) | |
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373 | (6 << R300_MSBD0_X_SHIFT))); |
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374 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); |
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375 | radeon_ring_write(rdev, |
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376 | ((6 << R300_MS_X3_SHIFT) | |
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377 | (6 << R300_MS_Y3_SHIFT) | |
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378 | (6 << R300_MS_X4_SHIFT) | |
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379 | (6 << R300_MS_Y4_SHIFT) | |
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380 | (6 << R300_MS_X5_SHIFT) | |
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381 | (6 << R300_MS_Y5_SHIFT) | |
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382 | (6 << R300_MSBD1_SHIFT))); |
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383 | radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); |
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384 | radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
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385 | radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); |
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386 | radeon_ring_write(rdev, |
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387 | R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
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388 | radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); |
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389 | radeon_ring_write(rdev, |
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390 | R300_GEOMETRY_ROUND_NEAREST | |
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391 | R300_COLOR_ROUND_NEAREST); |
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392 | radeon_ring_unlock_commit(rdev); |
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393 | } |
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394 | |||
395 | void r300_errata(struct radeon_device *rdev) |
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396 | { |
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397 | rdev->pll_errata = 0; |
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398 | |||
399 | if (rdev->family == CHIP_R300 && |
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400 | (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { |
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401 | rdev->pll_errata |= CHIP_ERRATA_R300_CG; |
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402 | } |
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403 | } |
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404 | |||
405 | int r300_mc_wait_for_idle(struct radeon_device *rdev) |
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406 | { |
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407 | unsigned i; |
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408 | uint32_t tmp; |
||
409 | |||
410 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
411 | /* read MC_STATUS */ |
||
412 | tmp = RREG32(0x0150); |
||
413 | if (tmp & (1 << 4)) { |
||
414 | return 0; |
||
415 | } |
||
416 | DRM_UDELAY(1); |
||
417 | } |
||
418 | return -1; |
||
419 | } |
||
420 | |||
421 | void r300_gpu_init(struct radeon_device *rdev) |
||
422 | { |
||
423 | uint32_t gb_tile_config, tmp; |
||
424 | |||
425 | r100_hdp_reset(rdev); |
||
426 | /* FIXME: rv380 one pipes ? */ |
||
427 | if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) { |
||
428 | /* r300,r350 */ |
||
429 | rdev->num_gb_pipes = 2; |
||
430 | } else { |
||
431 | /* rv350,rv370,rv380 */ |
||
432 | rdev->num_gb_pipes = 1; |
||
433 | } |
||
1179 | serge | 434 | rdev->num_z_pipes = 1; |
1120 | serge | 435 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
436 | switch (rdev->num_gb_pipes) { |
||
437 | case 2: |
||
438 | gb_tile_config |= R300_PIPE_COUNT_R300; |
||
439 | break; |
||
440 | case 3: |
||
441 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
||
442 | break; |
||
443 | case 4: |
||
444 | gb_tile_config |= R300_PIPE_COUNT_R420; |
||
445 | break; |
||
446 | default: |
||
447 | case 1: |
||
448 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
||
449 | break; |
||
450 | } |
||
451 | WREG32(R300_GB_TILE_CONFIG, gb_tile_config); |
||
452 | |||
453 | if (r100_gui_wait_for_idle(rdev)) { |
||
454 | printk(KERN_WARNING "Failed to wait GUI idle while " |
||
455 | "programming pipes. Bad things might happen.\n"); |
||
456 | } |
||
457 | |||
458 | tmp = RREG32(0x170C); |
||
459 | WREG32(0x170C, tmp | (1 << 31)); |
||
460 | |||
461 | WREG32(R300_RB2D_DSTCACHE_MODE, |
||
462 | R300_DC_AUTOFLUSH_ENABLE | |
||
463 | R300_DC_DC_DISABLE_IGNORE_PE); |
||
464 | |||
465 | if (r100_gui_wait_for_idle(rdev)) { |
||
466 | printk(KERN_WARNING "Failed to wait GUI idle while " |
||
467 | "programming pipes. Bad things might happen.\n"); |
||
468 | } |
||
469 | if (r300_mc_wait_for_idle(rdev)) { |
||
470 | printk(KERN_WARNING "Failed to wait MC idle while " |
||
471 | "programming pipes. Bad things might happen.\n"); |
||
472 | } |
||
1179 | serge | 473 | DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", |
474 | rdev->num_gb_pipes, rdev->num_z_pipes); |
||
1120 | serge | 475 | } |
476 | |||
477 | int r300_ga_reset(struct radeon_device *rdev) |
||
478 | { |
||
479 | uint32_t tmp; |
||
480 | bool reinit_cp; |
||
481 | int i; |
||
482 | |||
483 | reinit_cp = rdev->cp.ready; |
||
484 | rdev->cp.ready = false; |
||
485 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
486 | WREG32(RADEON_CP_CSQ_MODE, 0); |
||
487 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
||
488 | WREG32(RADEON_RBBM_SOFT_RESET, 0x32005); |
||
489 | (void)RREG32(RADEON_RBBM_SOFT_RESET); |
||
490 | udelay(200); |
||
491 | WREG32(RADEON_RBBM_SOFT_RESET, 0); |
||
492 | /* Wait to prevent race in RBBM_STATUS */ |
||
493 | mdelay(1); |
||
494 | tmp = RREG32(RADEON_RBBM_STATUS); |
||
495 | if (tmp & ((1 << 20) | (1 << 26))) { |
||
496 | DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp); |
||
497 | /* GA still busy soft reset it */ |
||
498 | WREG32(0x429C, 0x200); |
||
499 | WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
||
500 | WREG32(0x43E0, 0); |
||
501 | WREG32(0x43E4, 0); |
||
502 | WREG32(0x24AC, 0); |
||
503 | } |
||
504 | /* Wait to prevent race in RBBM_STATUS */ |
||
505 | mdelay(1); |
||
506 | tmp = RREG32(RADEON_RBBM_STATUS); |
||
507 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
||
508 | break; |
||
509 | } |
||
510 | } |
||
511 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
512 | tmp = RREG32(RADEON_RBBM_STATUS); |
||
513 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
||
514 | DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", |
||
515 | tmp); |
||
516 | if (reinit_cp) { |
||
517 | return r100_cp_init(rdev, rdev->cp.ring_size); |
||
518 | } |
||
519 | return 0; |
||
520 | } |
||
521 | DRM_UDELAY(1); |
||
522 | } |
||
523 | tmp = RREG32(RADEON_RBBM_STATUS); |
||
524 | DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); |
||
525 | return -1; |
||
526 | } |
||
527 | |||
528 | int r300_gpu_reset(struct radeon_device *rdev) |
||
529 | { |
||
530 | uint32_t status; |
||
531 | |||
532 | /* reset order likely matter */ |
||
533 | status = RREG32(RADEON_RBBM_STATUS); |
||
534 | /* reset HDP */ |
||
535 | r100_hdp_reset(rdev); |
||
536 | /* reset rb2d */ |
||
537 | if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { |
||
538 | r100_rb2d_reset(rdev); |
||
539 | } |
||
540 | /* reset GA */ |
||
541 | if (status & ((1 << 20) | (1 << 26))) { |
||
542 | r300_ga_reset(rdev); |
||
543 | } |
||
544 | /* reset CP */ |
||
545 | status = RREG32(RADEON_RBBM_STATUS); |
||
546 | if (status & (1 << 16)) { |
||
547 | r100_cp_reset(rdev); |
||
548 | } |
||
549 | /* Check if GPU is idle */ |
||
550 | status = RREG32(RADEON_RBBM_STATUS); |
||
551 | if (status & (1 << 31)) { |
||
552 | DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); |
||
553 | return -1; |
||
554 | } |
||
555 | DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
||
556 | return 0; |
||
557 | } |
||
558 | |||
559 | |||
560 | /* |
||
561 | * r300,r350,rv350,rv380 VRAM info |
||
562 | */ |
||
563 | void r300_vram_info(struct radeon_device *rdev) |
||
564 | { |
||
565 | uint32_t tmp; |
||
566 | |||
567 | /* DDR for all card after R300 & IGP */ |
||
568 | rdev->mc.vram_is_ddr = true; |
||
569 | tmp = RREG32(RADEON_MEM_CNTL); |
||
570 | if (tmp & R300_MEM_NUM_CHANNELS_MASK) { |
||
571 | rdev->mc.vram_width = 128; |
||
572 | } else { |
||
573 | rdev->mc.vram_width = 64; |
||
574 | } |
||
575 | |||
1179 | serge | 576 | r100_vram_init_sizes(rdev); |
1120 | serge | 577 | } |
578 | |||
579 | |||
580 | /* |
||
581 | * PCIE Lanes |
||
582 | */ |
||
583 | |||
584 | void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) |
||
585 | { |
||
586 | uint32_t link_width_cntl, mask; |
||
587 | |||
588 | if (rdev->flags & RADEON_IS_IGP) |
||
589 | return; |
||
590 | |||
591 | if (!(rdev->flags & RADEON_IS_PCIE)) |
||
592 | return; |
||
593 | |||
594 | /* FIXME wait for idle */ |
||
595 | |||
596 | switch (lanes) { |
||
597 | case 0: |
||
598 | mask = RADEON_PCIE_LC_LINK_WIDTH_X0; |
||
599 | break; |
||
600 | case 1: |
||
601 | mask = RADEON_PCIE_LC_LINK_WIDTH_X1; |
||
602 | break; |
||
603 | case 2: |
||
604 | mask = RADEON_PCIE_LC_LINK_WIDTH_X2; |
||
605 | break; |
||
606 | case 4: |
||
607 | mask = RADEON_PCIE_LC_LINK_WIDTH_X4; |
||
608 | break; |
||
609 | case 8: |
||
610 | mask = RADEON_PCIE_LC_LINK_WIDTH_X8; |
||
611 | break; |
||
612 | case 12: |
||
613 | mask = RADEON_PCIE_LC_LINK_WIDTH_X12; |
||
614 | break; |
||
615 | case 16: |
||
616 | default: |
||
617 | mask = RADEON_PCIE_LC_LINK_WIDTH_X16; |
||
618 | break; |
||
619 | } |
||
620 | |||
621 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
||
622 | |||
623 | if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == |
||
624 | (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) |
||
625 | return; |
||
626 | |||
627 | link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | |
||
628 | RADEON_PCIE_LC_RECONFIG_NOW | |
||
629 | RADEON_PCIE_LC_RECONFIG_LATER | |
||
630 | RADEON_PCIE_LC_SHORT_RECONFIG_EN); |
||
631 | link_width_cntl |= mask; |
||
632 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
||
633 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | |
||
634 | RADEON_PCIE_LC_RECONFIG_NOW)); |
||
635 | |||
636 | /* wait for lane set to complete */ |
||
637 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
||
638 | while (link_width_cntl == 0xffffffff) |
||
639 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
||
640 | |||
641 | } |
||
642 | |||
643 | |||
644 | /* |
||
645 | * Debugfs info |
||
646 | */ |
||
647 | #if defined(CONFIG_DEBUG_FS) |
||
648 | static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) |
||
649 | { |
||
650 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
651 | struct drm_device *dev = node->minor->dev; |
||
652 | struct radeon_device *rdev = dev->dev_private; |
||
653 | uint32_t tmp; |
||
654 | |||
655 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
||
656 | seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); |
||
657 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); |
||
658 | seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); |
||
659 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); |
||
660 | seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); |
||
661 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); |
||
662 | seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); |
||
663 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); |
||
664 | seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); |
||
665 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); |
||
666 | seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); |
||
667 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); |
||
668 | seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); |
||
669 | return 0; |
||
670 | } |
||
671 | |||
672 | static struct drm_info_list rv370_pcie_gart_info_list[] = { |
||
673 | {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, |
||
674 | }; |
||
675 | #endif |
||
676 | |||
677 | int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
||
678 | { |
||
679 | #if defined(CONFIG_DEBUG_FS) |
||
680 | return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); |
||
681 | #else |
||
682 | return 0; |
||
683 | #endif |
||
684 | } |
||
685 | |||
686 | |||
1128 | serge | 687 | #if 0 |
1120 | serge | 688 | /* |
689 | * CS functions |
||
690 | */ |
||
691 | static int r300_packet0_check(struct radeon_cs_parser *p, |
||
692 | struct radeon_cs_packet *pkt, |
||
693 | unsigned idx, unsigned reg) |
||
694 | { |
||
695 | struct radeon_cs_chunk *ib_chunk; |
||
696 | struct radeon_cs_reloc *reloc; |
||
1179 | serge | 697 | struct r100_cs_track *track; |
1120 | serge | 698 | volatile uint32_t *ib; |
1179 | serge | 699 | uint32_t tmp, tile_flags = 0; |
1120 | serge | 700 | unsigned i; |
701 | int r; |
||
702 | |||
703 | ib = p->ib->ptr; |
||
704 | ib_chunk = &p->chunks[p->chunk_ib_idx]; |
||
1179 | serge | 705 | track = (struct r100_cs_track *)p->track; |
1120 | serge | 706 | switch(reg) { |
1179 | serge | 707 | case AVIVO_D1MODE_VLINE_START_END: |
708 | case RADEON_CRTC_GUI_TRIG_VLINE: |
||
709 | r = r100_cs_packet_parse_vline(p); |
||
1120 | serge | 710 | if (r) { |
711 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
712 | idx, reg); |
||
713 | r100_cs_dump_packet(p, pkt); |
||
714 | return r; |
||
715 | } |
||
716 | break; |
||
1179 | serge | 717 | case RADEON_DST_PITCH_OFFSET: |
718 | case RADEON_SRC_PITCH_OFFSET: |
||
719 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
||
720 | if (r) |
||
721 | return r; |
||
722 | break; |
||
1120 | serge | 723 | case R300_RB3D_COLOROFFSET0: |
724 | case R300_RB3D_COLOROFFSET1: |
||
725 | case R300_RB3D_COLOROFFSET2: |
||
726 | case R300_RB3D_COLOROFFSET3: |
||
727 | i = (reg - R300_RB3D_COLOROFFSET0) >> 2; |
||
728 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
729 | if (r) { |
||
730 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
731 | idx, reg); |
||
732 | r100_cs_dump_packet(p, pkt); |
||
733 | return r; |
||
734 | } |
||
735 | track->cb[i].robj = reloc->robj; |
||
736 | track->cb[i].offset = ib_chunk->kdata[idx]; |
||
737 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
||
738 | break; |
||
739 | case R300_ZB_DEPTHOFFSET: |
||
740 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
741 | if (r) { |
||
742 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
743 | idx, reg); |
||
744 | r100_cs_dump_packet(p, pkt); |
||
745 | return r; |
||
746 | } |
||
747 | track->zb.robj = reloc->robj; |
||
748 | track->zb.offset = ib_chunk->kdata[idx]; |
||
749 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
||
750 | break; |
||
751 | case R300_TX_OFFSET_0: |
||
752 | case R300_TX_OFFSET_0+4: |
||
753 | case R300_TX_OFFSET_0+8: |
||
754 | case R300_TX_OFFSET_0+12: |
||
755 | case R300_TX_OFFSET_0+16: |
||
756 | case R300_TX_OFFSET_0+20: |
||
757 | case R300_TX_OFFSET_0+24: |
||
758 | case R300_TX_OFFSET_0+28: |
||
759 | case R300_TX_OFFSET_0+32: |
||
760 | case R300_TX_OFFSET_0+36: |
||
761 | case R300_TX_OFFSET_0+40: |
||
762 | case R300_TX_OFFSET_0+44: |
||
763 | case R300_TX_OFFSET_0+48: |
||
764 | case R300_TX_OFFSET_0+52: |
||
765 | case R300_TX_OFFSET_0+56: |
||
766 | case R300_TX_OFFSET_0+60: |
||
767 | i = (reg - R300_TX_OFFSET_0) >> 2; |
||
768 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
769 | if (r) { |
||
770 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
771 | idx, reg); |
||
772 | r100_cs_dump_packet(p, pkt); |
||
773 | return r; |
||
774 | } |
||
775 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
||
776 | track->textures[i].robj = reloc->robj; |
||
777 | break; |
||
778 | /* Tracked registers */ |
||
779 | case 0x2084: |
||
780 | /* VAP_VF_CNTL */ |
||
781 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
||
782 | break; |
||
783 | case 0x20B4: |
||
784 | /* VAP_VTX_SIZE */ |
||
785 | track->vtx_size = ib_chunk->kdata[idx] & 0x7F; |
||
786 | break; |
||
787 | case 0x2134: |
||
788 | /* VAP_VF_MAX_VTX_INDX */ |
||
789 | track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL; |
||
790 | break; |
||
791 | case 0x43E4: |
||
792 | /* SC_SCISSOR1 */ |
||
793 | track->maxy = ((ib_chunk->kdata[idx] >> 13) & 0x1FFF) + 1; |
||
794 | if (p->rdev->family < CHIP_RV515) { |
||
795 | track->maxy -= 1440; |
||
796 | } |
||
797 | break; |
||
798 | case 0x4E00: |
||
799 | /* RB3D_CCTL */ |
||
800 | track->num_cb = ((ib_chunk->kdata[idx] >> 5) & 0x3) + 1; |
||
801 | break; |
||
802 | case 0x4E38: |
||
803 | case 0x4E3C: |
||
804 | case 0x4E40: |
||
805 | case 0x4E44: |
||
806 | /* RB3D_COLORPITCH0 */ |
||
807 | /* RB3D_COLORPITCH1 */ |
||
808 | /* RB3D_COLORPITCH2 */ |
||
809 | /* RB3D_COLORPITCH3 */ |
||
1179 | serge | 810 | r = r100_cs_packet_next_reloc(p, &reloc); |
811 | if (r) { |
||
812 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
813 | idx, reg); |
||
814 | r100_cs_dump_packet(p, pkt); |
||
815 | return r; |
||
816 | } |
||
817 | |||
818 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
||
819 | tile_flags |= R300_COLOR_TILE_ENABLE; |
||
820 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
||
821 | tile_flags |= R300_COLOR_MICROTILE_ENABLE; |
||
822 | |||
823 | tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); |
||
824 | tmp |= tile_flags; |
||
825 | ib[idx] = tmp; |
||
826 | |||
1120 | serge | 827 | i = (reg - 0x4E38) >> 2; |
828 | track->cb[i].pitch = ib_chunk->kdata[idx] & 0x3FFE; |
||
829 | switch (((ib_chunk->kdata[idx] >> 21) & 0xF)) { |
||
830 | case 9: |
||
831 | case 11: |
||
832 | case 12: |
||
833 | track->cb[i].cpp = 1; |
||
834 | break; |
||
835 | case 3: |
||
836 | case 4: |
||
837 | case 13: |
||
838 | case 15: |
||
839 | track->cb[i].cpp = 2; |
||
840 | break; |
||
841 | case 6: |
||
842 | track->cb[i].cpp = 4; |
||
843 | break; |
||
844 | case 10: |
||
845 | track->cb[i].cpp = 8; |
||
846 | break; |
||
847 | case 7: |
||
848 | track->cb[i].cpp = 16; |
||
849 | break; |
||
850 | default: |
||
851 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
||
852 | ((ib_chunk->kdata[idx] >> 21) & 0xF)); |
||
853 | return -EINVAL; |
||
854 | } |
||
855 | break; |
||
856 | case 0x4F00: |
||
857 | /* ZB_CNTL */ |
||
858 | if (ib_chunk->kdata[idx] & 2) { |
||
859 | track->z_enabled = true; |
||
860 | } else { |
||
861 | track->z_enabled = false; |
||
862 | } |
||
863 | break; |
||
864 | case 0x4F10: |
||
865 | /* ZB_FORMAT */ |
||
866 | switch ((ib_chunk->kdata[idx] & 0xF)) { |
||
867 | case 0: |
||
868 | case 1: |
||
869 | track->zb.cpp = 2; |
||
870 | break; |
||
871 | case 2: |
||
872 | track->zb.cpp = 4; |
||
873 | break; |
||
874 | default: |
||
875 | DRM_ERROR("Invalid z buffer format (%d) !\n", |
||
876 | (ib_chunk->kdata[idx] & 0xF)); |
||
877 | return -EINVAL; |
||
878 | } |
||
879 | break; |
||
880 | case 0x4F24: |
||
881 | /* ZB_DEPTHPITCH */ |
||
1179 | serge | 882 | r = r100_cs_packet_next_reloc(p, &reloc); |
883 | if (r) { |
||
884 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
885 | idx, reg); |
||
886 | r100_cs_dump_packet(p, pkt); |
||
887 | return r; |
||
888 | } |
||
889 | |||
890 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
||
891 | tile_flags |= R300_DEPTHMACROTILE_ENABLE; |
||
892 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
||
893 | tile_flags |= R300_DEPTHMICROTILE_TILED;; |
||
894 | |||
895 | tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); |
||
896 | tmp |= tile_flags; |
||
897 | ib[idx] = tmp; |
||
898 | |||
1120 | serge | 899 | track->zb.pitch = ib_chunk->kdata[idx] & 0x3FFC; |
900 | break; |
||
901 | case 0x4104: |
||
902 | for (i = 0; i < 16; i++) { |
||
903 | bool enabled; |
||
904 | |||
905 | enabled = !!(ib_chunk->kdata[idx] & (1 << i)); |
||
906 | track->textures[i].enabled = enabled; |
||
907 | } |
||
908 | break; |
||
909 | case 0x44C0: |
||
910 | case 0x44C4: |
||
911 | case 0x44C8: |
||
912 | case 0x44CC: |
||
913 | case 0x44D0: |
||
914 | case 0x44D4: |
||
915 | case 0x44D8: |
||
916 | case 0x44DC: |
||
917 | case 0x44E0: |
||
918 | case 0x44E4: |
||
919 | case 0x44E8: |
||
920 | case 0x44EC: |
||
921 | case 0x44F0: |
||
922 | case 0x44F4: |
||
923 | case 0x44F8: |
||
924 | case 0x44FC: |
||
925 | /* TX_FORMAT1_[0-15] */ |
||
926 | i = (reg - 0x44C0) >> 2; |
||
927 | tmp = (ib_chunk->kdata[idx] >> 25) & 0x3; |
||
928 | track->textures[i].tex_coord_type = tmp; |
||
929 | switch ((ib_chunk->kdata[idx] & 0x1F)) { |
||
1179 | serge | 930 | case R300_TX_FORMAT_X8: |
931 | case R300_TX_FORMAT_Y4X4: |
||
932 | case R300_TX_FORMAT_Z3Y3X2: |
||
1120 | serge | 933 | track->textures[i].cpp = 1; |
934 | break; |
||
1179 | serge | 935 | case R300_TX_FORMAT_X16: |
936 | case R300_TX_FORMAT_Y8X8: |
||
937 | case R300_TX_FORMAT_Z5Y6X5: |
||
938 | case R300_TX_FORMAT_Z6Y5X5: |
||
939 | case R300_TX_FORMAT_W4Z4Y4X4: |
||
940 | case R300_TX_FORMAT_W1Z5Y5X5: |
||
941 | case R300_TX_FORMAT_DXT1: |
||
942 | case R300_TX_FORMAT_D3DMFT_CxV8U8: |
||
943 | case R300_TX_FORMAT_B8G8_B8G8: |
||
944 | case R300_TX_FORMAT_G8R8_G8B8: |
||
1120 | serge | 945 | track->textures[i].cpp = 2; |
946 | break; |
||
1179 | serge | 947 | case R300_TX_FORMAT_Y16X16: |
948 | case R300_TX_FORMAT_Z11Y11X10: |
||
949 | case R300_TX_FORMAT_Z10Y11X11: |
||
950 | case R300_TX_FORMAT_W8Z8Y8X8: |
||
951 | case R300_TX_FORMAT_W2Z10Y10X10: |
||
952 | case 0x17: |
||
953 | case R300_TX_FORMAT_FL_I32: |
||
954 | case 0x1e: |
||
955 | case R300_TX_FORMAT_DXT3: |
||
956 | case R300_TX_FORMAT_DXT5: |
||
1120 | serge | 957 | track->textures[i].cpp = 4; |
958 | break; |
||
1179 | serge | 959 | case R300_TX_FORMAT_W16Z16Y16X16: |
960 | case R300_TX_FORMAT_FL_R16G16B16A16: |
||
961 | case R300_TX_FORMAT_FL_I32A32: |
||
1120 | serge | 962 | track->textures[i].cpp = 8; |
963 | break; |
||
1179 | serge | 964 | case R300_TX_FORMAT_FL_R32G32B32A32: |
1120 | serge | 965 | track->textures[i].cpp = 16; |
966 | break; |
||
967 | default: |
||
968 | DRM_ERROR("Invalid texture format %u\n", |
||
969 | (ib_chunk->kdata[idx] & 0x1F)); |
||
970 | return -EINVAL; |
||
971 | break; |
||
972 | } |
||
973 | break; |
||
974 | case 0x4400: |
||
975 | case 0x4404: |
||
976 | case 0x4408: |
||
977 | case 0x440C: |
||
978 | case 0x4410: |
||
979 | case 0x4414: |
||
980 | case 0x4418: |
||
981 | case 0x441C: |
||
982 | case 0x4420: |
||
983 | case 0x4424: |
||
984 | case 0x4428: |
||
985 | case 0x442C: |
||
986 | case 0x4430: |
||
987 | case 0x4434: |
||
988 | case 0x4438: |
||
989 | case 0x443C: |
||
990 | /* TX_FILTER0_[0-15] */ |
||
991 | i = (reg - 0x4400) >> 2; |
||
1179 | serge | 992 | tmp = ib_chunk->kdata[idx] & 0x7; |
1120 | serge | 993 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
994 | track->textures[i].roundup_w = false; |
||
995 | } |
||
1179 | serge | 996 | tmp = (ib_chunk->kdata[idx] >> 3) & 0x7; |
1120 | serge | 997 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
998 | track->textures[i].roundup_h = false; |
||
999 | } |
||
1000 | break; |
||
1001 | case 0x4500: |
||
1002 | case 0x4504: |
||
1003 | case 0x4508: |
||
1004 | case 0x450C: |
||
1005 | case 0x4510: |
||
1006 | case 0x4514: |
||
1007 | case 0x4518: |
||
1008 | case 0x451C: |
||
1009 | case 0x4520: |
||
1010 | case 0x4524: |
||
1011 | case 0x4528: |
||
1012 | case 0x452C: |
||
1013 | case 0x4530: |
||
1014 | case 0x4534: |
||
1015 | case 0x4538: |
||
1016 | case 0x453C: |
||
1017 | /* TX_FORMAT2_[0-15] */ |
||
1018 | i = (reg - 0x4500) >> 2; |
||
1019 | tmp = ib_chunk->kdata[idx] & 0x3FFF; |
||
1020 | track->textures[i].pitch = tmp + 1; |
||
1021 | if (p->rdev->family >= CHIP_RV515) { |
||
1022 | tmp = ((ib_chunk->kdata[idx] >> 15) & 1) << 11; |
||
1023 | track->textures[i].width_11 = tmp; |
||
1024 | tmp = ((ib_chunk->kdata[idx] >> 16) & 1) << 11; |
||
1025 | track->textures[i].height_11 = tmp; |
||
1026 | } |
||
1027 | break; |
||
1028 | case 0x4480: |
||
1029 | case 0x4484: |
||
1030 | case 0x4488: |
||
1031 | case 0x448C: |
||
1032 | case 0x4490: |
||
1033 | case 0x4494: |
||
1034 | case 0x4498: |
||
1035 | case 0x449C: |
||
1036 | case 0x44A0: |
||
1037 | case 0x44A4: |
||
1038 | case 0x44A8: |
||
1039 | case 0x44AC: |
||
1040 | case 0x44B0: |
||
1041 | case 0x44B4: |
||
1042 | case 0x44B8: |
||
1043 | case 0x44BC: |
||
1044 | /* TX_FORMAT0_[0-15] */ |
||
1045 | i = (reg - 0x4480) >> 2; |
||
1046 | tmp = ib_chunk->kdata[idx] & 0x7FF; |
||
1047 | track->textures[i].width = tmp + 1; |
||
1048 | tmp = (ib_chunk->kdata[idx] >> 11) & 0x7FF; |
||
1049 | track->textures[i].height = tmp + 1; |
||
1050 | tmp = (ib_chunk->kdata[idx] >> 26) & 0xF; |
||
1051 | track->textures[i].num_levels = tmp; |
||
1052 | tmp = ib_chunk->kdata[idx] & (1 << 31); |
||
1053 | track->textures[i].use_pitch = !!tmp; |
||
1054 | tmp = (ib_chunk->kdata[idx] >> 22) & 0xF; |
||
1055 | track->textures[i].txdepth = tmp; |
||
1056 | break; |
||
1179 | serge | 1057 | case R300_ZB_ZPASS_ADDR: |
1058 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1059 | if (r) { |
||
1060 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1061 | idx, reg); |
||
1062 | r100_cs_dump_packet(p, pkt); |
||
1063 | return r; |
||
1064 | } |
||
1065 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
||
1066 | break; |
||
1067 | case 0x4be8: |
||
1068 | /* valid register only on RV530 */ |
||
1069 | if (p->rdev->family == CHIP_RV530) |
||
1070 | break; |
||
1071 | /* fallthrough do not move */ |
||
1120 | serge | 1072 | default: |
1073 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
||
1074 | reg, idx); |
||
1075 | return -EINVAL; |
||
1076 | } |
||
1077 | return 0; |
||
1078 | } |
||
1079 | |||
1080 | static int r300_packet3_check(struct radeon_cs_parser *p, |
||
1081 | struct radeon_cs_packet *pkt) |
||
1082 | { |
||
1083 | struct radeon_cs_chunk *ib_chunk; |
||
1179 | serge | 1084 | |
1120 | serge | 1085 | struct radeon_cs_reloc *reloc; |
1179 | serge | 1086 | struct r100_cs_track *track; |
1120 | serge | 1087 | volatile uint32_t *ib; |
1088 | unsigned idx; |
||
1089 | unsigned i, c; |
||
1090 | int r; |
||
1091 | |||
1092 | ib = p->ib->ptr; |
||
1093 | ib_chunk = &p->chunks[p->chunk_ib_idx]; |
||
1094 | idx = pkt->idx + 1; |
||
1179 | serge | 1095 | track = (struct r100_cs_track *)p->track; |
1120 | serge | 1096 | switch(pkt->opcode) { |
1097 | case PACKET3_3D_LOAD_VBPNTR: |
||
1098 | c = ib_chunk->kdata[idx++] & 0x1F; |
||
1099 | track->num_arrays = c; |
||
1100 | for (i = 0; i < (c - 1); i+=2, idx+=3) { |
||
1101 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1102 | if (r) { |
||
1103 | DRM_ERROR("No reloc for packet3 %d\n", |
||
1104 | pkt->opcode); |
||
1105 | r100_cs_dump_packet(p, pkt); |
||
1106 | return r; |
||
1107 | } |
||
1108 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
||
1109 | track->arrays[i + 0].robj = reloc->robj; |
||
1110 | track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; |
||
1111 | track->arrays[i + 0].esize &= 0x7F; |
||
1112 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1113 | if (r) { |
||
1114 | DRM_ERROR("No reloc for packet3 %d\n", |
||
1115 | pkt->opcode); |
||
1116 | r100_cs_dump_packet(p, pkt); |
||
1117 | return r; |
||
1118 | } |
||
1119 | ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset); |
||
1120 | track->arrays[i + 1].robj = reloc->robj; |
||
1121 | track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24; |
||
1122 | track->arrays[i + 1].esize &= 0x7F; |
||
1123 | } |
||
1124 | if (c & 1) { |
||
1125 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1126 | if (r) { |
||
1127 | DRM_ERROR("No reloc for packet3 %d\n", |
||
1128 | pkt->opcode); |
||
1129 | r100_cs_dump_packet(p, pkt); |
||
1130 | return r; |
||
1131 | } |
||
1132 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
||
1133 | track->arrays[i + 0].robj = reloc->robj; |
||
1134 | track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; |
||
1135 | track->arrays[i + 0].esize &= 0x7F; |
||
1136 | } |
||
1137 | break; |
||
1138 | case PACKET3_INDX_BUFFER: |
||
1139 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1140 | if (r) { |
||
1141 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
||
1142 | r100_cs_dump_packet(p, pkt); |
||
1143 | return r; |
||
1144 | } |
||
1145 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
||
1146 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
||
1147 | if (r) { |
||
1148 | return r; |
||
1149 | } |
||
1150 | break; |
||
1151 | /* Draw packet */ |
||
1152 | case PACKET3_3D_DRAW_IMMD: |
||
1153 | /* Number of dwords is vtx_size * (num_vertices - 1) |
||
1154 | * PRIM_WALK must be equal to 3 vertex data in embedded |
||
1155 | * in cmd stream */ |
||
1156 | if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) { |
||
1157 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
||
1158 | return -EINVAL; |
||
1159 | } |
||
1160 | track->vap_vf_cntl = ib_chunk->kdata[idx+1]; |
||
1161 | track->immd_dwords = pkt->count - 1; |
||
1179 | serge | 1162 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1163 | if (r) { |
1164 | return r; |
||
1165 | } |
||
1166 | break; |
||
1167 | case PACKET3_3D_DRAW_IMMD_2: |
||
1168 | /* Number of dwords is vtx_size * (num_vertices - 1) |
||
1169 | * PRIM_WALK must be equal to 3 vertex data in embedded |
||
1170 | * in cmd stream */ |
||
1171 | if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) { |
||
1172 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
||
1173 | return -EINVAL; |
||
1174 | } |
||
1175 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
||
1176 | track->immd_dwords = pkt->count; |
||
1179 | serge | 1177 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1178 | if (r) { |
1179 | return r; |
||
1180 | } |
||
1181 | break; |
||
1182 | case PACKET3_3D_DRAW_VBUF: |
||
1183 | track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; |
||
1179 | serge | 1184 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1185 | if (r) { |
1186 | return r; |
||
1187 | } |
||
1188 | break; |
||
1189 | case PACKET3_3D_DRAW_VBUF_2: |
||
1190 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
||
1179 | serge | 1191 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1192 | if (r) { |
1193 | return r; |
||
1194 | } |
||
1195 | break; |
||
1196 | case PACKET3_3D_DRAW_INDX: |
||
1197 | track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; |
||
1179 | serge | 1198 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1199 | if (r) { |
1200 | return r; |
||
1201 | } |
||
1202 | break; |
||
1203 | case PACKET3_3D_DRAW_INDX_2: |
||
1204 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
||
1179 | serge | 1205 | r = r100_cs_track_check(p->rdev, track); |
1120 | serge | 1206 | if (r) { |
1207 | return r; |
||
1208 | } |
||
1209 | break; |
||
1210 | case PACKET3_NOP: |
||
1211 | break; |
||
1212 | default: |
||
1213 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); |
||
1214 | return -EINVAL; |
||
1215 | } |
||
1216 | return 0; |
||
1217 | } |
||
1218 | |||
1219 | int r300_cs_parse(struct radeon_cs_parser *p) |
||
1220 | { |
||
1221 | struct radeon_cs_packet pkt; |
||
1179 | serge | 1222 | struct r100_cs_track *track; |
1120 | serge | 1223 | int r; |
1224 | |||
1179 | serge | 1225 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
1226 | r100_cs_track_clear(p->rdev, track); |
||
1227 | p->track = track; |
||
1120 | serge | 1228 | do { |
1229 | r = r100_cs_packet_parse(p, &pkt, p->idx); |
||
1230 | if (r) { |
||
1231 | return r; |
||
1232 | } |
||
1233 | p->idx += pkt.count + 2; |
||
1234 | switch (pkt.type) { |
||
1235 | case PACKET_TYPE0: |
||
1236 | r = r100_cs_parse_packet0(p, &pkt, |
||
1237 | p->rdev->config.r300.reg_safe_bm, |
||
1238 | p->rdev->config.r300.reg_safe_bm_size, |
||
1239 | &r300_packet0_check); |
||
1240 | break; |
||
1241 | case PACKET_TYPE2: |
||
1242 | break; |
||
1243 | case PACKET_TYPE3: |
||
1244 | r = r300_packet3_check(p, &pkt); |
||
1245 | break; |
||
1246 | default: |
||
1247 | DRM_ERROR("Unknown packet type %d !\n", pkt.type); |
||
1248 | return -EINVAL; |
||
1249 | } |
||
1250 | if (r) { |
||
1251 | return r; |
||
1252 | } |
||
1253 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
||
1254 | return 0; |
||
1255 | } |
||
1128 | serge | 1256 | #endif |
1257 | |||
1179 | serge | 1258 | |
1259 | void r300_set_reg_safe(struct radeon_device *rdev) |
||
1120 | serge | 1260 | { |
1261 | rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; |
||
1262 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); |
||
1179 | serge | 1263 | } |
1264 | |||
1265 | int r300_init(struct radeon_device *rdev) |
||
1266 | { |
||
1267 | r300_set_reg_safe(rdev); |
||
1120 | serge | 1268 | return 0; |
1269 | } |
||
1270 | |||
1179 | serge | 1271 | void r300_mc_program(struct radeon_device *rdev) |
1272 | { |
||
1273 | struct r100_mc_save save; |
||
1274 | int r; |
||
1120 | serge | 1275 | |
1179 | serge | 1276 | r = r100_debugfs_mc_info_init(rdev); |
1277 | if (r) { |
||
1278 | dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); |
||
1279 | } |
||
1280 | |||
1281 | /* Stops all mc clients */ |
||
1282 | r100_mc_stop(rdev, &save); |
||
1283 | if (rdev->flags & RADEON_IS_AGP) { |
||
1284 | WREG32(R_00014C_MC_AGP_LOCATION, |
||
1285 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
||
1286 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
||
1287 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
||
1288 | WREG32(R_00015C_AGP_BASE_2, |
||
1289 | upper_32_bits(rdev->mc.agp_base) & 0xff); |
||
1290 | } else { |
||
1291 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); |
||
1292 | WREG32(R_000170_AGP_BASE, 0); |
||
1293 | WREG32(R_00015C_AGP_BASE_2, 0); |
||
1294 | } |
||
1295 | /* Wait for mc idle */ |
||
1296 | if (r300_mc_wait_for_idle(rdev)) |
||
1297 | DRM_INFO("Failed to wait MC idle before programming MC.\n"); |
||
1298 | /* Program MC, should be a 32bits limited address space */ |
||
1299 | WREG32(R_000148_MC_FB_LOCATION, |
||
1300 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
||
1301 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
||
1302 | r100_mc_resume(rdev, &save); |
||
1303 | }>>><>><>><>><>>><>><>>><>><>><>><>><>><>><>><>><>><>>><>><>><>><>>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>><>><>><>><>><>><>>> |