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Rev | Author | Line No. | Line |
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1120 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | //#include |
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1125 | serge | 29 | #include "drmP.h" |
30 | #include "drm.h" |
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1120 | serge | 31 | #include "radeon_reg.h" |
32 | #include "radeon.h" |
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33 | |||
34 | /* r300,r350,rv350,rv370,rv380 depends on : */ |
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35 | void r100_hdp_reset(struct radeon_device *rdev); |
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36 | int r100_cp_reset(struct radeon_device *rdev); |
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37 | int r100_rb2d_reset(struct radeon_device *rdev); |
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38 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
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39 | int r100_pci_gart_enable(struct radeon_device *rdev); |
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40 | void r100_pci_gart_disable(struct radeon_device *rdev); |
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41 | void r100_mc_setup(struct radeon_device *rdev); |
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42 | void r100_mc_disable_clients(struct radeon_device *rdev); |
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43 | int r100_gui_wait_for_idle(struct radeon_device *rdev); |
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44 | int r100_cs_packet_parse(struct radeon_cs_parser *p, |
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45 | struct radeon_cs_packet *pkt, |
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46 | unsigned idx); |
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47 | int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, |
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48 | struct radeon_cs_reloc **cs_reloc); |
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49 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
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50 | struct radeon_cs_packet *pkt, |
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51 | const unsigned *auth, unsigned n, |
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52 | radeon_packet0_check_t check); |
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53 | void r100_cs_dump_packet(struct radeon_cs_parser *p, |
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54 | struct radeon_cs_packet *pkt); |
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55 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
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56 | struct radeon_cs_packet *pkt, |
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57 | struct radeon_object *robj); |
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58 | |||
59 | /* This files gather functions specifics to: |
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60 | * r300,r350,rv350,rv370,rv380 |
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61 | * |
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62 | * Some of these functions might be used by newer ASICs. |
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63 | */ |
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64 | void r300_gpu_init(struct radeon_device *rdev); |
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65 | int r300_mc_wait_for_idle(struct radeon_device *rdev); |
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66 | int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
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67 | |||
68 | |||
69 | /* |
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70 | * rv370,rv380 PCIE GART |
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71 | */ |
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72 | void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) |
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73 | { |
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74 | uint32_t tmp; |
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75 | int i; |
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76 | |||
77 | /* Workaround HW bug do flush 2 times */ |
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78 | for (i = 0; i < 2; i++) { |
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79 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
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80 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); |
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81 | (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
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82 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
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83 | mb(); |
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84 | } |
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85 | } |
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86 | |||
87 | int rv370_pcie_gart_enable(struct radeon_device *rdev) |
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88 | { |
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89 | uint32_t table_addr; |
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90 | uint32_t tmp; |
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91 | int r; |
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92 | |||
93 | /* Initialize common gart structure */ |
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94 | r = radeon_gart_init(rdev); |
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95 | if (r) { |
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96 | return r; |
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97 | } |
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1129 | serge | 98 | r = rv370_debugfs_pcie_gart_info_init(rdev); |
99 | if (r) { |
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100 | DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); |
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101 | } |
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1120 | serge | 102 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
103 | r = radeon_gart_table_vram_alloc(rdev); |
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104 | if (r) { |
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105 | return r; |
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106 | } |
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107 | /* discard memory request outside of configured range */ |
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108 | tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
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109 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
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110 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location); |
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111 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 4096; |
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112 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); |
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113 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); |
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114 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); |
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115 | table_addr = rdev->gart.table_addr; |
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116 | WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); |
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117 | /* FIXME: setup default page */ |
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118 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location); |
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119 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); |
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120 | /* Clear error */ |
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121 | WREG32_PCIE(0x18, 0); |
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122 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
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123 | tmp |= RADEON_PCIE_TX_GART_EN; |
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124 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
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125 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
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126 | rv370_pcie_gart_tlb_flush(rdev); |
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127 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n", |
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128 | rdev->mc.gtt_size >> 20, table_addr); |
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129 | rdev->gart.ready = true; |
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130 | return 0; |
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131 | } |
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132 | |||
133 | void rv370_pcie_gart_disable(struct radeon_device *rdev) |
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134 | { |
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135 | uint32_t tmp; |
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136 | |||
137 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
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138 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
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139 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); |
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140 | if (rdev->gart.table.vram.robj) { |
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141 | // radeon_object_kunmap(rdev->gart.table.vram.robj); |
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142 | // radeon_object_unpin(rdev->gart.table.vram.robj); |
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143 | } |
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144 | } |
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145 | |||
146 | int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
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147 | { |
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148 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
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149 | |||
150 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
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151 | return -EINVAL; |
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152 | } |
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1126 | serge | 153 | addr = (((u32)addr) >> 8) | ((upper_32_bits(addr) & 0xff) << 4) | 0xC; |
1120 | serge | 154 | writel(cpu_to_le32(addr), ((void __iomem *)ptr) + (i * 4)); |
155 | return 0; |
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156 | } |
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157 | |||
158 | int r300_gart_enable(struct radeon_device *rdev) |
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159 | { |
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160 | #if __OS_HAS_AGP |
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161 | if (rdev->flags & RADEON_IS_AGP) { |
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162 | if (rdev->family > CHIP_RV350) { |
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163 | rv370_pcie_gart_disable(rdev); |
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164 | } else { |
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165 | r100_pci_gart_disable(rdev); |
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166 | } |
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167 | return 0; |
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168 | } |
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169 | #endif |
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170 | if (rdev->flags & RADEON_IS_PCIE) { |
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171 | rdev->asic->gart_disable = &rv370_pcie_gart_disable; |
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172 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
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173 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
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174 | return rv370_pcie_gart_enable(rdev); |
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175 | } |
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1128 | serge | 176 | return r100_pci_gart_enable(rdev); |
1120 | serge | 177 | } |
178 | |||
1128 | serge | 179 | |
1120 | serge | 180 | /* |
181 | * MC |
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182 | */ |
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183 | int r300_mc_init(struct radeon_device *rdev) |
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184 | { |
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185 | int r; |
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186 | |||
1129 | serge | 187 | if (r100_debugfs_rbbm_init(rdev)) { |
188 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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189 | } |
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1120 | serge | 190 | |
191 | r300_gpu_init(rdev); |
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192 | r100_pci_gart_disable(rdev); |
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193 | if (rdev->flags & RADEON_IS_PCIE) { |
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194 | rv370_pcie_gart_disable(rdev); |
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195 | } |
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196 | |||
197 | /* Setup GPU memory space */ |
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198 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
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199 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
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200 | if (rdev->flags & RADEON_IS_AGP) { |
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201 | r = radeon_agp_init(rdev); |
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202 | if (r) { |
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203 | printk(KERN_WARNING "[drm] Disabling AGP\n"); |
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204 | rdev->flags &= ~RADEON_IS_AGP; |
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205 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
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206 | } else { |
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207 | rdev->mc.gtt_location = rdev->mc.agp_base; |
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208 | } |
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209 | } |
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210 | r = radeon_mc_setup(rdev); |
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211 | if (r) { |
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212 | return r; |
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213 | } |
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214 | |||
215 | /* Program GPU memory space */ |
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216 | r100_mc_disable_clients(rdev); |
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217 | if (r300_mc_wait_for_idle(rdev)) { |
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218 | printk(KERN_WARNING "Failed to wait MC idle while " |
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219 | "programming pipes. Bad things might happen.\n"); |
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220 | } |
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221 | r100_mc_setup(rdev); |
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222 | return 0; |
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223 | } |
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224 | |||
225 | void r300_mc_fini(struct radeon_device *rdev) |
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226 | { |
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227 | if (rdev->flags & RADEON_IS_PCIE) { |
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228 | rv370_pcie_gart_disable(rdev); |
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229 | radeon_gart_table_vram_free(rdev); |
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230 | } else { |
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231 | r100_pci_gart_disable(rdev); |
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232 | radeon_gart_table_ram_free(rdev); |
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233 | } |
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234 | radeon_gart_fini(rdev); |
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235 | } |
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236 | |||
237 | |||
238 | /* |
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239 | * Fence emission |
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240 | */ |
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241 | void r300_fence_ring_emit(struct radeon_device *rdev, |
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242 | struct radeon_fence *fence) |
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243 | { |
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244 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
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245 | * for enough space (today caller are ib schedule and buffer move) */ |
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246 | /* Write SC register so SC & US assert idle */ |
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247 | radeon_ring_write(rdev, PACKET0(0x43E0, 0)); |
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248 | radeon_ring_write(rdev, 0); |
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249 | radeon_ring_write(rdev, PACKET0(0x43E4, 0)); |
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250 | radeon_ring_write(rdev, 0); |
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251 | /* Flush 3D cache */ |
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252 | radeon_ring_write(rdev, PACKET0(0x4E4C, 0)); |
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253 | radeon_ring_write(rdev, (2 << 0)); |
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254 | radeon_ring_write(rdev, PACKET0(0x4F18, 0)); |
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255 | radeon_ring_write(rdev, (1 << 0)); |
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256 | /* Wait until IDLE & CLEAN */ |
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257 | radeon_ring_write(rdev, PACKET0(0x1720, 0)); |
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258 | radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9)); |
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259 | /* Emit fence sequence & fire IRQ */ |
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260 | radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); |
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261 | radeon_ring_write(rdev, fence->seq); |
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262 | radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
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263 | radeon_ring_write(rdev, RADEON_SW_INT_FIRE); |
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264 | } |
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265 | |||
266 | |||
1128 | serge | 267 | #if 0 |
268 | |||
1120 | serge | 269 | /* |
270 | * Global GPU functions |
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271 | */ |
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272 | int r300_copy_dma(struct radeon_device *rdev, |
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273 | uint64_t src_offset, |
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274 | uint64_t dst_offset, |
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275 | unsigned num_pages, |
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276 | struct radeon_fence *fence) |
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277 | { |
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278 | uint32_t size; |
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279 | uint32_t cur_size; |
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280 | int i, num_loops; |
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281 | int r = 0; |
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282 | |||
283 | /* radeon pitch is /64 */ |
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284 | size = num_pages << PAGE_SHIFT; |
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285 | num_loops = DIV_ROUND_UP(size, 0x1FFFFF); |
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286 | r = radeon_ring_lock(rdev, num_loops * 4 + 64); |
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287 | if (r) { |
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288 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
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289 | return r; |
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290 | } |
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291 | /* Must wait for 2D idle & clean before DMA or hangs might happen */ |
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292 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 )); |
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293 | radeon_ring_write(rdev, (1 << 16)); |
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294 | for (i = 0; i < num_loops; i++) { |
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295 | cur_size = size; |
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296 | if (cur_size > 0x1FFFFF) { |
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297 | cur_size = 0x1FFFFF; |
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298 | } |
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299 | size -= cur_size; |
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300 | radeon_ring_write(rdev, PACKET0(0x720, 2)); |
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301 | radeon_ring_write(rdev, src_offset); |
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302 | radeon_ring_write(rdev, dst_offset); |
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303 | radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30)); |
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304 | src_offset += cur_size; |
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305 | dst_offset += cur_size; |
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306 | } |
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307 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
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308 | radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE); |
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309 | if (fence) { |
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310 | r = radeon_fence_emit(rdev, fence); |
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311 | } |
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312 | radeon_ring_unlock_commit(rdev); |
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313 | return r; |
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314 | } |
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315 | |||
1128 | serge | 316 | #endif |
317 | |||
1120 | serge | 318 | void r300_ring_start(struct radeon_device *rdev) |
319 | { |
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320 | unsigned gb_tile_config; |
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321 | int r; |
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322 | |||
323 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
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324 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
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325 | switch(rdev->num_gb_pipes) { |
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326 | case 2: |
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327 | gb_tile_config |= R300_PIPE_COUNT_R300; |
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328 | break; |
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329 | case 3: |
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330 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
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331 | break; |
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332 | case 4: |
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333 | gb_tile_config |= R300_PIPE_COUNT_R420; |
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334 | break; |
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335 | case 1: |
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336 | default: |
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337 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
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338 | break; |
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339 | } |
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340 | |||
341 | r = radeon_ring_lock(rdev, 64); |
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342 | if (r) { |
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343 | return; |
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344 | } |
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345 | radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); |
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346 | radeon_ring_write(rdev, |
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347 | RADEON_ISYNC_ANY2D_IDLE3D | |
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348 | RADEON_ISYNC_ANY3D_IDLE2D | |
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349 | RADEON_ISYNC_WAIT_IDLEGUI | |
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350 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
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351 | radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); |
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352 | radeon_ring_write(rdev, gb_tile_config); |
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353 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
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354 | radeon_ring_write(rdev, |
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355 | RADEON_WAIT_2D_IDLECLEAN | |
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356 | RADEON_WAIT_3D_IDLECLEAN); |
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357 | radeon_ring_write(rdev, PACKET0(0x170C, 0)); |
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358 | radeon_ring_write(rdev, 1 << 31); |
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359 | radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); |
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360 | radeon_ring_write(rdev, 0); |
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361 | radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); |
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362 | radeon_ring_write(rdev, 0); |
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363 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
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364 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
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365 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
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366 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
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367 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
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368 | radeon_ring_write(rdev, |
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369 | RADEON_WAIT_2D_IDLECLEAN | |
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370 | RADEON_WAIT_3D_IDLECLEAN); |
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371 | radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); |
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372 | radeon_ring_write(rdev, 0); |
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373 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
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374 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
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375 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
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376 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
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377 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); |
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378 | radeon_ring_write(rdev, |
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379 | ((6 << R300_MS_X0_SHIFT) | |
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380 | (6 << R300_MS_Y0_SHIFT) | |
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381 | (6 << R300_MS_X1_SHIFT) | |
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382 | (6 << R300_MS_Y1_SHIFT) | |
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383 | (6 << R300_MS_X2_SHIFT) | |
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384 | (6 << R300_MS_Y2_SHIFT) | |
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385 | (6 << R300_MSBD0_Y_SHIFT) | |
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386 | (6 << R300_MSBD0_X_SHIFT))); |
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387 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); |
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388 | radeon_ring_write(rdev, |
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389 | ((6 << R300_MS_X3_SHIFT) | |
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390 | (6 << R300_MS_Y3_SHIFT) | |
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391 | (6 << R300_MS_X4_SHIFT) | |
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392 | (6 << R300_MS_Y4_SHIFT) | |
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393 | (6 << R300_MS_X5_SHIFT) | |
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394 | (6 << R300_MS_Y5_SHIFT) | |
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395 | (6 << R300_MSBD1_SHIFT))); |
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396 | radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); |
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397 | radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
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398 | radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); |
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399 | radeon_ring_write(rdev, |
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400 | R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
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401 | radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); |
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402 | radeon_ring_write(rdev, |
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403 | R300_GEOMETRY_ROUND_NEAREST | |
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404 | R300_COLOR_ROUND_NEAREST); |
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405 | radeon_ring_unlock_commit(rdev); |
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406 | } |
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407 | |||
408 | void r300_errata(struct radeon_device *rdev) |
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409 | { |
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410 | rdev->pll_errata = 0; |
||
411 | |||
412 | if (rdev->family == CHIP_R300 && |
||
413 | (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { |
||
414 | rdev->pll_errata |= CHIP_ERRATA_R300_CG; |
||
415 | } |
||
416 | } |
||
417 | |||
418 | int r300_mc_wait_for_idle(struct radeon_device *rdev) |
||
419 | { |
||
420 | unsigned i; |
||
421 | uint32_t tmp; |
||
422 | |||
423 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
424 | /* read MC_STATUS */ |
||
425 | tmp = RREG32(0x0150); |
||
426 | if (tmp & (1 << 4)) { |
||
427 | return 0; |
||
428 | } |
||
429 | DRM_UDELAY(1); |
||
430 | } |
||
431 | return -1; |
||
432 | } |
||
433 | |||
434 | void r300_gpu_init(struct radeon_device *rdev) |
||
435 | { |
||
436 | uint32_t gb_tile_config, tmp; |
||
437 | |||
438 | r100_hdp_reset(rdev); |
||
439 | /* FIXME: rv380 one pipes ? */ |
||
440 | if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) { |
||
441 | /* r300,r350 */ |
||
442 | rdev->num_gb_pipes = 2; |
||
443 | } else { |
||
444 | /* rv350,rv370,rv380 */ |
||
445 | rdev->num_gb_pipes = 1; |
||
446 | } |
||
447 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
||
448 | switch (rdev->num_gb_pipes) { |
||
449 | case 2: |
||
450 | gb_tile_config |= R300_PIPE_COUNT_R300; |
||
451 | break; |
||
452 | case 3: |
||
453 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
||
454 | break; |
||
455 | case 4: |
||
456 | gb_tile_config |= R300_PIPE_COUNT_R420; |
||
457 | break; |
||
458 | default: |
||
459 | case 1: |
||
460 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
||
461 | break; |
||
462 | } |
||
463 | WREG32(R300_GB_TILE_CONFIG, gb_tile_config); |
||
464 | |||
465 | if (r100_gui_wait_for_idle(rdev)) { |
||
466 | printk(KERN_WARNING "Failed to wait GUI idle while " |
||
467 | "programming pipes. Bad things might happen.\n"); |
||
468 | } |
||
469 | |||
470 | tmp = RREG32(0x170C); |
||
471 | WREG32(0x170C, tmp | (1 << 31)); |
||
472 | |||
473 | WREG32(R300_RB2D_DSTCACHE_MODE, |
||
474 | R300_DC_AUTOFLUSH_ENABLE | |
||
475 | R300_DC_DC_DISABLE_IGNORE_PE); |
||
476 | |||
477 | if (r100_gui_wait_for_idle(rdev)) { |
||
478 | printk(KERN_WARNING "Failed to wait GUI idle while " |
||
479 | "programming pipes. Bad things might happen.\n"); |
||
480 | } |
||
481 | if (r300_mc_wait_for_idle(rdev)) { |
||
482 | printk(KERN_WARNING "Failed to wait MC idle while " |
||
483 | "programming pipes. Bad things might happen.\n"); |
||
484 | } |
||
485 | DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes); |
||
486 | } |
||
487 | |||
488 | int r300_ga_reset(struct radeon_device *rdev) |
||
489 | { |
||
490 | uint32_t tmp; |
||
491 | bool reinit_cp; |
||
492 | int i; |
||
493 | |||
494 | reinit_cp = rdev->cp.ready; |
||
495 | rdev->cp.ready = false; |
||
496 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
497 | WREG32(RADEON_CP_CSQ_MODE, 0); |
||
498 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
||
499 | WREG32(RADEON_RBBM_SOFT_RESET, 0x32005); |
||
500 | (void)RREG32(RADEON_RBBM_SOFT_RESET); |
||
501 | udelay(200); |
||
502 | WREG32(RADEON_RBBM_SOFT_RESET, 0); |
||
503 | /* Wait to prevent race in RBBM_STATUS */ |
||
504 | mdelay(1); |
||
505 | tmp = RREG32(RADEON_RBBM_STATUS); |
||
506 | if (tmp & ((1 << 20) | (1 << 26))) { |
||
507 | DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp); |
||
508 | /* GA still busy soft reset it */ |
||
509 | WREG32(0x429C, 0x200); |
||
510 | WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
||
511 | WREG32(0x43E0, 0); |
||
512 | WREG32(0x43E4, 0); |
||
513 | WREG32(0x24AC, 0); |
||
514 | } |
||
515 | /* Wait to prevent race in RBBM_STATUS */ |
||
516 | mdelay(1); |
||
517 | tmp = RREG32(RADEON_RBBM_STATUS); |
||
518 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
||
519 | break; |
||
520 | } |
||
521 | } |
||
522 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
523 | tmp = RREG32(RADEON_RBBM_STATUS); |
||
524 | if (!(tmp & ((1 << 20) | (1 << 26)))) { |
||
525 | DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", |
||
526 | tmp); |
||
527 | if (reinit_cp) { |
||
528 | return r100_cp_init(rdev, rdev->cp.ring_size); |
||
529 | } |
||
530 | return 0; |
||
531 | } |
||
532 | DRM_UDELAY(1); |
||
533 | } |
||
534 | tmp = RREG32(RADEON_RBBM_STATUS); |
||
535 | DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); |
||
536 | return -1; |
||
537 | } |
||
538 | |||
539 | int r300_gpu_reset(struct radeon_device *rdev) |
||
540 | { |
||
541 | uint32_t status; |
||
542 | |||
543 | /* reset order likely matter */ |
||
544 | status = RREG32(RADEON_RBBM_STATUS); |
||
545 | /* reset HDP */ |
||
546 | r100_hdp_reset(rdev); |
||
547 | /* reset rb2d */ |
||
548 | if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { |
||
549 | r100_rb2d_reset(rdev); |
||
550 | } |
||
551 | /* reset GA */ |
||
552 | if (status & ((1 << 20) | (1 << 26))) { |
||
553 | r300_ga_reset(rdev); |
||
554 | } |
||
555 | /* reset CP */ |
||
556 | status = RREG32(RADEON_RBBM_STATUS); |
||
557 | if (status & (1 << 16)) { |
||
558 | r100_cp_reset(rdev); |
||
559 | } |
||
560 | /* Check if GPU is idle */ |
||
561 | status = RREG32(RADEON_RBBM_STATUS); |
||
562 | if (status & (1 << 31)) { |
||
563 | DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); |
||
564 | return -1; |
||
565 | } |
||
566 | DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
||
567 | return 0; |
||
568 | } |
||
569 | |||
570 | |||
571 | /* |
||
572 | * r300,r350,rv350,rv380 VRAM info |
||
573 | */ |
||
574 | void r300_vram_info(struct radeon_device *rdev) |
||
575 | { |
||
576 | uint32_t tmp; |
||
577 | |||
578 | /* DDR for all card after R300 & IGP */ |
||
579 | rdev->mc.vram_is_ddr = true; |
||
580 | tmp = RREG32(RADEON_MEM_CNTL); |
||
581 | if (tmp & R300_MEM_NUM_CHANNELS_MASK) { |
||
582 | rdev->mc.vram_width = 128; |
||
583 | } else { |
||
584 | rdev->mc.vram_width = 64; |
||
585 | } |
||
586 | rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
||
587 | |||
588 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
||
589 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
||
590 | } |
||
591 | |||
592 | |||
593 | /* |
||
594 | * Indirect registers accessor |
||
595 | */ |
||
596 | uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
||
597 | { |
||
598 | uint32_t r; |
||
599 | |||
600 | WREG8(RADEON_PCIE_INDEX, ((reg) & 0xff)); |
||
601 | (void)RREG32(RADEON_PCIE_INDEX); |
||
602 | r = RREG32(RADEON_PCIE_DATA); |
||
603 | return r; |
||
604 | } |
||
605 | |||
606 | void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
||
607 | { |
||
608 | WREG8(RADEON_PCIE_INDEX, ((reg) & 0xff)); |
||
609 | (void)RREG32(RADEON_PCIE_INDEX); |
||
610 | WREG32(RADEON_PCIE_DATA, (v)); |
||
611 | (void)RREG32(RADEON_PCIE_DATA); |
||
612 | } |
||
613 | |||
614 | /* |
||
615 | * PCIE Lanes |
||
616 | */ |
||
617 | |||
618 | void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) |
||
619 | { |
||
620 | uint32_t link_width_cntl, mask; |
||
621 | |||
622 | if (rdev->flags & RADEON_IS_IGP) |
||
623 | return; |
||
624 | |||
625 | if (!(rdev->flags & RADEON_IS_PCIE)) |
||
626 | return; |
||
627 | |||
628 | /* FIXME wait for idle */ |
||
629 | |||
630 | switch (lanes) { |
||
631 | case 0: |
||
632 | mask = RADEON_PCIE_LC_LINK_WIDTH_X0; |
||
633 | break; |
||
634 | case 1: |
||
635 | mask = RADEON_PCIE_LC_LINK_WIDTH_X1; |
||
636 | break; |
||
637 | case 2: |
||
638 | mask = RADEON_PCIE_LC_LINK_WIDTH_X2; |
||
639 | break; |
||
640 | case 4: |
||
641 | mask = RADEON_PCIE_LC_LINK_WIDTH_X4; |
||
642 | break; |
||
643 | case 8: |
||
644 | mask = RADEON_PCIE_LC_LINK_WIDTH_X8; |
||
645 | break; |
||
646 | case 12: |
||
647 | mask = RADEON_PCIE_LC_LINK_WIDTH_X12; |
||
648 | break; |
||
649 | case 16: |
||
650 | default: |
||
651 | mask = RADEON_PCIE_LC_LINK_WIDTH_X16; |
||
652 | break; |
||
653 | } |
||
654 | |||
655 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
||
656 | |||
657 | if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == |
||
658 | (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) |
||
659 | return; |
||
660 | |||
661 | link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | |
||
662 | RADEON_PCIE_LC_RECONFIG_NOW | |
||
663 | RADEON_PCIE_LC_RECONFIG_LATER | |
||
664 | RADEON_PCIE_LC_SHORT_RECONFIG_EN); |
||
665 | link_width_cntl |= mask; |
||
666 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
||
667 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | |
||
668 | RADEON_PCIE_LC_RECONFIG_NOW)); |
||
669 | |||
670 | /* wait for lane set to complete */ |
||
671 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
||
672 | while (link_width_cntl == 0xffffffff) |
||
673 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
||
674 | |||
675 | } |
||
676 | |||
677 | |||
678 | /* |
||
679 | * Debugfs info |
||
680 | */ |
||
681 | #if defined(CONFIG_DEBUG_FS) |
||
682 | static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) |
||
683 | { |
||
684 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
685 | struct drm_device *dev = node->minor->dev; |
||
686 | struct radeon_device *rdev = dev->dev_private; |
||
687 | uint32_t tmp; |
||
688 | |||
689 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
||
690 | seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); |
||
691 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); |
||
692 | seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); |
||
693 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); |
||
694 | seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); |
||
695 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); |
||
696 | seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); |
||
697 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); |
||
698 | seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); |
||
699 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); |
||
700 | seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); |
||
701 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); |
||
702 | seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); |
||
703 | return 0; |
||
704 | } |
||
705 | |||
706 | static struct drm_info_list rv370_pcie_gart_info_list[] = { |
||
707 | {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, |
||
708 | }; |
||
709 | #endif |
||
710 | |||
711 | int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
||
712 | { |
||
713 | #if defined(CONFIG_DEBUG_FS) |
||
714 | return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); |
||
715 | #else |
||
716 | return 0; |
||
717 | #endif |
||
718 | } |
||
719 | |||
720 | |||
1128 | serge | 721 | #if 0 |
1120 | serge | 722 | /* |
723 | * CS functions |
||
724 | */ |
||
725 | struct r300_cs_track_cb { |
||
726 | struct radeon_object *robj; |
||
727 | unsigned pitch; |
||
728 | unsigned cpp; |
||
729 | unsigned offset; |
||
730 | }; |
||
731 | |||
732 | struct r300_cs_track_array { |
||
733 | struct radeon_object *robj; |
||
734 | unsigned esize; |
||
735 | }; |
||
736 | |||
737 | struct r300_cs_track_texture { |
||
738 | struct radeon_object *robj; |
||
739 | unsigned pitch; |
||
740 | unsigned width; |
||
741 | unsigned height; |
||
742 | unsigned num_levels; |
||
743 | unsigned cpp; |
||
744 | unsigned tex_coord_type; |
||
745 | unsigned txdepth; |
||
746 | unsigned width_11; |
||
747 | unsigned height_11; |
||
748 | bool use_pitch; |
||
749 | bool enabled; |
||
750 | bool roundup_w; |
||
751 | bool roundup_h; |
||
752 | }; |
||
753 | |||
754 | struct r300_cs_track { |
||
755 | unsigned num_cb; |
||
756 | unsigned maxy; |
||
757 | unsigned vtx_size; |
||
758 | unsigned vap_vf_cntl; |
||
759 | unsigned immd_dwords; |
||
760 | unsigned num_arrays; |
||
761 | unsigned max_indx; |
||
762 | struct r300_cs_track_array arrays[11]; |
||
763 | struct r300_cs_track_cb cb[4]; |
||
764 | struct r300_cs_track_cb zb; |
||
765 | struct r300_cs_track_texture textures[16]; |
||
766 | bool z_enabled; |
||
767 | }; |
||
768 | |||
769 | static inline void r300_cs_track_texture_print(struct r300_cs_track_texture *t) |
||
770 | { |
||
771 | DRM_ERROR("pitch %d\n", t->pitch); |
||
772 | DRM_ERROR("width %d\n", t->width); |
||
773 | DRM_ERROR("height %d\n", t->height); |
||
774 | DRM_ERROR("num levels %d\n", t->num_levels); |
||
775 | DRM_ERROR("depth %d\n", t->txdepth); |
||
776 | DRM_ERROR("bpp %d\n", t->cpp); |
||
777 | DRM_ERROR("coordinate type %d\n", t->tex_coord_type); |
||
778 | DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); |
||
779 | DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); |
||
780 | } |
||
781 | |||
782 | static inline int r300_cs_track_texture_check(struct radeon_device *rdev, |
||
783 | struct r300_cs_track *track) |
||
784 | { |
||
785 | struct radeon_object *robj; |
||
786 | unsigned long size; |
||
787 | unsigned u, i, w, h; |
||
788 | |||
789 | for (u = 0; u < 16; u++) { |
||
790 | if (!track->textures[u].enabled) |
||
791 | continue; |
||
792 | robj = track->textures[u].robj; |
||
793 | if (robj == NULL) { |
||
794 | DRM_ERROR("No texture bound to unit %u\n", u); |
||
795 | return -EINVAL; |
||
796 | } |
||
797 | size = 0; |
||
798 | for (i = 0; i <= track->textures[u].num_levels; i++) { |
||
799 | if (track->textures[u].use_pitch) { |
||
800 | w = track->textures[u].pitch / (1 << i); |
||
801 | } else { |
||
802 | w = track->textures[u].width / (1 << i); |
||
803 | if (rdev->family >= CHIP_RV515) |
||
804 | w |= track->textures[u].width_11; |
||
805 | if (track->textures[u].roundup_w) |
||
806 | w = roundup_pow_of_two(w); |
||
807 | } |
||
808 | h = track->textures[u].height / (1 << i); |
||
809 | if (rdev->family >= CHIP_RV515) |
||
810 | h |= track->textures[u].height_11; |
||
811 | if (track->textures[u].roundup_h) |
||
812 | h = roundup_pow_of_two(h); |
||
813 | size += w * h; |
||
814 | } |
||
815 | size *= track->textures[u].cpp; |
||
816 | switch (track->textures[u].tex_coord_type) { |
||
817 | case 0: |
||
818 | break; |
||
819 | case 1: |
||
820 | size *= (1 << track->textures[u].txdepth); |
||
821 | break; |
||
822 | case 2: |
||
823 | size *= 6; |
||
824 | break; |
||
825 | default: |
||
826 | DRM_ERROR("Invalid texture coordinate type %u for unit " |
||
827 | "%u\n", track->textures[u].tex_coord_type, u); |
||
828 | return -EINVAL; |
||
829 | } |
||
830 | if (size > radeon_object_size(robj)) { |
||
831 | DRM_ERROR("Texture of unit %u needs %lu bytes but is " |
||
832 | "%lu\n", u, size, radeon_object_size(robj)); |
||
833 | r300_cs_track_texture_print(&track->textures[u]); |
||
834 | return -EINVAL; |
||
835 | } |
||
836 | } |
||
837 | return 0; |
||
838 | } |
||
839 | |||
840 | int r300_cs_track_check(struct radeon_device *rdev, struct r300_cs_track *track) |
||
841 | { |
||
842 | unsigned i; |
||
843 | unsigned long size; |
||
844 | unsigned prim_walk; |
||
845 | unsigned nverts; |
||
846 | |||
847 | for (i = 0; i < track->num_cb; i++) { |
||
848 | if (track->cb[i].robj == NULL) { |
||
849 | DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); |
||
850 | return -EINVAL; |
||
851 | } |
||
852 | size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; |
||
853 | size += track->cb[i].offset; |
||
854 | if (size > radeon_object_size(track->cb[i].robj)) { |
||
855 | DRM_ERROR("[drm] Buffer too small for color buffer %d " |
||
856 | "(need %lu have %lu) !\n", i, size, |
||
857 | radeon_object_size(track->cb[i].robj)); |
||
858 | DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", |
||
859 | i, track->cb[i].pitch, track->cb[i].cpp, |
||
860 | track->cb[i].offset, track->maxy); |
||
861 | return -EINVAL; |
||
862 | } |
||
863 | } |
||
864 | if (track->z_enabled) { |
||
865 | if (track->zb.robj == NULL) { |
||
866 | DRM_ERROR("[drm] No buffer for z buffer !\n"); |
||
867 | return -EINVAL; |
||
868 | } |
||
869 | size = track->zb.pitch * track->zb.cpp * track->maxy; |
||
870 | size += track->zb.offset; |
||
871 | if (size > radeon_object_size(track->zb.robj)) { |
||
872 | DRM_ERROR("[drm] Buffer too small for z buffer " |
||
873 | "(need %lu have %lu) !\n", size, |
||
874 | radeon_object_size(track->zb.robj)); |
||
875 | return -EINVAL; |
||
876 | } |
||
877 | } |
||
878 | prim_walk = (track->vap_vf_cntl >> 4) & 0x3; |
||
879 | nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; |
||
880 | switch (prim_walk) { |
||
881 | case 1: |
||
882 | for (i = 0; i < track->num_arrays; i++) { |
||
883 | size = track->arrays[i].esize * track->max_indx * 4; |
||
884 | if (track->arrays[i].robj == NULL) { |
||
885 | DRM_ERROR("(PW %u) Vertex array %u no buffer " |
||
886 | "bound\n", prim_walk, i); |
||
887 | return -EINVAL; |
||
888 | } |
||
889 | if (size > radeon_object_size(track->arrays[i].robj)) { |
||
890 | DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " |
||
891 | "have %lu dwords\n", prim_walk, i, |
||
892 | size >> 2, |
||
893 | radeon_object_size(track->arrays[i].robj) >> 2); |
||
894 | DRM_ERROR("Max indices %u\n", track->max_indx); |
||
895 | return -EINVAL; |
||
896 | } |
||
897 | } |
||
898 | break; |
||
899 | case 2: |
||
900 | for (i = 0; i < track->num_arrays; i++) { |
||
901 | size = track->arrays[i].esize * (nverts - 1) * 4; |
||
902 | if (track->arrays[i].robj == NULL) { |
||
903 | DRM_ERROR("(PW %u) Vertex array %u no buffer " |
||
904 | "bound\n", prim_walk, i); |
||
905 | return -EINVAL; |
||
906 | } |
||
907 | if (size > radeon_object_size(track->arrays[i].robj)) { |
||
908 | DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " |
||
909 | "have %lu dwords\n", prim_walk, i, size >> 2, |
||
910 | radeon_object_size(track->arrays[i].robj) >> 2); |
||
911 | return -EINVAL; |
||
912 | } |
||
913 | } |
||
914 | break; |
||
915 | case 3: |
||
916 | size = track->vtx_size * nverts; |
||
917 | if (size != track->immd_dwords) { |
||
918 | DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", |
||
919 | track->immd_dwords, size); |
||
920 | DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", |
||
921 | nverts, track->vtx_size); |
||
922 | return -EINVAL; |
||
923 | } |
||
924 | break; |
||
925 | default: |
||
926 | DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", |
||
927 | prim_walk); |
||
928 | return -EINVAL; |
||
929 | } |
||
930 | return r300_cs_track_texture_check(rdev, track); |
||
931 | } |
||
932 | |||
933 | static inline void r300_cs_track_clear(struct r300_cs_track *track) |
||
934 | { |
||
935 | unsigned i; |
||
936 | |||
937 | track->num_cb = 4; |
||
938 | track->maxy = 4096; |
||
939 | for (i = 0; i < track->num_cb; i++) { |
||
940 | track->cb[i].robj = NULL; |
||
941 | track->cb[i].pitch = 8192; |
||
942 | track->cb[i].cpp = 16; |
||
943 | track->cb[i].offset = 0; |
||
944 | } |
||
945 | track->z_enabled = true; |
||
946 | track->zb.robj = NULL; |
||
947 | track->zb.pitch = 8192; |
||
948 | track->zb.cpp = 4; |
||
949 | track->zb.offset = 0; |
||
950 | track->vtx_size = 0x7F; |
||
951 | track->immd_dwords = 0xFFFFFFFFUL; |
||
952 | track->num_arrays = 11; |
||
953 | track->max_indx = 0x00FFFFFFUL; |
||
954 | for (i = 0; i < track->num_arrays; i++) { |
||
955 | track->arrays[i].robj = NULL; |
||
956 | track->arrays[i].esize = 0x7F; |
||
957 | } |
||
958 | for (i = 0; i < 16; i++) { |
||
959 | track->textures[i].pitch = 16536; |
||
960 | track->textures[i].width = 16536; |
||
961 | track->textures[i].height = 16536; |
||
962 | track->textures[i].width_11 = 1 << 11; |
||
963 | track->textures[i].height_11 = 1 << 11; |
||
964 | track->textures[i].num_levels = 12; |
||
965 | track->textures[i].txdepth = 16; |
||
966 | track->textures[i].cpp = 64; |
||
967 | track->textures[i].tex_coord_type = 1; |
||
968 | track->textures[i].robj = NULL; |
||
969 | /* CS IB emission code makes sure texture unit are disabled */ |
||
970 | track->textures[i].enabled = false; |
||
971 | track->textures[i].roundup_w = true; |
||
972 | track->textures[i].roundup_h = true; |
||
973 | } |
||
974 | } |
||
975 | |||
1128 | serge | 976 | #endif |
977 | |||
1120 | serge | 978 | static const unsigned r300_reg_safe_bm[159] = { |
979 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
980 | 0xFFFFFFBF, 0xFFFFFFFF, 0xFFFFFFBF, 0xFFFFFFFF, |
||
981 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
982 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
983 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
984 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
985 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
986 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
987 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
988 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
989 | 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF, |
||
990 | 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF, |
||
991 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
992 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
993 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F, |
||
994 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
995 | 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000, |
||
996 | 0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF, |
||
997 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
998 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
999 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
1000 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
1001 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
1002 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
1003 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
1004 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
1005 | 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
1006 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
1007 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
1008 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
1009 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
1010 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
||
1011 | 0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFF, |
||
1012 | 0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF, |
||
1013 | 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, |
||
1014 | 0x00000000, 0x0000C100, 0x00000000, 0x00000000, |
||
1015 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
||
1016 | 0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF, |
||
1017 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
||
1018 | 0x0003FC01, 0xFFFFFFF8, 0xFE800B19, |
||
1019 | }; |
||
1020 | |||
1128 | serge | 1021 | #if 0 |
1022 | |||
1120 | serge | 1023 | static int r300_packet0_check(struct radeon_cs_parser *p, |
1024 | struct radeon_cs_packet *pkt, |
||
1025 | unsigned idx, unsigned reg) |
||
1026 | { |
||
1027 | struct radeon_cs_chunk *ib_chunk; |
||
1028 | struct radeon_cs_reloc *reloc; |
||
1029 | struct r300_cs_track *track; |
||
1030 | volatile uint32_t *ib; |
||
1031 | uint32_t tmp; |
||
1032 | unsigned i; |
||
1033 | int r; |
||
1034 | |||
1035 | ib = p->ib->ptr; |
||
1036 | ib_chunk = &p->chunks[p->chunk_ib_idx]; |
||
1037 | track = (struct r300_cs_track*)p->track; |
||
1038 | switch(reg) { |
||
1039 | case RADEON_DST_PITCH_OFFSET: |
||
1040 | case RADEON_SRC_PITCH_OFFSET: |
||
1041 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1042 | if (r) { |
||
1043 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1044 | idx, reg); |
||
1045 | r100_cs_dump_packet(p, pkt); |
||
1046 | return r; |
||
1047 | } |
||
1048 | tmp = ib_chunk->kdata[idx] & 0x003fffff; |
||
1049 | tmp += (((u32)reloc->lobj.gpu_offset) >> 10); |
||
1050 | ib[idx] = (ib_chunk->kdata[idx] & 0xffc00000) | tmp; |
||
1051 | break; |
||
1052 | case R300_RB3D_COLOROFFSET0: |
||
1053 | case R300_RB3D_COLOROFFSET1: |
||
1054 | case R300_RB3D_COLOROFFSET2: |
||
1055 | case R300_RB3D_COLOROFFSET3: |
||
1056 | i = (reg - R300_RB3D_COLOROFFSET0) >> 2; |
||
1057 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1058 | if (r) { |
||
1059 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1060 | idx, reg); |
||
1061 | r100_cs_dump_packet(p, pkt); |
||
1062 | return r; |
||
1063 | } |
||
1064 | track->cb[i].robj = reloc->robj; |
||
1065 | track->cb[i].offset = ib_chunk->kdata[idx]; |
||
1066 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
||
1067 | break; |
||
1068 | case R300_ZB_DEPTHOFFSET: |
||
1069 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1070 | if (r) { |
||
1071 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1072 | idx, reg); |
||
1073 | r100_cs_dump_packet(p, pkt); |
||
1074 | return r; |
||
1075 | } |
||
1076 | track->zb.robj = reloc->robj; |
||
1077 | track->zb.offset = ib_chunk->kdata[idx]; |
||
1078 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
||
1079 | break; |
||
1080 | case R300_TX_OFFSET_0: |
||
1081 | case R300_TX_OFFSET_0+4: |
||
1082 | case R300_TX_OFFSET_0+8: |
||
1083 | case R300_TX_OFFSET_0+12: |
||
1084 | case R300_TX_OFFSET_0+16: |
||
1085 | case R300_TX_OFFSET_0+20: |
||
1086 | case R300_TX_OFFSET_0+24: |
||
1087 | case R300_TX_OFFSET_0+28: |
||
1088 | case R300_TX_OFFSET_0+32: |
||
1089 | case R300_TX_OFFSET_0+36: |
||
1090 | case R300_TX_OFFSET_0+40: |
||
1091 | case R300_TX_OFFSET_0+44: |
||
1092 | case R300_TX_OFFSET_0+48: |
||
1093 | case R300_TX_OFFSET_0+52: |
||
1094 | case R300_TX_OFFSET_0+56: |
||
1095 | case R300_TX_OFFSET_0+60: |
||
1096 | i = (reg - R300_TX_OFFSET_0) >> 2; |
||
1097 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1098 | if (r) { |
||
1099 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1100 | idx, reg); |
||
1101 | r100_cs_dump_packet(p, pkt); |
||
1102 | return r; |
||
1103 | } |
||
1104 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
||
1105 | track->textures[i].robj = reloc->robj; |
||
1106 | break; |
||
1107 | /* Tracked registers */ |
||
1108 | case 0x2084: |
||
1109 | /* VAP_VF_CNTL */ |
||
1110 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
||
1111 | break; |
||
1112 | case 0x20B4: |
||
1113 | /* VAP_VTX_SIZE */ |
||
1114 | track->vtx_size = ib_chunk->kdata[idx] & 0x7F; |
||
1115 | break; |
||
1116 | case 0x2134: |
||
1117 | /* VAP_VF_MAX_VTX_INDX */ |
||
1118 | track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL; |
||
1119 | break; |
||
1120 | case 0x43E4: |
||
1121 | /* SC_SCISSOR1 */ |
||
1122 | track->maxy = ((ib_chunk->kdata[idx] >> 13) & 0x1FFF) + 1; |
||
1123 | if (p->rdev->family < CHIP_RV515) { |
||
1124 | track->maxy -= 1440; |
||
1125 | } |
||
1126 | break; |
||
1127 | case 0x4E00: |
||
1128 | /* RB3D_CCTL */ |
||
1129 | track->num_cb = ((ib_chunk->kdata[idx] >> 5) & 0x3) + 1; |
||
1130 | break; |
||
1131 | case 0x4E38: |
||
1132 | case 0x4E3C: |
||
1133 | case 0x4E40: |
||
1134 | case 0x4E44: |
||
1135 | /* RB3D_COLORPITCH0 */ |
||
1136 | /* RB3D_COLORPITCH1 */ |
||
1137 | /* RB3D_COLORPITCH2 */ |
||
1138 | /* RB3D_COLORPITCH3 */ |
||
1139 | i = (reg - 0x4E38) >> 2; |
||
1140 | track->cb[i].pitch = ib_chunk->kdata[idx] & 0x3FFE; |
||
1141 | switch (((ib_chunk->kdata[idx] >> 21) & 0xF)) { |
||
1142 | case 9: |
||
1143 | case 11: |
||
1144 | case 12: |
||
1145 | track->cb[i].cpp = 1; |
||
1146 | break; |
||
1147 | case 3: |
||
1148 | case 4: |
||
1149 | case 13: |
||
1150 | case 15: |
||
1151 | track->cb[i].cpp = 2; |
||
1152 | break; |
||
1153 | case 6: |
||
1154 | track->cb[i].cpp = 4; |
||
1155 | break; |
||
1156 | case 10: |
||
1157 | track->cb[i].cpp = 8; |
||
1158 | break; |
||
1159 | case 7: |
||
1160 | track->cb[i].cpp = 16; |
||
1161 | break; |
||
1162 | default: |
||
1163 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
||
1164 | ((ib_chunk->kdata[idx] >> 21) & 0xF)); |
||
1165 | return -EINVAL; |
||
1166 | } |
||
1167 | break; |
||
1168 | case 0x4F00: |
||
1169 | /* ZB_CNTL */ |
||
1170 | if (ib_chunk->kdata[idx] & 2) { |
||
1171 | track->z_enabled = true; |
||
1172 | } else { |
||
1173 | track->z_enabled = false; |
||
1174 | } |
||
1175 | break; |
||
1176 | case 0x4F10: |
||
1177 | /* ZB_FORMAT */ |
||
1178 | switch ((ib_chunk->kdata[idx] & 0xF)) { |
||
1179 | case 0: |
||
1180 | case 1: |
||
1181 | track->zb.cpp = 2; |
||
1182 | break; |
||
1183 | case 2: |
||
1184 | track->zb.cpp = 4; |
||
1185 | break; |
||
1186 | default: |
||
1187 | DRM_ERROR("Invalid z buffer format (%d) !\n", |
||
1188 | (ib_chunk->kdata[idx] & 0xF)); |
||
1189 | return -EINVAL; |
||
1190 | } |
||
1191 | break; |
||
1192 | case 0x4F24: |
||
1193 | /* ZB_DEPTHPITCH */ |
||
1194 | track->zb.pitch = ib_chunk->kdata[idx] & 0x3FFC; |
||
1195 | break; |
||
1196 | case 0x4104: |
||
1197 | for (i = 0; i < 16; i++) { |
||
1198 | bool enabled; |
||
1199 | |||
1200 | enabled = !!(ib_chunk->kdata[idx] & (1 << i)); |
||
1201 | track->textures[i].enabled = enabled; |
||
1202 | } |
||
1203 | break; |
||
1204 | case 0x44C0: |
||
1205 | case 0x44C4: |
||
1206 | case 0x44C8: |
||
1207 | case 0x44CC: |
||
1208 | case 0x44D0: |
||
1209 | case 0x44D4: |
||
1210 | case 0x44D8: |
||
1211 | case 0x44DC: |
||
1212 | case 0x44E0: |
||
1213 | case 0x44E4: |
||
1214 | case 0x44E8: |
||
1215 | case 0x44EC: |
||
1216 | case 0x44F0: |
||
1217 | case 0x44F4: |
||
1218 | case 0x44F8: |
||
1219 | case 0x44FC: |
||
1220 | /* TX_FORMAT1_[0-15] */ |
||
1221 | i = (reg - 0x44C0) >> 2; |
||
1222 | tmp = (ib_chunk->kdata[idx] >> 25) & 0x3; |
||
1223 | track->textures[i].tex_coord_type = tmp; |
||
1224 | switch ((ib_chunk->kdata[idx] & 0x1F)) { |
||
1225 | case 0: |
||
1226 | case 2: |
||
1227 | case 5: |
||
1228 | case 18: |
||
1229 | case 20: |
||
1230 | case 21: |
||
1231 | track->textures[i].cpp = 1; |
||
1232 | break; |
||
1233 | case 1: |
||
1234 | case 3: |
||
1235 | case 6: |
||
1236 | case 7: |
||
1237 | case 10: |
||
1238 | case 11: |
||
1239 | case 19: |
||
1240 | case 22: |
||
1241 | case 24: |
||
1242 | track->textures[i].cpp = 2; |
||
1243 | break; |
||
1244 | case 4: |
||
1245 | case 8: |
||
1246 | case 9: |
||
1247 | case 12: |
||
1248 | case 13: |
||
1249 | case 23: |
||
1250 | case 25: |
||
1251 | case 27: |
||
1252 | case 30: |
||
1253 | track->textures[i].cpp = 4; |
||
1254 | break; |
||
1255 | case 14: |
||
1256 | case 26: |
||
1257 | case 28: |
||
1258 | track->textures[i].cpp = 8; |
||
1259 | break; |
||
1260 | case 29: |
||
1261 | track->textures[i].cpp = 16; |
||
1262 | break; |
||
1263 | default: |
||
1264 | DRM_ERROR("Invalid texture format %u\n", |
||
1265 | (ib_chunk->kdata[idx] & 0x1F)); |
||
1266 | return -EINVAL; |
||
1267 | break; |
||
1268 | } |
||
1269 | break; |
||
1270 | case 0x4400: |
||
1271 | case 0x4404: |
||
1272 | case 0x4408: |
||
1273 | case 0x440C: |
||
1274 | case 0x4410: |
||
1275 | case 0x4414: |
||
1276 | case 0x4418: |
||
1277 | case 0x441C: |
||
1278 | case 0x4420: |
||
1279 | case 0x4424: |
||
1280 | case 0x4428: |
||
1281 | case 0x442C: |
||
1282 | case 0x4430: |
||
1283 | case 0x4434: |
||
1284 | case 0x4438: |
||
1285 | case 0x443C: |
||
1286 | /* TX_FILTER0_[0-15] */ |
||
1287 | i = (reg - 0x4400) >> 2; |
||
1288 | tmp = ib_chunk->kdata[idx] & 0x7;; |
||
1289 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
||
1290 | track->textures[i].roundup_w = false; |
||
1291 | } |
||
1292 | tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;; |
||
1293 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
||
1294 | track->textures[i].roundup_h = false; |
||
1295 | } |
||
1296 | break; |
||
1297 | case 0x4500: |
||
1298 | case 0x4504: |
||
1299 | case 0x4508: |
||
1300 | case 0x450C: |
||
1301 | case 0x4510: |
||
1302 | case 0x4514: |
||
1303 | case 0x4518: |
||
1304 | case 0x451C: |
||
1305 | case 0x4520: |
||
1306 | case 0x4524: |
||
1307 | case 0x4528: |
||
1308 | case 0x452C: |
||
1309 | case 0x4530: |
||
1310 | case 0x4534: |
||
1311 | case 0x4538: |
||
1312 | case 0x453C: |
||
1313 | /* TX_FORMAT2_[0-15] */ |
||
1314 | i = (reg - 0x4500) >> 2; |
||
1315 | tmp = ib_chunk->kdata[idx] & 0x3FFF; |
||
1316 | track->textures[i].pitch = tmp + 1; |
||
1317 | if (p->rdev->family >= CHIP_RV515) { |
||
1318 | tmp = ((ib_chunk->kdata[idx] >> 15) & 1) << 11; |
||
1319 | track->textures[i].width_11 = tmp; |
||
1320 | tmp = ((ib_chunk->kdata[idx] >> 16) & 1) << 11; |
||
1321 | track->textures[i].height_11 = tmp; |
||
1322 | } |
||
1323 | break; |
||
1324 | case 0x4480: |
||
1325 | case 0x4484: |
||
1326 | case 0x4488: |
||
1327 | case 0x448C: |
||
1328 | case 0x4490: |
||
1329 | case 0x4494: |
||
1330 | case 0x4498: |
||
1331 | case 0x449C: |
||
1332 | case 0x44A0: |
||
1333 | case 0x44A4: |
||
1334 | case 0x44A8: |
||
1335 | case 0x44AC: |
||
1336 | case 0x44B0: |
||
1337 | case 0x44B4: |
||
1338 | case 0x44B8: |
||
1339 | case 0x44BC: |
||
1340 | /* TX_FORMAT0_[0-15] */ |
||
1341 | i = (reg - 0x4480) >> 2; |
||
1342 | tmp = ib_chunk->kdata[idx] & 0x7FF; |
||
1343 | track->textures[i].width = tmp + 1; |
||
1344 | tmp = (ib_chunk->kdata[idx] >> 11) & 0x7FF; |
||
1345 | track->textures[i].height = tmp + 1; |
||
1346 | tmp = (ib_chunk->kdata[idx] >> 26) & 0xF; |
||
1347 | track->textures[i].num_levels = tmp; |
||
1348 | tmp = ib_chunk->kdata[idx] & (1 << 31); |
||
1349 | track->textures[i].use_pitch = !!tmp; |
||
1350 | tmp = (ib_chunk->kdata[idx] >> 22) & 0xF; |
||
1351 | track->textures[i].txdepth = tmp; |
||
1352 | break; |
||
1353 | default: |
||
1354 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
||
1355 | reg, idx); |
||
1356 | return -EINVAL; |
||
1357 | } |
||
1358 | return 0; |
||
1359 | } |
||
1360 | |||
1361 | static int r300_packet3_check(struct radeon_cs_parser *p, |
||
1362 | struct radeon_cs_packet *pkt) |
||
1363 | { |
||
1364 | struct radeon_cs_chunk *ib_chunk; |
||
1365 | struct radeon_cs_reloc *reloc; |
||
1366 | struct r300_cs_track *track; |
||
1367 | volatile uint32_t *ib; |
||
1368 | unsigned idx; |
||
1369 | unsigned i, c; |
||
1370 | int r; |
||
1371 | |||
1372 | ib = p->ib->ptr; |
||
1373 | ib_chunk = &p->chunks[p->chunk_ib_idx]; |
||
1374 | idx = pkt->idx + 1; |
||
1375 | track = (struct r300_cs_track*)p->track; |
||
1376 | switch(pkt->opcode) { |
||
1377 | case PACKET3_3D_LOAD_VBPNTR: |
||
1378 | c = ib_chunk->kdata[idx++] & 0x1F; |
||
1379 | track->num_arrays = c; |
||
1380 | for (i = 0; i < (c - 1); i+=2, idx+=3) { |
||
1381 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1382 | if (r) { |
||
1383 | DRM_ERROR("No reloc for packet3 %d\n", |
||
1384 | pkt->opcode); |
||
1385 | r100_cs_dump_packet(p, pkt); |
||
1386 | return r; |
||
1387 | } |
||
1388 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
||
1389 | track->arrays[i + 0].robj = reloc->robj; |
||
1390 | track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; |
||
1391 | track->arrays[i + 0].esize &= 0x7F; |
||
1392 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1393 | if (r) { |
||
1394 | DRM_ERROR("No reloc for packet3 %d\n", |
||
1395 | pkt->opcode); |
||
1396 | r100_cs_dump_packet(p, pkt); |
||
1397 | return r; |
||
1398 | } |
||
1399 | ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset); |
||
1400 | track->arrays[i + 1].robj = reloc->robj; |
||
1401 | track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24; |
||
1402 | track->arrays[i + 1].esize &= 0x7F; |
||
1403 | } |
||
1404 | if (c & 1) { |
||
1405 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1406 | if (r) { |
||
1407 | DRM_ERROR("No reloc for packet3 %d\n", |
||
1408 | pkt->opcode); |
||
1409 | r100_cs_dump_packet(p, pkt); |
||
1410 | return r; |
||
1411 | } |
||
1412 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
||
1413 | track->arrays[i + 0].robj = reloc->robj; |
||
1414 | track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; |
||
1415 | track->arrays[i + 0].esize &= 0x7F; |
||
1416 | } |
||
1417 | break; |
||
1418 | case PACKET3_INDX_BUFFER: |
||
1419 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1420 | if (r) { |
||
1421 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
||
1422 | r100_cs_dump_packet(p, pkt); |
||
1423 | return r; |
||
1424 | } |
||
1425 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
||
1426 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
||
1427 | if (r) { |
||
1428 | return r; |
||
1429 | } |
||
1430 | break; |
||
1431 | /* Draw packet */ |
||
1432 | case PACKET3_3D_DRAW_IMMD: |
||
1433 | /* Number of dwords is vtx_size * (num_vertices - 1) |
||
1434 | * PRIM_WALK must be equal to 3 vertex data in embedded |
||
1435 | * in cmd stream */ |
||
1436 | if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) { |
||
1437 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
||
1438 | return -EINVAL; |
||
1439 | } |
||
1440 | track->vap_vf_cntl = ib_chunk->kdata[idx+1]; |
||
1441 | track->immd_dwords = pkt->count - 1; |
||
1442 | r = r300_cs_track_check(p->rdev, track); |
||
1443 | if (r) { |
||
1444 | return r; |
||
1445 | } |
||
1446 | break; |
||
1447 | case PACKET3_3D_DRAW_IMMD_2: |
||
1448 | /* Number of dwords is vtx_size * (num_vertices - 1) |
||
1449 | * PRIM_WALK must be equal to 3 vertex data in embedded |
||
1450 | * in cmd stream */ |
||
1451 | if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) { |
||
1452 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
||
1453 | return -EINVAL; |
||
1454 | } |
||
1455 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
||
1456 | track->immd_dwords = pkt->count; |
||
1457 | r = r300_cs_track_check(p->rdev, track); |
||
1458 | if (r) { |
||
1459 | return r; |
||
1460 | } |
||
1461 | break; |
||
1462 | case PACKET3_3D_DRAW_VBUF: |
||
1463 | track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; |
||
1464 | r = r300_cs_track_check(p->rdev, track); |
||
1465 | if (r) { |
||
1466 | return r; |
||
1467 | } |
||
1468 | break; |
||
1469 | case PACKET3_3D_DRAW_VBUF_2: |
||
1470 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
||
1471 | r = r300_cs_track_check(p->rdev, track); |
||
1472 | if (r) { |
||
1473 | return r; |
||
1474 | } |
||
1475 | break; |
||
1476 | case PACKET3_3D_DRAW_INDX: |
||
1477 | track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; |
||
1478 | r = r300_cs_track_check(p->rdev, track); |
||
1479 | if (r) { |
||
1480 | return r; |
||
1481 | } |
||
1482 | break; |
||
1483 | case PACKET3_3D_DRAW_INDX_2: |
||
1484 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
||
1485 | r = r300_cs_track_check(p->rdev, track); |
||
1486 | if (r) { |
||
1487 | return r; |
||
1488 | } |
||
1489 | break; |
||
1490 | case PACKET3_NOP: |
||
1491 | break; |
||
1492 | default: |
||
1493 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); |
||
1494 | return -EINVAL; |
||
1495 | } |
||
1496 | return 0; |
||
1497 | } |
||
1498 | |||
1499 | int r300_cs_parse(struct radeon_cs_parser *p) |
||
1500 | { |
||
1501 | struct radeon_cs_packet pkt; |
||
1502 | struct r300_cs_track track; |
||
1503 | int r; |
||
1504 | |||
1505 | r300_cs_track_clear(&track); |
||
1506 | p->track = &track; |
||
1507 | do { |
||
1508 | r = r100_cs_packet_parse(p, &pkt, p->idx); |
||
1509 | if (r) { |
||
1510 | return r; |
||
1511 | } |
||
1512 | p->idx += pkt.count + 2; |
||
1513 | switch (pkt.type) { |
||
1514 | case PACKET_TYPE0: |
||
1515 | r = r100_cs_parse_packet0(p, &pkt, |
||
1516 | p->rdev->config.r300.reg_safe_bm, |
||
1517 | p->rdev->config.r300.reg_safe_bm_size, |
||
1518 | &r300_packet0_check); |
||
1519 | break; |
||
1520 | case PACKET_TYPE2: |
||
1521 | break; |
||
1522 | case PACKET_TYPE3: |
||
1523 | r = r300_packet3_check(p, &pkt); |
||
1524 | break; |
||
1525 | default: |
||
1526 | DRM_ERROR("Unknown packet type %d !\n", pkt.type); |
||
1527 | return -EINVAL; |
||
1528 | } |
||
1529 | if (r) { |
||
1530 | return r; |
||
1531 | } |
||
1532 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
||
1533 | return 0; |
||
1534 | } |
||
1535 | |||
1128 | serge | 1536 | #endif |
1537 | |||
1120 | serge | 1538 | int r300_init(struct radeon_device *rdev) |
1539 | { |
||
1540 | rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; |
||
1541 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); |
||
1542 | return 0; |
||
1543 | }>>><>><>><>><>>>><>><>>>>>>>><>><>><>><>=>>><>><>><>><>><>><>><>><>><>><>>><>><>><>><>>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>><>><>><>><>><>><>>> |
||
1544 |