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1179 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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2997 | Serge | 28 | #include |
29 | #include |
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1179 | serge | 30 | #include "radeon_reg.h" |
31 | #include "radeon.h" |
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1963 | serge | 32 | #include "radeon_asic.h" |
1179 | serge | 33 | |
1430 | serge | 34 | #include "r100d.h" |
1179 | serge | 35 | #include "r200_reg_safe.h" |
36 | |||
1963 | serge | 37 | #include "r100_track.h" |
38 | |||
1179 | serge | 39 | static int r200_get_vtx_size_0(uint32_t vtx_fmt_0) |
40 | { |
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41 | int vtx_size, i; |
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42 | vtx_size = 2; |
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43 | |||
44 | if (vtx_fmt_0 & R200_VTX_Z0) |
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45 | vtx_size++; |
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46 | if (vtx_fmt_0 & R200_VTX_W0) |
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47 | vtx_size++; |
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48 | /* blend weight */ |
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49 | if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT)) |
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50 | vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7; |
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51 | if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL) |
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52 | vtx_size++; |
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53 | if (vtx_fmt_0 & R200_VTX_N0) |
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54 | vtx_size += 3; |
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55 | if (vtx_fmt_0 & R200_VTX_POINT_SIZE) |
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56 | vtx_size++; |
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57 | if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG) |
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58 | vtx_size++; |
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59 | if (vtx_fmt_0 & R200_VTX_SHININESS_0) |
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60 | vtx_size++; |
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61 | if (vtx_fmt_0 & R200_VTX_SHININESS_1) |
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62 | vtx_size++; |
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63 | for (i = 0; i < 8; i++) { |
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64 | int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3; |
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65 | switch (color_size) { |
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66 | case 0: break; |
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67 | case 1: vtx_size++; break; |
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68 | case 2: vtx_size += 3; break; |
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69 | case 3: vtx_size += 4; break; |
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70 | } |
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71 | } |
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72 | if (vtx_fmt_0 & R200_VTX_XY1) |
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73 | vtx_size += 2; |
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74 | if (vtx_fmt_0 & R200_VTX_Z1) |
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75 | vtx_size++; |
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76 | if (vtx_fmt_0 & R200_VTX_W1) |
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77 | vtx_size++; |
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78 | if (vtx_fmt_0 & R200_VTX_N1) |
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79 | vtx_size += 3; |
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80 | return vtx_size; |
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81 | } |
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82 | |||
5271 | serge | 83 | struct radeon_fence *r200_copy_dma(struct radeon_device *rdev, |
1963 | serge | 84 | uint64_t src_offset, |
85 | uint64_t dst_offset, |
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2997 | Serge | 86 | unsigned num_gpu_pages, |
5271 | serge | 87 | struct reservation_object *resv) |
1963 | serge | 88 | { |
2997 | Serge | 89 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
5271 | serge | 90 | struct radeon_fence *fence; |
1963 | serge | 91 | uint32_t size; |
92 | uint32_t cur_size; |
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93 | int i, num_loops; |
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94 | int r = 0; |
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95 | |||
96 | /* radeon pitch is /64 */ |
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2997 | Serge | 97 | size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT; |
1963 | serge | 98 | num_loops = DIV_ROUND_UP(size, 0x1FFFFF); |
2997 | Serge | 99 | r = radeon_ring_lock(rdev, ring, num_loops * 4 + 64); |
1963 | serge | 100 | if (r) { |
101 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
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5271 | serge | 102 | return ERR_PTR(r); |
1963 | serge | 103 | } |
104 | /* Must wait for 2D idle & clean before DMA or hangs might happen */ |
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2997 | Serge | 105 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
106 | radeon_ring_write(ring, (1 << 16)); |
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1963 | serge | 107 | for (i = 0; i < num_loops; i++) { |
108 | cur_size = size; |
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109 | if (cur_size > 0x1FFFFF) { |
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110 | cur_size = 0x1FFFFF; |
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111 | } |
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112 | size -= cur_size; |
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2997 | Serge | 113 | radeon_ring_write(ring, PACKET0(0x720, 2)); |
114 | radeon_ring_write(ring, src_offset); |
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115 | radeon_ring_write(ring, dst_offset); |
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116 | radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30)); |
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1963 | serge | 117 | src_offset += cur_size; |
118 | dst_offset += cur_size; |
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119 | } |
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2997 | Serge | 120 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
121 | radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE); |
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5271 | serge | 122 | r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); |
123 | if (r) { |
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124 | radeon_ring_unlock_undo(rdev, ring); |
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125 | return ERR_PTR(r); |
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1963 | serge | 126 | } |
5078 | serge | 127 | radeon_ring_unlock_commit(rdev, ring, false); |
5271 | serge | 128 | return fence; |
1963 | serge | 129 | } |
130 | |||
5078 | serge | 131 | |
1179 | serge | 132 | static int r200_get_vtx_size_1(uint32_t vtx_fmt_1) |
133 | { |
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134 | int vtx_size, i, tex_size; |
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135 | vtx_size = 0; |
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136 | for (i = 0; i < 6; i++) { |
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137 | tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7; |
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138 | if (tex_size > 4) |
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139 | continue; |
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140 | vtx_size += tex_size; |
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141 | } |
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142 | return vtx_size; |
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143 | } |
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144 | |||
145 | int r200_packet0_check(struct radeon_cs_parser *p, |
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146 | struct radeon_cs_packet *pkt, |
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147 | unsigned idx, unsigned reg) |
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148 | { |
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5271 | serge | 149 | struct radeon_bo_list *reloc; |
1179 | serge | 150 | struct r100_cs_track *track; |
151 | volatile uint32_t *ib; |
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152 | uint32_t tmp; |
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153 | int r; |
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154 | int i; |
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155 | int face; |
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156 | u32 tile_flags = 0; |
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1221 | serge | 157 | u32 idx_value; |
1179 | serge | 158 | |
2997 | Serge | 159 | ib = p->ib.ptr; |
1179 | serge | 160 | track = (struct r100_cs_track *)p->track; |
1221 | serge | 161 | idx_value = radeon_get_ib_value(p, idx); |
1179 | serge | 162 | switch (reg) { |
163 | case RADEON_CRTC_GUI_TRIG_VLINE: |
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164 | r = r100_cs_packet_parse_vline(p); |
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165 | if (r) { |
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166 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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167 | idx, reg); |
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3764 | Serge | 168 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 169 | return r; |
170 | } |
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171 | break; |
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172 | /* FIXME: only allow PACKET3 blit? easier to check for out of |
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173 | * range access */ |
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174 | case RADEON_DST_PITCH_OFFSET: |
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175 | case RADEON_SRC_PITCH_OFFSET: |
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176 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
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177 | if (r) |
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178 | return r; |
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179 | break; |
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180 | case RADEON_RB3D_DEPTHOFFSET: |
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3764 | Serge | 181 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1179 | serge | 182 | if (r) { |
183 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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184 | idx, reg); |
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3764 | Serge | 185 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 186 | return r; |
187 | } |
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188 | track->zb.robj = reloc->robj; |
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1221 | serge | 189 | track->zb.offset = idx_value; |
1963 | serge | 190 | track->zb_dirty = true; |
5078 | serge | 191 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1179 | serge | 192 | break; |
193 | case RADEON_RB3D_COLOROFFSET: |
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3764 | Serge | 194 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1179 | serge | 195 | if (r) { |
196 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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197 | idx, reg); |
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3764 | Serge | 198 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 199 | return r; |
200 | } |
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201 | track->cb[0].robj = reloc->robj; |
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1221 | serge | 202 | track->cb[0].offset = idx_value; |
1963 | serge | 203 | track->cb_dirty = true; |
5078 | serge | 204 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1179 | serge | 205 | break; |
206 | case R200_PP_TXOFFSET_0: |
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207 | case R200_PP_TXOFFSET_1: |
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208 | case R200_PP_TXOFFSET_2: |
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209 | case R200_PP_TXOFFSET_3: |
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210 | case R200_PP_TXOFFSET_4: |
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211 | case R200_PP_TXOFFSET_5: |
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212 | i = (reg - R200_PP_TXOFFSET_0) / 24; |
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3764 | Serge | 213 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1179 | serge | 214 | if (r) { |
215 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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216 | idx, reg); |
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3764 | Serge | 217 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 218 | return r; |
219 | } |
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2997 | Serge | 220 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
5078 | serge | 221 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
2997 | Serge | 222 | tile_flags |= R200_TXO_MACRO_TILE; |
5078 | serge | 223 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
2997 | Serge | 224 | tile_flags |= R200_TXO_MICRO_TILE; |
225 | |||
226 | tmp = idx_value & ~(0x7 << 2); |
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227 | tmp |= tile_flags; |
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5078 | serge | 228 | ib[idx] = tmp + ((u32)reloc->gpu_offset); |
2997 | Serge | 229 | } else |
5078 | serge | 230 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1179 | serge | 231 | track->textures[i].robj = reloc->robj; |
1963 | serge | 232 | track->tex_dirty = true; |
1179 | serge | 233 | break; |
234 | case R200_PP_CUBIC_OFFSET_F1_0: |
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235 | case R200_PP_CUBIC_OFFSET_F2_0: |
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236 | case R200_PP_CUBIC_OFFSET_F3_0: |
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237 | case R200_PP_CUBIC_OFFSET_F4_0: |
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238 | case R200_PP_CUBIC_OFFSET_F5_0: |
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239 | case R200_PP_CUBIC_OFFSET_F1_1: |
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240 | case R200_PP_CUBIC_OFFSET_F2_1: |
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241 | case R200_PP_CUBIC_OFFSET_F3_1: |
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242 | case R200_PP_CUBIC_OFFSET_F4_1: |
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243 | case R200_PP_CUBIC_OFFSET_F5_1: |
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244 | case R200_PP_CUBIC_OFFSET_F1_2: |
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245 | case R200_PP_CUBIC_OFFSET_F2_2: |
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246 | case R200_PP_CUBIC_OFFSET_F3_2: |
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247 | case R200_PP_CUBIC_OFFSET_F4_2: |
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248 | case R200_PP_CUBIC_OFFSET_F5_2: |
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249 | case R200_PP_CUBIC_OFFSET_F1_3: |
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250 | case R200_PP_CUBIC_OFFSET_F2_3: |
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251 | case R200_PP_CUBIC_OFFSET_F3_3: |
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252 | case R200_PP_CUBIC_OFFSET_F4_3: |
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253 | case R200_PP_CUBIC_OFFSET_F5_3: |
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254 | case R200_PP_CUBIC_OFFSET_F1_4: |
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255 | case R200_PP_CUBIC_OFFSET_F2_4: |
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256 | case R200_PP_CUBIC_OFFSET_F3_4: |
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257 | case R200_PP_CUBIC_OFFSET_F4_4: |
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258 | case R200_PP_CUBIC_OFFSET_F5_4: |
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259 | case R200_PP_CUBIC_OFFSET_F1_5: |
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260 | case R200_PP_CUBIC_OFFSET_F2_5: |
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261 | case R200_PP_CUBIC_OFFSET_F3_5: |
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262 | case R200_PP_CUBIC_OFFSET_F4_5: |
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263 | case R200_PP_CUBIC_OFFSET_F5_5: |
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264 | i = (reg - R200_PP_TXOFFSET_0) / 24; |
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265 | face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4; |
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3764 | Serge | 266 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1179 | serge | 267 | if (r) { |
268 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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269 | idx, reg); |
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3764 | Serge | 270 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 271 | return r; |
272 | } |
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1221 | serge | 273 | track->textures[i].cube_info[face - 1].offset = idx_value; |
5078 | serge | 274 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1179 | serge | 275 | track->textures[i].cube_info[face - 1].robj = reloc->robj; |
1963 | serge | 276 | track->tex_dirty = true; |
1179 | serge | 277 | break; |
278 | case RADEON_RE_WIDTH_HEIGHT: |
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1221 | serge | 279 | track->maxy = ((idx_value >> 16) & 0x7FF); |
1963 | serge | 280 | track->cb_dirty = true; |
281 | track->zb_dirty = true; |
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1179 | serge | 282 | break; |
283 | case RADEON_RB3D_COLORPITCH: |
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3764 | Serge | 284 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1179 | serge | 285 | if (r) { |
286 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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287 | idx, reg); |
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3764 | Serge | 288 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 289 | return r; |
290 | } |
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291 | |||
2997 | Serge | 292 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
5078 | serge | 293 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
1179 | serge | 294 | tile_flags |= RADEON_COLOR_TILE_ENABLE; |
5078 | serge | 295 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
1179 | serge | 296 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
297 | |||
1221 | serge | 298 | tmp = idx_value & ~(0x7 << 16); |
1179 | serge | 299 | tmp |= tile_flags; |
300 | ib[idx] = tmp; |
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2997 | Serge | 301 | } else |
302 | ib[idx] = idx_value; |
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1179 | serge | 303 | |
1221 | serge | 304 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
1963 | serge | 305 | track->cb_dirty = true; |
1179 | serge | 306 | break; |
307 | case RADEON_RB3D_DEPTHPITCH: |
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1221 | serge | 308 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
1963 | serge | 309 | track->zb_dirty = true; |
1179 | serge | 310 | break; |
311 | case RADEON_RB3D_CNTL: |
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1221 | serge | 312 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
1179 | serge | 313 | case 7: |
314 | case 8: |
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315 | case 9: |
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316 | case 11: |
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317 | case 12: |
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318 | track->cb[0].cpp = 1; |
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319 | break; |
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320 | case 3: |
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321 | case 4: |
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322 | case 15: |
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323 | track->cb[0].cpp = 2; |
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324 | break; |
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325 | case 6: |
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326 | track->cb[0].cpp = 4; |
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327 | break; |
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328 | default: |
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329 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
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1221 | serge | 330 | ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
1179 | serge | 331 | return -EINVAL; |
332 | } |
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1221 | serge | 333 | if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) { |
1179 | serge | 334 | DRM_ERROR("No support for depth xy offset in kms\n"); |
335 | return -EINVAL; |
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336 | } |
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337 | |||
1221 | serge | 338 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
1963 | serge | 339 | track->cb_dirty = true; |
340 | track->zb_dirty = true; |
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1179 | serge | 341 | break; |
342 | case RADEON_RB3D_ZSTENCILCNTL: |
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1221 | serge | 343 | switch (idx_value & 0xf) { |
1179 | serge | 344 | case 0: |
345 | track->zb.cpp = 2; |
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346 | break; |
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347 | case 2: |
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348 | case 3: |
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349 | case 4: |
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350 | case 5: |
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351 | case 9: |
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352 | case 11: |
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353 | track->zb.cpp = 4; |
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354 | break; |
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355 | default: |
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356 | break; |
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357 | } |
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1963 | serge | 358 | track->zb_dirty = true; |
1179 | serge | 359 | break; |
360 | case RADEON_RB3D_ZPASS_ADDR: |
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3764 | Serge | 361 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1179 | serge | 362 | if (r) { |
363 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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364 | idx, reg); |
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3764 | Serge | 365 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 366 | return r; |
367 | } |
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5078 | serge | 368 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1179 | serge | 369 | break; |
370 | case RADEON_PP_CNTL: |
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371 | { |
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1221 | serge | 372 | uint32_t temp = idx_value >> 4; |
1179 | serge | 373 | for (i = 0; i < track->num_texture; i++) |
374 | track->textures[i].enabled = !!(temp & (1 << i)); |
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1963 | serge | 375 | track->tex_dirty = true; |
1179 | serge | 376 | } |
377 | break; |
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378 | case RADEON_SE_VF_CNTL: |
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1221 | serge | 379 | track->vap_vf_cntl = idx_value; |
1179 | serge | 380 | break; |
381 | case 0x210c: |
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382 | /* VAP_VF_MAX_VTX_INDX */ |
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1221 | serge | 383 | track->max_indx = idx_value & 0x00FFFFFFUL; |
1179 | serge | 384 | break; |
385 | case R200_SE_VTX_FMT_0: |
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1221 | serge | 386 | track->vtx_size = r200_get_vtx_size_0(idx_value); |
1179 | serge | 387 | break; |
388 | case R200_SE_VTX_FMT_1: |
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1221 | serge | 389 | track->vtx_size += r200_get_vtx_size_1(idx_value); |
1179 | serge | 390 | break; |
391 | case R200_PP_TXSIZE_0: |
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392 | case R200_PP_TXSIZE_1: |
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393 | case R200_PP_TXSIZE_2: |
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394 | case R200_PP_TXSIZE_3: |
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395 | case R200_PP_TXSIZE_4: |
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396 | case R200_PP_TXSIZE_5: |
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397 | i = (reg - R200_PP_TXSIZE_0) / 32; |
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1221 | serge | 398 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
399 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
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1963 | serge | 400 | track->tex_dirty = true; |
1179 | serge | 401 | break; |
402 | case R200_PP_TXPITCH_0: |
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403 | case R200_PP_TXPITCH_1: |
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404 | case R200_PP_TXPITCH_2: |
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405 | case R200_PP_TXPITCH_3: |
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406 | case R200_PP_TXPITCH_4: |
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407 | case R200_PP_TXPITCH_5: |
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408 | i = (reg - R200_PP_TXPITCH_0) / 32; |
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1221 | serge | 409 | track->textures[i].pitch = idx_value + 32; |
1963 | serge | 410 | track->tex_dirty = true; |
1179 | serge | 411 | break; |
412 | case R200_PP_TXFILTER_0: |
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413 | case R200_PP_TXFILTER_1: |
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414 | case R200_PP_TXFILTER_2: |
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415 | case R200_PP_TXFILTER_3: |
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416 | case R200_PP_TXFILTER_4: |
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417 | case R200_PP_TXFILTER_5: |
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418 | i = (reg - R200_PP_TXFILTER_0) / 32; |
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1221 | serge | 419 | track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK) |
1179 | serge | 420 | >> R200_MAX_MIP_LEVEL_SHIFT); |
1221 | serge | 421 | tmp = (idx_value >> 23) & 0x7; |
1179 | serge | 422 | if (tmp == 2 || tmp == 6) |
423 | track->textures[i].roundup_w = false; |
||
1221 | serge | 424 | tmp = (idx_value >> 27) & 0x7; |
1179 | serge | 425 | if (tmp == 2 || tmp == 6) |
426 | track->textures[i].roundup_h = false; |
||
1963 | serge | 427 | track->tex_dirty = true; |
1179 | serge | 428 | break; |
429 | case R200_PP_TXMULTI_CTL_0: |
||
430 | case R200_PP_TXMULTI_CTL_1: |
||
431 | case R200_PP_TXMULTI_CTL_2: |
||
432 | case R200_PP_TXMULTI_CTL_3: |
||
433 | case R200_PP_TXMULTI_CTL_4: |
||
434 | case R200_PP_TXMULTI_CTL_5: |
||
435 | i = (reg - R200_PP_TXMULTI_CTL_0) / 32; |
||
436 | break; |
||
437 | case R200_PP_TXFORMAT_X_0: |
||
438 | case R200_PP_TXFORMAT_X_1: |
||
439 | case R200_PP_TXFORMAT_X_2: |
||
440 | case R200_PP_TXFORMAT_X_3: |
||
441 | case R200_PP_TXFORMAT_X_4: |
||
442 | case R200_PP_TXFORMAT_X_5: |
||
443 | i = (reg - R200_PP_TXFORMAT_X_0) / 32; |
||
1221 | serge | 444 | track->textures[i].txdepth = idx_value & 0x7; |
445 | tmp = (idx_value >> 16) & 0x3; |
||
1179 | serge | 446 | /* 2D, 3D, CUBE */ |
447 | switch (tmp) { |
||
448 | case 0: |
||
1963 | serge | 449 | case 3: |
450 | case 4: |
||
1179 | serge | 451 | case 5: |
452 | case 6: |
||
453 | case 7: |
||
1403 | serge | 454 | /* 1D/2D */ |
1179 | serge | 455 | track->textures[i].tex_coord_type = 0; |
456 | break; |
||
457 | case 1: |
||
1403 | serge | 458 | /* CUBE */ |
459 | track->textures[i].tex_coord_type = 2; |
||
1179 | serge | 460 | break; |
461 | case 2: |
||
1403 | serge | 462 | /* 3D */ |
463 | track->textures[i].tex_coord_type = 1; |
||
1179 | serge | 464 | break; |
465 | } |
||
1963 | serge | 466 | track->tex_dirty = true; |
1179 | serge | 467 | break; |
468 | case R200_PP_TXFORMAT_0: |
||
469 | case R200_PP_TXFORMAT_1: |
||
470 | case R200_PP_TXFORMAT_2: |
||
471 | case R200_PP_TXFORMAT_3: |
||
472 | case R200_PP_TXFORMAT_4: |
||
473 | case R200_PP_TXFORMAT_5: |
||
474 | i = (reg - R200_PP_TXFORMAT_0) / 32; |
||
1221 | serge | 475 | if (idx_value & R200_TXFORMAT_NON_POWER2) { |
1179 | serge | 476 | track->textures[i].use_pitch = 1; |
477 | } else { |
||
478 | track->textures[i].use_pitch = 0; |
||
1221 | serge | 479 | track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
480 | track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
||
1179 | serge | 481 | } |
1963 | serge | 482 | if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE) |
483 | track->textures[i].lookup_disable = true; |
||
1221 | serge | 484 | switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
1179 | serge | 485 | case R200_TXFORMAT_I8: |
486 | case R200_TXFORMAT_RGB332: |
||
487 | case R200_TXFORMAT_Y8: |
||
488 | track->textures[i].cpp = 1; |
||
1963 | serge | 489 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1179 | serge | 490 | break; |
491 | case R200_TXFORMAT_AI88: |
||
492 | case R200_TXFORMAT_ARGB1555: |
||
493 | case R200_TXFORMAT_RGB565: |
||
494 | case R200_TXFORMAT_ARGB4444: |
||
495 | case R200_TXFORMAT_VYUY422: |
||
496 | case R200_TXFORMAT_YVYU422: |
||
497 | case R200_TXFORMAT_LDVDU655: |
||
498 | case R200_TXFORMAT_DVDU88: |
||
499 | case R200_TXFORMAT_AVYU4444: |
||
500 | track->textures[i].cpp = 2; |
||
1963 | serge | 501 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1179 | serge | 502 | break; |
503 | case R200_TXFORMAT_ARGB8888: |
||
504 | case R200_TXFORMAT_RGBA8888: |
||
505 | case R200_TXFORMAT_ABGR8888: |
||
506 | case R200_TXFORMAT_BGR111110: |
||
507 | case R200_TXFORMAT_LDVDU8888: |
||
1403 | serge | 508 | track->textures[i].cpp = 4; |
1963 | serge | 509 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1403 | serge | 510 | break; |
511 | case R200_TXFORMAT_DXT1: |
||
512 | track->textures[i].cpp = 1; |
||
513 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
||
514 | break; |
||
1179 | serge | 515 | case R200_TXFORMAT_DXT23: |
516 | case R200_TXFORMAT_DXT45: |
||
1403 | serge | 517 | track->textures[i].cpp = 1; |
518 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
||
1179 | serge | 519 | break; |
520 | } |
||
1221 | serge | 521 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
522 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
||
1963 | serge | 523 | track->tex_dirty = true; |
1179 | serge | 524 | break; |
525 | case R200_PP_CUBIC_FACES_0: |
||
526 | case R200_PP_CUBIC_FACES_1: |
||
527 | case R200_PP_CUBIC_FACES_2: |
||
528 | case R200_PP_CUBIC_FACES_3: |
||
529 | case R200_PP_CUBIC_FACES_4: |
||
530 | case R200_PP_CUBIC_FACES_5: |
||
1221 | serge | 531 | tmp = idx_value; |
1179 | serge | 532 | i = (reg - R200_PP_CUBIC_FACES_0) / 32; |
533 | for (face = 0; face < 4; face++) { |
||
534 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
||
535 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); |
||
536 | } |
||
1963 | serge | 537 | track->tex_dirty = true; |
1179 | serge | 538 | break; |
539 | default: |
||
540 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
||
541 | reg, idx); |
||
542 | return -EINVAL; |
||
543 | } |
||
544 | return 0; |
||
545 | } |
||
546 | |||
1221 | serge | 547 | void r200_set_safe_registers(struct radeon_device *rdev) |
1179 | serge | 548 | { |
549 | rdev->config.r100.reg_safe_bm = r200_reg_safe_bm; |
||
550 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm); |
||
551 | }><>><>>><>><>><>><>><>>><>><>>><>><>>><>><>>><> |