Rev 1430 | Rev 2005 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1179 | serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * Copyright 2009 Jerome Glisse. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: Dave Airlie |
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| 25 | * Alex Deucher |
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| 26 | * Jerome Glisse |
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| 27 | */ |
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| 28 | #include "drmP.h" |
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| 29 | #include "drm.h" |
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| 30 | #include "radeon_drm.h" |
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| 31 | #include "radeon_reg.h" |
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| 32 | #include "radeon.h" |
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| 1963 | serge | 33 | #include "radeon_asic.h" |
| 1179 | serge | 34 | |
| 1430 | serge | 35 | #include "r100d.h" |
| 1179 | serge | 36 | #include "r200_reg_safe.h" |
| 37 | |||
| 1963 | serge | 38 | #if 0 |
| 1179 | serge | 39 | |
| 1963 | serge | 40 | #include "r100_track.h" |
| 41 | |||
| 1179 | serge | 42 | static int r200_get_vtx_size_0(uint32_t vtx_fmt_0) |
| 43 | { |
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| 44 | int vtx_size, i; |
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| 45 | vtx_size = 2; |
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| 46 | |||
| 47 | if (vtx_fmt_0 & R200_VTX_Z0) |
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| 48 | vtx_size++; |
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| 49 | if (vtx_fmt_0 & R200_VTX_W0) |
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| 50 | vtx_size++; |
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| 51 | /* blend weight */ |
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| 52 | if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT)) |
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| 53 | vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7; |
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| 54 | if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL) |
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| 55 | vtx_size++; |
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| 56 | if (vtx_fmt_0 & R200_VTX_N0) |
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| 57 | vtx_size += 3; |
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| 58 | if (vtx_fmt_0 & R200_VTX_POINT_SIZE) |
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| 59 | vtx_size++; |
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| 60 | if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG) |
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| 61 | vtx_size++; |
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| 62 | if (vtx_fmt_0 & R200_VTX_SHININESS_0) |
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| 63 | vtx_size++; |
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| 64 | if (vtx_fmt_0 & R200_VTX_SHININESS_1) |
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| 65 | vtx_size++; |
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| 66 | for (i = 0; i < 8; i++) { |
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| 67 | int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3; |
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| 68 | switch (color_size) { |
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| 69 | case 0: break; |
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| 70 | case 1: vtx_size++; break; |
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| 71 | case 2: vtx_size += 3; break; |
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| 72 | case 3: vtx_size += 4; break; |
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| 73 | } |
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| 74 | } |
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| 75 | if (vtx_fmt_0 & R200_VTX_XY1) |
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| 76 | vtx_size += 2; |
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| 77 | if (vtx_fmt_0 & R200_VTX_Z1) |
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| 78 | vtx_size++; |
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| 79 | if (vtx_fmt_0 & R200_VTX_W1) |
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| 80 | vtx_size++; |
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| 81 | if (vtx_fmt_0 & R200_VTX_N1) |
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| 82 | vtx_size += 3; |
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| 83 | return vtx_size; |
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| 84 | } |
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| 85 | |||
| 1963 | serge | 86 | int r200_copy_dma(struct radeon_device *rdev, |
| 87 | uint64_t src_offset, |
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| 88 | uint64_t dst_offset, |
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| 89 | unsigned num_pages, |
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| 90 | struct radeon_fence *fence) |
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| 91 | { |
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| 92 | uint32_t size; |
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| 93 | uint32_t cur_size; |
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| 94 | int i, num_loops; |
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| 95 | int r = 0; |
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| 96 | |||
| 97 | /* radeon pitch is /64 */ |
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| 98 | size = num_pages << PAGE_SHIFT; |
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| 99 | num_loops = DIV_ROUND_UP(size, 0x1FFFFF); |
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| 100 | r = radeon_ring_lock(rdev, num_loops * 4 + 64); |
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| 101 | if (r) { |
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| 102 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
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| 103 | return r; |
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| 104 | } |
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| 105 | /* Must wait for 2D idle & clean before DMA or hangs might happen */ |
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| 106 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
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| 107 | radeon_ring_write(rdev, (1 << 16)); |
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| 108 | for (i = 0; i < num_loops; i++) { |
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| 109 | cur_size = size; |
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| 110 | if (cur_size > 0x1FFFFF) { |
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| 111 | cur_size = 0x1FFFFF; |
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| 112 | } |
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| 113 | size -= cur_size; |
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| 114 | radeon_ring_write(rdev, PACKET0(0x720, 2)); |
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| 115 | radeon_ring_write(rdev, src_offset); |
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| 116 | radeon_ring_write(rdev, dst_offset); |
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| 117 | radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30)); |
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| 118 | src_offset += cur_size; |
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| 119 | dst_offset += cur_size; |
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| 120 | } |
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| 121 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
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| 122 | radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE); |
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| 123 | if (fence) { |
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| 124 | r = radeon_fence_emit(rdev, fence); |
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| 125 | } |
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| 126 | radeon_ring_unlock_commit(rdev); |
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| 127 | return r; |
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| 128 | } |
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| 129 | |||
| 130 | |||
| 1179 | serge | 131 | static int r200_get_vtx_size_1(uint32_t vtx_fmt_1) |
| 132 | { |
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| 133 | int vtx_size, i, tex_size; |
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| 134 | vtx_size = 0; |
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| 135 | for (i = 0; i < 6; i++) { |
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| 136 | tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7; |
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| 137 | if (tex_size > 4) |
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| 138 | continue; |
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| 139 | vtx_size += tex_size; |
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| 140 | } |
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| 141 | return vtx_size; |
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| 142 | } |
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| 143 | |||
| 144 | int r200_packet0_check(struct radeon_cs_parser *p, |
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| 145 | struct radeon_cs_packet *pkt, |
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| 146 | unsigned idx, unsigned reg) |
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| 147 | { |
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| 148 | struct radeon_cs_reloc *reloc; |
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| 149 | struct r100_cs_track *track; |
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| 150 | volatile uint32_t *ib; |
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| 151 | uint32_t tmp; |
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| 152 | int r; |
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| 153 | int i; |
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| 154 | int face; |
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| 155 | u32 tile_flags = 0; |
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| 1221 | serge | 156 | u32 idx_value; |
| 1179 | serge | 157 | |
| 158 | ib = p->ib->ptr; |
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| 159 | track = (struct r100_cs_track *)p->track; |
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| 1221 | serge | 160 | idx_value = radeon_get_ib_value(p, idx); |
| 1179 | serge | 161 | switch (reg) { |
| 162 | case RADEON_CRTC_GUI_TRIG_VLINE: |
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| 163 | r = r100_cs_packet_parse_vline(p); |
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| 164 | if (r) { |
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| 165 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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| 166 | idx, reg); |
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| 167 | r100_cs_dump_packet(p, pkt); |
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| 168 | return r; |
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| 169 | } |
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| 170 | break; |
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| 171 | /* FIXME: only allow PACKET3 blit? easier to check for out of |
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| 172 | * range access */ |
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| 173 | case RADEON_DST_PITCH_OFFSET: |
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| 174 | case RADEON_SRC_PITCH_OFFSET: |
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| 175 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
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| 176 | if (r) |
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| 177 | return r; |
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| 178 | break; |
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| 179 | case RADEON_RB3D_DEPTHOFFSET: |
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| 180 | r = r100_cs_packet_next_reloc(p, &reloc); |
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| 181 | if (r) { |
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| 182 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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| 183 | idx, reg); |
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| 184 | r100_cs_dump_packet(p, pkt); |
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| 185 | return r; |
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| 186 | } |
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| 187 | track->zb.robj = reloc->robj; |
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| 1221 | serge | 188 | track->zb.offset = idx_value; |
| 1963 | serge | 189 | track->zb_dirty = true; |
| 1221 | serge | 190 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| 1179 | serge | 191 | break; |
| 192 | case RADEON_RB3D_COLOROFFSET: |
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| 193 | r = r100_cs_packet_next_reloc(p, &reloc); |
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| 194 | if (r) { |
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| 195 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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| 196 | idx, reg); |
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| 197 | r100_cs_dump_packet(p, pkt); |
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| 198 | return r; |
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| 199 | } |
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| 200 | track->cb[0].robj = reloc->robj; |
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| 1221 | serge | 201 | track->cb[0].offset = idx_value; |
| 1963 | serge | 202 | track->cb_dirty = true; |
| 1221 | serge | 203 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| 1179 | serge | 204 | break; |
| 205 | case R200_PP_TXOFFSET_0: |
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| 206 | case R200_PP_TXOFFSET_1: |
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| 207 | case R200_PP_TXOFFSET_2: |
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| 208 | case R200_PP_TXOFFSET_3: |
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| 209 | case R200_PP_TXOFFSET_4: |
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| 210 | case R200_PP_TXOFFSET_5: |
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| 211 | i = (reg - R200_PP_TXOFFSET_0) / 24; |
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| 212 | r = r100_cs_packet_next_reloc(p, &reloc); |
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| 213 | if (r) { |
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| 214 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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| 215 | idx, reg); |
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| 216 | r100_cs_dump_packet(p, pkt); |
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| 217 | return r; |
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| 218 | } |
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| 1221 | serge | 219 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| 1179 | serge | 220 | track->textures[i].robj = reloc->robj; |
| 1963 | serge | 221 | track->tex_dirty = true; |
| 1179 | serge | 222 | break; |
| 223 | case R200_PP_CUBIC_OFFSET_F1_0: |
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| 224 | case R200_PP_CUBIC_OFFSET_F2_0: |
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| 225 | case R200_PP_CUBIC_OFFSET_F3_0: |
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| 226 | case R200_PP_CUBIC_OFFSET_F4_0: |
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| 227 | case R200_PP_CUBIC_OFFSET_F5_0: |
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| 228 | case R200_PP_CUBIC_OFFSET_F1_1: |
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| 229 | case R200_PP_CUBIC_OFFSET_F2_1: |
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| 230 | case R200_PP_CUBIC_OFFSET_F3_1: |
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| 231 | case R200_PP_CUBIC_OFFSET_F4_1: |
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| 232 | case R200_PP_CUBIC_OFFSET_F5_1: |
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| 233 | case R200_PP_CUBIC_OFFSET_F1_2: |
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| 234 | case R200_PP_CUBIC_OFFSET_F2_2: |
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| 235 | case R200_PP_CUBIC_OFFSET_F3_2: |
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| 236 | case R200_PP_CUBIC_OFFSET_F4_2: |
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| 237 | case R200_PP_CUBIC_OFFSET_F5_2: |
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| 238 | case R200_PP_CUBIC_OFFSET_F1_3: |
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| 239 | case R200_PP_CUBIC_OFFSET_F2_3: |
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| 240 | case R200_PP_CUBIC_OFFSET_F3_3: |
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| 241 | case R200_PP_CUBIC_OFFSET_F4_3: |
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| 242 | case R200_PP_CUBIC_OFFSET_F5_3: |
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| 243 | case R200_PP_CUBIC_OFFSET_F1_4: |
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| 244 | case R200_PP_CUBIC_OFFSET_F2_4: |
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| 245 | case R200_PP_CUBIC_OFFSET_F3_4: |
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| 246 | case R200_PP_CUBIC_OFFSET_F4_4: |
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| 247 | case R200_PP_CUBIC_OFFSET_F5_4: |
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| 248 | case R200_PP_CUBIC_OFFSET_F1_5: |
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| 249 | case R200_PP_CUBIC_OFFSET_F2_5: |
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| 250 | case R200_PP_CUBIC_OFFSET_F3_5: |
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| 251 | case R200_PP_CUBIC_OFFSET_F4_5: |
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| 252 | case R200_PP_CUBIC_OFFSET_F5_5: |
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| 253 | i = (reg - R200_PP_TXOFFSET_0) / 24; |
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| 254 | face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4; |
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| 255 | r = r100_cs_packet_next_reloc(p, &reloc); |
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| 256 | if (r) { |
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| 257 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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| 258 | idx, reg); |
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| 259 | r100_cs_dump_packet(p, pkt); |
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| 260 | return r; |
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| 261 | } |
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| 1221 | serge | 262 | track->textures[i].cube_info[face - 1].offset = idx_value; |
| 263 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
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| 1179 | serge | 264 | track->textures[i].cube_info[face - 1].robj = reloc->robj; |
| 1963 | serge | 265 | track->tex_dirty = true; |
| 1179 | serge | 266 | break; |
| 267 | case RADEON_RE_WIDTH_HEIGHT: |
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| 1221 | serge | 268 | track->maxy = ((idx_value >> 16) & 0x7FF); |
| 1963 | serge | 269 | track->cb_dirty = true; |
| 270 | track->zb_dirty = true; |
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| 1179 | serge | 271 | break; |
| 272 | case RADEON_RB3D_COLORPITCH: |
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| 273 | r = r100_cs_packet_next_reloc(p, &reloc); |
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| 274 | if (r) { |
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| 275 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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| 276 | idx, reg); |
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| 277 | r100_cs_dump_packet(p, pkt); |
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| 278 | return r; |
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| 279 | } |
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| 280 | |||
| 281 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
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| 282 | tile_flags |= RADEON_COLOR_TILE_ENABLE; |
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| 283 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
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| 284 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
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| 285 | |||
| 1221 | serge | 286 | tmp = idx_value & ~(0x7 << 16); |
| 1179 | serge | 287 | tmp |= tile_flags; |
| 288 | ib[idx] = tmp; |
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| 289 | |||
| 1221 | serge | 290 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
| 1963 | serge | 291 | track->cb_dirty = true; |
| 1179 | serge | 292 | break; |
| 293 | case RADEON_RB3D_DEPTHPITCH: |
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| 1221 | serge | 294 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
| 1963 | serge | 295 | track->zb_dirty = true; |
| 1179 | serge | 296 | break; |
| 297 | case RADEON_RB3D_CNTL: |
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| 1221 | serge | 298 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
| 1179 | serge | 299 | case 7: |
| 300 | case 8: |
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| 301 | case 9: |
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| 302 | case 11: |
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| 303 | case 12: |
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| 304 | track->cb[0].cpp = 1; |
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| 305 | break; |
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| 306 | case 3: |
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| 307 | case 4: |
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| 308 | case 15: |
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| 309 | track->cb[0].cpp = 2; |
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| 310 | break; |
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| 311 | case 6: |
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| 312 | track->cb[0].cpp = 4; |
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| 313 | break; |
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| 314 | default: |
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| 315 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
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| 1221 | serge | 316 | ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
| 1179 | serge | 317 | return -EINVAL; |
| 318 | } |
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| 1221 | serge | 319 | if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) { |
| 1179 | serge | 320 | DRM_ERROR("No support for depth xy offset in kms\n"); |
| 321 | return -EINVAL; |
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| 322 | } |
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| 323 | |||
| 1221 | serge | 324 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
| 1963 | serge | 325 | track->cb_dirty = true; |
| 326 | track->zb_dirty = true; |
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| 1179 | serge | 327 | break; |
| 328 | case RADEON_RB3D_ZSTENCILCNTL: |
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| 1221 | serge | 329 | switch (idx_value & 0xf) { |
| 1179 | serge | 330 | case 0: |
| 331 | track->zb.cpp = 2; |
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| 332 | break; |
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| 333 | case 2: |
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| 334 | case 3: |
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| 335 | case 4: |
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| 336 | case 5: |
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| 337 | case 9: |
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| 338 | case 11: |
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| 339 | track->zb.cpp = 4; |
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| 340 | break; |
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| 341 | default: |
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| 342 | break; |
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| 343 | } |
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| 1963 | serge | 344 | track->zb_dirty = true; |
| 1179 | serge | 345 | break; |
| 346 | case RADEON_RB3D_ZPASS_ADDR: |
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| 347 | r = r100_cs_packet_next_reloc(p, &reloc); |
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| 348 | if (r) { |
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| 349 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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| 350 | idx, reg); |
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| 351 | r100_cs_dump_packet(p, pkt); |
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| 352 | return r; |
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| 353 | } |
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| 1221 | serge | 354 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| 1179 | serge | 355 | break; |
| 356 | case RADEON_PP_CNTL: |
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| 357 | { |
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| 1221 | serge | 358 | uint32_t temp = idx_value >> 4; |
| 1179 | serge | 359 | for (i = 0; i < track->num_texture; i++) |
| 360 | track->textures[i].enabled = !!(temp & (1 << i)); |
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| 1963 | serge | 361 | track->tex_dirty = true; |
| 1179 | serge | 362 | } |
| 363 | break; |
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| 364 | case RADEON_SE_VF_CNTL: |
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| 1221 | serge | 365 | track->vap_vf_cntl = idx_value; |
| 1179 | serge | 366 | break; |
| 367 | case 0x210c: |
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| 368 | /* VAP_VF_MAX_VTX_INDX */ |
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| 1221 | serge | 369 | track->max_indx = idx_value & 0x00FFFFFFUL; |
| 1179 | serge | 370 | break; |
| 371 | case R200_SE_VTX_FMT_0: |
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| 1221 | serge | 372 | track->vtx_size = r200_get_vtx_size_0(idx_value); |
| 1179 | serge | 373 | break; |
| 374 | case R200_SE_VTX_FMT_1: |
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| 1221 | serge | 375 | track->vtx_size += r200_get_vtx_size_1(idx_value); |
| 1179 | serge | 376 | break; |
| 377 | case R200_PP_TXSIZE_0: |
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| 378 | case R200_PP_TXSIZE_1: |
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| 379 | case R200_PP_TXSIZE_2: |
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| 380 | case R200_PP_TXSIZE_3: |
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| 381 | case R200_PP_TXSIZE_4: |
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| 382 | case R200_PP_TXSIZE_5: |
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| 383 | i = (reg - R200_PP_TXSIZE_0) / 32; |
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| 1221 | serge | 384 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
| 385 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
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| 1963 | serge | 386 | track->tex_dirty = true; |
| 1179 | serge | 387 | break; |
| 388 | case R200_PP_TXPITCH_0: |
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| 389 | case R200_PP_TXPITCH_1: |
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| 390 | case R200_PP_TXPITCH_2: |
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| 391 | case R200_PP_TXPITCH_3: |
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| 392 | case R200_PP_TXPITCH_4: |
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| 393 | case R200_PP_TXPITCH_5: |
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| 394 | i = (reg - R200_PP_TXPITCH_0) / 32; |
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| 1221 | serge | 395 | track->textures[i].pitch = idx_value + 32; |
| 1963 | serge | 396 | track->tex_dirty = true; |
| 1179 | serge | 397 | break; |
| 398 | case R200_PP_TXFILTER_0: |
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| 399 | case R200_PP_TXFILTER_1: |
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| 400 | case R200_PP_TXFILTER_2: |
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| 401 | case R200_PP_TXFILTER_3: |
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| 402 | case R200_PP_TXFILTER_4: |
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| 403 | case R200_PP_TXFILTER_5: |
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| 404 | i = (reg - R200_PP_TXFILTER_0) / 32; |
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| 1221 | serge | 405 | track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK) |
| 1179 | serge | 406 | >> R200_MAX_MIP_LEVEL_SHIFT); |
| 1221 | serge | 407 | tmp = (idx_value >> 23) & 0x7; |
| 1179 | serge | 408 | if (tmp == 2 || tmp == 6) |
| 409 | track->textures[i].roundup_w = false; |
||
| 1221 | serge | 410 | tmp = (idx_value >> 27) & 0x7; |
| 1179 | serge | 411 | if (tmp == 2 || tmp == 6) |
| 412 | track->textures[i].roundup_h = false; |
||
| 1963 | serge | 413 | track->tex_dirty = true; |
| 1179 | serge | 414 | break; |
| 415 | case R200_PP_TXMULTI_CTL_0: |
||
| 416 | case R200_PP_TXMULTI_CTL_1: |
||
| 417 | case R200_PP_TXMULTI_CTL_2: |
||
| 418 | case R200_PP_TXMULTI_CTL_3: |
||
| 419 | case R200_PP_TXMULTI_CTL_4: |
||
| 420 | case R200_PP_TXMULTI_CTL_5: |
||
| 421 | i = (reg - R200_PP_TXMULTI_CTL_0) / 32; |
||
| 422 | break; |
||
| 423 | case R200_PP_TXFORMAT_X_0: |
||
| 424 | case R200_PP_TXFORMAT_X_1: |
||
| 425 | case R200_PP_TXFORMAT_X_2: |
||
| 426 | case R200_PP_TXFORMAT_X_3: |
||
| 427 | case R200_PP_TXFORMAT_X_4: |
||
| 428 | case R200_PP_TXFORMAT_X_5: |
||
| 429 | i = (reg - R200_PP_TXFORMAT_X_0) / 32; |
||
| 1221 | serge | 430 | track->textures[i].txdepth = idx_value & 0x7; |
| 431 | tmp = (idx_value >> 16) & 0x3; |
||
| 1179 | serge | 432 | /* 2D, 3D, CUBE */ |
| 433 | switch (tmp) { |
||
| 434 | case 0: |
||
| 1963 | serge | 435 | case 3: |
| 436 | case 4: |
||
| 1179 | serge | 437 | case 5: |
| 438 | case 6: |
||
| 439 | case 7: |
||
| 1403 | serge | 440 | /* 1D/2D */ |
| 1179 | serge | 441 | track->textures[i].tex_coord_type = 0; |
| 442 | break; |
||
| 443 | case 1: |
||
| 1403 | serge | 444 | /* CUBE */ |
| 445 | track->textures[i].tex_coord_type = 2; |
||
| 1179 | serge | 446 | break; |
| 447 | case 2: |
||
| 1403 | serge | 448 | /* 3D */ |
| 449 | track->textures[i].tex_coord_type = 1; |
||
| 1179 | serge | 450 | break; |
| 451 | } |
||
| 1963 | serge | 452 | track->tex_dirty = true; |
| 1179 | serge | 453 | break; |
| 454 | case R200_PP_TXFORMAT_0: |
||
| 455 | case R200_PP_TXFORMAT_1: |
||
| 456 | case R200_PP_TXFORMAT_2: |
||
| 457 | case R200_PP_TXFORMAT_3: |
||
| 458 | case R200_PP_TXFORMAT_4: |
||
| 459 | case R200_PP_TXFORMAT_5: |
||
| 460 | i = (reg - R200_PP_TXFORMAT_0) / 32; |
||
| 1221 | serge | 461 | if (idx_value & R200_TXFORMAT_NON_POWER2) { |
| 1179 | serge | 462 | track->textures[i].use_pitch = 1; |
| 463 | } else { |
||
| 464 | track->textures[i].use_pitch = 0; |
||
| 1221 | serge | 465 | track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
| 466 | track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
||
| 1179 | serge | 467 | } |
| 1963 | serge | 468 | if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE) |
| 469 | track->textures[i].lookup_disable = true; |
||
| 1221 | serge | 470 | switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
| 1179 | serge | 471 | case R200_TXFORMAT_I8: |
| 472 | case R200_TXFORMAT_RGB332: |
||
| 473 | case R200_TXFORMAT_Y8: |
||
| 474 | track->textures[i].cpp = 1; |
||
| 1963 | serge | 475 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
| 1179 | serge | 476 | break; |
| 477 | case R200_TXFORMAT_AI88: |
||
| 478 | case R200_TXFORMAT_ARGB1555: |
||
| 479 | case R200_TXFORMAT_RGB565: |
||
| 480 | case R200_TXFORMAT_ARGB4444: |
||
| 481 | case R200_TXFORMAT_VYUY422: |
||
| 482 | case R200_TXFORMAT_YVYU422: |
||
| 483 | case R200_TXFORMAT_LDVDU655: |
||
| 484 | case R200_TXFORMAT_DVDU88: |
||
| 485 | case R200_TXFORMAT_AVYU4444: |
||
| 486 | track->textures[i].cpp = 2; |
||
| 1963 | serge | 487 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
| 1179 | serge | 488 | break; |
| 489 | case R200_TXFORMAT_ARGB8888: |
||
| 490 | case R200_TXFORMAT_RGBA8888: |
||
| 491 | case R200_TXFORMAT_ABGR8888: |
||
| 492 | case R200_TXFORMAT_BGR111110: |
||
| 493 | case R200_TXFORMAT_LDVDU8888: |
||
| 1403 | serge | 494 | track->textures[i].cpp = 4; |
| 1963 | serge | 495 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
| 1403 | serge | 496 | break; |
| 497 | case R200_TXFORMAT_DXT1: |
||
| 498 | track->textures[i].cpp = 1; |
||
| 499 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
||
| 500 | break; |
||
| 1179 | serge | 501 | case R200_TXFORMAT_DXT23: |
| 502 | case R200_TXFORMAT_DXT45: |
||
| 1403 | serge | 503 | track->textures[i].cpp = 1; |
| 504 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
||
| 1179 | serge | 505 | break; |
| 506 | } |
||
| 1221 | serge | 507 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
| 508 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
||
| 1963 | serge | 509 | track->tex_dirty = true; |
| 1179 | serge | 510 | break; |
| 511 | case R200_PP_CUBIC_FACES_0: |
||
| 512 | case R200_PP_CUBIC_FACES_1: |
||
| 513 | case R200_PP_CUBIC_FACES_2: |
||
| 514 | case R200_PP_CUBIC_FACES_3: |
||
| 515 | case R200_PP_CUBIC_FACES_4: |
||
| 516 | case R200_PP_CUBIC_FACES_5: |
||
| 1221 | serge | 517 | tmp = idx_value; |
| 1179 | serge | 518 | i = (reg - R200_PP_CUBIC_FACES_0) / 32; |
| 519 | for (face = 0; face < 4; face++) { |
||
| 520 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
||
| 521 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); |
||
| 522 | } |
||
| 1963 | serge | 523 | track->tex_dirty = true; |
| 1179 | serge | 524 | break; |
| 525 | default: |
||
| 526 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
||
| 527 | reg, idx); |
||
| 528 | return -EINVAL; |
||
| 529 | } |
||
| 530 | return 0; |
||
| 531 | } |
||
| 532 | #endif |
||
| 533 | |||
| 1221 | serge | 534 | void r200_set_safe_registers(struct radeon_device *rdev) |
| 1179 | serge | 535 | { |
| 536 | rdev->config.r100.reg_safe_bm = r200_reg_safe_bm; |
||
| 537 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm); |
||
| 538 | } |