Rev 1403 | Rev 1963 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1179 | serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
||
| 3 | * Copyright 2008 Red Hat Inc. |
||
| 4 | * Copyright 2009 Jerome Glisse. |
||
| 5 | * |
||
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
| 7 | * copy of this software and associated documentation files (the "Software"), |
||
| 8 | * to deal in the Software without restriction, including without limitation |
||
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
||
| 11 | * Software is furnished to do so, subject to the following conditions: |
||
| 12 | * |
||
| 13 | * The above copyright notice and this permission notice shall be included in |
||
| 14 | * all copies or substantial portions of the Software. |
||
| 15 | * |
||
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
||
| 23 | * |
||
| 24 | * Authors: Dave Airlie |
||
| 25 | * Alex Deucher |
||
| 26 | * Jerome Glisse |
||
| 27 | */ |
||
| 28 | #include "drmP.h" |
||
| 29 | #include "drm.h" |
||
| 30 | #include "radeon_drm.h" |
||
| 31 | #include "radeon_reg.h" |
||
| 32 | #include "radeon.h" |
||
| 33 | |||
| 1430 | serge | 34 | #include "r100d.h" |
| 1179 | serge | 35 | #include "r200_reg_safe.h" |
| 36 | |||
| 37 | //#include "r100_track.h" |
||
| 38 | |||
| 39 | #if 0 |
||
| 40 | static int r200_get_vtx_size_0(uint32_t vtx_fmt_0) |
||
| 41 | { |
||
| 42 | int vtx_size, i; |
||
| 43 | vtx_size = 2; |
||
| 44 | |||
| 45 | if (vtx_fmt_0 & R200_VTX_Z0) |
||
| 46 | vtx_size++; |
||
| 47 | if (vtx_fmt_0 & R200_VTX_W0) |
||
| 48 | vtx_size++; |
||
| 49 | /* blend weight */ |
||
| 50 | if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT)) |
||
| 51 | vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7; |
||
| 52 | if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL) |
||
| 53 | vtx_size++; |
||
| 54 | if (vtx_fmt_0 & R200_VTX_N0) |
||
| 55 | vtx_size += 3; |
||
| 56 | if (vtx_fmt_0 & R200_VTX_POINT_SIZE) |
||
| 57 | vtx_size++; |
||
| 58 | if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG) |
||
| 59 | vtx_size++; |
||
| 60 | if (vtx_fmt_0 & R200_VTX_SHININESS_0) |
||
| 61 | vtx_size++; |
||
| 62 | if (vtx_fmt_0 & R200_VTX_SHININESS_1) |
||
| 63 | vtx_size++; |
||
| 64 | for (i = 0; i < 8; i++) { |
||
| 65 | int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3; |
||
| 66 | switch (color_size) { |
||
| 67 | case 0: break; |
||
| 68 | case 1: vtx_size++; break; |
||
| 69 | case 2: vtx_size += 3; break; |
||
| 70 | case 3: vtx_size += 4; break; |
||
| 71 | } |
||
| 72 | } |
||
| 73 | if (vtx_fmt_0 & R200_VTX_XY1) |
||
| 74 | vtx_size += 2; |
||
| 75 | if (vtx_fmt_0 & R200_VTX_Z1) |
||
| 76 | vtx_size++; |
||
| 77 | if (vtx_fmt_0 & R200_VTX_W1) |
||
| 78 | vtx_size++; |
||
| 79 | if (vtx_fmt_0 & R200_VTX_N1) |
||
| 80 | vtx_size += 3; |
||
| 81 | return vtx_size; |
||
| 82 | } |
||
| 83 | |||
| 84 | static int r200_get_vtx_size_1(uint32_t vtx_fmt_1) |
||
| 85 | { |
||
| 86 | int vtx_size, i, tex_size; |
||
| 87 | vtx_size = 0; |
||
| 88 | for (i = 0; i < 6; i++) { |
||
| 89 | tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7; |
||
| 90 | if (tex_size > 4) |
||
| 91 | continue; |
||
| 92 | vtx_size += tex_size; |
||
| 93 | } |
||
| 94 | return vtx_size; |
||
| 95 | } |
||
| 96 | |||
| 97 | int r200_packet0_check(struct radeon_cs_parser *p, |
||
| 98 | struct radeon_cs_packet *pkt, |
||
| 99 | unsigned idx, unsigned reg) |
||
| 100 | { |
||
| 101 | struct radeon_cs_reloc *reloc; |
||
| 102 | struct r100_cs_track *track; |
||
| 103 | volatile uint32_t *ib; |
||
| 104 | uint32_t tmp; |
||
| 105 | int r; |
||
| 106 | int i; |
||
| 107 | int face; |
||
| 108 | u32 tile_flags = 0; |
||
| 1221 | serge | 109 | u32 idx_value; |
| 1179 | serge | 110 | |
| 111 | ib = p->ib->ptr; |
||
| 112 | track = (struct r100_cs_track *)p->track; |
||
| 1221 | serge | 113 | idx_value = radeon_get_ib_value(p, idx); |
| 1179 | serge | 114 | switch (reg) { |
| 115 | case RADEON_CRTC_GUI_TRIG_VLINE: |
||
| 116 | r = r100_cs_packet_parse_vline(p); |
||
| 117 | if (r) { |
||
| 118 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
| 119 | idx, reg); |
||
| 120 | r100_cs_dump_packet(p, pkt); |
||
| 121 | return r; |
||
| 122 | } |
||
| 123 | break; |
||
| 124 | /* FIXME: only allow PACKET3 blit? easier to check for out of |
||
| 125 | * range access */ |
||
| 126 | case RADEON_DST_PITCH_OFFSET: |
||
| 127 | case RADEON_SRC_PITCH_OFFSET: |
||
| 128 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
||
| 129 | if (r) |
||
| 130 | return r; |
||
| 131 | break; |
||
| 132 | case RADEON_RB3D_DEPTHOFFSET: |
||
| 133 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
| 134 | if (r) { |
||
| 135 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
| 136 | idx, reg); |
||
| 137 | r100_cs_dump_packet(p, pkt); |
||
| 138 | return r; |
||
| 139 | } |
||
| 140 | track->zb.robj = reloc->robj; |
||
| 1221 | serge | 141 | track->zb.offset = idx_value; |
| 142 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
||
| 1179 | serge | 143 | break; |
| 144 | case RADEON_RB3D_COLOROFFSET: |
||
| 145 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
| 146 | if (r) { |
||
| 147 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
| 148 | idx, reg); |
||
| 149 | r100_cs_dump_packet(p, pkt); |
||
| 150 | return r; |
||
| 151 | } |
||
| 152 | track->cb[0].robj = reloc->robj; |
||
| 1221 | serge | 153 | track->cb[0].offset = idx_value; |
| 154 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
||
| 1179 | serge | 155 | break; |
| 156 | case R200_PP_TXOFFSET_0: |
||
| 157 | case R200_PP_TXOFFSET_1: |
||
| 158 | case R200_PP_TXOFFSET_2: |
||
| 159 | case R200_PP_TXOFFSET_3: |
||
| 160 | case R200_PP_TXOFFSET_4: |
||
| 161 | case R200_PP_TXOFFSET_5: |
||
| 162 | i = (reg - R200_PP_TXOFFSET_0) / 24; |
||
| 163 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
| 164 | if (r) { |
||
| 165 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
| 166 | idx, reg); |
||
| 167 | r100_cs_dump_packet(p, pkt); |
||
| 168 | return r; |
||
| 169 | } |
||
| 1221 | serge | 170 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| 1179 | serge | 171 | track->textures[i].robj = reloc->robj; |
| 172 | break; |
||
| 173 | case R200_PP_CUBIC_OFFSET_F1_0: |
||
| 174 | case R200_PP_CUBIC_OFFSET_F2_0: |
||
| 175 | case R200_PP_CUBIC_OFFSET_F3_0: |
||
| 176 | case R200_PP_CUBIC_OFFSET_F4_0: |
||
| 177 | case R200_PP_CUBIC_OFFSET_F5_0: |
||
| 178 | case R200_PP_CUBIC_OFFSET_F1_1: |
||
| 179 | case R200_PP_CUBIC_OFFSET_F2_1: |
||
| 180 | case R200_PP_CUBIC_OFFSET_F3_1: |
||
| 181 | case R200_PP_CUBIC_OFFSET_F4_1: |
||
| 182 | case R200_PP_CUBIC_OFFSET_F5_1: |
||
| 183 | case R200_PP_CUBIC_OFFSET_F1_2: |
||
| 184 | case R200_PP_CUBIC_OFFSET_F2_2: |
||
| 185 | case R200_PP_CUBIC_OFFSET_F3_2: |
||
| 186 | case R200_PP_CUBIC_OFFSET_F4_2: |
||
| 187 | case R200_PP_CUBIC_OFFSET_F5_2: |
||
| 188 | case R200_PP_CUBIC_OFFSET_F1_3: |
||
| 189 | case R200_PP_CUBIC_OFFSET_F2_3: |
||
| 190 | case R200_PP_CUBIC_OFFSET_F3_3: |
||
| 191 | case R200_PP_CUBIC_OFFSET_F4_3: |
||
| 192 | case R200_PP_CUBIC_OFFSET_F5_3: |
||
| 193 | case R200_PP_CUBIC_OFFSET_F1_4: |
||
| 194 | case R200_PP_CUBIC_OFFSET_F2_4: |
||
| 195 | case R200_PP_CUBIC_OFFSET_F3_4: |
||
| 196 | case R200_PP_CUBIC_OFFSET_F4_4: |
||
| 197 | case R200_PP_CUBIC_OFFSET_F5_4: |
||
| 198 | case R200_PP_CUBIC_OFFSET_F1_5: |
||
| 199 | case R200_PP_CUBIC_OFFSET_F2_5: |
||
| 200 | case R200_PP_CUBIC_OFFSET_F3_5: |
||
| 201 | case R200_PP_CUBIC_OFFSET_F4_5: |
||
| 202 | case R200_PP_CUBIC_OFFSET_F5_5: |
||
| 203 | i = (reg - R200_PP_TXOFFSET_0) / 24; |
||
| 204 | face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4; |
||
| 205 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
| 206 | if (r) { |
||
| 207 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
| 208 | idx, reg); |
||
| 209 | r100_cs_dump_packet(p, pkt); |
||
| 210 | return r; |
||
| 211 | } |
||
| 1221 | serge | 212 | track->textures[i].cube_info[face - 1].offset = idx_value; |
| 213 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
||
| 1179 | serge | 214 | track->textures[i].cube_info[face - 1].robj = reloc->robj; |
| 215 | break; |
||
| 216 | case RADEON_RE_WIDTH_HEIGHT: |
||
| 1221 | serge | 217 | track->maxy = ((idx_value >> 16) & 0x7FF); |
| 1179 | serge | 218 | break; |
| 219 | case RADEON_RB3D_COLORPITCH: |
||
| 220 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
| 221 | if (r) { |
||
| 222 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
| 223 | idx, reg); |
||
| 224 | r100_cs_dump_packet(p, pkt); |
||
| 225 | return r; |
||
| 226 | } |
||
| 227 | |||
| 228 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
||
| 229 | tile_flags |= RADEON_COLOR_TILE_ENABLE; |
||
| 230 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
||
| 231 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
||
| 232 | |||
| 1221 | serge | 233 | tmp = idx_value & ~(0x7 << 16); |
| 1179 | serge | 234 | tmp |= tile_flags; |
| 235 | ib[idx] = tmp; |
||
| 236 | |||
| 1221 | serge | 237 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
| 1179 | serge | 238 | break; |
| 239 | case RADEON_RB3D_DEPTHPITCH: |
||
| 1221 | serge | 240 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
| 1179 | serge | 241 | break; |
| 242 | case RADEON_RB3D_CNTL: |
||
| 1221 | serge | 243 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
| 1179 | serge | 244 | case 7: |
| 245 | case 8: |
||
| 246 | case 9: |
||
| 247 | case 11: |
||
| 248 | case 12: |
||
| 249 | track->cb[0].cpp = 1; |
||
| 250 | break; |
||
| 251 | case 3: |
||
| 252 | case 4: |
||
| 253 | case 15: |
||
| 254 | track->cb[0].cpp = 2; |
||
| 255 | break; |
||
| 256 | case 6: |
||
| 257 | track->cb[0].cpp = 4; |
||
| 258 | break; |
||
| 259 | default: |
||
| 260 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
||
| 1221 | serge | 261 | ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
| 1179 | serge | 262 | return -EINVAL; |
| 263 | } |
||
| 1221 | serge | 264 | if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) { |
| 1179 | serge | 265 | DRM_ERROR("No support for depth xy offset in kms\n"); |
| 266 | return -EINVAL; |
||
| 267 | } |
||
| 268 | |||
| 1221 | serge | 269 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
| 1179 | serge | 270 | break; |
| 271 | case RADEON_RB3D_ZSTENCILCNTL: |
||
| 1221 | serge | 272 | switch (idx_value & 0xf) { |
| 1179 | serge | 273 | case 0: |
| 274 | track->zb.cpp = 2; |
||
| 275 | break; |
||
| 276 | case 2: |
||
| 277 | case 3: |
||
| 278 | case 4: |
||
| 279 | case 5: |
||
| 280 | case 9: |
||
| 281 | case 11: |
||
| 282 | track->zb.cpp = 4; |
||
| 283 | break; |
||
| 284 | default: |
||
| 285 | break; |
||
| 286 | } |
||
| 287 | break; |
||
| 288 | case RADEON_RB3D_ZPASS_ADDR: |
||
| 289 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
| 290 | if (r) { |
||
| 291 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
| 292 | idx, reg); |
||
| 293 | r100_cs_dump_packet(p, pkt); |
||
| 294 | return r; |
||
| 295 | } |
||
| 1221 | serge | 296 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| 1179 | serge | 297 | break; |
| 298 | case RADEON_PP_CNTL: |
||
| 299 | { |
||
| 1221 | serge | 300 | uint32_t temp = idx_value >> 4; |
| 1179 | serge | 301 | for (i = 0; i < track->num_texture; i++) |
| 302 | track->textures[i].enabled = !!(temp & (1 << i)); |
||
| 303 | } |
||
| 304 | break; |
||
| 305 | case RADEON_SE_VF_CNTL: |
||
| 1221 | serge | 306 | track->vap_vf_cntl = idx_value; |
| 1179 | serge | 307 | break; |
| 308 | case 0x210c: |
||
| 309 | /* VAP_VF_MAX_VTX_INDX */ |
||
| 1221 | serge | 310 | track->max_indx = idx_value & 0x00FFFFFFUL; |
| 1179 | serge | 311 | break; |
| 312 | case R200_SE_VTX_FMT_0: |
||
| 1221 | serge | 313 | track->vtx_size = r200_get_vtx_size_0(idx_value); |
| 1179 | serge | 314 | break; |
| 315 | case R200_SE_VTX_FMT_1: |
||
| 1221 | serge | 316 | track->vtx_size += r200_get_vtx_size_1(idx_value); |
| 1179 | serge | 317 | break; |
| 318 | case R200_PP_TXSIZE_0: |
||
| 319 | case R200_PP_TXSIZE_1: |
||
| 320 | case R200_PP_TXSIZE_2: |
||
| 321 | case R200_PP_TXSIZE_3: |
||
| 322 | case R200_PP_TXSIZE_4: |
||
| 323 | case R200_PP_TXSIZE_5: |
||
| 324 | i = (reg - R200_PP_TXSIZE_0) / 32; |
||
| 1221 | serge | 325 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
| 326 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
||
| 1179 | serge | 327 | break; |
| 328 | case R200_PP_TXPITCH_0: |
||
| 329 | case R200_PP_TXPITCH_1: |
||
| 330 | case R200_PP_TXPITCH_2: |
||
| 331 | case R200_PP_TXPITCH_3: |
||
| 332 | case R200_PP_TXPITCH_4: |
||
| 333 | case R200_PP_TXPITCH_5: |
||
| 334 | i = (reg - R200_PP_TXPITCH_0) / 32; |
||
| 1221 | serge | 335 | track->textures[i].pitch = idx_value + 32; |
| 1179 | serge | 336 | break; |
| 337 | case R200_PP_TXFILTER_0: |
||
| 338 | case R200_PP_TXFILTER_1: |
||
| 339 | case R200_PP_TXFILTER_2: |
||
| 340 | case R200_PP_TXFILTER_3: |
||
| 341 | case R200_PP_TXFILTER_4: |
||
| 342 | case R200_PP_TXFILTER_5: |
||
| 343 | i = (reg - R200_PP_TXFILTER_0) / 32; |
||
| 1221 | serge | 344 | track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK) |
| 1179 | serge | 345 | >> R200_MAX_MIP_LEVEL_SHIFT); |
| 1221 | serge | 346 | tmp = (idx_value >> 23) & 0x7; |
| 1179 | serge | 347 | if (tmp == 2 || tmp == 6) |
| 348 | track->textures[i].roundup_w = false; |
||
| 1221 | serge | 349 | tmp = (idx_value >> 27) & 0x7; |
| 1179 | serge | 350 | if (tmp == 2 || tmp == 6) |
| 351 | track->textures[i].roundup_h = false; |
||
| 352 | break; |
||
| 353 | case R200_PP_TXMULTI_CTL_0: |
||
| 354 | case R200_PP_TXMULTI_CTL_1: |
||
| 355 | case R200_PP_TXMULTI_CTL_2: |
||
| 356 | case R200_PP_TXMULTI_CTL_3: |
||
| 357 | case R200_PP_TXMULTI_CTL_4: |
||
| 358 | case R200_PP_TXMULTI_CTL_5: |
||
| 359 | i = (reg - R200_PP_TXMULTI_CTL_0) / 32; |
||
| 360 | break; |
||
| 361 | case R200_PP_TXFORMAT_X_0: |
||
| 362 | case R200_PP_TXFORMAT_X_1: |
||
| 363 | case R200_PP_TXFORMAT_X_2: |
||
| 364 | case R200_PP_TXFORMAT_X_3: |
||
| 365 | case R200_PP_TXFORMAT_X_4: |
||
| 366 | case R200_PP_TXFORMAT_X_5: |
||
| 367 | i = (reg - R200_PP_TXFORMAT_X_0) / 32; |
||
| 1221 | serge | 368 | track->textures[i].txdepth = idx_value & 0x7; |
| 369 | tmp = (idx_value >> 16) & 0x3; |
||
| 1179 | serge | 370 | /* 2D, 3D, CUBE */ |
| 371 | switch (tmp) { |
||
| 372 | case 0: |
||
| 373 | case 5: |
||
| 374 | case 6: |
||
| 375 | case 7: |
||
| 1403 | serge | 376 | /* 1D/2D */ |
| 1179 | serge | 377 | track->textures[i].tex_coord_type = 0; |
| 378 | break; |
||
| 379 | case 1: |
||
| 1403 | serge | 380 | /* CUBE */ |
| 381 | track->textures[i].tex_coord_type = 2; |
||
| 1179 | serge | 382 | break; |
| 383 | case 2: |
||
| 1403 | serge | 384 | /* 3D */ |
| 385 | track->textures[i].tex_coord_type = 1; |
||
| 1179 | serge | 386 | break; |
| 387 | } |
||
| 388 | break; |
||
| 389 | case R200_PP_TXFORMAT_0: |
||
| 390 | case R200_PP_TXFORMAT_1: |
||
| 391 | case R200_PP_TXFORMAT_2: |
||
| 392 | case R200_PP_TXFORMAT_3: |
||
| 393 | case R200_PP_TXFORMAT_4: |
||
| 394 | case R200_PP_TXFORMAT_5: |
||
| 395 | i = (reg - R200_PP_TXFORMAT_0) / 32; |
||
| 1221 | serge | 396 | if (idx_value & R200_TXFORMAT_NON_POWER2) { |
| 1179 | serge | 397 | track->textures[i].use_pitch = 1; |
| 398 | } else { |
||
| 399 | track->textures[i].use_pitch = 0; |
||
| 1221 | serge | 400 | track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
| 401 | track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
||
| 1179 | serge | 402 | } |
| 1221 | serge | 403 | switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
| 1179 | serge | 404 | case R200_TXFORMAT_I8: |
| 405 | case R200_TXFORMAT_RGB332: |
||
| 406 | case R200_TXFORMAT_Y8: |
||
| 407 | track->textures[i].cpp = 1; |
||
| 408 | break; |
||
| 409 | case R200_TXFORMAT_AI88: |
||
| 410 | case R200_TXFORMAT_ARGB1555: |
||
| 411 | case R200_TXFORMAT_RGB565: |
||
| 412 | case R200_TXFORMAT_ARGB4444: |
||
| 413 | case R200_TXFORMAT_VYUY422: |
||
| 414 | case R200_TXFORMAT_YVYU422: |
||
| 415 | case R200_TXFORMAT_LDVDU655: |
||
| 416 | case R200_TXFORMAT_DVDU88: |
||
| 417 | case R200_TXFORMAT_AVYU4444: |
||
| 418 | track->textures[i].cpp = 2; |
||
| 419 | break; |
||
| 420 | case R200_TXFORMAT_ARGB8888: |
||
| 421 | case R200_TXFORMAT_RGBA8888: |
||
| 422 | case R200_TXFORMAT_ABGR8888: |
||
| 423 | case R200_TXFORMAT_BGR111110: |
||
| 424 | case R200_TXFORMAT_LDVDU8888: |
||
| 1403 | serge | 425 | track->textures[i].cpp = 4; |
| 426 | break; |
||
| 427 | case R200_TXFORMAT_DXT1: |
||
| 428 | track->textures[i].cpp = 1; |
||
| 429 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
||
| 430 | break; |
||
| 1179 | serge | 431 | case R200_TXFORMAT_DXT23: |
| 432 | case R200_TXFORMAT_DXT45: |
||
| 1403 | serge | 433 | track->textures[i].cpp = 1; |
| 434 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
||
| 1179 | serge | 435 | break; |
| 436 | } |
||
| 1221 | serge | 437 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
| 438 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
||
| 1179 | serge | 439 | break; |
| 440 | case R200_PP_CUBIC_FACES_0: |
||
| 441 | case R200_PP_CUBIC_FACES_1: |
||
| 442 | case R200_PP_CUBIC_FACES_2: |
||
| 443 | case R200_PP_CUBIC_FACES_3: |
||
| 444 | case R200_PP_CUBIC_FACES_4: |
||
| 445 | case R200_PP_CUBIC_FACES_5: |
||
| 1221 | serge | 446 | tmp = idx_value; |
| 1179 | serge | 447 | i = (reg - R200_PP_CUBIC_FACES_0) / 32; |
| 448 | for (face = 0; face < 4; face++) { |
||
| 449 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
||
| 450 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); |
||
| 451 | } |
||
| 452 | break; |
||
| 453 | default: |
||
| 454 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
||
| 455 | reg, idx); |
||
| 456 | return -EINVAL; |
||
| 457 | } |
||
| 458 | return 0; |
||
| 459 | } |
||
| 460 | #endif |
||
| 461 | |||
| 1221 | serge | 462 | void r200_set_safe_registers(struct radeon_device *rdev) |
| 1179 | serge | 463 | { |
| 464 | rdev->config.r100.reg_safe_bm = r200_reg_safe_bm; |
||
| 465 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm); |
||
| 466 | } |