WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r100.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1179	serge	28	#include
1963	serge	29	#include
2997	Serge	30	#include
		31	#include
1117	serge	32	#include "radeon_reg.h"
		33	#include "radeon.h"
1963	serge	34	#include "radeon_asic.h"
1179	serge	35	#include "r100d.h"
1221	serge	36	#include "rs100d.h"
		37	#include "rv200d.h"
		38	#include "rv250d.h"
1963	serge	39	#include "atom.h"
1117	serge	40
1221	serge	41	#include
2997	Serge	42	#include
1221	serge	43
1179	serge	44	#include "r100_reg_safe.h"
		45	#include "rn50_reg_safe.h"
1221	serge	46
		47	/* Firmware Names */
		48	#define FIRMWARE_R100 "radeon/R100_cp.bin"
		49	#define FIRMWARE_R200 "radeon/R200_cp.bin"
		50	#define FIRMWARE_R300 "radeon/R300_cp.bin"
		51	#define FIRMWARE_R420 "radeon/R420_cp.bin"
		52	#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
		53	#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
		54	#define FIRMWARE_R520 "radeon/R520_cp.bin"
		55
		56	MODULE_FIRMWARE(FIRMWARE_R100);
		57	MODULE_FIRMWARE(FIRMWARE_R200);
		58	MODULE_FIRMWARE(FIRMWARE_R300);
		59	MODULE_FIRMWARE(FIRMWARE_R420);
		60	MODULE_FIRMWARE(FIRMWARE_RS690);
		61	MODULE_FIRMWARE(FIRMWARE_RS600);
		62	MODULE_FIRMWARE(FIRMWARE_R520);
		63
5078	serge	64	#include "r100_track.h"
1221	serge	65
1117	serge	66	/* This files gather functions specifics to:
		67	* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
2997	Serge	68	* and others in some cases.
1117	serge	69	*/
		70
3764	Serge	71	static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
		72	{
		73	if (crtc == 0) {
		74	if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
		75	return true;
		76	else
		77	return false;
		78	} else {
		79	if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
		80	return true;
		81	else
		82	return false;
		83	}
		84	}
		85
		86	static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
		87	{
		88	u32 vline1, vline2;
		89
		90	if (crtc == 0) {
		91	vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
		92	vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
		93	} else {
		94	vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
		95	vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
		96	}
		97	if (vline1 != vline2)
		98	return true;
		99	else
		100	return false;
		101	}
		102
2997	Serge	103	/**
		104	* r100_wait_for_vblank - vblank wait asic callback.
		105	*
		106	* @rdev: radeon_device pointer
		107	* @crtc: crtc to wait for vblank on
		108	*
		109	* Wait for vblank on the requested crtc (r1xx-r4xx).
		110	*/
		111	void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
		112	{
3764	Serge	113	unsigned i = 0;
2997	Serge	114
		115	if (crtc >= rdev->num_crtc)
		116	return;
		117
		118	if (crtc == 0) {
3764	Serge	119	if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
		120	return;
		121	} else {
		122	if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
		123	return;
		124	}
		125
		126	/* depending on when we hit vblank, we may be close to active; if so,
		127	* wait for another frame.
		128	*/
		129	while (r100_is_in_vblank(rdev, crtc)) {
		130	if (i++ % 100 == 0) {
		131	if (!r100_is_counter_moving(rdev, crtc))
2997	Serge	132	break;
		133	}
		134	}
3764	Serge	135
		136	while (!r100_is_in_vblank(rdev, crtc)) {
		137	if (i++ % 100 == 0) {
		138	if (!r100_is_counter_moving(rdev, crtc))
2997	Serge	139	break;
		140	}
		141	}
		142	}
5078	serge	143
		144	/**
		145	* r100_page_flip - pageflip callback.
		146	*
		147	* @rdev: radeon_device pointer
		148	* @crtc_id: crtc to cleanup pageflip on
		149	* @crtc_base: new address of the crtc (GPU MC address)
		150	*
		151	* Does the actual pageflip (r1xx-r4xx).
		152	* During vblank we take the crtc lock and wait for the update_pending
		153	* bit to go high, when it does, we release the lock, and allow the
		154	* double buffered update to take place.
		155	*/
		156	void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
1963	serge	157	{
		158	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
		159	u32 tmp = ((u32)crtc_base) \| RADEON_CRTC_OFFSET__OFFSET_LOCK;
2997	Serge	160	int i;
1963	serge	161
		162	/* Lock the graphics update lock */
		163	/* update the scanout addresses */
		164	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
		165
		166	/* Wait for update_pending to go high. */
2997	Serge	167	for (i = 0; i < rdev->usec_timeout; i++) {
		168	if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
		169	break;
		170	udelay(1);
		171	}
1963	serge	172	DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
		173
		174	/* Unlock the lock, so double-buffering can take place inside vblank */
		175	tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
		176	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
		177
5078	serge	178	}
		179
		180	/**
		181	* r100_page_flip_pending - check if page flip is still pending
		182	*
		183	* @rdev: radeon_device pointer
		184	* @crtc_id: crtc to check
		185	*
		186	* Check if the last pagefilp is still pending (r1xx-r4xx).
		187	* Returns the current update pending status.
		188	*/
		189	bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
		190	{
		191	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
		192
1963	serge	193	/* Return current update_pending status: */
5078	serge	194	return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
		195	RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
1963	serge	196	}
5078	serge	197
		198	/**
		199	* r100_pm_get_dynpm_state - look up dynpm power state callback.
		200	*
		201	* @rdev: radeon_device pointer
		202	*
		203	* Look up the optimal power state based on the
		204	* current state of the GPU (r1xx-r5xx).
		205	* Used for dynpm only.
		206	*/
		207	void r100_pm_get_dynpm_state(struct radeon_device *rdev)
		208	{
		209	int i;
		210	rdev->pm.dynpm_can_upclock = true;
		211	rdev->pm.dynpm_can_downclock = true;
		212
		213	switch (rdev->pm.dynpm_planned_action) {
		214	case DYNPM_ACTION_MINIMUM:
		215	rdev->pm.requested_power_state_index = 0;
		216	rdev->pm.dynpm_can_downclock = false;
		217	break;
		218	case DYNPM_ACTION_DOWNCLOCK:
		219	if (rdev->pm.current_power_state_index == 0) {
		220	rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
		221	rdev->pm.dynpm_can_downclock = false;
		222	} else {
		223	if (rdev->pm.active_crtc_count > 1) {
		224	for (i = 0; i < rdev->pm.num_power_states; i++) {
		225	if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
		226	continue;
		227	else if (i >= rdev->pm.current_power_state_index) {
		228	rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
		229	break;
		230	} else {
		231	rdev->pm.requested_power_state_index = i;
		232	break;
		233	}
		234	}
		235	} else
		236	rdev->pm.requested_power_state_index =
		237	rdev->pm.current_power_state_index - 1;
		238	}
		239	/* don't use the power state if crtcs are active and no display flag is set */
		240	if ((rdev->pm.active_crtc_count > 0) &&
		241	(rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
		242	RADEON_PM_MODE_NO_DISPLAY)) {
		243	rdev->pm.requested_power_state_index++;
		244	}
		245	break;
		246	case DYNPM_ACTION_UPCLOCK:
		247	if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
		248	rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
		249	rdev->pm.dynpm_can_upclock = false;
		250	} else {
		251	if (rdev->pm.active_crtc_count > 1) {
		252	for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
		253	if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
		254	continue;
		255	else if (i <= rdev->pm.current_power_state_index) {
		256	rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
		257	break;
		258	} else {
		259	rdev->pm.requested_power_state_index = i;
		260	break;
		261	}
		262	}
		263	} else
		264	rdev->pm.requested_power_state_index =
		265	rdev->pm.current_power_state_index + 1;
		266	}
		267	break;
		268	case DYNPM_ACTION_DEFAULT:
		269	rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
		270	rdev->pm.dynpm_can_upclock = false;
		271	break;
		272	case DYNPM_ACTION_NONE:
		273	default:
		274	DRM_ERROR("Requested mode for not defined action\n");
		275	return;
		276	}
		277	/* only one clock mode per power state */
		278	rdev->pm.requested_clock_mode_index = 0;
		279
		280	DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
		281	rdev->pm.power_state[rdev->pm.requested_power_state_index].
		282	clock_info[rdev->pm.requested_clock_mode_index].sclk,
		283	rdev->pm.power_state[rdev->pm.requested_power_state_index].
		284	clock_info[rdev->pm.requested_clock_mode_index].mclk,
		285	rdev->pm.power_state[rdev->pm.requested_power_state_index].
		286	pcie_lanes);
		287	}
		288
		289	/**
		290	* r100_pm_init_profile - Initialize power profiles callback.
		291	*
		292	* @rdev: radeon_device pointer
		293	*
		294	* Initialize the power states used in profile mode
		295	* (r1xx-r3xx).
		296	* Used for profile mode only.
		297	*/
		298	void r100_pm_init_profile(struct radeon_device *rdev)
		299	{
		300	/* default */
		301	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
		302	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
		303	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
		304	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
		305	/* low sh */
		306	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
		307	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
		308	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
		309	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
		310	/* mid sh */
		311	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
		312	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
		313	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
		314	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
		315	/* high sh */
		316	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
		317	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
		318	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
		319	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
		320	/* low mh */
		321	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
		322	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
		323	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
		324	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
		325	/* mid mh */
		326	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
		327	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
		328	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
		329	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
		330	/* high mh */
		331	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
		332	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
		333	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
		334	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
		335	}
		336
		337	/**
		338	* r100_pm_misc - set additional pm hw parameters callback.
		339	*
		340	* @rdev: radeon_device pointer
		341	*
		342	* Set non-clock parameters associated with a power state
		343	* (voltage, pcie lanes, etc.) (r1xx-r4xx).
		344	*/
		345	void r100_pm_misc(struct radeon_device *rdev)
		346	{
		347	int requested_index = rdev->pm.requested_power_state_index;
		348	struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
		349	struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
		350	u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
		351
		352	if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
		353	if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
		354	tmp = RREG32(voltage->gpio.reg);
		355	if (voltage->active_high)
		356	tmp \|= voltage->gpio.mask;
		357	else
		358	tmp &= ~(voltage->gpio.mask);
		359	WREG32(voltage->gpio.reg, tmp);
		360	if (voltage->delay)
		361	udelay(voltage->delay);
		362	} else {
		363	tmp = RREG32(voltage->gpio.reg);
		364	if (voltage->active_high)
		365	tmp &= ~voltage->gpio.mask;
		366	else
		367	tmp \|= voltage->gpio.mask;
		368	WREG32(voltage->gpio.reg, tmp);
		369	if (voltage->delay)
		370	udelay(voltage->delay);
		371	}
		372	}
		373
		374	sclk_cntl = RREG32_PLL(SCLK_CNTL);
		375	sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
		376	sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
		377	sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
		378	sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
		379	if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
		380	sclk_more_cntl \|= REDUCED_SPEED_SCLK_EN;
		381	if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
		382	sclk_cntl2 \|= REDUCED_SPEED_SCLK_MODE;
		383	else
		384	sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
		385	if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
		386	sclk_cntl2 \|= REDUCED_SPEED_SCLK_SEL(0);
		387	else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
		388	sclk_cntl2 \|= REDUCED_SPEED_SCLK_SEL(2);
		389	} else
		390	sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
		391
		392	if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
		393	sclk_more_cntl \|= IO_CG_VOLTAGE_DROP;
		394	if (voltage->delay) {
		395	sclk_more_cntl \|= VOLTAGE_DROP_SYNC;
		396	switch (voltage->delay) {
		397	case 33:
		398	sclk_more_cntl \|= VOLTAGE_DELAY_SEL(0);
		399	break;
		400	case 66:
		401	sclk_more_cntl \|= VOLTAGE_DELAY_SEL(1);
		402	break;
		403	case 99:
		404	sclk_more_cntl \|= VOLTAGE_DELAY_SEL(2);
		405	break;
		406	case 132:
		407	sclk_more_cntl \|= VOLTAGE_DELAY_SEL(3);
		408	break;
		409	}
		410	} else
		411	sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
		412	} else
		413	sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
		414
		415	if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
		416	sclk_cntl &= ~FORCE_HDP;
		417	else
		418	sclk_cntl \|= FORCE_HDP;
		419
		420	WREG32_PLL(SCLK_CNTL, sclk_cntl);
		421	WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
		422	WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
		423
		424	/* set pcie lanes */
		425	if ((rdev->flags & RADEON_IS_PCIE) &&
		426	!(rdev->flags & RADEON_IS_IGP) &&
		427	rdev->asic->pm.set_pcie_lanes &&
		428	(ps->pcie_lanes !=
		429	rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
		430	radeon_set_pcie_lanes(rdev,
		431	ps->pcie_lanes);
		432	DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
		433	}
		434	}
		435
		436	/**
		437	* r100_pm_prepare - pre-power state change callback.
		438	*
		439	* @rdev: radeon_device pointer
		440	*
		441	* Prepare for a power state change (r1xx-r4xx).
		442	*/
		443	void r100_pm_prepare(struct radeon_device *rdev)
		444	{
		445	struct drm_device *ddev = rdev->ddev;
		446	struct drm_crtc *crtc;
		447	struct radeon_crtc *radeon_crtc;
		448	u32 tmp;
		449
		450	/* disable any active CRTCs */
		451	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
		452	radeon_crtc = to_radeon_crtc(crtc);
		453	if (radeon_crtc->enabled) {
		454	if (radeon_crtc->crtc_id) {
		455	tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
		456	tmp \|= RADEON_CRTC2_DISP_REQ_EN_B;
		457	WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
		458	} else {
		459	tmp = RREG32(RADEON_CRTC_GEN_CNTL);
		460	tmp \|= RADEON_CRTC_DISP_REQ_EN_B;
		461	WREG32(RADEON_CRTC_GEN_CNTL, tmp);
		462	}
		463	}
		464	}
		465	}
		466
		467	/**
		468	* r100_pm_finish - post-power state change callback.
		469	*
		470	* @rdev: radeon_device pointer
		471	*
		472	* Clean up after a power state change (r1xx-r4xx).
		473	*/
		474	void r100_pm_finish(struct radeon_device *rdev)
		475	{
		476	struct drm_device *ddev = rdev->ddev;
		477	struct drm_crtc *crtc;
		478	struct radeon_crtc *radeon_crtc;
		479	u32 tmp;
		480
		481	/* enable any active CRTCs */
		482	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
		483	radeon_crtc = to_radeon_crtc(crtc);
		484	if (radeon_crtc->enabled) {
		485	if (radeon_crtc->crtc_id) {
		486	tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
		487	tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
		488	WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
		489	} else {
		490	tmp = RREG32(RADEON_CRTC_GEN_CNTL);
		491	tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
		492	WREG32(RADEON_CRTC_GEN_CNTL, tmp);
		493	}
		494	}
		495	}
		496	}
		497
		498	/**
		499	* r100_gui_idle - gui idle callback.
		500	*
		501	* @rdev: radeon_device pointer
		502	*
		503	* Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
		504	* Returns true if idle, false if not.
		505	*/
1963	serge	506	bool r100_gui_idle(struct radeon_device *rdev)
		507	{
		508	if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
		509	return false;
		510	else
		511	return true;
		512	}
		513
1321	serge	514	/* hpd for digital panel detect/disconnect */
2997	Serge	515	/**
		516	* r100_hpd_sense - hpd sense callback.
		517	*
		518	* @rdev: radeon_device pointer
		519	* @hpd: hpd (hotplug detect) pin
		520	*
		521	* Checks if a digital monitor is connected (r1xx-r4xx).
		522	* Returns true if connected, false if not connected.
		523	*/
1321	serge	524	bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
		525	{
		526	bool connected = false;
		527
		528	switch (hpd) {
		529	case RADEON_HPD_1:
		530	if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
		531	connected = true;
		532	break;
		533	case RADEON_HPD_2:
		534	if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
		535	connected = true;
		536	break;
		537	default:
		538	break;
		539	}
		540	return connected;
		541	}
		542
2997	Serge	543	/**
		544	* r100_hpd_set_polarity - hpd set polarity callback.
		545	*
		546	* @rdev: radeon_device pointer
		547	* @hpd: hpd (hotplug detect) pin
		548	*
		549	* Set the polarity of the hpd pin (r1xx-r4xx).
		550	*/
1321	serge	551	void r100_hpd_set_polarity(struct radeon_device *rdev,
		552	enum radeon_hpd_id hpd)
		553	{
		554	u32 tmp;
		555	bool connected = r100_hpd_sense(rdev, hpd);
		556
		557	switch (hpd) {
		558	case RADEON_HPD_1:
		559	tmp = RREG32(RADEON_FP_GEN_CNTL);
		560	if (connected)
		561	tmp &= ~RADEON_FP_DETECT_INT_POL;
		562	else
		563	tmp \|= RADEON_FP_DETECT_INT_POL;
		564	WREG32(RADEON_FP_GEN_CNTL, tmp);
		565	break;
		566	case RADEON_HPD_2:
		567	tmp = RREG32(RADEON_FP2_GEN_CNTL);
		568	if (connected)
		569	tmp &= ~RADEON_FP2_DETECT_INT_POL;
		570	else
		571	tmp \|= RADEON_FP2_DETECT_INT_POL;
		572	WREG32(RADEON_FP2_GEN_CNTL, tmp);
		573	break;
		574	default:
		575	break;
		576	}
		577	}
		578
2997	Serge	579	/**
		580	* r100_hpd_init - hpd setup callback.
		581	*
		582	* @rdev: radeon_device pointer
		583	*
		584	* Setup the hpd pins used by the card (r1xx-r4xx).
		585	* Set the polarity, and enable the hpd interrupts.
		586	*/
1321	serge	587	void r100_hpd_init(struct radeon_device *rdev)
		588	{
		589	struct drm_device *dev = rdev->ddev;
		590	struct drm_connector *connector;
2997	Serge	591	unsigned enable = 0;
1321	serge	592
		593	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		594	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2997	Serge	595	enable \|= 1 << radeon_connector->hpd.hpd;
		596	radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
1321	serge	597	}
2997	Serge	598	// radeon_irq_kms_enable_hpd(rdev, enable);
1321	serge	599	}
		600
2997	Serge	601	/**
		602	* r100_hpd_fini - hpd tear down callback.
		603	*
		604	* @rdev: radeon_device pointer
		605	*
		606	* Tear down the hpd pins used by the card (r1xx-r4xx).
		607	* Disable the hpd interrupts.
		608	*/
1321	serge	609	void r100_hpd_fini(struct radeon_device *rdev)
		610	{
		611	struct drm_device *dev = rdev->ddev;
		612	struct drm_connector *connector;
2997	Serge	613	unsigned disable = 0;
1321	serge	614
		615	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		616	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2997	Serge	617	disable \|= 1 << radeon_connector->hpd.hpd;
1321	serge	618	}
2997	Serge	619	// radeon_irq_kms_disable_hpd(rdev, disable);
1321	serge	620	}
		621
1117	serge	622	/*
		623	* PCI GART
		624	*/
		625	void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
		626	{
		627	/* TODO: can we do somethings here ? */
		628	/* It seems hw only cache one entry so we should discard this
		629	* entry otherwise if first GPU GART read hit this entry it
		630	* could end up in wrong address. */
		631	}
		632
1179	serge	633	int r100_pci_gart_init(struct radeon_device *rdev)
1117	serge	634	{
		635	int r;
		636
2997	Serge	637	if (rdev->gart.ptr) {
1963	serge	638	WARN(1, "R100 PCI GART already initialized\n");
1179	serge	639	return 0;
		640	}
1117	serge	641	/* Initialize common gart structure */
		642	r = radeon_gart_init(rdev);
1179	serge	643	if (r)
1117	serge	644	return r;
1268	serge	645	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
2997	Serge	646	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
		647	rdev->asic->gart.set_page = &r100_pci_gart_set_page;
1179	serge	648	return radeon_gart_table_ram_alloc(rdev);
		649	}
		650
		651	int r100_pci_gart_enable(struct radeon_device *rdev)
		652	{
		653	uint32_t tmp;
		654
1117	serge	655	/* discard memory request outside of configured range */
		656	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		657	WREG32(RADEON_AIC_CNTL, tmp);
		658	/* set address range for PCI address translate */
1430	serge	659	WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
		660	WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
1117	serge	661	/* set PCI GART page-table base address */
		662	WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
		663	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_PCIGART_TRANSLATE_EN;
		664	WREG32(RADEON_AIC_CNTL, tmp);
		665	r100_pci_gart_tlb_flush(rdev);
2997	Serge	666	DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
		667	(unsigned)(rdev->mc.gtt_size >> 20),
		668	(unsigned long long)rdev->gart.table_addr);
1117	serge	669	rdev->gart.ready = true;
		670	return 0;
		671	}
		672
		673	void r100_pci_gart_disable(struct radeon_device *rdev)
		674	{
		675	uint32_t tmp;
		676
		677	/* discard memory request outside of configured range */
		678	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		679	WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
		680	WREG32(RADEON_AIC_LO_ADDR, 0);
		681	WREG32(RADEON_AIC_HI_ADDR, 0);
		682	}
		683
5078	serge	684	void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
		685	uint64_t addr, uint32_t flags)
1117	serge	686	{
2997	Serge	687	u32 *gtt = rdev->gart.ptr;
		688	gtt[i] = cpu_to_le32(lower_32_bits(addr));
1117	serge	689	}
		690
1179	serge	691	void r100_pci_gart_fini(struct radeon_device *rdev)
1117	serge	692	{
1963	serge	693	radeon_gart_fini(rdev);
1117	serge	694	r100_pci_gart_disable(rdev);
1179	serge	695	radeon_gart_table_ram_free(rdev);
1117	serge	696	}
		697
2005	serge	698	int r100_irq_set(struct radeon_device *rdev)
		699	{
		700	uint32_t tmp = 0;
1117	serge	701
2005	serge	702	if (!rdev->irq.installed) {
		703	WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
		704	WREG32(R_000040_GEN_INT_CNTL, 0);
		705	return -EINVAL;
		706	}
2997	Serge	707	if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2005	serge	708	tmp \|= RADEON_SW_INT_ENABLE;
		709	}
		710	if (rdev->irq.crtc_vblank_int[0] \|\|
2997	Serge	711	atomic_read(&rdev->irq.pflip[0])) {
2005	serge	712	tmp \|= RADEON_CRTC_VBLANK_MASK;
		713	}
		714	if (rdev->irq.crtc_vblank_int[1] \|\|
2997	Serge	715	atomic_read(&rdev->irq.pflip[1])) {
2005	serge	716	tmp \|= RADEON_CRTC2_VBLANK_MASK;
		717	}
		718	if (rdev->irq.hpd[0]) {
		719	tmp \|= RADEON_FP_DETECT_MASK;
		720	}
		721	if (rdev->irq.hpd[1]) {
		722	tmp \|= RADEON_FP2_DETECT_MASK;
		723	}
		724	WREG32(RADEON_GEN_INT_CNTL, tmp);
		725	return 0;
		726	}
		727
1221	serge	728	void r100_irq_disable(struct radeon_device *rdev)
1117	serge	729	{
1221	serge	730	u32 tmp;
1117	serge	731
1221	serge	732	WREG32(R_000040_GEN_INT_CNTL, 0);
		733	/* Wait and acknowledge irq */
		734	mdelay(1);
		735	tmp = RREG32(R_000044_GEN_INT_STATUS);
		736	WREG32(R_000044_GEN_INT_STATUS, tmp);
1117	serge	737	}
		738
2997	Serge	739	static uint32_t r100_irq_ack(struct radeon_device *rdev)
1117	serge	740	{
1221	serge	741	uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
1321	serge	742	uint32_t irq_mask = RADEON_SW_INT_TEST \|
		743	RADEON_CRTC_VBLANK_STAT \| RADEON_CRTC2_VBLANK_STAT \|
		744	RADEON_FP_DETECT_STAT \| RADEON_FP2_DETECT_STAT;
1117	serge	745
1221	serge	746	if (irqs) {
		747	WREG32(RADEON_GEN_INT_STATUS, irqs);
1129	serge	748	}
1221	serge	749	return irqs & irq_mask;
1117	serge	750	}
		751
2005	serge	752	int r100_irq_process(struct radeon_device *rdev)
		753	{
		754	uint32_t status, msi_rearm;
		755	bool queue_hotplug = false;
1117	serge	756
2005	serge	757	status = r100_irq_ack(rdev);
		758	if (!status) {
		759	return IRQ_NONE;
		760	}
		761	if (rdev->shutdown) {
		762	return IRQ_NONE;
		763	}
		764	while (status) {
		765	/* SW interrupt */
		766	if (status & RADEON_SW_INT_TEST) {
2997	Serge	767	radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
2005	serge	768	}
		769	/* Vertical blank interrupts */
		770	if (status & RADEON_CRTC_VBLANK_STAT) {
		771	if (rdev->irq.crtc_vblank_int[0]) {
		772	// drm_handle_vblank(rdev->ddev, 0);
		773	rdev->pm.vblank_sync = true;
		774	// wake_up(&rdev->irq.vblank_queue);
		775	}
		776	// if (rdev->irq.pflip[0])
		777	// radeon_crtc_handle_flip(rdev, 0);
		778	}
		779	if (status & RADEON_CRTC2_VBLANK_STAT) {
		780	if (rdev->irq.crtc_vblank_int[1]) {
		781	// drm_handle_vblank(rdev->ddev, 1);
		782	rdev->pm.vblank_sync = true;
		783	// wake_up(&rdev->irq.vblank_queue);
		784	}
		785	// if (rdev->irq.pflip[1])
		786	// radeon_crtc_handle_flip(rdev, 1);
		787	}
		788	if (status & RADEON_FP_DETECT_STAT) {
		789	queue_hotplug = true;
		790	DRM_DEBUG("HPD1\n");
		791	}
		792	if (status & RADEON_FP2_DETECT_STAT) {
		793	queue_hotplug = true;
		794	DRM_DEBUG("HPD2\n");
		795	}
		796	status = r100_irq_ack(rdev);
		797	}
		798	// if (queue_hotplug)
		799	// schedule_work(&rdev->hotplug_work);
		800	if (rdev->msi_enabled) {
		801	switch (rdev->family) {
		802	case CHIP_RS400:
		803	case CHIP_RS480:
		804	msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
		805	WREG32(RADEON_AIC_CNTL, msi_rearm);
		806	WREG32(RADEON_AIC_CNTL, msi_rearm \| RS400_MSI_REARM);
		807	break;
		808	default:
2997	Serge	809	WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
2005	serge	810	break;
		811	}
		812	}
		813	return IRQ_HANDLED;
		814	}
		815
1403	serge	816	u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
		817	{
		818	if (crtc == 0)
		819	return RREG32(RADEON_CRTC_CRNT_FRAME);
		820	else
		821	return RREG32(RADEON_CRTC2_CRNT_FRAME);
		822	}
1117	serge	823
1404	serge	824	/* Who ever call radeon_fence_emit should call ring_lock and ask
		825	* for enough space (today caller are ib schedule and buffer move) */
1117	serge	826	void r100_fence_ring_emit(struct radeon_device *rdev,
		827	struct radeon_fence *fence)
		828	{
2997	Serge	829	struct radeon_ring *ring = &rdev->ring[fence->ring];
		830
1404	serge	831	/* We have to make sure that caches are flushed before
		832	* CPU might read something from VRAM. */
2997	Serge	833	radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
		834	radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
		835	radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
		836	radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
1117	serge	837	/* Wait until IDLE & CLEAN */
2997	Serge	838	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
		839	radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN \| RADEON_WAIT_3D_IDLECLEAN);
5078	serge	840	r100_ring_hdp_flush(rdev, ring);
1117	serge	841	/* Emit fence sequence & fire IRQ */
2997	Serge	842	radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
		843	radeon_ring_write(ring, fence->seq);
		844	radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
		845	radeon_ring_write(ring, RADEON_SW_INT_FIRE);
1117	serge	846	}
		847
5078	serge	848	bool r100_semaphore_ring_emit(struct radeon_device *rdev,
2997	Serge	849	struct radeon_ring *ring,
		850	struct radeon_semaphore *semaphore,
		851	bool emit_wait)
		852	{
		853	/* Unused on older asics, since we don't have semaphores or multiple rings */
		854	BUG();
5078	serge	855	return false;
2997	Serge	856	}
		857
1117	serge	858	int r100_copy_blit(struct radeon_device *rdev,
		859	uint64_t src_offset,
		860	uint64_t dst_offset,
2997	Serge	861	unsigned num_gpu_pages,
		862	struct radeon_fence **fence)
1117	serge	863	{
2997	Serge	864	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1117	serge	865	uint32_t cur_pages;
2997	Serge	866	uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
1117	serge	867	uint32_t pitch;
		868	uint32_t stride_pixels;
		869	unsigned ndw;
		870	int num_loops;
		871	int r = 0;
		872
		873	/* radeon limited to 16k stride */
		874	stride_bytes &= 0x3fff;
		875	/* radeon pitch is /64 */
		876	pitch = stride_bytes / 64;
		877	stride_pixels = stride_bytes / 4;
2997	Serge	878	num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
1117	serge	879
		880	/* Ask for enough room for blit + flush + fence */
		881	ndw = 64 + (10 * num_loops);
2997	Serge	882	r = radeon_ring_lock(rdev, ring, ndw);
1117	serge	883	if (r) {
		884	DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
		885	return -EINVAL;
		886	}
2997	Serge	887	while (num_gpu_pages > 0) {
		888	cur_pages = num_gpu_pages;
1117	serge	889	if (cur_pages > 8191) {
		890	cur_pages = 8191;
		891	}
2997	Serge	892	num_gpu_pages -= cur_pages;
1117	serge	893
		894	/* pages are in Y direction - height
		895	page width in X direction - width */
2997	Serge	896	radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
		897	radeon_ring_write(ring,
1117	serge	898	RADEON_GMC_SRC_PITCH_OFFSET_CNTL \|
		899	RADEON_GMC_DST_PITCH_OFFSET_CNTL \|
		900	RADEON_GMC_SRC_CLIPPING \|
		901	RADEON_GMC_DST_CLIPPING \|
		902	RADEON_GMC_BRUSH_NONE \|
		903	(RADEON_COLOR_FORMAT_ARGB8888 << 8) \|
		904	RADEON_GMC_SRC_DATATYPE_COLOR \|
		905	RADEON_ROP3_S \|
		906	RADEON_DP_SRC_SOURCE_MEMORY \|
		907	RADEON_GMC_CLR_CMP_CNTL_DIS \|
		908	RADEON_GMC_WR_MSK_DIS);
2997	Serge	909	radeon_ring_write(ring, (pitch << 22) \| (src_offset >> 10));
		910	radeon_ring_write(ring, (pitch << 22) \| (dst_offset >> 10));
		911	radeon_ring_write(ring, (0x1fff) \| (0x1fff << 16));
		912	radeon_ring_write(ring, 0);
		913	radeon_ring_write(ring, (0x1fff) \| (0x1fff << 16));
		914	radeon_ring_write(ring, num_gpu_pages);
		915	radeon_ring_write(ring, num_gpu_pages);
		916	radeon_ring_write(ring, cur_pages \| (stride_pixels << 16));
1117	serge	917	}
2997	Serge	918	radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
		919	radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
		920	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
		921	radeon_ring_write(ring,
1117	serge	922	RADEON_WAIT_2D_IDLECLEAN \|
		923	RADEON_WAIT_HOST_IDLECLEAN \|
		924	RADEON_WAIT_DMA_GUI_IDLE);
		925	if (fence) {
2997	Serge	926	r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
1117	serge	927	}
5078	serge	928	radeon_ring_unlock_commit(rdev, ring, false);
1117	serge	929	return r;
		930	}
		931
1179	serge	932	static int r100_cp_wait_for_idle(struct radeon_device *rdev)
		933	{
		934	unsigned i;
		935	u32 tmp;
		936
		937	for (i = 0; i < rdev->usec_timeout; i++) {
		938	tmp = RREG32(R_000E40_RBBM_STATUS);
		939	if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
		940	return 0;
		941	}
		942	udelay(1);
		943	}
		944	return -1;
		945	}
		946
2997	Serge	947	void r100_ring_start(struct radeon_device rdev, struct radeon_ring ring)
1117	serge	948	{
		949	int r;
		950
2997	Serge	951	r = radeon_ring_lock(rdev, ring, 2);
1117	serge	952	if (r) {
		953	return;
		954	}
2997	Serge	955	radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
		956	radeon_ring_write(ring,
1117	serge	957	RADEON_ISYNC_ANY2D_IDLE3D \|
		958	RADEON_ISYNC_ANY3D_IDLE2D \|
		959	RADEON_ISYNC_WAIT_IDLEGUI \|
		960	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
5078	serge	961	radeon_ring_unlock_commit(rdev, ring, false);
1117	serge	962	}
		963
1221	serge	964
		965	/* Load the microcode for the CP */
		966	static int r100_cp_init_microcode(struct radeon_device *rdev)
1117	serge	967	{
1221	serge	968	const char *fw_name = NULL;
		969	int err;
1117	serge	970
1963	serge	971	DRM_DEBUG_KMS("\n");
1117	serge	972
		973	if ((rdev->family == CHIP_R100) \|\| (rdev->family == CHIP_RV100) \|\|
		974	(rdev->family == CHIP_RV200) \|\| (rdev->family == CHIP_RS100) \|\|
		975	(rdev->family == CHIP_RS200)) {
		976	DRM_INFO("Loading R100 Microcode\n");
1221	serge	977	fw_name = FIRMWARE_R100;
1117	serge	978	} else if ((rdev->family == CHIP_R200) \|\|
		979	(rdev->family == CHIP_RV250) \|\|
		980	(rdev->family == CHIP_RV280) \|\|
		981	(rdev->family == CHIP_RS300)) {
		982	DRM_INFO("Loading R200 Microcode\n");
1221	serge	983	fw_name = FIRMWARE_R200;
1117	serge	984	} else if ((rdev->family == CHIP_R300) \|\|
		985	(rdev->family == CHIP_R350) \|\|
		986	(rdev->family == CHIP_RV350) \|\|
		987	(rdev->family == CHIP_RV380) \|\|
		988	(rdev->family == CHIP_RS400) \|\|
		989	(rdev->family == CHIP_RS480)) {
		990	DRM_INFO("Loading R300 Microcode\n");
1221	serge	991	fw_name = FIRMWARE_R300;
1117	serge	992	} else if ((rdev->family == CHIP_R420) \|\|
		993	(rdev->family == CHIP_R423) \|\|
		994	(rdev->family == CHIP_RV410)) {
		995	DRM_INFO("Loading R400 Microcode\n");
1221	serge	996	fw_name = FIRMWARE_R420;
1117	serge	997	} else if ((rdev->family == CHIP_RS690) \|\|
		998	(rdev->family == CHIP_RS740)) {
		999	DRM_INFO("Loading RS690/RS740 Microcode\n");
1221	serge	1000	fw_name = FIRMWARE_RS690;
1117	serge	1001	} else if (rdev->family == CHIP_RS600) {
		1002	DRM_INFO("Loading RS600 Microcode\n");
1221	serge	1003	fw_name = FIRMWARE_RS600;
1117	serge	1004	} else if ((rdev->family == CHIP_RV515) \|\|
		1005	(rdev->family == CHIP_R520) \|\|
		1006	(rdev->family == CHIP_RV530) \|\|
		1007	(rdev->family == CHIP_R580) \|\|
		1008	(rdev->family == CHIP_RV560) \|\|
		1009	(rdev->family == CHIP_RV570)) {
		1010	DRM_INFO("Loading R500 Microcode\n");
1221	serge	1011	fw_name = FIRMWARE_R520;
1117	serge	1012	}
1221	serge	1013
5078	serge	1014	err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1221	serge	1015	if (err) {
		1016	printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
		1017	fw_name);
		1018	} else if (rdev->me_fw->size % 8) {
		1019	printk(KERN_ERR
		1020	"radeon_cp: Bogus length %zu in firmware \"%s\"\n",
		1021	rdev->me_fw->size, fw_name);
		1022	err = -EINVAL;
		1023	release_firmware(rdev->me_fw);
		1024	rdev->me_fw = NULL;
1117	serge	1025	}
1221	serge	1026	return err;
1117	serge	1027	}
		1028
5078	serge	1029	u32 r100_gfx_get_rptr(struct radeon_device *rdev,
		1030	struct radeon_ring *ring)
		1031	{
		1032	u32 rptr;
		1033
		1034	if (rdev->wb.enabled)
		1035	rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
		1036	else
		1037	rptr = RREG32(RADEON_CP_RB_RPTR);
		1038
		1039	return rptr;
		1040	}
		1041
		1042	u32 r100_gfx_get_wptr(struct radeon_device *rdev,
		1043	struct radeon_ring *ring)
		1044	{
		1045	u32 wptr;
		1046
		1047	wptr = RREG32(RADEON_CP_RB_WPTR);
		1048
		1049	return wptr;
		1050	}
		1051
		1052	void r100_gfx_set_wptr(struct radeon_device *rdev,
		1053	struct radeon_ring *ring)
		1054	{
		1055	WREG32(RADEON_CP_RB_WPTR, ring->wptr);
		1056	(void)RREG32(RADEON_CP_RB_WPTR);
		1057	}
		1058
		1059	/**
		1060	* r100_ring_hdp_flush - flush Host Data Path via the ring buffer
		1061	* rdev: radeon device structure
		1062	* ring: ring buffer struct for emitting packets
		1063	*/
		1064	void r100_ring_hdp_flush(struct radeon_device rdev, struct radeon_ring ring)
		1065	{
		1066	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		1067	radeon_ring_write(ring, rdev->config.r100.hdp_cntl \|
		1068	RADEON_HDP_READ_BUFFER_INVALIDATE);
		1069	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		1070	radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
		1071	}
		1072
1221	serge	1073	static void r100_cp_load_microcode(struct radeon_device *rdev)
		1074	{
		1075	const __be32 *fw_data;
		1076	int i, size;
		1077
		1078	if (r100_gui_wait_for_idle(rdev)) {
		1079	printk(KERN_WARNING "Failed to wait GUI idle while "
		1080	"programming pipes. Bad things might happen.\n");
		1081	}
		1082
		1083	if (rdev->me_fw) {
		1084	size = rdev->me_fw->size / 4;
		1085	fw_data = (const __be32 *)&rdev->me_fw->data[0];
		1086	WREG32(RADEON_CP_ME_RAM_ADDR, 0);
		1087	for (i = 0; i < size; i += 2) {
		1088	WREG32(RADEON_CP_ME_RAM_DATAH,
		1089	be32_to_cpup(&fw_data[i]));
		1090	WREG32(RADEON_CP_ME_RAM_DATAL,
		1091	be32_to_cpup(&fw_data[i + 1]));
		1092	}
		1093	}
		1094	}
		1095
1117	serge	1096	int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
		1097	{
2997	Serge	1098	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1117	serge	1099	unsigned rb_bufsz;
		1100	unsigned rb_blksz;
		1101	unsigned max_fetch;
		1102	unsigned pre_write_timer;
		1103	unsigned pre_write_limit;
		1104	unsigned indirect2_start;
		1105	unsigned indirect1_start;
		1106	uint32_t tmp;
		1107	int r;
		1108
1129	serge	1109	if (r100_debugfs_cp_init(rdev)) {
		1110	DRM_ERROR("Failed to register debugfs file for CP !\n");
		1111	}
1179	serge	1112	if (!rdev->me_fw) {
		1113	r = r100_cp_init_microcode(rdev);
		1114	if (r) {
		1115	DRM_ERROR("Failed to load firmware!\n");
		1116	return r;
		1117	}
		1118	}
		1119
1117	serge	1120	/* Align ring size */
5078	serge	1121	rb_bufsz = order_base_2(ring_size / 8);
1117	serge	1122	ring_size = (1 << (rb_bufsz + 1)) * 4;
		1123	r100_cp_load_microcode(rdev);
2997	Serge	1124	r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
5078	serge	1125	RADEON_CP_PACKET2);
1117	serge	1126	if (r) {
		1127	return r;
		1128	}
		1129	/* Each time the cp read 1024 bytes (16 dword/quadword) update
		1130	* the rptr copy in system ram */
		1131	rb_blksz = 9;
		1132	/* cp will read 128bytes at a time (4 dwords) */
		1133	max_fetch = 1;
2997	Serge	1134	ring->align_mask = 16 - 1;
1117	serge	1135	/* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
		1136	pre_write_timer = 64;
		1137	/* Force CP_RB_WPTR write if written more than one time before the
		1138	* delay expire
		1139	*/
		1140	pre_write_limit = 0;
		1141	/* Setup the cp cache like this (cache size is 96 dwords) :
		1142	* RING 0 to 15
		1143	* INDIRECT1 16 to 79
		1144	* INDIRECT2 80 to 95
		1145	* So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		1146	* indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
		1147	* indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		1148	* Idea being that most of the gpu cmd will be through indirect1 buffer
		1149	* so it gets the bigger cache.
		1150	*/
		1151	indirect2_start = 80;
		1152	indirect1_start = 16;
		1153	/* cp setup */
		1154	WREG32(0x718, pre_write_timer \| (pre_write_limit << 28));
1268	serge	1155	tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) \|
1117	serge	1156	REG_SET(RADEON_RB_BLKSZ, rb_blksz) \|
1963	serge	1157	REG_SET(RADEON_MAX_FETCH, max_fetch));
1268	serge	1158	#ifdef __BIG_ENDIAN
		1159	tmp \|= RADEON_BUF_SWAP_32BIT;
		1160	#endif
1963	serge	1161	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_NO_UPDATE);
1268	serge	1162
1117	serge	1163	/* Set ring address */
2997	Serge	1164	DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
		1165	WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1117	serge	1166	/* Force read & write ptr to 0 */
1963	serge	1167	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA \| RADEON_RB_NO_UPDATE);
1117	serge	1168	WREG32(RADEON_CP_RB_RPTR_WR, 0);
2997	Serge	1169	ring->wptr = 0;
		1170	WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1963	serge	1171
		1172	/* set the wb address whether it's enabled or not */
		1173	WREG32(R_00070C_CP_RB_RPTR_ADDR,
		1174	S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
		1175	WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
		1176
		1177	if (rdev->wb.enabled)
		1178	WREG32(R_000770_SCRATCH_UMSK, 0xff);
		1179	else {
		1180	tmp \|= RADEON_RB_NO_UPDATE;
		1181	WREG32(R_000770_SCRATCH_UMSK, 0);
		1182	}
		1183
1117	serge	1184	WREG32(RADEON_CP_RB_CNTL, tmp);
		1185	udelay(10);
		1186	/* Set cp mode to bus mastering & enable cp*/
		1187	WREG32(RADEON_CP_CSQ_MODE,
		1188	REG_SET(RADEON_INDIRECT2_START, indirect2_start) \|
		1189	REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1963	serge	1190	WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
		1191	WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1117	serge	1192	WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
2997	Serge	1193	radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
		1194	r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1117	serge	1195	if (r) {
		1196	DRM_ERROR("radeon: cp isn't working (%d).\n", r);
		1197	return r;
		1198	}
2997	Serge	1199	ring->ready = true;
3192	Serge	1200	radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
		1201
		1202	if (!ring->rptr_save_reg /* not resuming from suspend */
		1203	&& radeon_ring_supports_scratch_reg(rdev, ring)) {
		1204	r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
		1205	if (r) {
		1206	DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
		1207	ring->rptr_save_reg = 0;
		1208	}
		1209	}
1117	serge	1210	return 0;
		1211	}
		1212
		1213	void r100_cp_fini(struct radeon_device *rdev)
		1214	{
1179	serge	1215	if (r100_cp_wait_for_idle(rdev)) {
		1216	DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
		1217	}
1117	serge	1218	/* Disable ring */
1179	serge	1219	r100_cp_disable(rdev);
3192	Serge	1220	radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
2997	Serge	1221	radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1117	serge	1222	DRM_INFO("radeon: cp finalized\n");
		1223	}
		1224
		1225	void r100_cp_disable(struct radeon_device *rdev)
		1226	{
		1227	/* Disable ring */
3192	Serge	1228	radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2997	Serge	1229	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1117	serge	1230	WREG32(RADEON_CP_CSQ_MODE, 0);
		1231	WREG32(RADEON_CP_CSQ_CNTL, 0);
1963	serge	1232	WREG32(R_000770_SCRATCH_UMSK, 0);
1117	serge	1233	if (r100_gui_wait_for_idle(rdev)) {
		1234	printk(KERN_WARNING "Failed to wait GUI idle while "
		1235	"programming pipes. Bad things might happen.\n");
		1236	}
		1237	}
		1238
2997	Serge	1239	/*
		1240	* CS functions
		1241	*/
		1242	int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
		1243	struct radeon_cs_packet *pkt,
		1244	unsigned idx,
		1245	unsigned reg)
1179	serge	1246	{
2997	Serge	1247	int r;
		1248	u32 tile_flags = 0;
		1249	u32 tmp;
		1250	struct radeon_cs_reloc *reloc;
		1251	u32 value;
		1252
3764	Serge	1253	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2997	Serge	1254	if (r) {
		1255	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1256	idx, reg);
3764	Serge	1257	radeon_cs_dump_packet(p, pkt);
2997	Serge	1258	return r;
		1259	}
		1260
		1261	value = radeon_get_ib_value(p, idx);
		1262	tmp = value & 0x003fffff;
5078	serge	1263	tmp += (((u32)reloc->gpu_offset) >> 10);
2997	Serge	1264
		1265	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
5078	serge	1266	if (reloc->tiling_flags & RADEON_TILING_MACRO)
2997	Serge	1267	tile_flags \|= RADEON_DST_TILE_MACRO;
5078	serge	1268	if (reloc->tiling_flags & RADEON_TILING_MICRO) {
2997	Serge	1269	if (reg == RADEON_SRC_PITCH_OFFSET) {
		1270	DRM_ERROR("Cannot src blit from microtiled surface\n");
3764	Serge	1271	radeon_cs_dump_packet(p, pkt);
2997	Serge	1272	return -EINVAL;
		1273	}
		1274	tile_flags \|= RADEON_DST_TILE_MICRO;
		1275	}
		1276
		1277	tmp \|= tile_flags;
		1278	p->ib.ptr[idx] = (value & 0x3fc00000) \| tmp;
		1279	} else
		1280	p->ib.ptr[idx] = (value & 0xffc00000) \| tmp;
		1281	return 0;
1179	serge	1282	}
		1283
2997	Serge	1284	int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
		1285	struct radeon_cs_packet *pkt,
		1286	int idx)
		1287	{
		1288	unsigned c, i;
		1289	struct radeon_cs_reloc *reloc;
		1290	struct r100_cs_track *track;
		1291	int r = 0;
		1292	volatile uint32_t *ib;
		1293	u32 idx_value;
1179	serge	1294
2997	Serge	1295	ib = p->ib.ptr;
		1296	track = (struct r100_cs_track *)p->track;
		1297	c = radeon_get_ib_value(p, idx++) & 0x1F;
		1298	if (c > 16) {
		1299	DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
		1300	pkt->opcode);
3764	Serge	1301	radeon_cs_dump_packet(p, pkt);
2997	Serge	1302	return -EINVAL;
		1303	}
		1304	track->num_arrays = c;
		1305	for (i = 0; i < (c - 1); i+=2, idx+=3) {
3764	Serge	1306	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2997	Serge	1307	if (r) {
		1308	DRM_ERROR("No reloc for packet3 %d\n",
		1309	pkt->opcode);
3764	Serge	1310	radeon_cs_dump_packet(p, pkt);
2997	Serge	1311	return r;
		1312	}
		1313	idx_value = radeon_get_ib_value(p, idx);
5078	serge	1314	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
2997	Serge	1315
		1316	track->arrays[i + 0].esize = idx_value >> 8;
		1317	track->arrays[i + 0].robj = reloc->robj;
		1318	track->arrays[i + 0].esize &= 0x7F;
3764	Serge	1319	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2997	Serge	1320	if (r) {
		1321	DRM_ERROR("No reloc for packet3 %d\n",
		1322	pkt->opcode);
3764	Serge	1323	radeon_cs_dump_packet(p, pkt);
2997	Serge	1324	return r;
		1325	}
5078	serge	1326	ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
2997	Serge	1327	track->arrays[i + 1].robj = reloc->robj;
		1328	track->arrays[i + 1].esize = idx_value >> 24;
		1329	track->arrays[i + 1].esize &= 0x7F;
		1330	}
		1331	if (c & 1) {
3764	Serge	1332	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2997	Serge	1333	if (r) {
		1334	DRM_ERROR("No reloc for packet3 %d\n",
		1335	pkt->opcode);
3764	Serge	1336	radeon_cs_dump_packet(p, pkt);
2997	Serge	1337	return r;
		1338	}
		1339	idx_value = radeon_get_ib_value(p, idx);
5078	serge	1340	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
2997	Serge	1341	track->arrays[i + 0].robj = reloc->robj;
		1342	track->arrays[i + 0].esize = idx_value >> 8;
		1343	track->arrays[i + 0].esize &= 0x7F;
		1344	}
		1345	return r;
		1346	}
		1347
1117	serge	1348	int r100_cs_parse_packet0(struct radeon_cs_parser *p,
		1349	struct radeon_cs_packet *pkt,
		1350	const unsigned *auth, unsigned n,
		1351	radeon_packet0_check_t check)
		1352	{
		1353	unsigned reg;
		1354	unsigned i, j, m;
		1355	unsigned idx;
		1356	int r;
		1357
		1358	idx = pkt->idx + 1;
		1359	reg = pkt->reg;
		1360	/* Check that register fall into register range
		1361	* determined by the number of entry (n) in the
		1362	* safe register bitmap.
		1363	*/
		1364	if (pkt->one_reg_wr) {
		1365	if ((reg >> 7) > n) {
		1366	return -EINVAL;
		1367	}
		1368	} else {
		1369	if (((reg + (pkt->count << 2)) >> 7) > n) {
		1370	return -EINVAL;
		1371	}
		1372	}
		1373	for (i = 0; i <= pkt->count; i++, idx++) {
		1374	j = (reg >> 7);
		1375	m = 1 << ((reg >> 2) & 31);
		1376	if (auth[j] & m) {
		1377	r = check(p, pkt, idx, reg);
		1378	if (r) {
		1379	return r;
		1380	}
		1381	}
		1382	if (pkt->one_reg_wr) {
		1383	if (!(auth[j] & m)) {
		1384	break;
		1385	}
		1386	} else {
		1387	reg += 4;
		1388	}
		1389	}
		1390	return 0;
		1391	}
		1392
		1393	/**
1179	serge	1394	* r100_cs_packet_next_vline() - parse userspace VLINE packet
		1395	* @parser: parser structure holding parsing context.
		1396	*
		1397	* Userspace sends a special sequence for VLINE waits.
		1398	* PACKET0 - VLINE_START_END + value
		1399	* PACKET0 - WAIT_UNTIL +_value
		1400	* RELOC (P3) - crtc_id in reloc.
		1401	*
		1402	* This function parses this and relocates the VLINE START END
		1403	* and WAIT UNTIL packets to the correct crtc.
		1404	* It also detects a switched off crtc and nulls out the
		1405	* wait in that case.
		1406	*/
		1407	int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
		1408	{
		1409	struct drm_crtc *crtc;
		1410	struct radeon_crtc *radeon_crtc;
		1411	struct radeon_cs_packet p3reloc, waitreloc;
		1412	int crtc_id;
		1413	int r;
		1414	uint32_t header, h_idx, reg;
1221	serge	1415	volatile uint32_t *ib;
1179	serge	1416
2997	Serge	1417	ib = p->ib.ptr;
1179	serge	1418
		1419	/* parse the wait until */
3764	Serge	1420	r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1179	serge	1421	if (r)
		1422	return r;
		1423
		1424	/* check its a wait until and only 1 count */
		1425	if (waitreloc.reg != RADEON_WAIT_UNTIL \|\|
		1426	waitreloc.count != 0) {
		1427	DRM_ERROR("vline wait had illegal wait until segment\n");
1963	serge	1428	return -EINVAL;
1179	serge	1429	}
		1430
1221	serge	1431	if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1179	serge	1432	DRM_ERROR("vline wait had illegal wait until\n");
1963	serge	1433	return -EINVAL;
1179	serge	1434	}
		1435
		1436	/* jump over the NOP */
3764	Serge	1437	r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1179	serge	1438	if (r)
		1439	return r;
		1440
		1441	h_idx = p->idx - 2;
1221	serge	1442	p->idx += waitreloc.count + 2;
		1443	p->idx += p3reloc.count + 2;
1179	serge	1444
1221	serge	1445	header = radeon_get_ib_value(p, h_idx);
		1446	crtc_id = radeon_get_ib_value(p, h_idx + 5);
3764	Serge	1447	reg = R100_CP_PACKET0_GET_REG(header);
5078	serge	1448	crtc = drm_crtc_find(p->rdev->ddev, crtc_id);
		1449	if (!crtc) {
1179	serge	1450	DRM_ERROR("cannot find crtc %d\n", crtc_id);
5078	serge	1451	return -ENOENT;
1179	serge	1452	}
		1453	radeon_crtc = to_radeon_crtc(crtc);
		1454	crtc_id = radeon_crtc->crtc_id;
		1455
		1456	if (!crtc->enabled) {
		1457	/* if the CRTC isn't enabled - we need to nop out the wait until */
1221	serge	1458	ib[h_idx + 2] = PACKET2(0);
		1459	ib[h_idx + 3] = PACKET2(0);
1179	serge	1460	} else if (crtc_id == 1) {
		1461	switch (reg) {
		1462	case AVIVO_D1MODE_VLINE_START_END:
1221	serge	1463	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	1464	header \|= AVIVO_D2MODE_VLINE_START_END >> 2;
		1465	break;
		1466	case RADEON_CRTC_GUI_TRIG_VLINE:
1221	serge	1467	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	1468	header \|= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
		1469	break;
		1470	default:
		1471	DRM_ERROR("unknown crtc reloc\n");
1963	serge	1472	return -EINVAL;
1179	serge	1473	}
1221	serge	1474	ib[h_idx] = header;
		1475	ib[h_idx + 3] \|= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1179	serge	1476	}
1963	serge	1477
		1478	return 0;
1179	serge	1479	}
		1480
		1481	static int r100_get_vtx_size(uint32_t vtx_fmt)
		1482	{
		1483	int vtx_size;
		1484	vtx_size = 2;
		1485	/* ordered according to bits in spec */
		1486	if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
		1487	vtx_size++;
		1488	if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
		1489	vtx_size += 3;
		1490	if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
		1491	vtx_size++;
		1492	if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
		1493	vtx_size++;
		1494	if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
		1495	vtx_size += 3;
		1496	if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
		1497	vtx_size++;
		1498	if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
		1499	vtx_size++;
		1500	if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
		1501	vtx_size += 2;
		1502	if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
		1503	vtx_size += 2;
		1504	if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
		1505	vtx_size++;
		1506	if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
		1507	vtx_size += 2;
		1508	if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
		1509	vtx_size++;
		1510	if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
		1511	vtx_size += 2;
		1512	if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
		1513	vtx_size++;
		1514	if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
		1515	vtx_size++;
		1516	/* blend weight */
		1517	if (vtx_fmt & (0x7 << 15))
		1518	vtx_size += (vtx_fmt >> 15) & 0x7;
		1519	if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
		1520	vtx_size += 3;
		1521	if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
		1522	vtx_size += 2;
		1523	if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
		1524	vtx_size++;
		1525	if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
		1526	vtx_size++;
		1527	if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
		1528	vtx_size++;
		1529	if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
		1530	vtx_size++;
		1531	return vtx_size;
		1532	}
		1533
1117	serge	1534	static int r100_packet0_check(struct radeon_cs_parser *p,
1179	serge	1535	struct radeon_cs_packet *pkt,
		1536	unsigned idx, unsigned reg)
1117	serge	1537	{
		1538	struct radeon_cs_reloc *reloc;
1179	serge	1539	struct r100_cs_track *track;
1117	serge	1540	volatile uint32_t *ib;
		1541	uint32_t tmp;
		1542	int r;
1179	serge	1543	int i, face;
		1544	u32 tile_flags = 0;
1221	serge	1545	u32 idx_value;
1117	serge	1546
2997	Serge	1547	ib = p->ib.ptr;
1179	serge	1548	track = (struct r100_cs_track *)p->track;
		1549
1221	serge	1550	idx_value = radeon_get_ib_value(p, idx);
		1551
1117	serge	1552	switch (reg) {
1179	serge	1553	case RADEON_CRTC_GUI_TRIG_VLINE:
		1554	r = r100_cs_packet_parse_vline(p);
		1555	if (r) {
		1556	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1557	idx, reg);
3764	Serge	1558	radeon_cs_dump_packet(p, pkt);
1179	serge	1559	return r;
		1560	}
		1561	break;
1117	serge	1562	/* FIXME: only allow PACKET3 blit? easier to check for out of
		1563	* range access */
		1564	case RADEON_DST_PITCH_OFFSET:
		1565	case RADEON_SRC_PITCH_OFFSET:
1179	serge	1566	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		1567	if (r)
		1568	return r;
		1569	break;
		1570	case RADEON_RB3D_DEPTHOFFSET:
3764	Serge	1571	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1117	serge	1572	if (r) {
		1573	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1574	idx, reg);
3764	Serge	1575	radeon_cs_dump_packet(p, pkt);
1117	serge	1576	return r;
		1577	}
1179	serge	1578	track->zb.robj = reloc->robj;
1221	serge	1579	track->zb.offset = idx_value;
1963	serge	1580	track->zb_dirty = true;
5078	serge	1581	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1117	serge	1582	break;
		1583	case RADEON_RB3D_COLOROFFSET:
3764	Serge	1584	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1179	serge	1585	if (r) {
		1586	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1587	idx, reg);
3764	Serge	1588	radeon_cs_dump_packet(p, pkt);
1179	serge	1589	return r;
		1590	}
		1591	track->cb[0].robj = reloc->robj;
1221	serge	1592	track->cb[0].offset = idx_value;
1963	serge	1593	track->cb_dirty = true;
5078	serge	1594	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1179	serge	1595	break;
1117	serge	1596	case RADEON_PP_TXOFFSET_0:
		1597	case RADEON_PP_TXOFFSET_1:
		1598	case RADEON_PP_TXOFFSET_2:
1179	serge	1599	i = (reg - RADEON_PP_TXOFFSET_0) / 24;
3764	Serge	1600	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1179	serge	1601	if (r) {
		1602	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1603	idx, reg);
3764	Serge	1604	radeon_cs_dump_packet(p, pkt);
1179	serge	1605	return r;
		1606	}
2997	Serge	1607	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
5078	serge	1608	if (reloc->tiling_flags & RADEON_TILING_MACRO)
2997	Serge	1609	tile_flags \|= RADEON_TXO_MACRO_TILE;
5078	serge	1610	if (reloc->tiling_flags & RADEON_TILING_MICRO)
2997	Serge	1611	tile_flags \|= RADEON_TXO_MICRO_TILE_X2;
		1612
		1613	tmp = idx_value & ~(0x7 << 2);
		1614	tmp \|= tile_flags;
5078	serge	1615	ib[idx] = tmp + ((u32)reloc->gpu_offset);
2997	Serge	1616	} else
5078	serge	1617	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1179	serge	1618	track->textures[i].robj = reloc->robj;
1963	serge	1619	track->tex_dirty = true;
1179	serge	1620	break;
		1621	case RADEON_PP_CUBIC_OFFSET_T0_0:
		1622	case RADEON_PP_CUBIC_OFFSET_T0_1:
		1623	case RADEON_PP_CUBIC_OFFSET_T0_2:
		1624	case RADEON_PP_CUBIC_OFFSET_T0_3:
		1625	case RADEON_PP_CUBIC_OFFSET_T0_4:
		1626	i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
3764	Serge	1627	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1179	serge	1628	if (r) {
		1629	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1630	idx, reg);
3764	Serge	1631	radeon_cs_dump_packet(p, pkt);
1179	serge	1632	return r;
		1633	}
1221	serge	1634	track->textures[0].cube_info[i].offset = idx_value;
5078	serge	1635	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1179	serge	1636	track->textures[0].cube_info[i].robj = reloc->robj;
1963	serge	1637	track->tex_dirty = true;
1179	serge	1638	break;
		1639	case RADEON_PP_CUBIC_OFFSET_T1_0:
		1640	case RADEON_PP_CUBIC_OFFSET_T1_1:
		1641	case RADEON_PP_CUBIC_OFFSET_T1_2:
		1642	case RADEON_PP_CUBIC_OFFSET_T1_3:
		1643	case RADEON_PP_CUBIC_OFFSET_T1_4:
		1644	i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
3764	Serge	1645	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1179	serge	1646	if (r) {
		1647	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1648	idx, reg);
3764	Serge	1649	radeon_cs_dump_packet(p, pkt);
1179	serge	1650	return r;
		1651	}
1221	serge	1652	track->textures[1].cube_info[i].offset = idx_value;
5078	serge	1653	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1179	serge	1654	track->textures[1].cube_info[i].robj = reloc->robj;
1963	serge	1655	track->tex_dirty = true;
1179	serge	1656	break;
		1657	case RADEON_PP_CUBIC_OFFSET_T2_0:
		1658	case RADEON_PP_CUBIC_OFFSET_T2_1:
		1659	case RADEON_PP_CUBIC_OFFSET_T2_2:
		1660	case RADEON_PP_CUBIC_OFFSET_T2_3:
		1661	case RADEON_PP_CUBIC_OFFSET_T2_4:
		1662	i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
3764	Serge	1663	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1117	serge	1664	if (r) {
		1665	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1666	idx, reg);
3764	Serge	1667	radeon_cs_dump_packet(p, pkt);
1117	serge	1668	return r;
		1669	}
1221	serge	1670	track->textures[2].cube_info[i].offset = idx_value;
5078	serge	1671	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1179	serge	1672	track->textures[2].cube_info[i].robj = reloc->robj;
1963	serge	1673	track->tex_dirty = true;
1179	serge	1674	break;
		1675	case RADEON_RE_WIDTH_HEIGHT:
1221	serge	1676	track->maxy = ((idx_value >> 16) & 0x7FF);
1963	serge	1677	track->cb_dirty = true;
		1678	track->zb_dirty = true;
1117	serge	1679	break;
1179	serge	1680	case RADEON_RB3D_COLORPITCH:
3764	Serge	1681	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1179	serge	1682	if (r) {
		1683	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1684	idx, reg);
3764	Serge	1685	radeon_cs_dump_packet(p, pkt);
1179	serge	1686	return r;
		1687	}
2997	Serge	1688	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
5078	serge	1689	if (reloc->tiling_flags & RADEON_TILING_MACRO)
1179	serge	1690	tile_flags \|= RADEON_COLOR_TILE_ENABLE;
5078	serge	1691	if (reloc->tiling_flags & RADEON_TILING_MICRO)
1179	serge	1692	tile_flags \|= RADEON_COLOR_MICROTILE_ENABLE;
		1693
1221	serge	1694	tmp = idx_value & ~(0x7 << 16);
1179	serge	1695	tmp \|= tile_flags;
		1696	ib[idx] = tmp;
2997	Serge	1697	} else
		1698	ib[idx] = idx_value;
1179	serge	1699
1221	serge	1700	track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1963	serge	1701	track->cb_dirty = true;
1179	serge	1702	break;
		1703	case RADEON_RB3D_DEPTHPITCH:
1221	serge	1704	track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1963	serge	1705	track->zb_dirty = true;
1179	serge	1706	break;
		1707	case RADEON_RB3D_CNTL:
1221	serge	1708	switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1179	serge	1709	case 7:
		1710	case 8:
		1711	case 9:
		1712	case 11:
		1713	case 12:
		1714	track->cb[0].cpp = 1;
		1715	break;
		1716	case 3:
		1717	case 4:
		1718	case 15:
		1719	track->cb[0].cpp = 2;
		1720	break;
		1721	case 6:
		1722	track->cb[0].cpp = 4;
		1723	break;
1117	serge	1724	default:
1179	serge	1725	DRM_ERROR("Invalid color buffer format (%d) !\n",
1221	serge	1726	((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1179	serge	1727	return -EINVAL;
		1728	}
1221	serge	1729	track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1963	serge	1730	track->cb_dirty = true;
		1731	track->zb_dirty = true;
1179	serge	1732	break;
		1733	case RADEON_RB3D_ZSTENCILCNTL:
1221	serge	1734	switch (idx_value & 0xf) {
1179	serge	1735	case 0:
		1736	track->zb.cpp = 2;
1117	serge	1737	break;
1179	serge	1738	case 2:
		1739	case 3:
		1740	case 4:
		1741	case 5:
		1742	case 9:
		1743	case 11:
		1744	track->zb.cpp = 4;
		1745	break;
		1746	default:
		1747	break;
1117	serge	1748	}
1963	serge	1749	track->zb_dirty = true;
1117	serge	1750	break;
1179	serge	1751	case RADEON_RB3D_ZPASS_ADDR:
3764	Serge	1752	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1179	serge	1753	if (r) {
		1754	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1755	idx, reg);
3764	Serge	1756	radeon_cs_dump_packet(p, pkt);
1179	serge	1757	return r;
		1758	}
5078	serge	1759	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1179	serge	1760	break;
		1761	case RADEON_PP_CNTL:
		1762	{
1221	serge	1763	uint32_t temp = idx_value >> 4;
1179	serge	1764	for (i = 0; i < track->num_texture; i++)
		1765	track->textures[i].enabled = !!(temp & (1 << i));
1963	serge	1766	track->tex_dirty = true;
1117	serge	1767	}
1179	serge	1768	break;
		1769	case RADEON_SE_VF_CNTL:
1221	serge	1770	track->vap_vf_cntl = idx_value;
1179	serge	1771	break;
		1772	case RADEON_SE_VTX_FMT:
1221	serge	1773	track->vtx_size = r100_get_vtx_size(idx_value);
1179	serge	1774	break;
		1775	case RADEON_PP_TEX_SIZE_0:
		1776	case RADEON_PP_TEX_SIZE_1:
		1777	case RADEON_PP_TEX_SIZE_2:
		1778	i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1221	serge	1779	track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
		1780	track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1963	serge	1781	track->tex_dirty = true;
1179	serge	1782	break;
		1783	case RADEON_PP_TEX_PITCH_0:
		1784	case RADEON_PP_TEX_PITCH_1:
		1785	case RADEON_PP_TEX_PITCH_2:
		1786	i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1221	serge	1787	track->textures[i].pitch = idx_value + 32;
1963	serge	1788	track->tex_dirty = true;
1179	serge	1789	break;
		1790	case RADEON_PP_TXFILTER_0:
		1791	case RADEON_PP_TXFILTER_1:
		1792	case RADEON_PP_TXFILTER_2:
		1793	i = (reg - RADEON_PP_TXFILTER_0) / 24;
1221	serge	1794	track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1179	serge	1795	>> RADEON_MAX_MIP_LEVEL_SHIFT);
1221	serge	1796	tmp = (idx_value >> 23) & 0x7;
1179	serge	1797	if (tmp == 2 \|\| tmp == 6)
		1798	track->textures[i].roundup_w = false;
1221	serge	1799	tmp = (idx_value >> 27) & 0x7;
1179	serge	1800	if (tmp == 2 \|\| tmp == 6)
		1801	track->textures[i].roundup_h = false;
1963	serge	1802	track->tex_dirty = true;
1179	serge	1803	break;
		1804	case RADEON_PP_TXFORMAT_0:
		1805	case RADEON_PP_TXFORMAT_1:
		1806	case RADEON_PP_TXFORMAT_2:
		1807	i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1221	serge	1808	if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1179	serge	1809	track->textures[i].use_pitch = 1;
		1810	} else {
		1811	track->textures[i].use_pitch = 0;
1221	serge	1812	track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
		1813	track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1179	serge	1814	}
1221	serge	1815	if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1179	serge	1816	track->textures[i].tex_coord_type = 2;
1221	serge	1817	switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1179	serge	1818	case RADEON_TXFORMAT_I8:
		1819	case RADEON_TXFORMAT_RGB332:
		1820	case RADEON_TXFORMAT_Y8:
		1821	track->textures[i].cpp = 1;
1963	serge	1822	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1823	break;
		1824	case RADEON_TXFORMAT_AI88:
		1825	case RADEON_TXFORMAT_ARGB1555:
		1826	case RADEON_TXFORMAT_RGB565:
		1827	case RADEON_TXFORMAT_ARGB4444:
		1828	case RADEON_TXFORMAT_VYUY422:
		1829	case RADEON_TXFORMAT_YVYU422:
		1830	case RADEON_TXFORMAT_SHADOW16:
		1831	case RADEON_TXFORMAT_LDUDV655:
		1832	case RADEON_TXFORMAT_DUDV88:
		1833	track->textures[i].cpp = 2;
1963	serge	1834	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1835	break;
		1836	case RADEON_TXFORMAT_ARGB8888:
		1837	case RADEON_TXFORMAT_RGBA8888:
		1838	case RADEON_TXFORMAT_SHADOW32:
		1839	case RADEON_TXFORMAT_LDUDUV8888:
		1840	track->textures[i].cpp = 4;
1963	serge	1841	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1842	break;
1403	serge	1843	case RADEON_TXFORMAT_DXT1:
		1844	track->textures[i].cpp = 1;
		1845	track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
		1846	break;
		1847	case RADEON_TXFORMAT_DXT23:
		1848	case RADEON_TXFORMAT_DXT45:
		1849	track->textures[i].cpp = 1;
		1850	track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
		1851	break;
1179	serge	1852	}
1221	serge	1853	track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
		1854	track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1963	serge	1855	track->tex_dirty = true;
1179	serge	1856	break;
		1857	case RADEON_PP_CUBIC_FACES_0:
		1858	case RADEON_PP_CUBIC_FACES_1:
		1859	case RADEON_PP_CUBIC_FACES_2:
1221	serge	1860	tmp = idx_value;
1179	serge	1861	i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
		1862	for (face = 0; face < 4; face++) {
		1863	track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
		1864	track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
		1865	}
1963	serge	1866	track->tex_dirty = true;
1179	serge	1867	break;
		1868	default:
		1869	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
		1870	reg, idx);
		1871	return -EINVAL;
1117	serge	1872	}
		1873	return 0;
		1874	}
		1875
		1876	int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
		1877	struct radeon_cs_packet *pkt,
1321	serge	1878	struct radeon_bo *robj)
1117	serge	1879	{
		1880	unsigned idx;
1221	serge	1881	u32 value;
1117	serge	1882	idx = pkt->idx + 1;
1221	serge	1883	value = radeon_get_ib_value(p, idx + 2);
1321	serge	1884	if ((value + 1) > radeon_bo_size(robj)) {
1117	serge	1885	DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
		1886	"(need %u have %lu) !\n",
1221	serge	1887	value + 1,
1321	serge	1888	radeon_bo_size(robj));
1117	serge	1889	return -EINVAL;
		1890	}
		1891	return 0;
		1892	}
		1893
		1894	static int r100_packet3_check(struct radeon_cs_parser *p,
		1895	struct radeon_cs_packet *pkt)
		1896	{
		1897	struct radeon_cs_reloc *reloc;
1179	serge	1898	struct r100_cs_track *track;
1117	serge	1899	unsigned idx;
		1900	volatile uint32_t *ib;
		1901	int r;
		1902
2997	Serge	1903	ib = p->ib.ptr;
1117	serge	1904	idx = pkt->idx + 1;
1179	serge	1905	track = (struct r100_cs_track *)p->track;
1117	serge	1906	switch (pkt->opcode) {
		1907	case PACKET3_3D_LOAD_VBPNTR:
1221	serge	1908	r = r100_packet3_load_vbpntr(p, pkt, idx);
		1909	if (r)
1117	serge	1910	return r;
		1911	break;
		1912	case PACKET3_INDX_BUFFER:
3764	Serge	1913	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1117	serge	1914	if (r) {
		1915	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
3764	Serge	1916	radeon_cs_dump_packet(p, pkt);
1117	serge	1917	return r;
		1918	}
5078	serge	1919	ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1117	serge	1920	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		1921	if (r) {
		1922	return r;
		1923	}
		1924	break;
		1925	case 0x23:
		1926	/* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
3764	Serge	1927	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1117	serge	1928	if (r) {
		1929	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
3764	Serge	1930	radeon_cs_dump_packet(p, pkt);
1117	serge	1931	return r;
		1932	}
5078	serge	1933	ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1179	serge	1934	track->num_arrays = 1;
1221	serge	1935	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1179	serge	1936
		1937	track->arrays[0].robj = reloc->robj;
		1938	track->arrays[0].esize = track->vtx_size;
		1939
1221	serge	1940	track->max_indx = radeon_get_ib_value(p, idx+1);
1179	serge	1941
1221	serge	1942	track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1179	serge	1943	track->immd_dwords = pkt->count - 1;
		1944	r = r100_cs_track_check(p->rdev, track);
		1945	if (r)
		1946	return r;
1117	serge	1947	break;
		1948	case PACKET3_3D_DRAW_IMMD:
1221	serge	1949	if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1179	serge	1950	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1951	return -EINVAL;
		1952	}
1403	serge	1953	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1221	serge	1954	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1955	track->immd_dwords = pkt->count - 1;
		1956	r = r100_cs_track_check(p->rdev, track);
		1957	if (r)
		1958	return r;
		1959	break;
1117	serge	1960	/* triggers drawing using in-packet vertex data */
		1961	case PACKET3_3D_DRAW_IMMD_2:
1221	serge	1962	if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1179	serge	1963	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1964	return -EINVAL;
		1965	}
1221	serge	1966	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1967	track->immd_dwords = pkt->count;
		1968	r = r100_cs_track_check(p->rdev, track);
		1969	if (r)
		1970	return r;
		1971	break;
1117	serge	1972	/* triggers drawing using in-packet vertex data */
		1973	case PACKET3_3D_DRAW_VBUF_2:
1221	serge	1974	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1975	r = r100_cs_track_check(p->rdev, track);
		1976	if (r)
		1977	return r;
		1978	break;
1117	serge	1979	/* triggers drawing of vertex buffers setup elsewhere */
		1980	case PACKET3_3D_DRAW_INDX_2:
1221	serge	1981	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1982	r = r100_cs_track_check(p->rdev, track);
		1983	if (r)
		1984	return r;
		1985	break;
1117	serge	1986	/* triggers drawing using indices to vertex buffer */
		1987	case PACKET3_3D_DRAW_VBUF:
1221	serge	1988	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1989	r = r100_cs_track_check(p->rdev, track);
		1990	if (r)
		1991	return r;
		1992	break;
1117	serge	1993	/* triggers drawing of vertex buffers setup elsewhere */
		1994	case PACKET3_3D_DRAW_INDX:
1221	serge	1995	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1996	r = r100_cs_track_check(p->rdev, track);
		1997	if (r)
		1998	return r;
		1999	break;
1117	serge	2000	/* triggers drawing using indices to vertex buffer */
1963	serge	2001	case PACKET3_3D_CLEAR_HIZ:
		2002	case PACKET3_3D_CLEAR_ZMASK:
		2003	if (p->rdev->hyperz_filp != p->filp)
		2004	return -EINVAL;
		2005	break;
1117	serge	2006	case PACKET3_NOP:
		2007	break;
		2008	default:
		2009	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		2010	return -EINVAL;
		2011	}
		2012	return 0;
		2013	}
		2014
		2015	int r100_cs_parse(struct radeon_cs_parser *p)
		2016	{
		2017	struct radeon_cs_packet pkt;
1179	serge	2018	struct r100_cs_track *track;
1117	serge	2019	int r;
		2020
1179	serge	2021	track = kzalloc(sizeof(*track), GFP_KERNEL);
2997	Serge	2022	if (!track)
		2023	return -ENOMEM;
1179	serge	2024	r100_cs_track_clear(p->rdev, track);
		2025	p->track = track;
1117	serge	2026	do {
3764	Serge	2027	r = radeon_cs_packet_parse(p, &pkt, p->idx);
1117	serge	2028	if (r) {
		2029	return r;
		2030	}
		2031	p->idx += pkt.count + 2;
		2032	switch (pkt.type) {
3764	Serge	2033	case RADEON_PACKET_TYPE0:
1179	serge	2034	if (p->rdev->family >= CHIP_R200)
		2035	r = r100_cs_parse_packet0(p, &pkt,
		2036	p->rdev->config.r100.reg_safe_bm,
		2037	p->rdev->config.r100.reg_safe_bm_size,
		2038	&r200_packet0_check);
		2039	else
		2040	r = r100_cs_parse_packet0(p, &pkt,
		2041	p->rdev->config.r100.reg_safe_bm,
		2042	p->rdev->config.r100.reg_safe_bm_size,
		2043	&r100_packet0_check);
1117	serge	2044	break;
3764	Serge	2045	case RADEON_PACKET_TYPE2:
1117	serge	2046	break;
3764	Serge	2047	case RADEON_PACKET_TYPE3:
1117	serge	2048	r = r100_packet3_check(p, &pkt);
		2049	break;
		2050	default:
		2051	DRM_ERROR("Unknown packet type %d !\n",
		2052	pkt.type);
		2053	return -EINVAL;
		2054	}
3764	Serge	2055	if (r)
1117	serge	2056	return r;
		2057	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
		2058	return 0;
		2059	}
		2060
2997	Serge	2061	static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
		2062	{
		2063	DRM_ERROR("pitch %d\n", t->pitch);
		2064	DRM_ERROR("use_pitch %d\n", t->use_pitch);
		2065	DRM_ERROR("width %d\n", t->width);
		2066	DRM_ERROR("width_11 %d\n", t->width_11);
		2067	DRM_ERROR("height %d\n", t->height);
		2068	DRM_ERROR("height_11 %d\n", t->height_11);
		2069	DRM_ERROR("num levels %d\n", t->num_levels);
		2070	DRM_ERROR("depth %d\n", t->txdepth);
		2071	DRM_ERROR("bpp %d\n", t->cpp);
		2072	DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
		2073	DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
		2074	DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
		2075	DRM_ERROR("compress format %d\n", t->compress_format);
		2076	}
1117	serge	2077
2997	Serge	2078	static int r100_track_compress_size(int compress_format, int w, int h)
1117	serge	2079	{
2997	Serge	2080	int block_width, block_height, block_bytes;
		2081	int wblocks, hblocks;
		2082	int min_wblocks;
		2083	int sz;
1117	serge	2084
2997	Serge	2085	block_width = 4;
		2086	block_height = 4;
		2087
		2088	switch (compress_format) {
		2089	case R100_TRACK_COMP_DXT1:
		2090	block_bytes = 8;
		2091	min_wblocks = 4;
		2092	break;
		2093	default:
		2094	case R100_TRACK_COMP_DXT35:
		2095	block_bytes = 16;
		2096	min_wblocks = 2;
		2097	break;
1117	serge	2098	}
		2099
2997	Serge	2100	hblocks = (h + block_height - 1) / block_height;
		2101	wblocks = (w + block_width - 1) / block_width;
		2102	if (wblocks < min_wblocks)
		2103	wblocks = min_wblocks;
		2104	sz = wblocks * hblocks * block_bytes;
		2105	return sz;
		2106	}
		2107
		2108	static int r100_cs_track_cube(struct radeon_device *rdev,
		2109	struct r100_cs_track *track, unsigned idx)
		2110	{
		2111	unsigned face, w, h;
		2112	struct radeon_bo *cube_robj;
		2113	unsigned long size;
		2114	unsigned compress_format = track->textures[idx].compress_format;
		2115
		2116	for (face = 0; face < 5; face++) {
		2117	cube_robj = track->textures[idx].cube_info[face].robj;
		2118	w = track->textures[idx].cube_info[face].width;
		2119	h = track->textures[idx].cube_info[face].height;
		2120
		2121	if (compress_format) {
		2122	size = r100_track_compress_size(compress_format, w, h);
		2123	} else
		2124	size = w * h;
		2125	size *= track->textures[idx].cpp;
		2126
		2127	size += track->textures[idx].cube_info[face].offset;
		2128
		2129	if (size > radeon_bo_size(cube_robj)) {
		2130	DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
		2131	size, radeon_bo_size(cube_robj));
		2132	r100_cs_track_texture_print(&track->textures[idx]);
		2133	return -1;
		2134	}
1117	serge	2135	}
2997	Serge	2136	return 0;
1117	serge	2137	}
		2138
2997	Serge	2139	static int r100_cs_track_texture_check(struct radeon_device *rdev,
		2140	struct r100_cs_track *track)
1117	serge	2141	{
2997	Serge	2142	struct radeon_bo *robj;
		2143	unsigned long size;
		2144	unsigned u, i, w, h, d;
		2145	int ret;
1117	serge	2146
2997	Serge	2147	for (u = 0; u < track->num_texture; u++) {
		2148	if (!track->textures[u].enabled)
		2149	continue;
		2150	if (track->textures[u].lookup_disable)
		2151	continue;
		2152	robj = track->textures[u].robj;
		2153	if (robj == NULL) {
		2154	DRM_ERROR("No texture bound to unit %u\n", u);
		2155	return -EINVAL;
		2156	}
		2157	size = 0;
		2158	for (i = 0; i <= track->textures[u].num_levels; i++) {
		2159	if (track->textures[u].use_pitch) {
		2160	if (rdev->family < CHIP_R300)
		2161	w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
		2162	else
		2163	w = track->textures[u].pitch / (1 << i);
		2164	} else {
		2165	w = track->textures[u].width;
		2166	if (rdev->family >= CHIP_RV515)
		2167	w \|= track->textures[u].width_11;
		2168	w = w / (1 << i);
		2169	if (track->textures[u].roundup_w)
		2170	w = roundup_pow_of_two(w);
		2171	}
		2172	h = track->textures[u].height;
		2173	if (rdev->family >= CHIP_RV515)
		2174	h \|= track->textures[u].height_11;
		2175	h = h / (1 << i);
		2176	if (track->textures[u].roundup_h)
		2177	h = roundup_pow_of_two(h);
		2178	if (track->textures[u].tex_coord_type == 1) {
		2179	d = (1 << track->textures[u].txdepth) / (1 << i);
		2180	if (!d)
		2181	d = 1;
		2182	} else {
		2183	d = 1;
		2184	}
		2185	if (track->textures[u].compress_format) {
		2186
		2187	size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
		2188	/* compressed textures are block based */
		2189	} else
		2190	size += w * h * d;
		2191	}
		2192	size *= track->textures[u].cpp;
		2193
		2194	switch (track->textures[u].tex_coord_type) {
		2195	case 0:
		2196	case 1:
		2197	break;
		2198	case 2:
		2199	if (track->separate_cube) {
		2200	ret = r100_cs_track_cube(rdev, track, u);
		2201	if (ret)
		2202	return ret;
		2203	} else
		2204	size *= 6;
		2205	break;
		2206	default:
		2207	DRM_ERROR("Invalid texture coordinate type %u for unit "
		2208	"%u\n", track->textures[u].tex_coord_type, u);
		2209	return -EINVAL;
		2210	}
		2211	if (size > radeon_bo_size(robj)) {
		2212	DRM_ERROR("Texture of unit %u needs %lu bytes but is "
		2213	"%lu\n", u, size, radeon_bo_size(robj));
		2214	r100_cs_track_texture_print(&track->textures[u]);
		2215	return -EINVAL;
		2216	}
1117	serge	2217	}
2997	Serge	2218	return 0;
		2219	}
		2220
		2221	int r100_cs_track_check(struct radeon_device rdev, struct r100_cs_track track)
		2222	{
		2223	unsigned i;
		2224	unsigned long size;
		2225	unsigned prim_walk;
		2226	unsigned nverts;
		2227	unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
		2228
		2229	if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
		2230	!track->blend_read_enable)
		2231	num_cb = 0;
		2232
		2233	for (i = 0; i < num_cb; i++) {
		2234	if (track->cb[i].robj == NULL) {
		2235	DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
		2236	return -EINVAL;
1117	serge	2237	}
2997	Serge	2238	size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
		2239	size += track->cb[i].offset;
		2240	if (size > radeon_bo_size(track->cb[i].robj)) {
		2241	DRM_ERROR("[drm] Buffer too small for color buffer %d "
		2242	"(need %lu have %lu) !\n", i, size,
		2243	radeon_bo_size(track->cb[i].robj));
		2244	DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
		2245	i, track->cb[i].pitch, track->cb[i].cpp,
		2246	track->cb[i].offset, track->maxy);
		2247	return -EINVAL;
		2248	}
1117	serge	2249	}
2997	Serge	2250	track->cb_dirty = false;
		2251
		2252	if (track->zb_dirty && track->z_enabled) {
		2253	if (track->zb.robj == NULL) {
		2254	DRM_ERROR("[drm] No buffer for z buffer !\n");
		2255	return -EINVAL;
		2256	}
		2257	size = track->zb.pitch * track->zb.cpp * track->maxy;
		2258	size += track->zb.offset;
		2259	if (size > radeon_bo_size(track->zb.robj)) {
		2260	DRM_ERROR("[drm] Buffer too small for z buffer "
		2261	"(need %lu have %lu) !\n", size,
		2262	radeon_bo_size(track->zb.robj));
		2263	DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
		2264	track->zb.pitch, track->zb.cpp,
		2265	track->zb.offset, track->maxy);
		2266	return -EINVAL;
		2267	}
		2268	}
		2269	track->zb_dirty = false;
		2270
		2271	if (track->aa_dirty && track->aaresolve) {
		2272	if (track->aa.robj == NULL) {
		2273	DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
		2274	return -EINVAL;
		2275	}
		2276	/* I believe the format comes from colorbuffer0. */
		2277	size = track->aa.pitch * track->cb[0].cpp * track->maxy;
		2278	size += track->aa.offset;
		2279	if (size > radeon_bo_size(track->aa.robj)) {
		2280	DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
		2281	"(need %lu have %lu) !\n", i, size,
		2282	radeon_bo_size(track->aa.robj));
		2283	DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
		2284	i, track->aa.pitch, track->cb[0].cpp,
		2285	track->aa.offset, track->maxy);
		2286	return -EINVAL;
		2287	}
		2288	}
		2289	track->aa_dirty = false;
		2290
		2291	prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
		2292	if (track->vap_vf_cntl & (1 << 14)) {
		2293	nverts = track->vap_alt_nverts;
		2294	} else {
		2295	nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
		2296	}
		2297	switch (prim_walk) {
		2298	case 1:
		2299	for (i = 0; i < track->num_arrays; i++) {
		2300	size = track->arrays[i].esize * track->max_indx * 4;
		2301	if (track->arrays[i].robj == NULL) {
		2302	DRM_ERROR("(PW %u) Vertex array %u no buffer "
		2303	"bound\n", prim_walk, i);
		2304	return -EINVAL;
		2305	}
		2306	if (size > radeon_bo_size(track->arrays[i].robj)) {
		2307	dev_err(rdev->dev, "(PW %u) Vertex array %u "
		2308	"need %lu dwords have %lu dwords\n",
		2309	prim_walk, i, size >> 2,
		2310	radeon_bo_size(track->arrays[i].robj)
		2311	>> 2);
		2312	DRM_ERROR("Max indices %u\n", track->max_indx);
		2313	return -EINVAL;
		2314	}
		2315	}
		2316	break;
		2317	case 2:
		2318	for (i = 0; i < track->num_arrays; i++) {
		2319	size = track->arrays[i].esize * (nverts - 1) * 4;
		2320	if (track->arrays[i].robj == NULL) {
		2321	DRM_ERROR("(PW %u) Vertex array %u no buffer "
		2322	"bound\n", prim_walk, i);
		2323	return -EINVAL;
		2324	}
		2325	if (size > radeon_bo_size(track->arrays[i].robj)) {
		2326	dev_err(rdev->dev, "(PW %u) Vertex array %u "
		2327	"need %lu dwords have %lu dwords\n",
		2328	prim_walk, i, size >> 2,
		2329	radeon_bo_size(track->arrays[i].robj)
		2330	>> 2);
		2331	return -EINVAL;
		2332	}
		2333	}
		2334	break;
		2335	case 3:
		2336	size = track->vtx_size * nverts;
		2337	if (size != track->immd_dwords) {
		2338	DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
		2339	track->immd_dwords, size);
		2340	DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
		2341	nverts, track->vtx_size);
		2342	return -EINVAL;
		2343	}
		2344	break;
		2345	default:
		2346	DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
		2347	prim_walk);
		2348	return -EINVAL;
		2349	}
		2350
		2351	if (track->tex_dirty) {
		2352	track->tex_dirty = false;
		2353	return r100_cs_track_texture_check(rdev, track);
		2354	}
		2355	return 0;
1117	serge	2356	}
		2357
2997	Serge	2358	void r100_cs_track_clear(struct radeon_device rdev, struct r100_cs_track track)
1117	serge	2359	{
2997	Serge	2360	unsigned i, face;
1117	serge	2361
2997	Serge	2362	track->cb_dirty = true;
		2363	track->zb_dirty = true;
		2364	track->tex_dirty = true;
		2365	track->aa_dirty = true;
1117	serge	2366
2997	Serge	2367	if (rdev->family < CHIP_R300) {
		2368	track->num_cb = 1;
		2369	if (rdev->family <= CHIP_RS200)
		2370	track->num_texture = 3;
		2371	else
		2372	track->num_texture = 6;
		2373	track->maxy = 2048;
		2374	track->separate_cube = 1;
		2375	} else {
		2376	track->num_cb = 4;
		2377	track->num_texture = 16;
		2378	track->maxy = 4096;
		2379	track->separate_cube = 0;
		2380	track->aaresolve = false;
		2381	track->aa.robj = NULL;
		2382	}
		2383
		2384	for (i = 0; i < track->num_cb; i++) {
		2385	track->cb[i].robj = NULL;
		2386	track->cb[i].pitch = 8192;
		2387	track->cb[i].cpp = 16;
		2388	track->cb[i].offset = 0;
		2389	}
		2390	track->z_enabled = true;
		2391	track->zb.robj = NULL;
		2392	track->zb.pitch = 8192;
		2393	track->zb.cpp = 4;
		2394	track->zb.offset = 0;
		2395	track->vtx_size = 0x7F;
		2396	track->immd_dwords = 0xFFFFFFFFUL;
		2397	track->num_arrays = 11;
		2398	track->max_indx = 0x00FFFFFFUL;
		2399	for (i = 0; i < track->num_arrays; i++) {
		2400	track->arrays[i].robj = NULL;
		2401	track->arrays[i].esize = 0x7F;
		2402	}
		2403	for (i = 0; i < track->num_texture; i++) {
		2404	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
		2405	track->textures[i].pitch = 16536;
		2406	track->textures[i].width = 16536;
		2407	track->textures[i].height = 16536;
		2408	track->textures[i].width_11 = 1 << 11;
		2409	track->textures[i].height_11 = 1 << 11;
		2410	track->textures[i].num_levels = 12;
		2411	if (rdev->family <= CHIP_RS200) {
		2412	track->textures[i].tex_coord_type = 0;
		2413	track->textures[i].txdepth = 0;
		2414	} else {
		2415	track->textures[i].txdepth = 16;
		2416	track->textures[i].tex_coord_type = 1;
1117	serge	2417	}
2997	Serge	2418	track->textures[i].cpp = 64;
		2419	track->textures[i].robj = NULL;
		2420	/* CS IB emission code makes sure texture unit are disabled */
		2421	track->textures[i].enabled = false;
		2422	track->textures[i].lookup_disable = false;
		2423	track->textures[i].roundup_w = true;
		2424	track->textures[i].roundup_h = true;
		2425	if (track->separate_cube)
		2426	for (face = 0; face < 5; face++) {
		2427	track->textures[i].cube_info[face].robj = NULL;
		2428	track->textures[i].cube_info[face].width = 16536;
		2429	track->textures[i].cube_info[face].height = 16536;
		2430	track->textures[i].cube_info[face].offset = 0;
		2431	}
1117	serge	2432	}
		2433	}
		2434
2997	Serge	2435	/*
		2436	* Global GPU functions
		2437	*/
		2438	static void r100_errata(struct radeon_device *rdev)
1117	serge	2439	{
2997	Serge	2440	rdev->pll_errata = 0;
		2441
		2442	if (rdev->family == CHIP_RV200 \|\| rdev->family == CHIP_RS200) {
		2443	rdev->pll_errata \|= CHIP_ERRATA_PLL_DUMMYREADS;
		2444	}
		2445
		2446	if (rdev->family == CHIP_RV100 \|\|
		2447	rdev->family == CHIP_RS100 \|\|
		2448	rdev->family == CHIP_RS200) {
		2449	rdev->pll_errata \|= CHIP_ERRATA_PLL_DELAY;
		2450	}
		2451	}
		2452
		2453	static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
		2454	{
1117	serge	2455	unsigned i;
		2456	uint32_t tmp;
		2457
		2458	for (i = 0; i < rdev->usec_timeout; i++) {
		2459	tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
		2460	if (tmp >= n) {
		2461	return 0;
		2462	}
		2463	DRM_UDELAY(1);
		2464	}
		2465	return -1;
		2466	}
		2467
		2468	int r100_gui_wait_for_idle(struct radeon_device *rdev)
		2469	{
		2470	unsigned i;
		2471	uint32_t tmp;
		2472
		2473	if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
		2474	printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
		2475	" Bad things might happen.\n");
		2476	}
		2477	for (i = 0; i < rdev->usec_timeout; i++) {
		2478	tmp = RREG32(RADEON_RBBM_STATUS);
1430	serge	2479	if (!(tmp & RADEON_RBBM_ACTIVE)) {
1117	serge	2480	return 0;
		2481	}
		2482	DRM_UDELAY(1);
		2483	}
		2484	return -1;
		2485	}
		2486
		2487	int r100_mc_wait_for_idle(struct radeon_device *rdev)
		2488	{
		2489	unsigned i;
		2490	uint32_t tmp;
		2491
		2492	for (i = 0; i < rdev->usec_timeout; i++) {
		2493	/* read MC_STATUS */
1430	serge	2494	tmp = RREG32(RADEON_MC_STATUS);
		2495	if (tmp & RADEON_MC_IDLE) {
1117	serge	2496	return 0;
		2497	}
		2498	DRM_UDELAY(1);
		2499	}
		2500	return -1;
		2501	}
		2502
2997	Serge	2503	bool r100_gpu_is_lockup(struct radeon_device rdev, struct radeon_ring ring)
1117	serge	2504	{
1963	serge	2505	u32 rbbm_status;
1117	serge	2506
1963	serge	2507	rbbm_status = RREG32(R_000E40_RBBM_STATUS);
		2508	if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
5078	serge	2509	radeon_ring_lockup_update(rdev, ring);
1963	serge	2510	return false;
1117	serge	2511	}
2997	Serge	2512	return radeon_ring_test_lockup(rdev, ring);
1117	serge	2513	}
		2514
2997	Serge	2515	/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
		2516	void r100_enable_bm(struct radeon_device *rdev)
		2517	{
		2518	uint32_t tmp;
		2519	/* Enable bus mastering */
		2520	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
		2521	WREG32(RADEON_BUS_CNTL, tmp);
		2522	}
		2523
1963	serge	2524	void r100_bm_disable(struct radeon_device *rdev)
1117	serge	2525	{
1963	serge	2526	u32 tmp;
1117	serge	2527
1963	serge	2528	/* disable bus mastering */
		2529	tmp = RREG32(R_000030_BUS_CNTL);
		2530	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000044);
		2531	mdelay(1);
		2532	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000042);
		2533	mdelay(1);
		2534	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000040);
		2535	tmp = RREG32(RADEON_BUS_CNTL);
		2536	mdelay(1);
2997	Serge	2537	pci_clear_master(rdev->pdev);
1963	serge	2538	mdelay(1);
		2539	}
		2540
		2541	int r100_asic_reset(struct radeon_device *rdev)
		2542	{
		2543	struct r100_mc_save save;
		2544	u32 status, tmp;
		2545	int ret = 0;
		2546
		2547	status = RREG32(R_000E40_RBBM_STATUS);
		2548	if (!G_000E40_GUI_ACTIVE(status)) {
		2549	return 0;
1117	serge	2550	}
1963	serge	2551	r100_mc_stop(rdev, &save);
		2552	status = RREG32(R_000E40_RBBM_STATUS);
		2553	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		2554	/* stop CP */
		2555	WREG32(RADEON_CP_CSQ_CNTL, 0);
		2556	tmp = RREG32(RADEON_CP_RB_CNTL);
		2557	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);
		2558	WREG32(RADEON_CP_RB_RPTR_WR, 0);
		2559	WREG32(RADEON_CP_RB_WPTR, 0);
		2560	WREG32(RADEON_CP_RB_CNTL, tmp);
		2561	/* save PCI state */
		2562	// pci_save_state(rdev->pdev);
		2563	/* disable bus mastering */
		2564	r100_bm_disable(rdev);
		2565	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) \|
		2566	S_0000F0_SOFT_RESET_RE(1) \|
		2567	S_0000F0_SOFT_RESET_PP(1) \|
		2568	S_0000F0_SOFT_RESET_RB(1));
		2569	RREG32(R_0000F0_RBBM_SOFT_RESET);
		2570	mdelay(500);
		2571	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		2572	mdelay(1);
		2573	status = RREG32(R_000E40_RBBM_STATUS);
		2574	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
1117	serge	2575	/* reset CP */
1963	serge	2576	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
		2577	RREG32(R_0000F0_RBBM_SOFT_RESET);
		2578	mdelay(500);
		2579	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		2580	mdelay(1);
		2581	status = RREG32(R_000E40_RBBM_STATUS);
		2582	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		2583	/* restore PCI & busmastering */
		2584	// pci_restore_state(rdev->pdev);
		2585	r100_enable_bm(rdev);
1117	serge	2586	/* Check if GPU is idle */
1963	serge	2587	if (G_000E40_SE_BUSY(status) \|\| G_000E40_RE_BUSY(status) \|\|
		2588	G_000E40_TAM_BUSY(status) \|\| G_000E40_PB_BUSY(status)) {
		2589	dev_err(rdev->dev, "failed to reset GPU\n");
		2590	ret = -1;
		2591	} else
		2592	dev_info(rdev->dev, "GPU reset succeed\n");
		2593	r100_mc_resume(rdev, &save);
		2594	return ret;
1117	serge	2595	}
		2596
1321	serge	2597	void r100_set_common_regs(struct radeon_device *rdev)
		2598	{
1430	serge	2599	struct drm_device *dev = rdev->ddev;
		2600	bool force_dac2 = false;
1963	serge	2601	u32 tmp;
1430	serge	2602
1321	serge	2603	/* set these so they don't interfere with anything */
		2604	WREG32(RADEON_OV0_SCALE_CNTL, 0);
		2605	WREG32(RADEON_SUBPIC_CNTL, 0);
		2606	WREG32(RADEON_VIPH_CONTROL, 0);
		2607	WREG32(RADEON_I2C_CNTL_1, 0);
		2608	WREG32(RADEON_DVI_I2C_CNTL_1, 0);
		2609	WREG32(RADEON_CAP0_TRIG_CNTL, 0);
		2610	WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1430	serge	2611
		2612	/* always set up dac2 on rn50 and some rv100 as lots
		2613	* of servers seem to wire it up to a VGA port but
		2614	* don't report it in the bios connector
		2615	* table.
		2616	*/
		2617	switch (dev->pdev->device) {
		2618	/* RN50 */
		2619	case 0x515e:
		2620	case 0x5969:
		2621	force_dac2 = true;
		2622	break;
		2623	/* RV100*/
		2624	case 0x5159:
		2625	case 0x515a:
		2626	/* DELL triple head servers */
		2627	if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
		2628	((dev->pdev->subsystem_device == 0x016c) \|\|
		2629	(dev->pdev->subsystem_device == 0x016d) \|\|
		2630	(dev->pdev->subsystem_device == 0x016e) \|\|
		2631	(dev->pdev->subsystem_device == 0x016f) \|\|
		2632	(dev->pdev->subsystem_device == 0x0170) \|\|
		2633	(dev->pdev->subsystem_device == 0x017d) \|\|
		2634	(dev->pdev->subsystem_device == 0x017e) \|\|
		2635	(dev->pdev->subsystem_device == 0x0183) \|\|
		2636	(dev->pdev->subsystem_device == 0x018a) \|\|
		2637	(dev->pdev->subsystem_device == 0x019a)))
		2638	force_dac2 = true;
		2639	break;
		2640	}
		2641
		2642	if (force_dac2) {
		2643	u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
		2644	u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		2645	u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
		2646
		2647	/* For CRT on DAC2, don't turn it on if BIOS didn't
		2648	enable it, even it's detected.
		2649	*/
		2650
		2651	/* force it to crtc0 */
		2652	dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
		2653	dac2_cntl \|= RADEON_DAC2_DAC2_CLK_SEL;
		2654	disp_hw_debug \|= RADEON_CRT2_DISP1_SEL;
		2655
		2656	/* set up the TV DAC */
		2657	tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL \|
		2658	RADEON_TV_DAC_STD_MASK \|
		2659	RADEON_TV_DAC_RDACPD \|
		2660	RADEON_TV_DAC_GDACPD \|
		2661	RADEON_TV_DAC_BDACPD \|
		2662	RADEON_TV_DAC_BGADJ_MASK \|
		2663	RADEON_TV_DAC_DACADJ_MASK);
		2664	tv_dac_cntl \|= (RADEON_TV_DAC_NBLANK \|
		2665	RADEON_TV_DAC_NHOLD \|
		2666	RADEON_TV_DAC_STD_PS2 \|
		2667	(0x58 << 16));
		2668
		2669	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		2670	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		2671	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		2672	}
1963	serge	2673
		2674	/* switch PM block to ACPI mode */
		2675	tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
		2676	tmp &= ~RADEON_PM_MODE_SEL;
		2677	WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
		2678
1321	serge	2679	}
1117	serge	2680
		2681	/*
		2682	* VRAM info
		2683	*/
		2684	static void r100_vram_get_type(struct radeon_device *rdev)
		2685	{
		2686	uint32_t tmp;
		2687
		2688	rdev->mc.vram_is_ddr = false;
		2689	if (rdev->flags & RADEON_IS_IGP)
		2690	rdev->mc.vram_is_ddr = true;
		2691	else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
		2692	rdev->mc.vram_is_ddr = true;
		2693	if ((rdev->family == CHIP_RV100) \|\|
		2694	(rdev->family == CHIP_RS100) \|\|
		2695	(rdev->family == CHIP_RS200)) {
		2696	tmp = RREG32(RADEON_MEM_CNTL);
		2697	if (tmp & RV100_HALF_MODE) {
		2698	rdev->mc.vram_width = 32;
		2699	} else {
		2700	rdev->mc.vram_width = 64;
		2701	}
		2702	if (rdev->flags & RADEON_SINGLE_CRTC) {
		2703	rdev->mc.vram_width /= 4;
		2704	rdev->mc.vram_is_ddr = true;
		2705	}
		2706	} else if (rdev->family <= CHIP_RV280) {
		2707	tmp = RREG32(RADEON_MEM_CNTL);
		2708	if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
		2709	rdev->mc.vram_width = 128;
		2710	} else {
		2711	rdev->mc.vram_width = 64;
		2712	}
		2713	} else {
		2714	/* newer IGPs */
		2715	rdev->mc.vram_width = 128;
		2716	}
		2717	}
		2718
1179	serge	2719	static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1117	serge	2720	{
1179	serge	2721	u32 aper_size;
		2722	u8 byte;
1117	serge	2723
1179	serge	2724	aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
		2725
		2726	/* Set HDP_APER_CNTL only on cards that are known not to be broken,
		2727	* that is has the 2nd generation multifunction PCI interface
		2728	*/
		2729	if (rdev->family == CHIP_RV280 \|\|
		2730	rdev->family >= CHIP_RV350) {
		2731	WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
		2732	~RADEON_HDP_APER_CNTL);
		2733	DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
		2734	return aper_size * 2;
		2735	}
		2736
		2737	/* Older cards have all sorts of funny issues to deal with. First
		2738	* check if it's a multifunction card by reading the PCI config
		2739	* header type... Limit those to one aperture size
		2740	*/
		2741	// pci_read_config_byte(rdev->pdev, 0xe, &byte);
		2742	// if (byte & 0x80) {
		2743	// DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
		2744	// DRM_INFO("Limiting VRAM to one aperture\n");
		2745	// return aper_size;
		2746	// }
		2747
		2748	/* Single function older card. We read HDP_APER_CNTL to see how the BIOS
		2749	* have set it up. We don't write this as it's broken on some ASICs but
		2750	* we expect the BIOS to have done the right thing (might be too optimistic...)
		2751	*/
		2752	if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
		2753	return aper_size * 2;
		2754	return aper_size;
		2755	}
		2756
		2757	void r100_vram_init_sizes(struct radeon_device *rdev)
		2758	{
		2759	u64 config_aper_size;
		2760
1430	serge	2761	/* work out accessible VRAM */
1963	serge	2762	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
		2763	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1430	serge	2764	rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
		2765	/* FIXME we don't use the second aperture yet when we could use it */
		2766	if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
		2767	rdev->mc.visible_vram_size = rdev->mc.aper_size;
1179	serge	2768	config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1117	serge	2769	if (rdev->flags & RADEON_IS_IGP) {
		2770	uint32_t tom;
		2771	/* read NB_TOM to get the amount of ram stolen for the GPU */
		2772	tom = RREG32(RADEON_NB_TOM);
1179	serge	2773	rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
		2774	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
		2775	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	2776	} else {
1179	serge	2777	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1117	serge	2778	/* Some production boards of m6 will report 0
		2779	* if it's 8 MB
		2780	*/
1179	serge	2781	if (rdev->mc.real_vram_size == 0) {
		2782	rdev->mc.real_vram_size = 8192 * 1024;
		2783	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1117	serge	2784	}
1179	serge	2785	/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1430	serge	2786	* Novell bug 204882 + along with lots of ubuntu ones
		2787	*/
1963	serge	2788	if (rdev->mc.aper_size > config_aper_size)
		2789	config_aper_size = rdev->mc.aper_size;
		2790
1179	serge	2791	if (config_aper_size > rdev->mc.real_vram_size)
		2792	rdev->mc.mc_vram_size = config_aper_size;
		2793	else
		2794	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	2795	}
		2796	}
		2797
1179	serge	2798	void r100_vga_set_state(struct radeon_device *rdev, bool state)
		2799	{
		2800	uint32_t temp;
		2801
		2802	temp = RREG32(RADEON_CONFIG_CNTL);
		2803	if (state == false) {
1963	serge	2804	temp &= ~RADEON_CFG_VGA_RAM_EN;
		2805	temp \|= RADEON_CFG_VGA_IO_DIS;
1179	serge	2806	} else {
1963	serge	2807	temp &= ~RADEON_CFG_VGA_IO_DIS;
1179	serge	2808	}
		2809	WREG32(RADEON_CONFIG_CNTL, temp);
		2810	}
		2811
2997	Serge	2812	static void r100_mc_init(struct radeon_device *rdev)
1179	serge	2813	{
1430	serge	2814	u64 base;
		2815
1179	serge	2816	r100_vram_get_type(rdev);
		2817	r100_vram_init_sizes(rdev);
1430	serge	2818	base = rdev->mc.aper_base;
		2819	if (rdev->flags & RADEON_IS_IGP)
		2820	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
		2821	radeon_vram_location(rdev, &rdev->mc, base);
1963	serge	2822	rdev->mc.gtt_base_align = 0;
1430	serge	2823	if (!(rdev->flags & RADEON_IS_AGP))
		2824	radeon_gtt_location(rdev, &rdev->mc);
1963	serge	2825	radeon_update_bandwidth_info(rdev);
1179	serge	2826	}
		2827
		2828
1117	serge	2829	/*
		2830	* Indirect registers accessor
		2831	*/
		2832	void r100_pll_errata_after_index(struct radeon_device *rdev)
		2833	{
1963	serge	2834	if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
1117	serge	2835	(void)RREG32(RADEON_CLOCK_CNTL_DATA);
		2836	(void)RREG32(RADEON_CRTC_GEN_CNTL);
1963	serge	2837	}
1117	serge	2838	}
		2839
		2840	static void r100_pll_errata_after_data(struct radeon_device *rdev)
		2841	{
		2842	/* This workarounds is necessary on RV100, RS100 and RS200 chips
		2843	* or the chip could hang on a subsequent access
		2844	*/
		2845	if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2997	Serge	2846	mdelay(5);
1117	serge	2847	}
		2848
		2849	/* This function is required to workaround a hardware bug in some (all?)
		2850	* revisions of the R300. This workaround should be called after every
		2851	* CLOCK_CNTL_INDEX register access. If not, register reads afterward
		2852	* may not be correct.
		2853	*/
		2854	if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
		2855	uint32_t save, tmp;
		2856
		2857	save = RREG32(RADEON_CLOCK_CNTL_INDEX);
		2858	tmp = save & ~(0x3f \| RADEON_PLL_WR_EN);
		2859	WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
		2860	tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
		2861	WREG32(RADEON_CLOCK_CNTL_INDEX, save);
		2862	}
		2863	}
		2864
		2865	uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
		2866	{
5078	serge	2867	unsigned long flags;
1117	serge	2868	uint32_t data;
		2869
5078	serge	2870	spin_lock_irqsave(&rdev->pll_idx_lock, flags);
1117	serge	2871	WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
		2872	r100_pll_errata_after_index(rdev);
		2873	data = RREG32(RADEON_CLOCK_CNTL_DATA);
		2874	r100_pll_errata_after_data(rdev);
5078	serge	2875	spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
1117	serge	2876	return data;
		2877	}
		2878
		2879	void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		2880	{
5078	serge	2881	unsigned long flags;
		2882
		2883	spin_lock_irqsave(&rdev->pll_idx_lock, flags);
1117	serge	2884	WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) \| RADEON_PLL_WR_EN));
		2885	r100_pll_errata_after_index(rdev);
		2886	WREG32(RADEON_CLOCK_CNTL_DATA, v);
		2887	r100_pll_errata_after_data(rdev);
5078	serge	2888	spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
1117	serge	2889	}
		2890
2997	Serge	2891	static void r100_set_safe_registers(struct radeon_device *rdev)
1117	serge	2892	{
1179	serge	2893	if (ASIC_IS_RN50(rdev)) {
		2894	rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
		2895	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
		2896	} else if (rdev->family < CHIP_R200) {
		2897	rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
		2898	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
		2899	} else {
1221	serge	2900	r200_set_safe_registers(rdev);
1117	serge	2901	}
		2902	}
		2903
1129	serge	2904	/*
		2905	* Debugfs info
		2906	*/
		2907	#if defined(CONFIG_DEBUG_FS)
		2908	static int r100_debugfs_rbbm_info(struct seq_file m, void data)
		2909	{
		2910	struct drm_info_node node = (struct drm_info_node ) m->private;
		2911	struct drm_device *dev = node->minor->dev;
		2912	struct radeon_device *rdev = dev->dev_private;
		2913	uint32_t reg, value;
		2914	unsigned i;
		2915
		2916	seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
		2917	seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
		2918	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2919	for (i = 0; i < 64; i++) {
		2920	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i \| 0x100);
		2921	reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
		2922	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
		2923	value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
		2924	seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
		2925	}
		2926	return 0;
		2927	}
		2928
		2929	static int r100_debugfs_cp_ring_info(struct seq_file m, void data)
		2930	{
		2931	struct drm_info_node node = (struct drm_info_node ) m->private;
		2932	struct drm_device *dev = node->minor->dev;
		2933	struct radeon_device *rdev = dev->dev_private;
2997	Serge	2934	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1129	serge	2935	uint32_t rdp, wdp;
		2936	unsigned count, i, j;
		2937
2997	Serge	2938	radeon_ring_free_size(rdev, ring);
1129	serge	2939	rdp = RREG32(RADEON_CP_RB_RPTR);
		2940	wdp = RREG32(RADEON_CP_RB_WPTR);
2997	Serge	2941	count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
1129	serge	2942	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2943	seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
		2944	seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2997	Serge	2945	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
1129	serge	2946	seq_printf(m, "%u dwords in ring\n", count);
5078	serge	2947	if (ring->ready) {
1129	serge	2948	for (j = 0; j <= count; j++) {
2997	Serge	2949	i = (rdp + j) & ring->ptr_mask;
		2950	seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
1129	serge	2951	}
5078	serge	2952	}
1129	serge	2953	return 0;
		2954	}
		2955
		2956
		2957	static int r100_debugfs_cp_csq_fifo(struct seq_file m, void data)
		2958	{
		2959	struct drm_info_node node = (struct drm_info_node ) m->private;
		2960	struct drm_device *dev = node->minor->dev;
		2961	struct radeon_device *rdev = dev->dev_private;
		2962	uint32_t csq_stat, csq2_stat, tmp;
		2963	unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
		2964	unsigned i;
		2965
		2966	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2967	seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
		2968	csq_stat = RREG32(RADEON_CP_CSQ_STAT);
		2969	csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
		2970	r_rptr = (csq_stat >> 0) & 0x3ff;
		2971	r_wptr = (csq_stat >> 10) & 0x3ff;
		2972	ib1_rptr = (csq_stat >> 20) & 0x3ff;
		2973	ib1_wptr = (csq2_stat >> 0) & 0x3ff;
		2974	ib2_rptr = (csq2_stat >> 10) & 0x3ff;
		2975	ib2_wptr = (csq2_stat >> 20) & 0x3ff;
		2976	seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
		2977	seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
		2978	seq_printf(m, "Ring rptr %u\n", r_rptr);
		2979	seq_printf(m, "Ring wptr %u\n", r_wptr);
		2980	seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
		2981	seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
		2982	seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
		2983	seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
		2984	/* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
		2985	* 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
		2986	seq_printf(m, "Ring fifo:\n");
		2987	for (i = 0; i < 256; i++) {
		2988	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2989	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2990	seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
		2991	}
		2992	seq_printf(m, "Indirect1 fifo:\n");
		2993	for (i = 256; i <= 512; i++) {
		2994	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2995	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2996	seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
		2997	}
		2998	seq_printf(m, "Indirect2 fifo:\n");
		2999	for (i = 640; i < ib1_wptr; i++) {
		3000	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		3001	tmp = RREG32(RADEON_CP_CSQ_DATA);
		3002	seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
		3003	}
		3004	return 0;
		3005	}
		3006
		3007	static int r100_debugfs_mc_info(struct seq_file m, void data)
		3008	{
		3009	struct drm_info_node node = (struct drm_info_node ) m->private;
		3010	struct drm_device *dev = node->minor->dev;
		3011	struct radeon_device *rdev = dev->dev_private;
		3012	uint32_t tmp;
		3013
		3014	tmp = RREG32(RADEON_CONFIG_MEMSIZE);
		3015	seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
		3016	tmp = RREG32(RADEON_MC_FB_LOCATION);
		3017	seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
		3018	tmp = RREG32(RADEON_BUS_CNTL);
		3019	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
		3020	tmp = RREG32(RADEON_MC_AGP_LOCATION);
		3021	seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
		3022	tmp = RREG32(RADEON_AGP_BASE);
		3023	seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
		3024	tmp = RREG32(RADEON_HOST_PATH_CNTL);
		3025	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
		3026	tmp = RREG32(0x01D0);
		3027	seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
		3028	tmp = RREG32(RADEON_AIC_LO_ADDR);
		3029	seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
		3030	tmp = RREG32(RADEON_AIC_HI_ADDR);
		3031	seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
		3032	tmp = RREG32(0x01E4);
		3033	seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
		3034	return 0;
		3035	}
		3036
		3037	static struct drm_info_list r100_debugfs_rbbm_list[] = {
		3038	{"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
		3039	};
		3040
		3041	static struct drm_info_list r100_debugfs_cp_list[] = {
		3042	{"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
		3043	{"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
		3044	};
		3045
		3046	static struct drm_info_list r100_debugfs_mc_info_list[] = {
		3047	{"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
		3048	};
		3049	#endif
		3050
		3051	int r100_debugfs_rbbm_init(struct radeon_device *rdev)
		3052	{
		3053	#if defined(CONFIG_DEBUG_FS)
		3054	return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
		3055	#else
		3056	return 0;
		3057	#endif
		3058	}
		3059
		3060	int r100_debugfs_cp_init(struct radeon_device *rdev)
		3061	{
		3062	#if defined(CONFIG_DEBUG_FS)
		3063	return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
		3064	#else
		3065	return 0;
		3066	#endif
		3067	}
		3068
		3069	int r100_debugfs_mc_info_init(struct radeon_device *rdev)
		3070	{
		3071	#if defined(CONFIG_DEBUG_FS)
		3072	return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
		3073	#else
		3074	return 0;
		3075	#endif
		3076	}
1179	serge	3077
		3078	int r100_set_surface_reg(struct radeon_device *rdev, int reg,
		3079	uint32_t tiling_flags, uint32_t pitch,
		3080	uint32_t offset, uint32_t obj_size)
		3081	{
		3082	int surf_index = reg * 16;
		3083	int flags = 0;
		3084
		3085	if (rdev->family <= CHIP_RS200) {
		3086	if ((tiling_flags & (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		3087	== (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		3088	flags \|= RADEON_SURF_TILE_COLOR_BOTH;
		3089	if (tiling_flags & RADEON_TILING_MACRO)
		3090	flags \|= RADEON_SURF_TILE_COLOR_MACRO;
5078	serge	3091	/* setting pitch to 0 disables tiling */
		3092	if ((tiling_flags & (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		3093	== 0)
		3094	pitch = 0;
1179	serge	3095	} else if (rdev->family <= CHIP_RV280) {
		3096	if (tiling_flags & (RADEON_TILING_MACRO))
		3097	flags \|= R200_SURF_TILE_COLOR_MACRO;
		3098	if (tiling_flags & RADEON_TILING_MICRO)
		3099	flags \|= R200_SURF_TILE_COLOR_MICRO;
		3100	} else {
		3101	if (tiling_flags & RADEON_TILING_MACRO)
		3102	flags \|= R300_SURF_TILE_MACRO;
		3103	if (tiling_flags & RADEON_TILING_MICRO)
		3104	flags \|= R300_SURF_TILE_MICRO;
		3105	}
		3106
		3107	if (tiling_flags & RADEON_TILING_SWAP_16BIT)
		3108	flags \|= RADEON_SURF_AP0_SWP_16BPP \| RADEON_SURF_AP1_SWP_16BPP;
		3109	if (tiling_flags & RADEON_TILING_SWAP_32BIT)
		3110	flags \|= RADEON_SURF_AP0_SWP_32BPP \| RADEON_SURF_AP1_SWP_32BPP;
		3111
1963	serge	3112	/* r100/r200 divide by 16 */
		3113	if (rdev->family < CHIP_R300)
		3114	flags \|= pitch / 16;
		3115	else
		3116	flags \|= pitch / 8;
		3117
		3118
		3119	DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
1179	serge	3120	WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
		3121	WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
		3122	WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
		3123	return 0;
		3124	}
		3125
		3126	void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
		3127	{
		3128	int surf_index = reg * 16;
		3129	WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
		3130	}
		3131
		3132	void r100_bandwidth_update(struct radeon_device *rdev)
		3133	{
		3134	fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
		3135	fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
		3136	fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
		3137	uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
		3138	fixed20_12 memtcas_ff[8] = {
1963	serge	3139	dfixed_init(1),
		3140	dfixed_init(2),
		3141	dfixed_init(3),
		3142	dfixed_init(0),
		3143	dfixed_init_half(1),
		3144	dfixed_init_half(2),
		3145	dfixed_init(0),
1179	serge	3146	};
		3147	fixed20_12 memtcas_rs480_ff[8] = {
1963	serge	3148	dfixed_init(0),
		3149	dfixed_init(1),
		3150	dfixed_init(2),
		3151	dfixed_init(3),
		3152	dfixed_init(0),
		3153	dfixed_init_half(1),
		3154	dfixed_init_half(2),
		3155	dfixed_init_half(3),
1179	serge	3156	};
		3157	fixed20_12 memtcas2_ff[8] = {
1963	serge	3158	dfixed_init(0),
		3159	dfixed_init(1),
		3160	dfixed_init(2),
		3161	dfixed_init(3),
		3162	dfixed_init(4),
		3163	dfixed_init(5),
		3164	dfixed_init(6),
		3165	dfixed_init(7),
1179	serge	3166	};
		3167	fixed20_12 memtrbs[8] = {
1963	serge	3168	dfixed_init(1),
		3169	dfixed_init_half(1),
		3170	dfixed_init(2),
		3171	dfixed_init_half(2),
		3172	dfixed_init(3),
		3173	dfixed_init_half(3),
		3174	dfixed_init(4),
		3175	dfixed_init_half(4)
1179	serge	3176	};
		3177	fixed20_12 memtrbs_r4xx[8] = {
1963	serge	3178	dfixed_init(4),
		3179	dfixed_init(5),
		3180	dfixed_init(6),
		3181	dfixed_init(7),
		3182	dfixed_init(8),
		3183	dfixed_init(9),
		3184	dfixed_init(10),
		3185	dfixed_init(11)
1179	serge	3186	};
		3187	fixed20_12 min_mem_eff;
		3188	fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
		3189	fixed20_12 cur_latency_mclk, cur_latency_sclk;
		3190	fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
		3191	disp_drain_rate2, read_return_rate;
		3192	fixed20_12 time_disp1_drop_priority;
		3193	int c;
		3194	int cur_size = 16; /* in octawords */
		3195	int critical_point = 0, critical_point2;
		3196	/* uint32_t read_return_rate, time_disp1_drop_priority; */
		3197	int stop_req, max_stop_req;
		3198	struct drm_display_mode *mode1 = NULL;
		3199	struct drm_display_mode *mode2 = NULL;
		3200	uint32_t pixel_bytes1 = 0;
		3201	uint32_t pixel_bytes2 = 0;
		3202
1963	serge	3203	radeon_update_display_priority(rdev);
		3204
1179	serge	3205	if (rdev->mode_info.crtcs[0]->base.enabled) {
		3206	mode1 = &rdev->mode_info.crtcs[0]->base.mode;
5078	serge	3207	pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8;
1179	serge	3208	}
1221	serge	3209	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
1179	serge	3210	if (rdev->mode_info.crtcs[1]->base.enabled) {
		3211	mode2 = &rdev->mode_info.crtcs[1]->base.mode;
5078	serge	3212	pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8;
1179	serge	3213	}
1221	serge	3214	}
1179	serge	3215
1963	serge	3216	min_mem_eff.full = dfixed_const_8(0);
1179	serge	3217	/* get modes */
		3218	if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
		3219	uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
		3220	mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
		3221	mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
		3222	/* check crtc enables */
		3223	if (mode2)
		3224	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
		3225	if (mode1)
		3226	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
		3227	WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
		3228	}
		3229
		3230	/*
		3231	* determine is there is enough bw for current mode
		3232	*/
1963	serge	3233	sclk_ff = rdev->pm.sclk;
		3234	mclk_ff = rdev->pm.mclk;
1179	serge	3235
		3236	temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
1963	serge	3237	temp_ff.full = dfixed_const(temp);
		3238	mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
1179	serge	3239
		3240	pix_clk.full = 0;
		3241	pix_clk2.full = 0;
		3242	peak_disp_bw.full = 0;
		3243	if (mode1) {
1963	serge	3244	temp_ff.full = dfixed_const(1000);
		3245	pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
		3246	pix_clk.full = dfixed_div(pix_clk, temp_ff);
		3247	temp_ff.full = dfixed_const(pixel_bytes1);
		3248	peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
1179	serge	3249	}
		3250	if (mode2) {
1963	serge	3251	temp_ff.full = dfixed_const(1000);
		3252	pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
		3253	pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
		3254	temp_ff.full = dfixed_const(pixel_bytes2);
		3255	peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
1179	serge	3256	}
		3257
1963	serge	3258	mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
1179	serge	3259	if (peak_disp_bw.full >= mem_bw.full) {
		3260	DRM_ERROR("You may not have enough display bandwidth for current mode\n"
		3261	"If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
		3262	}
		3263
		3264	/* Get values from the EXT_MEM_CNTL register...converting its contents. */
		3265	temp = RREG32(RADEON_MEM_TIMING_CNTL);
		3266	if ((rdev->family == CHIP_RV100) \|\| (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
		3267	mem_trcd = ((temp >> 2) & 0x3) + 1;
		3268	mem_trp = ((temp & 0x3)) + 1;
		3269	mem_tras = ((temp & 0x70) >> 4) + 1;
		3270	} else if (rdev->family == CHIP_R300 \|\|
		3271	rdev->family == CHIP_R350) { /* r300, r350 */
		3272	mem_trcd = (temp & 0x7) + 1;
		3273	mem_trp = ((temp >> 8) & 0x7) + 1;
		3274	mem_tras = ((temp >> 11) & 0xf) + 4;
		3275	} else if (rdev->family == CHIP_RV350 \|\|
		3276	rdev->family <= CHIP_RV380) {
		3277	/* rv3x0 */
		3278	mem_trcd = (temp & 0x7) + 3;
		3279	mem_trp = ((temp >> 8) & 0x7) + 3;
		3280	mem_tras = ((temp >> 11) & 0xf) + 6;
		3281	} else if (rdev->family == CHIP_R420 \|\|
		3282	rdev->family == CHIP_R423 \|\|
		3283	rdev->family == CHIP_RV410) {
		3284	/* r4xx */
		3285	mem_trcd = (temp & 0xf) + 3;
		3286	if (mem_trcd > 15)
		3287	mem_trcd = 15;
		3288	mem_trp = ((temp >> 8) & 0xf) + 3;
		3289	if (mem_trp > 15)
		3290	mem_trp = 15;
		3291	mem_tras = ((temp >> 12) & 0x1f) + 6;
		3292	if (mem_tras > 31)
		3293	mem_tras = 31;
		3294	} else { /* RV200, R200 */
		3295	mem_trcd = (temp & 0x7) + 1;
		3296	mem_trp = ((temp >> 8) & 0x7) + 1;
		3297	mem_tras = ((temp >> 12) & 0xf) + 4;
		3298	}
		3299	/* convert to FF */
1963	serge	3300	trcd_ff.full = dfixed_const(mem_trcd);
		3301	trp_ff.full = dfixed_const(mem_trp);
		3302	tras_ff.full = dfixed_const(mem_tras);
1179	serge	3303
		3304	/* Get values from the MEM_SDRAM_MODE_REG register...converting its */
		3305	temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		3306	data = (temp & (7 << 20)) >> 20;
		3307	if ((rdev->family == CHIP_RV100) \|\| rdev->flags & RADEON_IS_IGP) {
		3308	if (rdev->family == CHIP_RS480) /* don't think rs400 */
		3309	tcas_ff = memtcas_rs480_ff[data];
		3310	else
		3311	tcas_ff = memtcas_ff[data];
		3312	} else
		3313	tcas_ff = memtcas2_ff[data];
		3314
		3315	if (rdev->family == CHIP_RS400 \|\|
		3316	rdev->family == CHIP_RS480) {
		3317	/* extra cas latency stored in bits 23-25 0-4 clocks */
		3318	data = (temp >> 23) & 0x7;
		3319	if (data < 5)
1963	serge	3320	tcas_ff.full += dfixed_const(data);
1179	serge	3321	}
		3322
		3323	if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
		3324	/* on the R300, Tcas is included in Trbs.
		3325	*/
		3326	temp = RREG32(RADEON_MEM_CNTL);
		3327	data = (R300_MEM_NUM_CHANNELS_MASK & temp);
		3328	if (data == 1) {
		3329	if (R300_MEM_USE_CD_CH_ONLY & temp) {
		3330	temp = RREG32(R300_MC_IND_INDEX);
		3331	temp &= ~R300_MC_IND_ADDR_MASK;
		3332	temp \|= R300_MC_READ_CNTL_CD_mcind;
		3333	WREG32(R300_MC_IND_INDEX, temp);
		3334	temp = RREG32(R300_MC_IND_DATA);
		3335	data = (R300_MEM_RBS_POSITION_C_MASK & temp);
		3336	} else {
		3337	temp = RREG32(R300_MC_READ_CNTL_AB);
		3338	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		3339	}
		3340	} else {
		3341	temp = RREG32(R300_MC_READ_CNTL_AB);
		3342	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		3343	}
		3344	if (rdev->family == CHIP_RV410 \|\|
		3345	rdev->family == CHIP_R420 \|\|
		3346	rdev->family == CHIP_R423)
		3347	trbs_ff = memtrbs_r4xx[data];
		3348	else
		3349	trbs_ff = memtrbs[data];
		3350	tcas_ff.full += trbs_ff.full;
		3351	}
		3352
		3353	sclk_eff_ff.full = sclk_ff.full;
		3354
		3355	if (rdev->flags & RADEON_IS_AGP) {
		3356	fixed20_12 agpmode_ff;
1963	serge	3357	agpmode_ff.full = dfixed_const(radeon_agpmode);
		3358	temp_ff.full = dfixed_const_666(16);
		3359	sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
1179	serge	3360	}
		3361	/* TODO PCIE lanes may affect this - agpmode == 16?? */
		3362
		3363	if (ASIC_IS_R300(rdev)) {
1963	serge	3364	sclk_delay_ff.full = dfixed_const(250);
1179	serge	3365	} else {
		3366	if ((rdev->family == CHIP_RV100) \|\|
		3367	rdev->flags & RADEON_IS_IGP) {
		3368	if (rdev->mc.vram_is_ddr)
1963	serge	3369	sclk_delay_ff.full = dfixed_const(41);
1179	serge	3370	else
1963	serge	3371	sclk_delay_ff.full = dfixed_const(33);
1179	serge	3372	} else {
		3373	if (rdev->mc.vram_width == 128)
1963	serge	3374	sclk_delay_ff.full = dfixed_const(57);
1179	serge	3375	else
1963	serge	3376	sclk_delay_ff.full = dfixed_const(41);
1179	serge	3377	}
		3378	}
		3379
1963	serge	3380	mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
1179	serge	3381
		3382	if (rdev->mc.vram_is_ddr) {
		3383	if (rdev->mc.vram_width == 32) {
1963	serge	3384	k1.full = dfixed_const(40);
1179	serge	3385	c = 3;
		3386	} else {
1963	serge	3387	k1.full = dfixed_const(20);
1179	serge	3388	c = 1;
		3389	}
		3390	} else {
1963	serge	3391	k1.full = dfixed_const(40);
1179	serge	3392	c = 3;
		3393	}
		3394
1963	serge	3395	temp_ff.full = dfixed_const(2);
		3396	mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
		3397	temp_ff.full = dfixed_const(c);
		3398	mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
		3399	temp_ff.full = dfixed_const(4);
		3400	mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
		3401	mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
1179	serge	3402	mc_latency_mclk.full += k1.full;
		3403
1963	serge	3404	mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
		3405	mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
1179	serge	3406
		3407	/*
		3408	HW cursor time assuming worst case of full size colour cursor.
		3409	*/
1963	serge	3410	temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
1179	serge	3411	temp_ff.full += trcd_ff.full;
		3412	if (temp_ff.full < tras_ff.full)
		3413	temp_ff.full = tras_ff.full;
1963	serge	3414	cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
1179	serge	3415
1963	serge	3416	temp_ff.full = dfixed_const(cur_size);
		3417	cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
1179	serge	3418	/*
		3419	Find the total latency for the display data.
		3420	*/
1963	serge	3421	disp_latency_overhead.full = dfixed_const(8);
		3422	disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
1179	serge	3423	mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
		3424	mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
		3425
		3426	if (mc_latency_mclk.full > mc_latency_sclk.full)
		3427	disp_latency.full = mc_latency_mclk.full;
		3428	else
		3429	disp_latency.full = mc_latency_sclk.full;
		3430
		3431	/* setup Max GRPH_STOP_REQ default value */
		3432	if (ASIC_IS_RV100(rdev))
		3433	max_stop_req = 0x5c;
		3434	else
		3435	max_stop_req = 0x7c;
		3436
		3437	if (mode1) {
		3438	/* CRTC1
		3439	Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
		3440	GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
		3441	*/
		3442	stop_req = mode1->hdisplay * pixel_bytes1 / 16;
		3443
		3444	if (stop_req > max_stop_req)
		3445	stop_req = max_stop_req;
		3446
		3447	/*
		3448	Find the drain rate of the display buffer.
		3449	*/
1963	serge	3450	temp_ff.full = dfixed_const((16/pixel_bytes1));
		3451	disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
1179	serge	3452
		3453	/*
		3454	Find the critical point of the display buffer.
		3455	*/
1963	serge	3456	crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
		3457	crit_point_ff.full += dfixed_const_half(0);
1179	serge	3458
1963	serge	3459	critical_point = dfixed_trunc(crit_point_ff);
1179	serge	3460
		3461	if (rdev->disp_priority == 2) {
		3462	critical_point = 0;
		3463	}
		3464
		3465	/*
		3466	The critical point should never be above max_stop_req-4. Setting
		3467	GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
		3468	*/
		3469	if (max_stop_req - critical_point < 4)
		3470	critical_point = 0;
		3471
		3472	if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
		3473	/* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
		3474	critical_point = 0x10;
		3475	}
		3476
		3477	temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
		3478	temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
		3479	temp \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		3480	temp &= ~(RADEON_GRPH_START_REQ_MASK);
		3481	if ((rdev->family == CHIP_R350) &&
		3482	(stop_req > 0x15)) {
		3483	stop_req -= 0x10;
		3484	}
		3485	temp \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		3486	temp \|= RADEON_GRPH_BUFFER_SIZE;
		3487	temp &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		3488	RADEON_GRPH_CRITICAL_AT_SOF \|
		3489	RADEON_GRPH_STOP_CNTL);
		3490	/*
		3491	Write the result into the register.
		3492	*/
		3493	WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		3494	(critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		3495
		3496	#if 0
		3497	if ((rdev->family == CHIP_RS400) \|\|
		3498	(rdev->family == CHIP_RS480)) {
		3499	/* attempt to program RS400 disp regs correctly ??? */
		3500	temp = RREG32(RS400_DISP1_REG_CNTL);
		3501	temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK \|
		3502	RS400_DISP1_STOP_REQ_LEVEL_MASK);
		3503	WREG32(RS400_DISP1_REQ_CNTL1, (temp \|
		3504	(critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		3505	(critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		3506	temp = RREG32(RS400_DMIF_MEM_CNTL1);
		3507	temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK \|
		3508	RS400_DISP1_CRITICAL_POINT_STOP_MASK);
		3509	WREG32(RS400_DMIF_MEM_CNTL1, (temp \|
		3510	(critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) \|
		3511	(critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
		3512	}
		3513	#endif
		3514
1963	serge	3515	DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
1179	serge	3516	/* (unsigned int)info->SavedReg->grph_buffer_cntl, */
		3517	(unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
		3518	}
		3519
		3520	if (mode2) {
		3521	u32 grph2_cntl;
		3522	stop_req = mode2->hdisplay * pixel_bytes2 / 16;
		3523
		3524	if (stop_req > max_stop_req)
		3525	stop_req = max_stop_req;
		3526
		3527	/*
		3528	Find the drain rate of the display buffer.
		3529	*/
1963	serge	3530	temp_ff.full = dfixed_const((16/pixel_bytes2));
		3531	disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
1179	serge	3532
		3533	grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
		3534	grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
		3535	grph2_cntl \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		3536	grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
		3537	if ((rdev->family == CHIP_R350) &&
		3538	(stop_req > 0x15)) {
		3539	stop_req -= 0x10;
		3540	}
		3541	grph2_cntl \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		3542	grph2_cntl \|= RADEON_GRPH_BUFFER_SIZE;
		3543	grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		3544	RADEON_GRPH_CRITICAL_AT_SOF \|
		3545	RADEON_GRPH_STOP_CNTL);
		3546
		3547	if ((rdev->family == CHIP_RS100) \|\|
		3548	(rdev->family == CHIP_RS200))
		3549	critical_point2 = 0;
		3550	else {
		3551	temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
1963	serge	3552	temp_ff.full = dfixed_const(temp);
		3553	temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
1179	serge	3554	if (sclk_ff.full < temp_ff.full)
		3555	temp_ff.full = sclk_ff.full;
		3556
		3557	read_return_rate.full = temp_ff.full;
		3558
		3559	if (mode1) {
		3560	temp_ff.full = read_return_rate.full - disp_drain_rate.full;
1963	serge	3561	time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
1179	serge	3562	} else {
		3563	time_disp1_drop_priority.full = 0;
		3564	}
		3565	crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
1963	serge	3566	crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
		3567	crit_point_ff.full += dfixed_const_half(0);
1179	serge	3568
1963	serge	3569	critical_point2 = dfixed_trunc(crit_point_ff);
1179	serge	3570
		3571	if (rdev->disp_priority == 2) {
		3572	critical_point2 = 0;
		3573	}
		3574
		3575	if (max_stop_req - critical_point2 < 4)
		3576	critical_point2 = 0;
		3577
		3578	}
		3579
		3580	if (critical_point2 == 0 && rdev->family == CHIP_R300) {
		3581	/* some R300 cards have problem with this set to 0 */
		3582	critical_point2 = 0x10;
		3583	}
		3584
		3585	WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		3586	(critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		3587
		3588	if ((rdev->family == CHIP_RS400) \|\|
		3589	(rdev->family == CHIP_RS480)) {
		3590	#if 0
		3591	/* attempt to program RS400 disp2 regs correctly ??? */
		3592	temp = RREG32(RS400_DISP2_REQ_CNTL1);
		3593	temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK \|
		3594	RS400_DISP2_STOP_REQ_LEVEL_MASK);
		3595	WREG32(RS400_DISP2_REQ_CNTL1, (temp \|
		3596	(critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		3597	(critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		3598	temp = RREG32(RS400_DISP2_REQ_CNTL2);
		3599	temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK \|
		3600	RS400_DISP2_CRITICAL_POINT_STOP_MASK);
		3601	WREG32(RS400_DISP2_REQ_CNTL2, (temp \|
		3602	(critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) \|
		3603	(critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
		3604	#endif
		3605	WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
		3606	WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
		3607	WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
		3608	WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
		3609	}
		3610
1963	serge	3611	DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
1179	serge	3612	(unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
		3613	}
		3614	}
		3615
2997	Serge	3616	int r100_ring_test(struct radeon_device rdev, struct radeon_ring ring)
1963	serge	3617	{
1412	serge	3618	uint32_t scratch;
		3619	uint32_t tmp = 0;
		3620	unsigned i;
		3621	int r;
1179	serge	3622
1412	serge	3623	r = radeon_scratch_get(rdev, &scratch);
		3624	if (r) {
		3625	DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
		3626	return r;
		3627	}
		3628	WREG32(scratch, 0xCAFEDEAD);
2997	Serge	3629	r = radeon_ring_lock(rdev, ring, 2);
1412	serge	3630	if (r) {
		3631	DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
		3632	radeon_scratch_free(rdev, scratch);
		3633	return r;
		3634	}
2997	Serge	3635	radeon_ring_write(ring, PACKET0(scratch, 0));
		3636	radeon_ring_write(ring, 0xDEADBEEF);
5078	serge	3637	radeon_ring_unlock_commit(rdev, ring, false);
1412	serge	3638	for (i = 0; i < rdev->usec_timeout; i++) {
		3639	tmp = RREG32(scratch);
		3640	if (tmp == 0xDEADBEEF) {
		3641	break;
		3642	}
		3643	DRM_UDELAY(1);
		3644	}
		3645	if (i < rdev->usec_timeout) {
		3646	DRM_INFO("ring test succeeded in %d usecs\n", i);
		3647	} else {
1963	serge	3648	DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1412	serge	3649	scratch, tmp);
		3650	r = -EINVAL;
		3651	}
		3652	radeon_scratch_free(rdev, scratch);
		3653	return r;
		3654	}
		3655
1963	serge	3656	void r100_ring_ib_execute(struct radeon_device rdev, struct radeon_ib ib)
		3657	{
2997	Serge	3658	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
		3659
		3660	if (ring->rptr_save_reg) {
		3661	u32 next_rptr = ring->wptr + 2 + 3;
		3662	radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
		3663	radeon_ring_write(ring, next_rptr);
		3664	}
		3665
		3666	radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
		3667	radeon_ring_write(ring, ib->gpu_addr);
		3668	radeon_ring_write(ring, ib->length_dw);
1963	serge	3669	}
		3670
2997	Serge	3671	int r100_ib_test(struct radeon_device rdev, struct radeon_ring ring)
1963	serge	3672	{
2997	Serge	3673	struct radeon_ib ib;
1963	serge	3674	uint32_t scratch;
		3675	uint32_t tmp = 0;
		3676	unsigned i;
		3677	int r;
		3678
		3679	r = radeon_scratch_get(rdev, &scratch);
		3680	if (r) {
		3681	DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
		3682	return r;
		3683	}
		3684	WREG32(scratch, 0xCAFEDEAD);
2997	Serge	3685	r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
1963	serge	3686	if (r) {
2997	Serge	3687	DRM_ERROR("radeon: failed to get ib (%d).\n", r);
		3688	goto free_scratch;
1963	serge	3689	}
2997	Serge	3690	ib.ptr[0] = PACKET0(scratch, 0);
		3691	ib.ptr[1] = 0xDEADBEEF;
		3692	ib.ptr[2] = PACKET2(0);
		3693	ib.ptr[3] = PACKET2(0);
		3694	ib.ptr[4] = PACKET2(0);
		3695	ib.ptr[5] = PACKET2(0);
		3696	ib.ptr[6] = PACKET2(0);
		3697	ib.ptr[7] = PACKET2(0);
		3698	ib.length_dw = 8;
5078	serge	3699	r = radeon_ib_schedule(rdev, &ib, NULL, false);
1963	serge	3700	if (r) {
2997	Serge	3701	DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
		3702	goto free_ib;
1963	serge	3703	}
2997	Serge	3704	r = radeon_fence_wait(ib.fence, false);
1963	serge	3705	if (r) {
2997	Serge	3706	DRM_ERROR("radeon: fence wait failed (%d).\n", r);
		3707	goto free_ib;
1963	serge	3708	}
		3709	for (i = 0; i < rdev->usec_timeout; i++) {
		3710	tmp = RREG32(scratch);
		3711	if (tmp == 0xDEADBEEF) {
		3712	break;
		3713	}
		3714	DRM_UDELAY(1);
		3715	}
		3716	if (i < rdev->usec_timeout) {
		3717	DRM_INFO("ib test succeeded in %u usecs\n", i);
		3718	} else {
		3719	DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
		3720	scratch, tmp);
		3721	r = -EINVAL;
		3722	}
2997	Serge	3723	free_ib:
		3724	radeon_ib_free(rdev, &ib);
		3725	free_scratch:
1963	serge	3726	radeon_scratch_free(rdev, scratch);
		3727	return r;
		3728	}
		3729
1179	serge	3730	void r100_mc_stop(struct radeon_device rdev, struct r100_mc_save save)
		3731	{
		3732	/* Shutdown CP we shouldn't need to do that but better be safe than
		3733	* sorry
		3734	*/
2997	Serge	3735	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1179	serge	3736	WREG32(R_000740_CP_CSQ_CNTL, 0);
		3737
		3738	/* Save few CRTC registers */
1221	serge	3739	save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
1179	serge	3740	save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
		3741	save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
		3742	save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
		3743	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3744	save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
		3745	save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
		3746	}
		3747
		3748	/* Disable VGA aperture access */
1221	serge	3749	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
1179	serge	3750	/* Disable cursor, overlay, crtc */
		3751	WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET \| S_000260_CUR_LOCK(1));
		3752	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL \|
		3753	S_000054_CRTC_DISPLAY_DIS(1));
		3754	WREG32(R_000050_CRTC_GEN_CNTL,
		3755	(C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) \|
		3756	S_000050_CRTC_DISP_REQ_EN_B(1));
		3757	WREG32(R_000420_OV0_SCALE_CNTL,
		3758	C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
		3759	WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
		3760	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3761	WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET \|
		3762	S_000360_CUR2_LOCK(1));
		3763	WREG32(R_0003F8_CRTC2_GEN_CNTL,
		3764	(C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) \|
		3765	S_0003F8_CRTC2_DISPLAY_DIS(1) \|
		3766	S_0003F8_CRTC2_DISP_REQ_EN_B(1));
		3767	WREG32(R_000360_CUR2_OFFSET,
		3768	C_000360_CUR2_LOCK & save->CUR2_OFFSET);
		3769	}
		3770	}
		3771
		3772	void r100_mc_resume(struct radeon_device rdev, struct r100_mc_save save)
		3773	{
		3774	/* Update base address for crtc */
1430	serge	3775	WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
1179	serge	3776	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
1430	serge	3777	WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
1179	serge	3778	}
		3779	/* Restore CRTC registers */
1221	serge	3780	WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
1179	serge	3781	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
		3782	WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
		3783	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3784	WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
		3785	}
		3786	}
		3787
1221	serge	3788	void r100_vga_render_disable(struct radeon_device *rdev)
		3789	{
		3790	u32 tmp;
		3791
		3792	tmp = RREG8(R_0003C2_GENMO_WT);
		3793	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
		3794	}
		3795
		3796	static void r100_debugfs(struct radeon_device *rdev)
		3797	{
		3798	int r;
		3799
		3800	r = r100_debugfs_mc_info_init(rdev);
		3801	if (r)
		3802	dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		3803	}
		3804
		3805	static void r100_mc_program(struct radeon_device *rdev)
		3806	{
		3807	struct r100_mc_save save;
		3808
		3809	/* Stops all mc clients */
		3810	r100_mc_stop(rdev, &save);
		3811	if (rdev->flags & RADEON_IS_AGP) {
		3812	WREG32(R_00014C_MC_AGP_LOCATION,
		3813	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		3814	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		3815	WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		3816	if (rdev->family > CHIP_RV200)
		3817	WREG32(R_00015C_AGP_BASE_2,
		3818	upper_32_bits(rdev->mc.agp_base) & 0xff);
		3819	} else {
		3820	WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		3821	WREG32(R_000170_AGP_BASE, 0);
		3822	if (rdev->family > CHIP_RV200)
		3823	WREG32(R_00015C_AGP_BASE_2, 0);
		3824	}
		3825	/* Wait for mc idle */
		3826	if (r100_mc_wait_for_idle(rdev))
		3827	dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
		3828	/* Program MC, should be a 32bits limited address space */
		3829	WREG32(R_000148_MC_FB_LOCATION,
		3830	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		3831	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		3832	r100_mc_resume(rdev, &save);
		3833	}
		3834
2997	Serge	3835	static void r100_clock_startup(struct radeon_device *rdev)
1221	serge	3836	{
		3837	u32 tmp;
		3838
		3839	if (radeon_dynclks != -1 && radeon_dynclks)
		3840	radeon_legacy_set_clock_gating(rdev, 1);
		3841	/* We need to force on some of the block */
		3842	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
		3843	tmp \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		3844	if ((rdev->family == CHIP_RV250) \|\| (rdev->family == CHIP_RV280))
		3845	tmp \|= S_00000D_FORCE_DISP1(1) \| S_00000D_FORCE_DISP2(1);
		3846	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
		3847	}
		3848
		3849	static int r100_startup(struct radeon_device *rdev)
		3850	{
		3851	int r;
		3852
1321	serge	3853	/* set common regs */
		3854	r100_set_common_regs(rdev);
		3855	/* program mc */
1221	serge	3856	r100_mc_program(rdev);
		3857	/* Resume clock */
		3858	r100_clock_startup(rdev);
		3859	/* Initialize GART (initialize after TTM so we can allocate
		3860	* memory through TTM but finalize after TTM) */
1321	serge	3861	r100_enable_bm(rdev);
1221	serge	3862	if (rdev->flags & RADEON_IS_PCI) {
		3863	r = r100_pci_gart_enable(rdev);
		3864	if (r)
		3865	return r;
		3866	}
2005	serge	3867
		3868	/* allocate wb buffer */
		3869	r = radeon_wb_init(rdev);
		3870	if (r)
		3871	return r;
		3872
3120	serge	3873	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
		3874	if (r) {
		3875	dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
		3876	return r;
		3877	}
		3878
1221	serge	3879	/* Enable IRQ */
3764	Serge	3880	if (!rdev->irq.installed) {
		3881	r = radeon_irq_kms_init(rdev);
		3882	if (r)
		3883	return r;
		3884	}
		3885
2005	serge	3886	r100_irq_set(rdev);
1404	serge	3887	rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1221	serge	3888	/* 1M ring buffer */
1412	serge	3889	r = r100_cp_init(rdev, 1024 * 1024);
		3890	if (r) {
1963	serge	3891	dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1412	serge	3892	return r;
		3893	}
2997	Serge	3894
		3895	r = radeon_ib_pool_init(rdev);
2005	serge	3896	if (r) {
2997	Serge	3897	dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2005	serge	3898	return r;
		3899	}
3120	serge	3900
1221	serge	3901	return 0;
		3902	}
		3903
1963	serge	3904	/*
		3905	* Due to how kexec works, it can leave the hw fully initialised when it
		3906	* boots the new kernel. However doing our init sequence with the CP and
		3907	* WB stuff setup causes GPU hangs on the RN50 at least. So at startup
		3908	* do some quick sanity checks and restore sane values to avoid this
		3909	* problem.
		3910	*/
		3911	void r100_restore_sanity(struct radeon_device *rdev)
		3912	{
		3913	u32 tmp;
1221	serge	3914
1963	serge	3915	tmp = RREG32(RADEON_CP_CSQ_CNTL);
		3916	if (tmp) {
		3917	WREG32(RADEON_CP_CSQ_CNTL, 0);
		3918	}
		3919	tmp = RREG32(RADEON_CP_RB_CNTL);
		3920	if (tmp) {
		3921	WREG32(RADEON_CP_RB_CNTL, 0);
		3922	}
		3923	tmp = RREG32(RADEON_SCRATCH_UMSK);
		3924	if (tmp) {
		3925	WREG32(RADEON_SCRATCH_UMSK, 0);
		3926	}
		3927	}
1221	serge	3928
		3929	int r100_init(struct radeon_device *rdev)
		3930	{
		3931	int r;
		3932
		3933	/* Register debugfs file specific to this group of asics */
		3934	r100_debugfs(rdev);
		3935	/* Disable VGA */
		3936	r100_vga_render_disable(rdev);
		3937	/* Initialize scratch registers */
		3938	radeon_scratch_init(rdev);
		3939	/* Initialize surface registers */
		3940	radeon_surface_init(rdev);
1963	serge	3941	/* sanity check some register to avoid hangs like after kexec */
		3942	r100_restore_sanity(rdev);
1221	serge	3943	/* TODO: disable VGA need to use VGA request */
		3944	/* BIOS*/
		3945	if (!radeon_get_bios(rdev)) {
		3946	if (ASIC_IS_AVIVO(rdev))
		3947	return -EINVAL;
		3948	}
		3949	if (rdev->is_atom_bios) {
		3950	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		3951	return -EINVAL;
		3952	} else {
		3953	r = radeon_combios_init(rdev);
		3954	if (r)
		3955	return r;
		3956	}
		3957	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
1963	serge	3958	if (radeon_asic_reset(rdev)) {
1221	serge	3959	dev_warn(rdev->dev,
		3960	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		3961	RREG32(R_000E40_RBBM_STATUS),
		3962	RREG32(R_0007C0_CP_STAT));
		3963	}
		3964	/* check if cards are posted or not */
1321	serge	3965	if (radeon_boot_test_post_card(rdev) == false)
		3966	return -EINVAL;
1221	serge	3967	/* Set asic errata */
		3968	r100_errata(rdev);
		3969	/* Initialize clocks */
		3970	radeon_get_clock_info(rdev->ddev);
1430	serge	3971	/* initialize AGP */
		3972	if (rdev->flags & RADEON_IS_AGP) {
		3973	r = radeon_agp_init(rdev);
		3974	if (r) {
		3975	radeon_agp_disable(rdev);
		3976	}
		3977	}
		3978	/* initialize VRAM */
		3979	r100_mc_init(rdev);
1221	serge	3980	/* Fence driver */
2005	serge	3981	r = radeon_fence_driver_init(rdev);
		3982	if (r)
		3983	return r;
1221	serge	3984	/* Memory manager */
1321	serge	3985	r = radeon_bo_init(rdev);
1221	serge	3986	if (r)
		3987	return r;
		3988	if (rdev->flags & RADEON_IS_PCI) {
		3989	r = r100_pci_gart_init(rdev);
		3990	if (r)
		3991	return r;
		3992	}
		3993	r100_set_safe_registers(rdev);
2997	Serge	3994
5078	serge	3995	/* Initialize power management */
		3996	radeon_pm_init(rdev);
		3997
1221	serge	3998	rdev->accel_working = true;
		3999	r = r100_startup(rdev);
		4000	if (r) {
		4001	/* Somethings want wront with the accel init stop accel */
		4002	dev_err(rdev->dev, "Disabling GPU acceleration\n");
		4003	if (rdev->flags & RADEON_IS_PCI)
		4004	r100_pci_gart_fini(rdev);
		4005	rdev->accel_working = false;
		4006	}
		4007	return 0;
		4008	}
2997	Serge	4009
		4010	u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
		4011	{
		4012	if (reg < rdev->rio_mem_size)
		4013	return ioread32(rdev->rio_mem + reg);
		4014	else {
		4015	iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
		4016	return ioread32(rdev->rio_mem + RADEON_MM_DATA);
		4017	}
		4018	}
		4019
		4020	void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		4021	{
		4022	if (reg < rdev->rio_mem_size)
		4023	iowrite32(v, rdev->rio_mem + reg);
		4024	else {
		4025	iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
		4026	iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
		4027	}
		4028	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r100.c – Rev 5078