WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r100.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1179	serge	28	#include
1963	serge	29	#include
2997	Serge	30	#include
		31	#include
1117	serge	32	#include "radeon_reg.h"
		33	#include "radeon.h"
1963	serge	34	#include "radeon_asic.h"
1179	serge	35	#include "r100d.h"
1221	serge	36	#include "rs100d.h"
		37	#include "rv200d.h"
		38	#include "rv250d.h"
1963	serge	39	#include "atom.h"
1117	serge	40
1221	serge	41	#include
2997	Serge	42	#include
1221	serge	43
1179	serge	44	#include "r100_reg_safe.h"
		45	#include "rn50_reg_safe.h"
1221	serge	46
		47	/* Firmware Names */
		48	#define FIRMWARE_R100 "radeon/R100_cp.bin"
		49	#define FIRMWARE_R200 "radeon/R200_cp.bin"
		50	#define FIRMWARE_R300 "radeon/R300_cp.bin"
		51	#define FIRMWARE_R420 "radeon/R420_cp.bin"
		52	#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
		53	#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
		54	#define FIRMWARE_R520 "radeon/R520_cp.bin"
		55
		56	MODULE_FIRMWARE(FIRMWARE_R100);
		57	MODULE_FIRMWARE(FIRMWARE_R200);
		58	MODULE_FIRMWARE(FIRMWARE_R300);
		59	MODULE_FIRMWARE(FIRMWARE_R420);
		60	MODULE_FIRMWARE(FIRMWARE_RS690);
		61	MODULE_FIRMWARE(FIRMWARE_RS600);
		62	MODULE_FIRMWARE(FIRMWARE_R520);
		63
		64
1117	serge	65	/* This files gather functions specifics to:
		66	* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
2997	Serge	67	* and others in some cases.
1117	serge	68	*/
		69
2997	Serge	70	/**
		71	* r100_wait_for_vblank - vblank wait asic callback.
		72	*
		73	* @rdev: radeon_device pointer
		74	* @crtc: crtc to wait for vblank on
		75	*
		76	* Wait for vblank on the requested crtc (r1xx-r4xx).
		77	*/
		78	void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
		79	{
		80	int i;
		81
		82	if (crtc >= rdev->num_crtc)
		83	return;
		84
		85	if (crtc == 0) {
		86	if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
		87	for (i = 0; i < rdev->usec_timeout; i++) {
		88	if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
		89	break;
		90	udelay(1);
		91	}
		92	for (i = 0; i < rdev->usec_timeout; i++) {
		93	if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
		94	break;
		95	udelay(1);
		96	}
		97	}
		98	} else {
		99	if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
		100	for (i = 0; i < rdev->usec_timeout; i++) {
		101	if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
		102	break;
		103	udelay(1);
		104	}
		105	for (i = 0; i < rdev->usec_timeout; i++) {
		106	if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
		107	break;
		108	udelay(1);
		109	}
		110	}
		111	}
		112	}
1963	serge	113	u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
		114	{
		115	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
		116	u32 tmp = ((u32)crtc_base) \| RADEON_CRTC_OFFSET__OFFSET_LOCK;
2997	Serge	117	int i;
1963	serge	118
		119	/* Lock the graphics update lock */
		120	/* update the scanout addresses */
		121	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
		122
		123	/* Wait for update_pending to go high. */
2997	Serge	124	for (i = 0; i < rdev->usec_timeout; i++) {
		125	if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
		126	break;
		127	udelay(1);
		128	}
1963	serge	129	DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
		130
		131	/* Unlock the lock, so double-buffering can take place inside vblank */
		132	tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
		133	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
		134
		135	/* Return current update_pending status: */
		136	return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
		137	}
		138	bool r100_gui_idle(struct radeon_device *rdev)
		139	{
		140	if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
		141	return false;
		142	else
		143	return true;
		144	}
		145
1321	serge	146	/* hpd for digital panel detect/disconnect */
2997	Serge	147	/**
		148	* r100_hpd_sense - hpd sense callback.
		149	*
		150	* @rdev: radeon_device pointer
		151	* @hpd: hpd (hotplug detect) pin
		152	*
		153	* Checks if a digital monitor is connected (r1xx-r4xx).
		154	* Returns true if connected, false if not connected.
		155	*/
1321	serge	156	bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
		157	{
		158	bool connected = false;
		159
		160	switch (hpd) {
		161	case RADEON_HPD_1:
		162	if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
		163	connected = true;
		164	break;
		165	case RADEON_HPD_2:
		166	if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
		167	connected = true;
		168	break;
		169	default:
		170	break;
		171	}
		172	return connected;
		173	}
		174
2997	Serge	175	/**
		176	* r100_hpd_set_polarity - hpd set polarity callback.
		177	*
		178	* @rdev: radeon_device pointer
		179	* @hpd: hpd (hotplug detect) pin
		180	*
		181	* Set the polarity of the hpd pin (r1xx-r4xx).
		182	*/
1321	serge	183	void r100_hpd_set_polarity(struct radeon_device *rdev,
		184	enum radeon_hpd_id hpd)
		185	{
		186	u32 tmp;
		187	bool connected = r100_hpd_sense(rdev, hpd);
		188
		189	switch (hpd) {
		190	case RADEON_HPD_1:
		191	tmp = RREG32(RADEON_FP_GEN_CNTL);
		192	if (connected)
		193	tmp &= ~RADEON_FP_DETECT_INT_POL;
		194	else
		195	tmp \|= RADEON_FP_DETECT_INT_POL;
		196	WREG32(RADEON_FP_GEN_CNTL, tmp);
		197	break;
		198	case RADEON_HPD_2:
		199	tmp = RREG32(RADEON_FP2_GEN_CNTL);
		200	if (connected)
		201	tmp &= ~RADEON_FP2_DETECT_INT_POL;
		202	else
		203	tmp \|= RADEON_FP2_DETECT_INT_POL;
		204	WREG32(RADEON_FP2_GEN_CNTL, tmp);
		205	break;
		206	default:
		207	break;
		208	}
		209	}
		210
2997	Serge	211	/**
		212	* r100_hpd_init - hpd setup callback.
		213	*
		214	* @rdev: radeon_device pointer
		215	*
		216	* Setup the hpd pins used by the card (r1xx-r4xx).
		217	* Set the polarity, and enable the hpd interrupts.
		218	*/
1321	serge	219	void r100_hpd_init(struct radeon_device *rdev)
		220	{
		221	struct drm_device *dev = rdev->ddev;
		222	struct drm_connector *connector;
2997	Serge	223	unsigned enable = 0;
1321	serge	224
		225	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		226	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2997	Serge	227	enable \|= 1 << radeon_connector->hpd.hpd;
		228	radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
1321	serge	229	}
2997	Serge	230	// radeon_irq_kms_enable_hpd(rdev, enable);
1321	serge	231	}
		232
2997	Serge	233	/**
		234	* r100_hpd_fini - hpd tear down callback.
		235	*
		236	* @rdev: radeon_device pointer
		237	*
		238	* Tear down the hpd pins used by the card (r1xx-r4xx).
		239	* Disable the hpd interrupts.
		240	*/
1321	serge	241	void r100_hpd_fini(struct radeon_device *rdev)
		242	{
		243	struct drm_device *dev = rdev->ddev;
		244	struct drm_connector *connector;
2997	Serge	245	unsigned disable = 0;
1321	serge	246
		247	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		248	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2997	Serge	249	disable \|= 1 << radeon_connector->hpd.hpd;
1321	serge	250	}
2997	Serge	251	// radeon_irq_kms_disable_hpd(rdev, disable);
1321	serge	252	}
		253
1117	serge	254	/*
		255	* PCI GART
		256	*/
		257	void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
		258	{
		259	/* TODO: can we do somethings here ? */
		260	/* It seems hw only cache one entry so we should discard this
		261	* entry otherwise if first GPU GART read hit this entry it
		262	* could end up in wrong address. */
		263	}
		264
1179	serge	265	int r100_pci_gart_init(struct radeon_device *rdev)
1117	serge	266	{
		267	int r;
		268
2997	Serge	269	if (rdev->gart.ptr) {
1963	serge	270	WARN(1, "R100 PCI GART already initialized\n");
1179	serge	271	return 0;
		272	}
1117	serge	273	/* Initialize common gart structure */
		274	r = radeon_gart_init(rdev);
1179	serge	275	if (r)
1117	serge	276	return r;
1268	serge	277	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
2997	Serge	278	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
		279	rdev->asic->gart.set_page = &r100_pci_gart_set_page;
1179	serge	280	return radeon_gart_table_ram_alloc(rdev);
		281	}
		282
		283	int r100_pci_gart_enable(struct radeon_device *rdev)
		284	{
		285	uint32_t tmp;
		286
1430	serge	287	radeon_gart_restore(rdev);
1117	serge	288	/* discard memory request outside of configured range */
		289	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		290	WREG32(RADEON_AIC_CNTL, tmp);
		291	/* set address range for PCI address translate */
1430	serge	292	WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
		293	WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
1117	serge	294	/* set PCI GART page-table base address */
		295	WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
		296	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_PCIGART_TRANSLATE_EN;
		297	WREG32(RADEON_AIC_CNTL, tmp);
		298	r100_pci_gart_tlb_flush(rdev);
2997	Serge	299	DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
		300	(unsigned)(rdev->mc.gtt_size >> 20),
		301	(unsigned long long)rdev->gart.table_addr);
1117	serge	302	rdev->gart.ready = true;
		303	return 0;
		304	}
		305
		306	void r100_pci_gart_disable(struct radeon_device *rdev)
		307	{
		308	uint32_t tmp;
		309
		310	/* discard memory request outside of configured range */
		311	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		312	WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
		313	WREG32(RADEON_AIC_LO_ADDR, 0);
		314	WREG32(RADEON_AIC_HI_ADDR, 0);
		315	}
		316
		317	int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
		318	{
2997	Serge	319	u32 *gtt = rdev->gart.ptr;
		320
1117	serge	321	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
		322	return -EINVAL;
		323	}
2997	Serge	324	gtt[i] = cpu_to_le32(lower_32_bits(addr));
1117	serge	325	return 0;
		326	}
		327
1179	serge	328	void r100_pci_gart_fini(struct radeon_device *rdev)
1117	serge	329	{
1963	serge	330	radeon_gart_fini(rdev);
1117	serge	331	r100_pci_gart_disable(rdev);
1179	serge	332	radeon_gart_table_ram_free(rdev);
1117	serge	333	}
		334
2005	serge	335	int r100_irq_set(struct radeon_device *rdev)
		336	{
		337	uint32_t tmp = 0;
1117	serge	338
2005	serge	339	if (!rdev->irq.installed) {
		340	WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
		341	WREG32(R_000040_GEN_INT_CNTL, 0);
		342	return -EINVAL;
		343	}
2997	Serge	344	if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2005	serge	345	tmp \|= RADEON_SW_INT_ENABLE;
		346	}
		347	if (rdev->irq.crtc_vblank_int[0] \|\|
2997	Serge	348	atomic_read(&rdev->irq.pflip[0])) {
2005	serge	349	tmp \|= RADEON_CRTC_VBLANK_MASK;
		350	}
		351	if (rdev->irq.crtc_vblank_int[1] \|\|
2997	Serge	352	atomic_read(&rdev->irq.pflip[1])) {
2005	serge	353	tmp \|= RADEON_CRTC2_VBLANK_MASK;
		354	}
		355	if (rdev->irq.hpd[0]) {
		356	tmp \|= RADEON_FP_DETECT_MASK;
		357	}
		358	if (rdev->irq.hpd[1]) {
		359	tmp \|= RADEON_FP2_DETECT_MASK;
		360	}
		361	WREG32(RADEON_GEN_INT_CNTL, tmp);
		362	return 0;
		363	}
		364
1221	serge	365	void r100_irq_disable(struct radeon_device *rdev)
1117	serge	366	{
1221	serge	367	u32 tmp;
1117	serge	368
1221	serge	369	WREG32(R_000040_GEN_INT_CNTL, 0);
		370	/* Wait and acknowledge irq */
		371	mdelay(1);
		372	tmp = RREG32(R_000044_GEN_INT_STATUS);
		373	WREG32(R_000044_GEN_INT_STATUS, tmp);
1117	serge	374	}
		375
2997	Serge	376	static uint32_t r100_irq_ack(struct radeon_device *rdev)
1117	serge	377	{
1221	serge	378	uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
1321	serge	379	uint32_t irq_mask = RADEON_SW_INT_TEST \|
		380	RADEON_CRTC_VBLANK_STAT \| RADEON_CRTC2_VBLANK_STAT \|
		381	RADEON_FP_DETECT_STAT \| RADEON_FP2_DETECT_STAT;
1117	serge	382
1221	serge	383	if (irqs) {
		384	WREG32(RADEON_GEN_INT_STATUS, irqs);
1129	serge	385	}
1221	serge	386	return irqs & irq_mask;
1117	serge	387	}
		388
2005	serge	389	int r100_irq_process(struct radeon_device *rdev)
		390	{
		391	uint32_t status, msi_rearm;
		392	bool queue_hotplug = false;
1117	serge	393
2005	serge	394	status = r100_irq_ack(rdev);
		395	if (!status) {
		396	return IRQ_NONE;
		397	}
		398	if (rdev->shutdown) {
		399	return IRQ_NONE;
		400	}
		401	while (status) {
		402	/* SW interrupt */
		403	if (status & RADEON_SW_INT_TEST) {
2997	Serge	404	radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
2005	serge	405	}
		406	/* Vertical blank interrupts */
		407	if (status & RADEON_CRTC_VBLANK_STAT) {
		408	if (rdev->irq.crtc_vblank_int[0]) {
		409	// drm_handle_vblank(rdev->ddev, 0);
		410	rdev->pm.vblank_sync = true;
		411	// wake_up(&rdev->irq.vblank_queue);
		412	}
		413	// if (rdev->irq.pflip[0])
		414	// radeon_crtc_handle_flip(rdev, 0);
		415	}
		416	if (status & RADEON_CRTC2_VBLANK_STAT) {
		417	if (rdev->irq.crtc_vblank_int[1]) {
		418	// drm_handle_vblank(rdev->ddev, 1);
		419	rdev->pm.vblank_sync = true;
		420	// wake_up(&rdev->irq.vblank_queue);
		421	}
		422	// if (rdev->irq.pflip[1])
		423	// radeon_crtc_handle_flip(rdev, 1);
		424	}
		425	if (status & RADEON_FP_DETECT_STAT) {
		426	queue_hotplug = true;
		427	DRM_DEBUG("HPD1\n");
		428	}
		429	if (status & RADEON_FP2_DETECT_STAT) {
		430	queue_hotplug = true;
		431	DRM_DEBUG("HPD2\n");
		432	}
		433	status = r100_irq_ack(rdev);
		434	}
		435	// if (queue_hotplug)
		436	// schedule_work(&rdev->hotplug_work);
		437	if (rdev->msi_enabled) {
		438	switch (rdev->family) {
		439	case CHIP_RS400:
		440	case CHIP_RS480:
		441	msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
		442	WREG32(RADEON_AIC_CNTL, msi_rearm);
		443	WREG32(RADEON_AIC_CNTL, msi_rearm \| RS400_MSI_REARM);
		444	break;
		445	default:
2997	Serge	446	WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
2005	serge	447	break;
		448	}
		449	}
		450	return IRQ_HANDLED;
		451	}
		452
1403	serge	453	u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
		454	{
		455	if (crtc == 0)
		456	return RREG32(RADEON_CRTC_CRNT_FRAME);
		457	else
		458	return RREG32(RADEON_CRTC2_CRNT_FRAME);
		459	}
1117	serge	460
1404	serge	461	/* Who ever call radeon_fence_emit should call ring_lock and ask
		462	* for enough space (today caller are ib schedule and buffer move) */
1117	serge	463	void r100_fence_ring_emit(struct radeon_device *rdev,
		464	struct radeon_fence *fence)
		465	{
2997	Serge	466	struct radeon_ring *ring = &rdev->ring[fence->ring];
		467
1404	serge	468	/* We have to make sure that caches are flushed before
		469	* CPU might read something from VRAM. */
2997	Serge	470	radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
		471	radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
		472	radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
		473	radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
1117	serge	474	/* Wait until IDLE & CLEAN */
2997	Serge	475	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
		476	radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN \| RADEON_WAIT_3D_IDLECLEAN);
		477	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		478	radeon_ring_write(ring, rdev->config.r100.hdp_cntl \|
1403	serge	479	RADEON_HDP_READ_BUFFER_INVALIDATE);
2997	Serge	480	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		481	radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
1117	serge	482	/* Emit fence sequence & fire IRQ */
2997	Serge	483	radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
		484	radeon_ring_write(ring, fence->seq);
		485	radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
		486	radeon_ring_write(ring, RADEON_SW_INT_FIRE);
1117	serge	487	}
		488
2997	Serge	489	void r100_semaphore_ring_emit(struct radeon_device *rdev,
		490	struct radeon_ring *ring,
		491	struct radeon_semaphore *semaphore,
		492	bool emit_wait)
		493	{
		494	/* Unused on older asics, since we don't have semaphores or multiple rings */
		495	BUG();
		496	}
		497
1117	serge	498	int r100_copy_blit(struct radeon_device *rdev,
		499	uint64_t src_offset,
		500	uint64_t dst_offset,
2997	Serge	501	unsigned num_gpu_pages,
		502	struct radeon_fence **fence)
1117	serge	503	{
2997	Serge	504	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1117	serge	505	uint32_t cur_pages;
2997	Serge	506	uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
1117	serge	507	uint32_t pitch;
		508	uint32_t stride_pixels;
		509	unsigned ndw;
		510	int num_loops;
		511	int r = 0;
		512
		513	/* radeon limited to 16k stride */
		514	stride_bytes &= 0x3fff;
		515	/* radeon pitch is /64 */
		516	pitch = stride_bytes / 64;
		517	stride_pixels = stride_bytes / 4;
2997	Serge	518	num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
1117	serge	519
		520	/* Ask for enough room for blit + flush + fence */
		521	ndw = 64 + (10 * num_loops);
2997	Serge	522	r = radeon_ring_lock(rdev, ring, ndw);
1117	serge	523	if (r) {
		524	DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
		525	return -EINVAL;
		526	}
2997	Serge	527	while (num_gpu_pages > 0) {
		528	cur_pages = num_gpu_pages;
1117	serge	529	if (cur_pages > 8191) {
		530	cur_pages = 8191;
		531	}
2997	Serge	532	num_gpu_pages -= cur_pages;
1117	serge	533
		534	/* pages are in Y direction - height
		535	page width in X direction - width */
2997	Serge	536	radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
		537	radeon_ring_write(ring,
1117	serge	538	RADEON_GMC_SRC_PITCH_OFFSET_CNTL \|
		539	RADEON_GMC_DST_PITCH_OFFSET_CNTL \|
		540	RADEON_GMC_SRC_CLIPPING \|
		541	RADEON_GMC_DST_CLIPPING \|
		542	RADEON_GMC_BRUSH_NONE \|
		543	(RADEON_COLOR_FORMAT_ARGB8888 << 8) \|
		544	RADEON_GMC_SRC_DATATYPE_COLOR \|
		545	RADEON_ROP3_S \|
		546	RADEON_DP_SRC_SOURCE_MEMORY \|
		547	RADEON_GMC_CLR_CMP_CNTL_DIS \|
		548	RADEON_GMC_WR_MSK_DIS);
2997	Serge	549	radeon_ring_write(ring, (pitch << 22) \| (src_offset >> 10));
		550	radeon_ring_write(ring, (pitch << 22) \| (dst_offset >> 10));
		551	radeon_ring_write(ring, (0x1fff) \| (0x1fff << 16));
		552	radeon_ring_write(ring, 0);
		553	radeon_ring_write(ring, (0x1fff) \| (0x1fff << 16));
		554	radeon_ring_write(ring, num_gpu_pages);
		555	radeon_ring_write(ring, num_gpu_pages);
		556	radeon_ring_write(ring, cur_pages \| (stride_pixels << 16));
1117	serge	557	}
2997	Serge	558	radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
		559	radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
		560	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
		561	radeon_ring_write(ring,
1117	serge	562	RADEON_WAIT_2D_IDLECLEAN \|
		563	RADEON_WAIT_HOST_IDLECLEAN \|
		564	RADEON_WAIT_DMA_GUI_IDLE);
		565	if (fence) {
2997	Serge	566	r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
1117	serge	567	}
2997	Serge	568	radeon_ring_unlock_commit(rdev, ring);
1117	serge	569	return r;
		570	}
		571
1179	serge	572	static int r100_cp_wait_for_idle(struct radeon_device *rdev)
		573	{
		574	unsigned i;
		575	u32 tmp;
		576
		577	for (i = 0; i < rdev->usec_timeout; i++) {
		578	tmp = RREG32(R_000E40_RBBM_STATUS);
		579	if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
		580	return 0;
		581	}
		582	udelay(1);
		583	}
		584	return -1;
		585	}
		586
2997	Serge	587	void r100_ring_start(struct radeon_device rdev, struct radeon_ring ring)
1117	serge	588	{
		589	int r;
		590
2997	Serge	591	r = radeon_ring_lock(rdev, ring, 2);
1117	serge	592	if (r) {
		593	return;
		594	}
2997	Serge	595	radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
		596	radeon_ring_write(ring,
1117	serge	597	RADEON_ISYNC_ANY2D_IDLE3D \|
		598	RADEON_ISYNC_ANY3D_IDLE2D \|
		599	RADEON_ISYNC_WAIT_IDLEGUI \|
		600	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
2997	Serge	601	radeon_ring_unlock_commit(rdev, ring);
1117	serge	602	}
		603
1221	serge	604
		605	/* Load the microcode for the CP */
		606	static int r100_cp_init_microcode(struct radeon_device *rdev)
1117	serge	607	{
1221	serge	608	struct platform_device *pdev;
		609	const char *fw_name = NULL;
		610	int err;
1117	serge	611
1963	serge	612	DRM_DEBUG_KMS("\n");
1117	serge	613
1412	serge	614	pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
		615	err = IS_ERR(pdev);
		616	if (err) {
		617	printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
		618	return -EINVAL;
		619	}
1117	serge	620	if ((rdev->family == CHIP_R100) \|\| (rdev->family == CHIP_RV100) \|\|
		621	(rdev->family == CHIP_RV200) \|\| (rdev->family == CHIP_RS100) \|\|
		622	(rdev->family == CHIP_RS200)) {
		623	DRM_INFO("Loading R100 Microcode\n");
1221	serge	624	fw_name = FIRMWARE_R100;
1117	serge	625	} else if ((rdev->family == CHIP_R200) \|\|
		626	(rdev->family == CHIP_RV250) \|\|
		627	(rdev->family == CHIP_RV280) \|\|
		628	(rdev->family == CHIP_RS300)) {
		629	DRM_INFO("Loading R200 Microcode\n");
1221	serge	630	fw_name = FIRMWARE_R200;
1117	serge	631	} else if ((rdev->family == CHIP_R300) \|\|
		632	(rdev->family == CHIP_R350) \|\|
		633	(rdev->family == CHIP_RV350) \|\|
		634	(rdev->family == CHIP_RV380) \|\|
		635	(rdev->family == CHIP_RS400) \|\|
		636	(rdev->family == CHIP_RS480)) {
		637	DRM_INFO("Loading R300 Microcode\n");
1221	serge	638	fw_name = FIRMWARE_R300;
1117	serge	639	} else if ((rdev->family == CHIP_R420) \|\|
		640	(rdev->family == CHIP_R423) \|\|
		641	(rdev->family == CHIP_RV410)) {
		642	DRM_INFO("Loading R400 Microcode\n");
1221	serge	643	fw_name = FIRMWARE_R420;
1117	serge	644	} else if ((rdev->family == CHIP_RS690) \|\|
		645	(rdev->family == CHIP_RS740)) {
		646	DRM_INFO("Loading RS690/RS740 Microcode\n");
1221	serge	647	fw_name = FIRMWARE_RS690;
1117	serge	648	} else if (rdev->family == CHIP_RS600) {
		649	DRM_INFO("Loading RS600 Microcode\n");
1221	serge	650	fw_name = FIRMWARE_RS600;
1117	serge	651	} else if ((rdev->family == CHIP_RV515) \|\|
		652	(rdev->family == CHIP_R520) \|\|
		653	(rdev->family == CHIP_RV530) \|\|
		654	(rdev->family == CHIP_R580) \|\|
		655	(rdev->family == CHIP_RV560) \|\|
		656	(rdev->family == CHIP_RV570)) {
		657	DRM_INFO("Loading R500 Microcode\n");
1221	serge	658	fw_name = FIRMWARE_R520;
1117	serge	659	}
1221	serge	660
1412	serge	661	err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
		662	platform_device_unregister(pdev);
1221	serge	663	if (err) {
		664	printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
		665	fw_name);
		666	} else if (rdev->me_fw->size % 8) {
		667	printk(KERN_ERR
		668	"radeon_cp: Bogus length %zu in firmware \"%s\"\n",
		669	rdev->me_fw->size, fw_name);
		670	err = -EINVAL;
		671	release_firmware(rdev->me_fw);
		672	rdev->me_fw = NULL;
1117	serge	673	}
1221	serge	674	return err;
1117	serge	675	}
		676
1221	serge	677	static void r100_cp_load_microcode(struct radeon_device *rdev)
		678	{
		679	const __be32 *fw_data;
		680	int i, size;
		681
		682	if (r100_gui_wait_for_idle(rdev)) {
		683	printk(KERN_WARNING "Failed to wait GUI idle while "
		684	"programming pipes. Bad things might happen.\n");
		685	}
		686
		687	if (rdev->me_fw) {
		688	size = rdev->me_fw->size / 4;
		689	fw_data = (const __be32 *)&rdev->me_fw->data[0];
		690	WREG32(RADEON_CP_ME_RAM_ADDR, 0);
		691	for (i = 0; i < size; i += 2) {
		692	WREG32(RADEON_CP_ME_RAM_DATAH,
		693	be32_to_cpup(&fw_data[i]));
		694	WREG32(RADEON_CP_ME_RAM_DATAL,
		695	be32_to_cpup(&fw_data[i + 1]));
		696	}
		697	}
		698	}
		699
1117	serge	700	int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
		701	{
2997	Serge	702	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1117	serge	703	unsigned rb_bufsz;
		704	unsigned rb_blksz;
		705	unsigned max_fetch;
		706	unsigned pre_write_timer;
		707	unsigned pre_write_limit;
		708	unsigned indirect2_start;
		709	unsigned indirect1_start;
		710	uint32_t tmp;
		711	int r;
		712
1129	serge	713	if (r100_debugfs_cp_init(rdev)) {
		714	DRM_ERROR("Failed to register debugfs file for CP !\n");
		715	}
1179	serge	716	if (!rdev->me_fw) {
		717	r = r100_cp_init_microcode(rdev);
		718	if (r) {
		719	DRM_ERROR("Failed to load firmware!\n");
		720	return r;
		721	}
		722	}
		723
1117	serge	724	/* Align ring size */
		725	rb_bufsz = drm_order(ring_size / 8);
		726	ring_size = (1 << (rb_bufsz + 1)) * 4;
		727	r100_cp_load_microcode(rdev);
2997	Serge	728	r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
		729	RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
		730	0, 0x7fffff, RADEON_CP_PACKET2);
1117	serge	731	if (r) {
		732	return r;
		733	}
		734	/* Each time the cp read 1024 bytes (16 dword/quadword) update
		735	* the rptr copy in system ram */
		736	rb_blksz = 9;
		737	/* cp will read 128bytes at a time (4 dwords) */
		738	max_fetch = 1;
2997	Serge	739	ring->align_mask = 16 - 1;
1117	serge	740	/* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
		741	pre_write_timer = 64;
		742	/* Force CP_RB_WPTR write if written more than one time before the
		743	* delay expire
		744	*/
		745	pre_write_limit = 0;
		746	/* Setup the cp cache like this (cache size is 96 dwords) :
		747	* RING 0 to 15
		748	* INDIRECT1 16 to 79
		749	* INDIRECT2 80 to 95
		750	* So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		751	* indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
		752	* indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		753	* Idea being that most of the gpu cmd will be through indirect1 buffer
		754	* so it gets the bigger cache.
		755	*/
		756	indirect2_start = 80;
		757	indirect1_start = 16;
		758	/* cp setup */
		759	WREG32(0x718, pre_write_timer \| (pre_write_limit << 28));
1268	serge	760	tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) \|
1117	serge	761	REG_SET(RADEON_RB_BLKSZ, rb_blksz) \|
1963	serge	762	REG_SET(RADEON_MAX_FETCH, max_fetch));
1268	serge	763	#ifdef __BIG_ENDIAN
		764	tmp \|= RADEON_BUF_SWAP_32BIT;
		765	#endif
1963	serge	766	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_NO_UPDATE);
1268	serge	767
1117	serge	768	/* Set ring address */
2997	Serge	769	DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
		770	WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1117	serge	771	/* Force read & write ptr to 0 */
1963	serge	772	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA \| RADEON_RB_NO_UPDATE);
1117	serge	773	WREG32(RADEON_CP_RB_RPTR_WR, 0);
2997	Serge	774	ring->wptr = 0;
		775	WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1963	serge	776
		777	/* set the wb address whether it's enabled or not */
		778	WREG32(R_00070C_CP_RB_RPTR_ADDR,
		779	S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
		780	WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
		781
		782	if (rdev->wb.enabled)
		783	WREG32(R_000770_SCRATCH_UMSK, 0xff);
		784	else {
		785	tmp \|= RADEON_RB_NO_UPDATE;
		786	WREG32(R_000770_SCRATCH_UMSK, 0);
		787	}
		788
1117	serge	789	WREG32(RADEON_CP_RB_CNTL, tmp);
		790	udelay(10);
2997	Serge	791	ring->rptr = RREG32(RADEON_CP_RB_RPTR);
1117	serge	792	/* Set cp mode to bus mastering & enable cp*/
		793	WREG32(RADEON_CP_CSQ_MODE,
		794	REG_SET(RADEON_INDIRECT2_START, indirect2_start) \|
		795	REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1963	serge	796	WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
		797	WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1117	serge	798	WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
2997	Serge	799	radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
		800	r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1117	serge	801	if (r) {
		802	DRM_ERROR("radeon: cp isn't working (%d).\n", r);
		803	return r;
		804	}
2997	Serge	805	ring->ready = true;
3192	Serge	806	radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
		807
		808	if (!ring->rptr_save_reg /* not resuming from suspend */
		809	&& radeon_ring_supports_scratch_reg(rdev, ring)) {
		810	r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
		811	if (r) {
		812	DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
		813	ring->rptr_save_reg = 0;
		814	}
		815	}
1117	serge	816	return 0;
		817	}
		818
		819	void r100_cp_fini(struct radeon_device *rdev)
		820	{
1179	serge	821	if (r100_cp_wait_for_idle(rdev)) {
		822	DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
		823	}
1117	serge	824	/* Disable ring */
1179	serge	825	r100_cp_disable(rdev);
3192	Serge	826	radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
2997	Serge	827	radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1117	serge	828	DRM_INFO("radeon: cp finalized\n");
		829	}
		830
		831	void r100_cp_disable(struct radeon_device *rdev)
		832	{
		833	/* Disable ring */
3192	Serge	834	radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2997	Serge	835	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1117	serge	836	WREG32(RADEON_CP_CSQ_MODE, 0);
		837	WREG32(RADEON_CP_CSQ_CNTL, 0);
1963	serge	838	WREG32(R_000770_SCRATCH_UMSK, 0);
1117	serge	839	if (r100_gui_wait_for_idle(rdev)) {
		840	printk(KERN_WARNING "Failed to wait GUI idle while "
		841	"programming pipes. Bad things might happen.\n");
		842	}
		843	}
		844
2997	Serge	845	#if 0
		846	/*
		847	* CS functions
		848	*/
		849	int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
		850	struct radeon_cs_packet *pkt,
		851	unsigned idx,
		852	unsigned reg)
1179	serge	853	{
2997	Serge	854	int r;
		855	u32 tile_flags = 0;
		856	u32 tmp;
		857	struct radeon_cs_reloc *reloc;
		858	u32 value;
		859
		860	r = r100_cs_packet_next_reloc(p, &reloc);
		861	if (r) {
		862	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		863	idx, reg);
		864	r100_cs_dump_packet(p, pkt);
		865	return r;
		866	}
		867
		868	value = radeon_get_ib_value(p, idx);
		869	tmp = value & 0x003fffff;
		870	tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
		871
		872	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
		873	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		874	tile_flags \|= RADEON_DST_TILE_MACRO;
		875	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
		876	if (reg == RADEON_SRC_PITCH_OFFSET) {
		877	DRM_ERROR("Cannot src blit from microtiled surface\n");
		878	r100_cs_dump_packet(p, pkt);
		879	return -EINVAL;
		880	}
		881	tile_flags \|= RADEON_DST_TILE_MICRO;
		882	}
		883
		884	tmp \|= tile_flags;
		885	p->ib.ptr[idx] = (value & 0x3fc00000) \| tmp;
		886	} else
		887	p->ib.ptr[idx] = (value & 0xffc00000) \| tmp;
		888	return 0;
1179	serge	889	}
		890
2997	Serge	891	int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
		892	struct radeon_cs_packet *pkt,
		893	int idx)
		894	{
		895	unsigned c, i;
		896	struct radeon_cs_reloc *reloc;
		897	struct r100_cs_track *track;
		898	int r = 0;
		899	volatile uint32_t *ib;
		900	u32 idx_value;
1179	serge	901
2997	Serge	902	ib = p->ib.ptr;
		903	track = (struct r100_cs_track *)p->track;
		904	c = radeon_get_ib_value(p, idx++) & 0x1F;
		905	if (c > 16) {
		906	DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
		907	pkt->opcode);
		908	r100_cs_dump_packet(p, pkt);
		909	return -EINVAL;
		910	}
		911	track->num_arrays = c;
		912	for (i = 0; i < (c - 1); i+=2, idx+=3) {
		913	r = r100_cs_packet_next_reloc(p, &reloc);
		914	if (r) {
		915	DRM_ERROR("No reloc for packet3 %d\n",
		916	pkt->opcode);
		917	r100_cs_dump_packet(p, pkt);
		918	return r;
		919	}
		920	idx_value = radeon_get_ib_value(p, idx);
		921	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
		922
		923	track->arrays[i + 0].esize = idx_value >> 8;
		924	track->arrays[i + 0].robj = reloc->robj;
		925	track->arrays[i + 0].esize &= 0x7F;
		926	r = r100_cs_packet_next_reloc(p, &reloc);
		927	if (r) {
		928	DRM_ERROR("No reloc for packet3 %d\n",
		929	pkt->opcode);
		930	r100_cs_dump_packet(p, pkt);
		931	return r;
		932	}
		933	ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
		934	track->arrays[i + 1].robj = reloc->robj;
		935	track->arrays[i + 1].esize = idx_value >> 24;
		936	track->arrays[i + 1].esize &= 0x7F;
		937	}
		938	if (c & 1) {
		939	r = r100_cs_packet_next_reloc(p, &reloc);
		940	if (r) {
		941	DRM_ERROR("No reloc for packet3 %d\n",
		942	pkt->opcode);
		943	r100_cs_dump_packet(p, pkt);
		944	return r;
		945	}
		946	idx_value = radeon_get_ib_value(p, idx);
		947	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
		948	track->arrays[i + 0].robj = reloc->robj;
		949	track->arrays[i + 0].esize = idx_value >> 8;
		950	track->arrays[i + 0].esize &= 0x7F;
		951	}
		952	return r;
		953	}
		954
1117	serge	955	int r100_cs_parse_packet0(struct radeon_cs_parser *p,
		956	struct radeon_cs_packet *pkt,
		957	const unsigned *auth, unsigned n,
		958	radeon_packet0_check_t check)
		959	{
		960	unsigned reg;
		961	unsigned i, j, m;
		962	unsigned idx;
		963	int r;
		964
		965	idx = pkt->idx + 1;
		966	reg = pkt->reg;
		967	/* Check that register fall into register range
		968	* determined by the number of entry (n) in the
		969	* safe register bitmap.
		970	*/
		971	if (pkt->one_reg_wr) {
		972	if ((reg >> 7) > n) {
		973	return -EINVAL;
		974	}
		975	} else {
		976	if (((reg + (pkt->count << 2)) >> 7) > n) {
		977	return -EINVAL;
		978	}
		979	}
		980	for (i = 0; i <= pkt->count; i++, idx++) {
		981	j = (reg >> 7);
		982	m = 1 << ((reg >> 2) & 31);
		983	if (auth[j] & m) {
		984	r = check(p, pkt, idx, reg);
		985	if (r) {
		986	return r;
		987	}
		988	}
		989	if (pkt->one_reg_wr) {
		990	if (!(auth[j] & m)) {
		991	break;
		992	}
		993	} else {
		994	reg += 4;
		995	}
		996	}
		997	return 0;
		998	}
		999
		1000	void r100_cs_dump_packet(struct radeon_cs_parser *p,
		1001	struct radeon_cs_packet *pkt)
		1002	{
		1003	volatile uint32_t *ib;
		1004	unsigned i;
		1005	unsigned idx;
		1006
2997	Serge	1007	ib = p->ib.ptr;
1117	serge	1008	idx = pkt->idx;
		1009	for (i = 0; i <= (pkt->count + 1); i++, idx++) {
		1010	DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
		1011	}
		1012	}
		1013
		1014	/**
		1015	* r100_cs_packet_parse() - parse cp packet and point ib index to next packet
		1016	* @parser: parser structure holding parsing context.
		1017	* @pkt: where to store packet informations
		1018	*
		1019	* Assume that chunk_ib_index is properly set. Will return -EINVAL
		1020	* if packet is bigger than remaining ib size. or if packets is unknown.
		1021	**/
		1022	int r100_cs_packet_parse(struct radeon_cs_parser *p,
		1023	struct radeon_cs_packet *pkt,
		1024	unsigned idx)
		1025	{
		1026	struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1179	serge	1027	uint32_t header;
1117	serge	1028
		1029	if (idx >= ib_chunk->length_dw) {
		1030	DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
		1031	idx, ib_chunk->length_dw);
		1032	return -EINVAL;
		1033	}
1221	serge	1034	header = radeon_get_ib_value(p, idx);
1117	serge	1035	pkt->idx = idx;
		1036	pkt->type = CP_PACKET_GET_TYPE(header);
		1037	pkt->count = CP_PACKET_GET_COUNT(header);
		1038	switch (pkt->type) {
		1039	case PACKET_TYPE0:
		1040	pkt->reg = CP_PACKET0_GET_REG(header);
		1041	pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
		1042	break;
		1043	case PACKET_TYPE3:
		1044	pkt->opcode = CP_PACKET3_GET_OPCODE(header);
		1045	break;
		1046	case PACKET_TYPE2:
		1047	pkt->count = -1;
		1048	break;
		1049	default:
		1050	DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
		1051	return -EINVAL;
		1052	}
		1053	if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
		1054	DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
		1055	pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
		1056	return -EINVAL;
		1057	}
		1058	return 0;
		1059	}
		1060
		1061	/**
1179	serge	1062	* r100_cs_packet_next_vline() - parse userspace VLINE packet
		1063	* @parser: parser structure holding parsing context.
		1064	*
		1065	* Userspace sends a special sequence for VLINE waits.
		1066	* PACKET0 - VLINE_START_END + value
		1067	* PACKET0 - WAIT_UNTIL +_value
		1068	* RELOC (P3) - crtc_id in reloc.
		1069	*
		1070	* This function parses this and relocates the VLINE START END
		1071	* and WAIT UNTIL packets to the correct crtc.
		1072	* It also detects a switched off crtc and nulls out the
		1073	* wait in that case.
		1074	*/
		1075	int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
		1076	{
		1077	struct drm_mode_object *obj;
		1078	struct drm_crtc *crtc;
		1079	struct radeon_crtc *radeon_crtc;
		1080	struct radeon_cs_packet p3reloc, waitreloc;
		1081	int crtc_id;
		1082	int r;
		1083	uint32_t header, h_idx, reg;
1221	serge	1084	volatile uint32_t *ib;
1179	serge	1085
2997	Serge	1086	ib = p->ib.ptr;
1179	serge	1087
		1088	/* parse the wait until */
		1089	r = r100_cs_packet_parse(p, &waitreloc, p->idx);
		1090	if (r)
		1091	return r;
		1092
		1093	/* check its a wait until and only 1 count */
		1094	if (waitreloc.reg != RADEON_WAIT_UNTIL \|\|
		1095	waitreloc.count != 0) {
		1096	DRM_ERROR("vline wait had illegal wait until segment\n");
1963	serge	1097	return -EINVAL;
1179	serge	1098	}
		1099
1221	serge	1100	if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1179	serge	1101	DRM_ERROR("vline wait had illegal wait until\n");
1963	serge	1102	return -EINVAL;
1179	serge	1103	}
		1104
		1105	/* jump over the NOP */
1221	serge	1106	r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1179	serge	1107	if (r)
		1108	return r;
		1109
		1110	h_idx = p->idx - 2;
1221	serge	1111	p->idx += waitreloc.count + 2;
		1112	p->idx += p3reloc.count + 2;
1179	serge	1113
1221	serge	1114	header = radeon_get_ib_value(p, h_idx);
		1115	crtc_id = radeon_get_ib_value(p, h_idx + 5);
		1116	reg = CP_PACKET0_GET_REG(header);
1179	serge	1117	obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
		1118	if (!obj) {
		1119	DRM_ERROR("cannot find crtc %d\n", crtc_id);
1963	serge	1120	return -EINVAL;
1179	serge	1121	}
		1122	crtc = obj_to_crtc(obj);
		1123	radeon_crtc = to_radeon_crtc(crtc);
		1124	crtc_id = radeon_crtc->crtc_id;
		1125
		1126	if (!crtc->enabled) {
		1127	/* if the CRTC isn't enabled - we need to nop out the wait until */
1221	serge	1128	ib[h_idx + 2] = PACKET2(0);
		1129	ib[h_idx + 3] = PACKET2(0);
1179	serge	1130	} else if (crtc_id == 1) {
		1131	switch (reg) {
		1132	case AVIVO_D1MODE_VLINE_START_END:
1221	serge	1133	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	1134	header \|= AVIVO_D2MODE_VLINE_START_END >> 2;
		1135	break;
		1136	case RADEON_CRTC_GUI_TRIG_VLINE:
1221	serge	1137	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	1138	header \|= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
		1139	break;
		1140	default:
		1141	DRM_ERROR("unknown crtc reloc\n");
1963	serge	1142	return -EINVAL;
1179	serge	1143	}
1221	serge	1144	ib[h_idx] = header;
		1145	ib[h_idx + 3] \|= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1179	serge	1146	}
1963	serge	1147
		1148	return 0;
1179	serge	1149	}
		1150
		1151	/**
1117	serge	1152	* r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
		1153	* @parser: parser structure holding parsing context.
		1154	* @data: pointer to relocation data
		1155	* @offset_start: starting offset
		1156	* @offset_mask: offset mask (to align start offset on)
		1157	* @reloc: reloc informations
		1158	*
		1159	* Check next packet is relocation packet3, do bo validation and compute
		1160	* GPU offset using the provided start.
		1161	**/
		1162	int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
		1163	struct radeon_cs_reloc **cs_reloc)
		1164	{
		1165	struct radeon_cs_chunk *relocs_chunk;
		1166	struct radeon_cs_packet p3reloc;
		1167	unsigned idx;
		1168	int r;
		1169
		1170	if (p->chunk_relocs_idx == -1) {
		1171	DRM_ERROR("No relocation chunk !\n");
		1172	return -EINVAL;
		1173	}
		1174	*cs_reloc = NULL;
		1175	relocs_chunk = &p->chunks[p->chunk_relocs_idx];
		1176	r = r100_cs_packet_parse(p, &p3reloc, p->idx);
		1177	if (r) {
		1178	return r;
		1179	}
		1180	p->idx += p3reloc.count + 2;
		1181	if (p3reloc.type != PACKET_TYPE3 \|\| p3reloc.opcode != PACKET3_NOP) {
		1182	DRM_ERROR("No packet3 for relocation for packet at %d.\n",
		1183	p3reloc.idx);
		1184	r100_cs_dump_packet(p, &p3reloc);
		1185	return -EINVAL;
		1186	}
1221	serge	1187	idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1117	serge	1188	if (idx >= relocs_chunk->length_dw) {
		1189	DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
		1190	idx, relocs_chunk->length_dw);
		1191	r100_cs_dump_packet(p, &p3reloc);
		1192	return -EINVAL;
		1193	}
		1194	/* FIXME: we assume reloc size is 4 dwords */
		1195	*cs_reloc = p->relocs_ptr[(idx / 4)];
		1196	return 0;
		1197	}
		1198
1179	serge	1199	static int r100_get_vtx_size(uint32_t vtx_fmt)
		1200	{
		1201	int vtx_size;
		1202	vtx_size = 2;
		1203	/* ordered according to bits in spec */
		1204	if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
		1205	vtx_size++;
		1206	if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
		1207	vtx_size += 3;
		1208	if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
		1209	vtx_size++;
		1210	if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
		1211	vtx_size++;
		1212	if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
		1213	vtx_size += 3;
		1214	if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
		1215	vtx_size++;
		1216	if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
		1217	vtx_size++;
		1218	if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
		1219	vtx_size += 2;
		1220	if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
		1221	vtx_size += 2;
		1222	if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
		1223	vtx_size++;
		1224	if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
		1225	vtx_size += 2;
		1226	if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
		1227	vtx_size++;
		1228	if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
		1229	vtx_size += 2;
		1230	if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
		1231	vtx_size++;
		1232	if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
		1233	vtx_size++;
		1234	/* blend weight */
		1235	if (vtx_fmt & (0x7 << 15))
		1236	vtx_size += (vtx_fmt >> 15) & 0x7;
		1237	if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
		1238	vtx_size += 3;
		1239	if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
		1240	vtx_size += 2;
		1241	if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
		1242	vtx_size++;
		1243	if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
		1244	vtx_size++;
		1245	if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
		1246	vtx_size++;
		1247	if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
		1248	vtx_size++;
		1249	return vtx_size;
		1250	}
		1251
1117	serge	1252	static int r100_packet0_check(struct radeon_cs_parser *p,
1179	serge	1253	struct radeon_cs_packet *pkt,
		1254	unsigned idx, unsigned reg)
1117	serge	1255	{
		1256	struct radeon_cs_reloc *reloc;
1179	serge	1257	struct r100_cs_track *track;
1117	serge	1258	volatile uint32_t *ib;
		1259	uint32_t tmp;
		1260	int r;
1179	serge	1261	int i, face;
		1262	u32 tile_flags = 0;
1221	serge	1263	u32 idx_value;
1117	serge	1264
2997	Serge	1265	ib = p->ib.ptr;
1179	serge	1266	track = (struct r100_cs_track *)p->track;
		1267
1221	serge	1268	idx_value = radeon_get_ib_value(p, idx);
		1269
1117	serge	1270	switch (reg) {
1179	serge	1271	case RADEON_CRTC_GUI_TRIG_VLINE:
		1272	r = r100_cs_packet_parse_vline(p);
		1273	if (r) {
		1274	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1275	idx, reg);
		1276	r100_cs_dump_packet(p, pkt);
		1277	return r;
		1278	}
		1279	break;
1117	serge	1280	/* FIXME: only allow PACKET3 blit? easier to check for out of
		1281	* range access */
		1282	case RADEON_DST_PITCH_OFFSET:
		1283	case RADEON_SRC_PITCH_OFFSET:
1179	serge	1284	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		1285	if (r)
		1286	return r;
		1287	break;
		1288	case RADEON_RB3D_DEPTHOFFSET:
1117	serge	1289	r = r100_cs_packet_next_reloc(p, &reloc);
		1290	if (r) {
		1291	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1292	idx, reg);
		1293	r100_cs_dump_packet(p, pkt);
		1294	return r;
		1295	}
1179	serge	1296	track->zb.robj = reloc->robj;
1221	serge	1297	track->zb.offset = idx_value;
1963	serge	1298	track->zb_dirty = true;
1221	serge	1299	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1117	serge	1300	break;
		1301	case RADEON_RB3D_COLOROFFSET:
1179	serge	1302	r = r100_cs_packet_next_reloc(p, &reloc);
		1303	if (r) {
		1304	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1305	idx, reg);
		1306	r100_cs_dump_packet(p, pkt);
		1307	return r;
		1308	}
		1309	track->cb[0].robj = reloc->robj;
1221	serge	1310	track->cb[0].offset = idx_value;
1963	serge	1311	track->cb_dirty = true;
1221	serge	1312	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1313	break;
1117	serge	1314	case RADEON_PP_TXOFFSET_0:
		1315	case RADEON_PP_TXOFFSET_1:
		1316	case RADEON_PP_TXOFFSET_2:
1179	serge	1317	i = (reg - RADEON_PP_TXOFFSET_0) / 24;
		1318	r = r100_cs_packet_next_reloc(p, &reloc);
		1319	if (r) {
		1320	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1321	idx, reg);
		1322	r100_cs_dump_packet(p, pkt);
		1323	return r;
		1324	}
2997	Serge	1325	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
		1326	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		1327	tile_flags \|= RADEON_TXO_MACRO_TILE;
		1328	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		1329	tile_flags \|= RADEON_TXO_MICRO_TILE_X2;
		1330
		1331	tmp = idx_value & ~(0x7 << 2);
		1332	tmp \|= tile_flags;
		1333	ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
		1334	} else
1221	serge	1335	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1336	track->textures[i].robj = reloc->robj;
1963	serge	1337	track->tex_dirty = true;
1179	serge	1338	break;
		1339	case RADEON_PP_CUBIC_OFFSET_T0_0:
		1340	case RADEON_PP_CUBIC_OFFSET_T0_1:
		1341	case RADEON_PP_CUBIC_OFFSET_T0_2:
		1342	case RADEON_PP_CUBIC_OFFSET_T0_3:
		1343	case RADEON_PP_CUBIC_OFFSET_T0_4:
		1344	i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
		1345	r = r100_cs_packet_next_reloc(p, &reloc);
		1346	if (r) {
		1347	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1348	idx, reg);
		1349	r100_cs_dump_packet(p, pkt);
		1350	return r;
		1351	}
1221	serge	1352	track->textures[0].cube_info[i].offset = idx_value;
		1353	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1354	track->textures[0].cube_info[i].robj = reloc->robj;
1963	serge	1355	track->tex_dirty = true;
1179	serge	1356	break;
		1357	case RADEON_PP_CUBIC_OFFSET_T1_0:
		1358	case RADEON_PP_CUBIC_OFFSET_T1_1:
		1359	case RADEON_PP_CUBIC_OFFSET_T1_2:
		1360	case RADEON_PP_CUBIC_OFFSET_T1_3:
		1361	case RADEON_PP_CUBIC_OFFSET_T1_4:
		1362	i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
		1363	r = r100_cs_packet_next_reloc(p, &reloc);
		1364	if (r) {
		1365	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1366	idx, reg);
		1367	r100_cs_dump_packet(p, pkt);
		1368	return r;
		1369	}
1221	serge	1370	track->textures[1].cube_info[i].offset = idx_value;
		1371	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1372	track->textures[1].cube_info[i].robj = reloc->robj;
1963	serge	1373	track->tex_dirty = true;
1179	serge	1374	break;
		1375	case RADEON_PP_CUBIC_OFFSET_T2_0:
		1376	case RADEON_PP_CUBIC_OFFSET_T2_1:
		1377	case RADEON_PP_CUBIC_OFFSET_T2_2:
		1378	case RADEON_PP_CUBIC_OFFSET_T2_3:
		1379	case RADEON_PP_CUBIC_OFFSET_T2_4:
		1380	i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1117	serge	1381	r = r100_cs_packet_next_reloc(p, &reloc);
		1382	if (r) {
		1383	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1384	idx, reg);
		1385	r100_cs_dump_packet(p, pkt);
		1386	return r;
		1387	}
1221	serge	1388	track->textures[2].cube_info[i].offset = idx_value;
		1389	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1390	track->textures[2].cube_info[i].robj = reloc->robj;
1963	serge	1391	track->tex_dirty = true;
1179	serge	1392	break;
		1393	case RADEON_RE_WIDTH_HEIGHT:
1221	serge	1394	track->maxy = ((idx_value >> 16) & 0x7FF);
1963	serge	1395	track->cb_dirty = true;
		1396	track->zb_dirty = true;
1117	serge	1397	break;
1179	serge	1398	case RADEON_RB3D_COLORPITCH:
		1399	r = r100_cs_packet_next_reloc(p, &reloc);
		1400	if (r) {
		1401	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1402	idx, reg);
		1403	r100_cs_dump_packet(p, pkt);
		1404	return r;
		1405	}
2997	Serge	1406	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1179	serge	1407	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		1408	tile_flags \|= RADEON_COLOR_TILE_ENABLE;
		1409	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		1410	tile_flags \|= RADEON_COLOR_MICROTILE_ENABLE;
		1411
1221	serge	1412	tmp = idx_value & ~(0x7 << 16);
1179	serge	1413	tmp \|= tile_flags;
		1414	ib[idx] = tmp;
2997	Serge	1415	} else
		1416	ib[idx] = idx_value;
1179	serge	1417
1221	serge	1418	track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1963	serge	1419	track->cb_dirty = true;
1179	serge	1420	break;
		1421	case RADEON_RB3D_DEPTHPITCH:
1221	serge	1422	track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1963	serge	1423	track->zb_dirty = true;
1179	serge	1424	break;
		1425	case RADEON_RB3D_CNTL:
1221	serge	1426	switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1179	serge	1427	case 7:
		1428	case 8:
		1429	case 9:
		1430	case 11:
		1431	case 12:
		1432	track->cb[0].cpp = 1;
		1433	break;
		1434	case 3:
		1435	case 4:
		1436	case 15:
		1437	track->cb[0].cpp = 2;
		1438	break;
		1439	case 6:
		1440	track->cb[0].cpp = 4;
		1441	break;
1117	serge	1442	default:
1179	serge	1443	DRM_ERROR("Invalid color buffer format (%d) !\n",
1221	serge	1444	((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1179	serge	1445	return -EINVAL;
		1446	}
1221	serge	1447	track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1963	serge	1448	track->cb_dirty = true;
		1449	track->zb_dirty = true;
1179	serge	1450	break;
		1451	case RADEON_RB3D_ZSTENCILCNTL:
1221	serge	1452	switch (idx_value & 0xf) {
1179	serge	1453	case 0:
		1454	track->zb.cpp = 2;
1117	serge	1455	break;
1179	serge	1456	case 2:
		1457	case 3:
		1458	case 4:
		1459	case 5:
		1460	case 9:
		1461	case 11:
		1462	track->zb.cpp = 4;
		1463	break;
		1464	default:
		1465	break;
1117	serge	1466	}
1963	serge	1467	track->zb_dirty = true;
1117	serge	1468	break;
1179	serge	1469	case RADEON_RB3D_ZPASS_ADDR:
		1470	r = r100_cs_packet_next_reloc(p, &reloc);
		1471	if (r) {
		1472	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1473	idx, reg);
		1474	r100_cs_dump_packet(p, pkt);
		1475	return r;
		1476	}
1221	serge	1477	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1478	break;
		1479	case RADEON_PP_CNTL:
		1480	{
1221	serge	1481	uint32_t temp = idx_value >> 4;
1179	serge	1482	for (i = 0; i < track->num_texture; i++)
		1483	track->textures[i].enabled = !!(temp & (1 << i));
1963	serge	1484	track->tex_dirty = true;
1117	serge	1485	}
1179	serge	1486	break;
		1487	case RADEON_SE_VF_CNTL:
1221	serge	1488	track->vap_vf_cntl = idx_value;
1179	serge	1489	break;
		1490	case RADEON_SE_VTX_FMT:
1221	serge	1491	track->vtx_size = r100_get_vtx_size(idx_value);
1179	serge	1492	break;
		1493	case RADEON_PP_TEX_SIZE_0:
		1494	case RADEON_PP_TEX_SIZE_1:
		1495	case RADEON_PP_TEX_SIZE_2:
		1496	i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1221	serge	1497	track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
		1498	track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1963	serge	1499	track->tex_dirty = true;
1179	serge	1500	break;
		1501	case RADEON_PP_TEX_PITCH_0:
		1502	case RADEON_PP_TEX_PITCH_1:
		1503	case RADEON_PP_TEX_PITCH_2:
		1504	i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1221	serge	1505	track->textures[i].pitch = idx_value + 32;
1963	serge	1506	track->tex_dirty = true;
1179	serge	1507	break;
		1508	case RADEON_PP_TXFILTER_0:
		1509	case RADEON_PP_TXFILTER_1:
		1510	case RADEON_PP_TXFILTER_2:
		1511	i = (reg - RADEON_PP_TXFILTER_0) / 24;
1221	serge	1512	track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1179	serge	1513	>> RADEON_MAX_MIP_LEVEL_SHIFT);
1221	serge	1514	tmp = (idx_value >> 23) & 0x7;
1179	serge	1515	if (tmp == 2 \|\| tmp == 6)
		1516	track->textures[i].roundup_w = false;
1221	serge	1517	tmp = (idx_value >> 27) & 0x7;
1179	serge	1518	if (tmp == 2 \|\| tmp == 6)
		1519	track->textures[i].roundup_h = false;
1963	serge	1520	track->tex_dirty = true;
1179	serge	1521	break;
		1522	case RADEON_PP_TXFORMAT_0:
		1523	case RADEON_PP_TXFORMAT_1:
		1524	case RADEON_PP_TXFORMAT_2:
		1525	i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1221	serge	1526	if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1179	serge	1527	track->textures[i].use_pitch = 1;
		1528	} else {
		1529	track->textures[i].use_pitch = 0;
1221	serge	1530	track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
		1531	track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1179	serge	1532	}
1221	serge	1533	if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1179	serge	1534	track->textures[i].tex_coord_type = 2;
1221	serge	1535	switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1179	serge	1536	case RADEON_TXFORMAT_I8:
		1537	case RADEON_TXFORMAT_RGB332:
		1538	case RADEON_TXFORMAT_Y8:
		1539	track->textures[i].cpp = 1;
1963	serge	1540	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1541	break;
		1542	case RADEON_TXFORMAT_AI88:
		1543	case RADEON_TXFORMAT_ARGB1555:
		1544	case RADEON_TXFORMAT_RGB565:
		1545	case RADEON_TXFORMAT_ARGB4444:
		1546	case RADEON_TXFORMAT_VYUY422:
		1547	case RADEON_TXFORMAT_YVYU422:
		1548	case RADEON_TXFORMAT_SHADOW16:
		1549	case RADEON_TXFORMAT_LDUDV655:
		1550	case RADEON_TXFORMAT_DUDV88:
		1551	track->textures[i].cpp = 2;
1963	serge	1552	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1553	break;
		1554	case RADEON_TXFORMAT_ARGB8888:
		1555	case RADEON_TXFORMAT_RGBA8888:
		1556	case RADEON_TXFORMAT_SHADOW32:
		1557	case RADEON_TXFORMAT_LDUDUV8888:
		1558	track->textures[i].cpp = 4;
1963	serge	1559	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1560	break;
1403	serge	1561	case RADEON_TXFORMAT_DXT1:
		1562	track->textures[i].cpp = 1;
		1563	track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
		1564	break;
		1565	case RADEON_TXFORMAT_DXT23:
		1566	case RADEON_TXFORMAT_DXT45:
		1567	track->textures[i].cpp = 1;
		1568	track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
		1569	break;
1179	serge	1570	}
1221	serge	1571	track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
		1572	track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1963	serge	1573	track->tex_dirty = true;
1179	serge	1574	break;
		1575	case RADEON_PP_CUBIC_FACES_0:
		1576	case RADEON_PP_CUBIC_FACES_1:
		1577	case RADEON_PP_CUBIC_FACES_2:
1221	serge	1578	tmp = idx_value;
1179	serge	1579	i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
		1580	for (face = 0; face < 4; face++) {
		1581	track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
		1582	track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
		1583	}
1963	serge	1584	track->tex_dirty = true;
1179	serge	1585	break;
		1586	default:
		1587	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
		1588	reg, idx);
		1589	return -EINVAL;
1117	serge	1590	}
		1591	return 0;
		1592	}
		1593
		1594	int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
		1595	struct radeon_cs_packet *pkt,
1321	serge	1596	struct radeon_bo *robj)
1117	serge	1597	{
		1598	unsigned idx;
1221	serge	1599	u32 value;
1117	serge	1600	idx = pkt->idx + 1;
1221	serge	1601	value = radeon_get_ib_value(p, idx + 2);
1321	serge	1602	if ((value + 1) > radeon_bo_size(robj)) {
1117	serge	1603	DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
		1604	"(need %u have %lu) !\n",
1221	serge	1605	value + 1,
1321	serge	1606	radeon_bo_size(robj));
1117	serge	1607	return -EINVAL;
		1608	}
		1609	return 0;
		1610	}
		1611
		1612	static int r100_packet3_check(struct radeon_cs_parser *p,
		1613	struct radeon_cs_packet *pkt)
		1614	{
		1615	struct radeon_cs_reloc *reloc;
1179	serge	1616	struct r100_cs_track *track;
1117	serge	1617	unsigned idx;
		1618	volatile uint32_t *ib;
		1619	int r;
		1620
2997	Serge	1621	ib = p->ib.ptr;
1117	serge	1622	idx = pkt->idx + 1;
1179	serge	1623	track = (struct r100_cs_track *)p->track;
1117	serge	1624	switch (pkt->opcode) {
		1625	case PACKET3_3D_LOAD_VBPNTR:
1221	serge	1626	r = r100_packet3_load_vbpntr(p, pkt, idx);
		1627	if (r)
1117	serge	1628	return r;
		1629	break;
		1630	case PACKET3_INDX_BUFFER:
		1631	r = r100_cs_packet_next_reloc(p, &reloc);
		1632	if (r) {
		1633	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1634	r100_cs_dump_packet(p, pkt);
		1635	return r;
		1636	}
1221	serge	1637	ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1117	serge	1638	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		1639	if (r) {
		1640	return r;
		1641	}
		1642	break;
		1643	case 0x23:
		1644	/* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
		1645	r = r100_cs_packet_next_reloc(p, &reloc);
		1646	if (r) {
		1647	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1648	r100_cs_dump_packet(p, pkt);
		1649	return r;
		1650	}
1221	serge	1651	ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1179	serge	1652	track->num_arrays = 1;
1221	serge	1653	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1179	serge	1654
		1655	track->arrays[0].robj = reloc->robj;
		1656	track->arrays[0].esize = track->vtx_size;
		1657
1221	serge	1658	track->max_indx = radeon_get_ib_value(p, idx+1);
1179	serge	1659
1221	serge	1660	track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1179	serge	1661	track->immd_dwords = pkt->count - 1;
		1662	r = r100_cs_track_check(p->rdev, track);
		1663	if (r)
		1664	return r;
1117	serge	1665	break;
		1666	case PACKET3_3D_DRAW_IMMD:
1221	serge	1667	if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1179	serge	1668	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1669	return -EINVAL;
		1670	}
1403	serge	1671	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1221	serge	1672	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1673	track->immd_dwords = pkt->count - 1;
		1674	r = r100_cs_track_check(p->rdev, track);
		1675	if (r)
		1676	return r;
		1677	break;
1117	serge	1678	/* triggers drawing using in-packet vertex data */
		1679	case PACKET3_3D_DRAW_IMMD_2:
1221	serge	1680	if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1179	serge	1681	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1682	return -EINVAL;
		1683	}
1221	serge	1684	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1685	track->immd_dwords = pkt->count;
		1686	r = r100_cs_track_check(p->rdev, track);
		1687	if (r)
		1688	return r;
		1689	break;
1117	serge	1690	/* triggers drawing using in-packet vertex data */
		1691	case PACKET3_3D_DRAW_VBUF_2:
1221	serge	1692	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1693	r = r100_cs_track_check(p->rdev, track);
		1694	if (r)
		1695	return r;
		1696	break;
1117	serge	1697	/* triggers drawing of vertex buffers setup elsewhere */
		1698	case PACKET3_3D_DRAW_INDX_2:
1221	serge	1699	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1700	r = r100_cs_track_check(p->rdev, track);
		1701	if (r)
		1702	return r;
		1703	break;
1117	serge	1704	/* triggers drawing using indices to vertex buffer */
		1705	case PACKET3_3D_DRAW_VBUF:
1221	serge	1706	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1707	r = r100_cs_track_check(p->rdev, track);
		1708	if (r)
		1709	return r;
		1710	break;
1117	serge	1711	/* triggers drawing of vertex buffers setup elsewhere */
		1712	case PACKET3_3D_DRAW_INDX:
1221	serge	1713	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1714	r = r100_cs_track_check(p->rdev, track);
		1715	if (r)
		1716	return r;
		1717	break;
1117	serge	1718	/* triggers drawing using indices to vertex buffer */
1963	serge	1719	case PACKET3_3D_CLEAR_HIZ:
		1720	case PACKET3_3D_CLEAR_ZMASK:
		1721	if (p->rdev->hyperz_filp != p->filp)
		1722	return -EINVAL;
		1723	break;
1117	serge	1724	case PACKET3_NOP:
		1725	break;
		1726	default:
		1727	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		1728	return -EINVAL;
		1729	}
		1730	return 0;
		1731	}
		1732
		1733	int r100_cs_parse(struct radeon_cs_parser *p)
		1734	{
		1735	struct radeon_cs_packet pkt;
1179	serge	1736	struct r100_cs_track *track;
1117	serge	1737	int r;
		1738
1179	serge	1739	track = kzalloc(sizeof(*track), GFP_KERNEL);
2997	Serge	1740	if (!track)
		1741	return -ENOMEM;
1179	serge	1742	r100_cs_track_clear(p->rdev, track);
		1743	p->track = track;
1117	serge	1744	do {
		1745	r = r100_cs_packet_parse(p, &pkt, p->idx);
		1746	if (r) {
		1747	return r;
		1748	}
		1749	p->idx += pkt.count + 2;
		1750	switch (pkt.type) {
		1751	case PACKET_TYPE0:
1179	serge	1752	if (p->rdev->family >= CHIP_R200)
		1753	r = r100_cs_parse_packet0(p, &pkt,
		1754	p->rdev->config.r100.reg_safe_bm,
		1755	p->rdev->config.r100.reg_safe_bm_size,
		1756	&r200_packet0_check);
		1757	else
		1758	r = r100_cs_parse_packet0(p, &pkt,
		1759	p->rdev->config.r100.reg_safe_bm,
		1760	p->rdev->config.r100.reg_safe_bm_size,
		1761	&r100_packet0_check);
1117	serge	1762	break;
		1763	case PACKET_TYPE2:
		1764	break;
		1765	case PACKET_TYPE3:
		1766	r = r100_packet3_check(p, &pkt);
		1767	break;
		1768	default:
		1769	DRM_ERROR("Unknown packet type %d !\n",
		1770	pkt.type);
		1771	return -EINVAL;
		1772	}
		1773	if (r) {
		1774	return r;
		1775	}
		1776	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
		1777	return 0;
		1778	}
		1779
2997	Serge	1780	static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
		1781	{
		1782	DRM_ERROR("pitch %d\n", t->pitch);
		1783	DRM_ERROR("use_pitch %d\n", t->use_pitch);
		1784	DRM_ERROR("width %d\n", t->width);
		1785	DRM_ERROR("width_11 %d\n", t->width_11);
		1786	DRM_ERROR("height %d\n", t->height);
		1787	DRM_ERROR("height_11 %d\n", t->height_11);
		1788	DRM_ERROR("num levels %d\n", t->num_levels);
		1789	DRM_ERROR("depth %d\n", t->txdepth);
		1790	DRM_ERROR("bpp %d\n", t->cpp);
		1791	DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
		1792	DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
		1793	DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
		1794	DRM_ERROR("compress format %d\n", t->compress_format);
		1795	}
1117	serge	1796
2997	Serge	1797	static int r100_track_compress_size(int compress_format, int w, int h)
1117	serge	1798	{
2997	Serge	1799	int block_width, block_height, block_bytes;
		1800	int wblocks, hblocks;
		1801	int min_wblocks;
		1802	int sz;
1117	serge	1803
2997	Serge	1804	block_width = 4;
		1805	block_height = 4;
		1806
		1807	switch (compress_format) {
		1808	case R100_TRACK_COMP_DXT1:
		1809	block_bytes = 8;
		1810	min_wblocks = 4;
		1811	break;
		1812	default:
		1813	case R100_TRACK_COMP_DXT35:
		1814	block_bytes = 16;
		1815	min_wblocks = 2;
		1816	break;
1117	serge	1817	}
		1818
2997	Serge	1819	hblocks = (h + block_height - 1) / block_height;
		1820	wblocks = (w + block_width - 1) / block_width;
		1821	if (wblocks < min_wblocks)
		1822	wblocks = min_wblocks;
		1823	sz = wblocks * hblocks * block_bytes;
		1824	return sz;
		1825	}
		1826
		1827	static int r100_cs_track_cube(struct radeon_device *rdev,
		1828	struct r100_cs_track *track, unsigned idx)
		1829	{
		1830	unsigned face, w, h;
		1831	struct radeon_bo *cube_robj;
		1832	unsigned long size;
		1833	unsigned compress_format = track->textures[idx].compress_format;
		1834
		1835	for (face = 0; face < 5; face++) {
		1836	cube_robj = track->textures[idx].cube_info[face].robj;
		1837	w = track->textures[idx].cube_info[face].width;
		1838	h = track->textures[idx].cube_info[face].height;
		1839
		1840	if (compress_format) {
		1841	size = r100_track_compress_size(compress_format, w, h);
		1842	} else
		1843	size = w * h;
		1844	size *= track->textures[idx].cpp;
		1845
		1846	size += track->textures[idx].cube_info[face].offset;
		1847
		1848	if (size > radeon_bo_size(cube_robj)) {
		1849	DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
		1850	size, radeon_bo_size(cube_robj));
		1851	r100_cs_track_texture_print(&track->textures[idx]);
		1852	return -1;
		1853	}
1117	serge	1854	}
2997	Serge	1855	return 0;
1117	serge	1856	}
		1857
2997	Serge	1858	static int r100_cs_track_texture_check(struct radeon_device *rdev,
		1859	struct r100_cs_track *track)
1117	serge	1860	{
2997	Serge	1861	struct radeon_bo *robj;
		1862	unsigned long size;
		1863	unsigned u, i, w, h, d;
		1864	int ret;
1117	serge	1865
2997	Serge	1866	for (u = 0; u < track->num_texture; u++) {
		1867	if (!track->textures[u].enabled)
		1868	continue;
		1869	if (track->textures[u].lookup_disable)
		1870	continue;
		1871	robj = track->textures[u].robj;
		1872	if (robj == NULL) {
		1873	DRM_ERROR("No texture bound to unit %u\n", u);
		1874	return -EINVAL;
		1875	}
		1876	size = 0;
		1877	for (i = 0; i <= track->textures[u].num_levels; i++) {
		1878	if (track->textures[u].use_pitch) {
		1879	if (rdev->family < CHIP_R300)
		1880	w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
		1881	else
		1882	w = track->textures[u].pitch / (1 << i);
		1883	} else {
		1884	w = track->textures[u].width;
		1885	if (rdev->family >= CHIP_RV515)
		1886	w \|= track->textures[u].width_11;
		1887	w = w / (1 << i);
		1888	if (track->textures[u].roundup_w)
		1889	w = roundup_pow_of_two(w);
		1890	}
		1891	h = track->textures[u].height;
		1892	if (rdev->family >= CHIP_RV515)
		1893	h \|= track->textures[u].height_11;
		1894	h = h / (1 << i);
		1895	if (track->textures[u].roundup_h)
		1896	h = roundup_pow_of_two(h);
		1897	if (track->textures[u].tex_coord_type == 1) {
		1898	d = (1 << track->textures[u].txdepth) / (1 << i);
		1899	if (!d)
		1900	d = 1;
		1901	} else {
		1902	d = 1;
		1903	}
		1904	if (track->textures[u].compress_format) {
		1905
		1906	size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
		1907	/* compressed textures are block based */
		1908	} else
		1909	size += w * h * d;
		1910	}
		1911	size *= track->textures[u].cpp;
		1912
		1913	switch (track->textures[u].tex_coord_type) {
		1914	case 0:
		1915	case 1:
		1916	break;
		1917	case 2:
		1918	if (track->separate_cube) {
		1919	ret = r100_cs_track_cube(rdev, track, u);
		1920	if (ret)
		1921	return ret;
		1922	} else
		1923	size *= 6;
		1924	break;
		1925	default:
		1926	DRM_ERROR("Invalid texture coordinate type %u for unit "
		1927	"%u\n", track->textures[u].tex_coord_type, u);
		1928	return -EINVAL;
		1929	}
		1930	if (size > radeon_bo_size(robj)) {
		1931	DRM_ERROR("Texture of unit %u needs %lu bytes but is "
		1932	"%lu\n", u, size, radeon_bo_size(robj));
		1933	r100_cs_track_texture_print(&track->textures[u]);
		1934	return -EINVAL;
		1935	}
1117	serge	1936	}
2997	Serge	1937	return 0;
		1938	}
		1939
		1940	int r100_cs_track_check(struct radeon_device rdev, struct r100_cs_track track)
		1941	{
		1942	unsigned i;
		1943	unsigned long size;
		1944	unsigned prim_walk;
		1945	unsigned nverts;
		1946	unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
		1947
		1948	if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
		1949	!track->blend_read_enable)
		1950	num_cb = 0;
		1951
		1952	for (i = 0; i < num_cb; i++) {
		1953	if (track->cb[i].robj == NULL) {
		1954	DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
		1955	return -EINVAL;
1117	serge	1956	}
2997	Serge	1957	size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
		1958	size += track->cb[i].offset;
		1959	if (size > radeon_bo_size(track->cb[i].robj)) {
		1960	DRM_ERROR("[drm] Buffer too small for color buffer %d "
		1961	"(need %lu have %lu) !\n", i, size,
		1962	radeon_bo_size(track->cb[i].robj));
		1963	DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
		1964	i, track->cb[i].pitch, track->cb[i].cpp,
		1965	track->cb[i].offset, track->maxy);
		1966	return -EINVAL;
		1967	}
1117	serge	1968	}
2997	Serge	1969	track->cb_dirty = false;
		1970
		1971	if (track->zb_dirty && track->z_enabled) {
		1972	if (track->zb.robj == NULL) {
		1973	DRM_ERROR("[drm] No buffer for z buffer !\n");
		1974	return -EINVAL;
		1975	}
		1976	size = track->zb.pitch * track->zb.cpp * track->maxy;
		1977	size += track->zb.offset;
		1978	if (size > radeon_bo_size(track->zb.robj)) {
		1979	DRM_ERROR("[drm] Buffer too small for z buffer "
		1980	"(need %lu have %lu) !\n", size,
		1981	radeon_bo_size(track->zb.robj));
		1982	DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
		1983	track->zb.pitch, track->zb.cpp,
		1984	track->zb.offset, track->maxy);
		1985	return -EINVAL;
		1986	}
		1987	}
		1988	track->zb_dirty = false;
		1989
		1990	if (track->aa_dirty && track->aaresolve) {
		1991	if (track->aa.robj == NULL) {
		1992	DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
		1993	return -EINVAL;
		1994	}
		1995	/* I believe the format comes from colorbuffer0. */
		1996	size = track->aa.pitch * track->cb[0].cpp * track->maxy;
		1997	size += track->aa.offset;
		1998	if (size > radeon_bo_size(track->aa.robj)) {
		1999	DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
		2000	"(need %lu have %lu) !\n", i, size,
		2001	radeon_bo_size(track->aa.robj));
		2002	DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
		2003	i, track->aa.pitch, track->cb[0].cpp,
		2004	track->aa.offset, track->maxy);
		2005	return -EINVAL;
		2006	}
		2007	}
		2008	track->aa_dirty = false;
		2009
		2010	prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
		2011	if (track->vap_vf_cntl & (1 << 14)) {
		2012	nverts = track->vap_alt_nverts;
		2013	} else {
		2014	nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
		2015	}
		2016	switch (prim_walk) {
		2017	case 1:
		2018	for (i = 0; i < track->num_arrays; i++) {
		2019	size = track->arrays[i].esize * track->max_indx * 4;
		2020	if (track->arrays[i].robj == NULL) {
		2021	DRM_ERROR("(PW %u) Vertex array %u no buffer "
		2022	"bound\n", prim_walk, i);
		2023	return -EINVAL;
		2024	}
		2025	if (size > radeon_bo_size(track->arrays[i].robj)) {
		2026	dev_err(rdev->dev, "(PW %u) Vertex array %u "
		2027	"need %lu dwords have %lu dwords\n",
		2028	prim_walk, i, size >> 2,
		2029	radeon_bo_size(track->arrays[i].robj)
		2030	>> 2);
		2031	DRM_ERROR("Max indices %u\n", track->max_indx);
		2032	return -EINVAL;
		2033	}
		2034	}
		2035	break;
		2036	case 2:
		2037	for (i = 0; i < track->num_arrays; i++) {
		2038	size = track->arrays[i].esize * (nverts - 1) * 4;
		2039	if (track->arrays[i].robj == NULL) {
		2040	DRM_ERROR("(PW %u) Vertex array %u no buffer "
		2041	"bound\n", prim_walk, i);
		2042	return -EINVAL;
		2043	}
		2044	if (size > radeon_bo_size(track->arrays[i].robj)) {
		2045	dev_err(rdev->dev, "(PW %u) Vertex array %u "
		2046	"need %lu dwords have %lu dwords\n",
		2047	prim_walk, i, size >> 2,
		2048	radeon_bo_size(track->arrays[i].robj)
		2049	>> 2);
		2050	return -EINVAL;
		2051	}
		2052	}
		2053	break;
		2054	case 3:
		2055	size = track->vtx_size * nverts;
		2056	if (size != track->immd_dwords) {
		2057	DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
		2058	track->immd_dwords, size);
		2059	DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
		2060	nverts, track->vtx_size);
		2061	return -EINVAL;
		2062	}
		2063	break;
		2064	default:
		2065	DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
		2066	prim_walk);
		2067	return -EINVAL;
		2068	}
		2069
		2070	if (track->tex_dirty) {
		2071	track->tex_dirty = false;
		2072	return r100_cs_track_texture_check(rdev, track);
		2073	}
		2074	return 0;
1117	serge	2075	}
		2076
2997	Serge	2077	void r100_cs_track_clear(struct radeon_device rdev, struct r100_cs_track track)
1117	serge	2078	{
2997	Serge	2079	unsigned i, face;
1117	serge	2080
2997	Serge	2081	track->cb_dirty = true;
		2082	track->zb_dirty = true;
		2083	track->tex_dirty = true;
		2084	track->aa_dirty = true;
1117	serge	2085
2997	Serge	2086	if (rdev->family < CHIP_R300) {
		2087	track->num_cb = 1;
		2088	if (rdev->family <= CHIP_RS200)
		2089	track->num_texture = 3;
		2090	else
		2091	track->num_texture = 6;
		2092	track->maxy = 2048;
		2093	track->separate_cube = 1;
		2094	} else {
		2095	track->num_cb = 4;
		2096	track->num_texture = 16;
		2097	track->maxy = 4096;
		2098	track->separate_cube = 0;
		2099	track->aaresolve = false;
		2100	track->aa.robj = NULL;
		2101	}
		2102
		2103	for (i = 0; i < track->num_cb; i++) {
		2104	track->cb[i].robj = NULL;
		2105	track->cb[i].pitch = 8192;
		2106	track->cb[i].cpp = 16;
		2107	track->cb[i].offset = 0;
		2108	}
		2109	track->z_enabled = true;
		2110	track->zb.robj = NULL;
		2111	track->zb.pitch = 8192;
		2112	track->zb.cpp = 4;
		2113	track->zb.offset = 0;
		2114	track->vtx_size = 0x7F;
		2115	track->immd_dwords = 0xFFFFFFFFUL;
		2116	track->num_arrays = 11;
		2117	track->max_indx = 0x00FFFFFFUL;
		2118	for (i = 0; i < track->num_arrays; i++) {
		2119	track->arrays[i].robj = NULL;
		2120	track->arrays[i].esize = 0x7F;
		2121	}
		2122	for (i = 0; i < track->num_texture; i++) {
		2123	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
		2124	track->textures[i].pitch = 16536;
		2125	track->textures[i].width = 16536;
		2126	track->textures[i].height = 16536;
		2127	track->textures[i].width_11 = 1 << 11;
		2128	track->textures[i].height_11 = 1 << 11;
		2129	track->textures[i].num_levels = 12;
		2130	if (rdev->family <= CHIP_RS200) {
		2131	track->textures[i].tex_coord_type = 0;
		2132	track->textures[i].txdepth = 0;
		2133	} else {
		2134	track->textures[i].txdepth = 16;
		2135	track->textures[i].tex_coord_type = 1;
1117	serge	2136	}
2997	Serge	2137	track->textures[i].cpp = 64;
		2138	track->textures[i].robj = NULL;
		2139	/* CS IB emission code makes sure texture unit are disabled */
		2140	track->textures[i].enabled = false;
		2141	track->textures[i].lookup_disable = false;
		2142	track->textures[i].roundup_w = true;
		2143	track->textures[i].roundup_h = true;
		2144	if (track->separate_cube)
		2145	for (face = 0; face < 5; face++) {
		2146	track->textures[i].cube_info[face].robj = NULL;
		2147	track->textures[i].cube_info[face].width = 16536;
		2148	track->textures[i].cube_info[face].height = 16536;
		2149	track->textures[i].cube_info[face].offset = 0;
		2150	}
1117	serge	2151	}
		2152	}
2997	Serge	2153	#endif
1117	serge	2154
2997	Serge	2155	/*
		2156	* Global GPU functions
		2157	*/
		2158	static void r100_errata(struct radeon_device *rdev)
1117	serge	2159	{
2997	Serge	2160	rdev->pll_errata = 0;
		2161
		2162	if (rdev->family == CHIP_RV200 \|\| rdev->family == CHIP_RS200) {
		2163	rdev->pll_errata \|= CHIP_ERRATA_PLL_DUMMYREADS;
		2164	}
		2165
		2166	if (rdev->family == CHIP_RV100 \|\|
		2167	rdev->family == CHIP_RS100 \|\|
		2168	rdev->family == CHIP_RS200) {
		2169	rdev->pll_errata \|= CHIP_ERRATA_PLL_DELAY;
		2170	}
		2171	}
		2172
		2173	static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
		2174	{
1117	serge	2175	unsigned i;
		2176	uint32_t tmp;
		2177
		2178	for (i = 0; i < rdev->usec_timeout; i++) {
		2179	tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
		2180	if (tmp >= n) {
		2181	return 0;
		2182	}
		2183	DRM_UDELAY(1);
		2184	}
		2185	return -1;
		2186	}
		2187
		2188	int r100_gui_wait_for_idle(struct radeon_device *rdev)
		2189	{
		2190	unsigned i;
		2191	uint32_t tmp;
		2192
		2193	if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
		2194	printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
		2195	" Bad things might happen.\n");
		2196	}
		2197	for (i = 0; i < rdev->usec_timeout; i++) {
		2198	tmp = RREG32(RADEON_RBBM_STATUS);
1430	serge	2199	if (!(tmp & RADEON_RBBM_ACTIVE)) {
1117	serge	2200	return 0;
		2201	}
		2202	DRM_UDELAY(1);
		2203	}
		2204	return -1;
		2205	}
		2206
		2207	int r100_mc_wait_for_idle(struct radeon_device *rdev)
		2208	{
		2209	unsigned i;
		2210	uint32_t tmp;
		2211
		2212	for (i = 0; i < rdev->usec_timeout; i++) {
		2213	/* read MC_STATUS */
1430	serge	2214	tmp = RREG32(RADEON_MC_STATUS);
		2215	if (tmp & RADEON_MC_IDLE) {
1117	serge	2216	return 0;
		2217	}
		2218	DRM_UDELAY(1);
		2219	}
		2220	return -1;
		2221	}
		2222
2997	Serge	2223	bool r100_gpu_is_lockup(struct radeon_device rdev, struct radeon_ring ring)
1117	serge	2224	{
1963	serge	2225	u32 rbbm_status;
1117	serge	2226
1963	serge	2227	rbbm_status = RREG32(R_000E40_RBBM_STATUS);
		2228	if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2997	Serge	2229	radeon_ring_lockup_update(ring);
1963	serge	2230	return false;
1117	serge	2231	}
1963	serge	2232	/* force CP activities */
2997	Serge	2233	radeon_ring_force_activity(rdev, ring);
		2234	return radeon_ring_test_lockup(rdev, ring);
1117	serge	2235	}
		2236
2997	Serge	2237	/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
		2238	void r100_enable_bm(struct radeon_device *rdev)
		2239	{
		2240	uint32_t tmp;
		2241	/* Enable bus mastering */
		2242	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
		2243	WREG32(RADEON_BUS_CNTL, tmp);
		2244	}
		2245
1963	serge	2246	void r100_bm_disable(struct radeon_device *rdev)
1117	serge	2247	{
1963	serge	2248	u32 tmp;
1117	serge	2249
1963	serge	2250	/* disable bus mastering */
		2251	tmp = RREG32(R_000030_BUS_CNTL);
		2252	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000044);
		2253	mdelay(1);
		2254	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000042);
		2255	mdelay(1);
		2256	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000040);
		2257	tmp = RREG32(RADEON_BUS_CNTL);
		2258	mdelay(1);
2997	Serge	2259	pci_clear_master(rdev->pdev);
1963	serge	2260	mdelay(1);
		2261	}
		2262
		2263	int r100_asic_reset(struct radeon_device *rdev)
		2264	{
		2265	struct r100_mc_save save;
		2266	u32 status, tmp;
		2267	int ret = 0;
		2268
		2269	status = RREG32(R_000E40_RBBM_STATUS);
		2270	if (!G_000E40_GUI_ACTIVE(status)) {
		2271	return 0;
1117	serge	2272	}
1963	serge	2273	r100_mc_stop(rdev, &save);
		2274	status = RREG32(R_000E40_RBBM_STATUS);
		2275	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		2276	/* stop CP */
		2277	WREG32(RADEON_CP_CSQ_CNTL, 0);
		2278	tmp = RREG32(RADEON_CP_RB_CNTL);
		2279	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);
		2280	WREG32(RADEON_CP_RB_RPTR_WR, 0);
		2281	WREG32(RADEON_CP_RB_WPTR, 0);
		2282	WREG32(RADEON_CP_RB_CNTL, tmp);
		2283	/* save PCI state */
		2284	// pci_save_state(rdev->pdev);
		2285	/* disable bus mastering */
		2286	r100_bm_disable(rdev);
		2287	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) \|
		2288	S_0000F0_SOFT_RESET_RE(1) \|
		2289	S_0000F0_SOFT_RESET_PP(1) \|
		2290	S_0000F0_SOFT_RESET_RB(1));
		2291	RREG32(R_0000F0_RBBM_SOFT_RESET);
		2292	mdelay(500);
		2293	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		2294	mdelay(1);
		2295	status = RREG32(R_000E40_RBBM_STATUS);
		2296	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
1117	serge	2297	/* reset CP */
1963	serge	2298	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
		2299	RREG32(R_0000F0_RBBM_SOFT_RESET);
		2300	mdelay(500);
		2301	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		2302	mdelay(1);
		2303	status = RREG32(R_000E40_RBBM_STATUS);
		2304	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		2305	/* restore PCI & busmastering */
		2306	// pci_restore_state(rdev->pdev);
		2307	r100_enable_bm(rdev);
1117	serge	2308	/* Check if GPU is idle */
1963	serge	2309	if (G_000E40_SE_BUSY(status) \|\| G_000E40_RE_BUSY(status) \|\|
		2310	G_000E40_TAM_BUSY(status) \|\| G_000E40_PB_BUSY(status)) {
		2311	dev_err(rdev->dev, "failed to reset GPU\n");
		2312	ret = -1;
		2313	} else
		2314	dev_info(rdev->dev, "GPU reset succeed\n");
		2315	r100_mc_resume(rdev, &save);
		2316	return ret;
1117	serge	2317	}
		2318
1321	serge	2319	void r100_set_common_regs(struct radeon_device *rdev)
		2320	{
1430	serge	2321	struct drm_device *dev = rdev->ddev;
		2322	bool force_dac2 = false;
1963	serge	2323	u32 tmp;
1430	serge	2324
1321	serge	2325	/* set these so they don't interfere with anything */
		2326	WREG32(RADEON_OV0_SCALE_CNTL, 0);
		2327	WREG32(RADEON_SUBPIC_CNTL, 0);
		2328	WREG32(RADEON_VIPH_CONTROL, 0);
		2329	WREG32(RADEON_I2C_CNTL_1, 0);
		2330	WREG32(RADEON_DVI_I2C_CNTL_1, 0);
		2331	WREG32(RADEON_CAP0_TRIG_CNTL, 0);
		2332	WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1430	serge	2333
		2334	/* always set up dac2 on rn50 and some rv100 as lots
		2335	* of servers seem to wire it up to a VGA port but
		2336	* don't report it in the bios connector
		2337	* table.
		2338	*/
		2339	switch (dev->pdev->device) {
		2340	/* RN50 */
		2341	case 0x515e:
		2342	case 0x5969:
		2343	force_dac2 = true;
		2344	break;
		2345	/* RV100*/
		2346	case 0x5159:
		2347	case 0x515a:
		2348	/* DELL triple head servers */
		2349	if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
		2350	((dev->pdev->subsystem_device == 0x016c) \|\|
		2351	(dev->pdev->subsystem_device == 0x016d) \|\|
		2352	(dev->pdev->subsystem_device == 0x016e) \|\|
		2353	(dev->pdev->subsystem_device == 0x016f) \|\|
		2354	(dev->pdev->subsystem_device == 0x0170) \|\|
		2355	(dev->pdev->subsystem_device == 0x017d) \|\|
		2356	(dev->pdev->subsystem_device == 0x017e) \|\|
		2357	(dev->pdev->subsystem_device == 0x0183) \|\|
		2358	(dev->pdev->subsystem_device == 0x018a) \|\|
		2359	(dev->pdev->subsystem_device == 0x019a)))
		2360	force_dac2 = true;
		2361	break;
		2362	}
		2363
		2364	if (force_dac2) {
		2365	u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
		2366	u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		2367	u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
		2368
		2369	/* For CRT on DAC2, don't turn it on if BIOS didn't
		2370	enable it, even it's detected.
		2371	*/
		2372
		2373	/* force it to crtc0 */
		2374	dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
		2375	dac2_cntl \|= RADEON_DAC2_DAC2_CLK_SEL;
		2376	disp_hw_debug \|= RADEON_CRT2_DISP1_SEL;
		2377
		2378	/* set up the TV DAC */
		2379	tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL \|
		2380	RADEON_TV_DAC_STD_MASK \|
		2381	RADEON_TV_DAC_RDACPD \|
		2382	RADEON_TV_DAC_GDACPD \|
		2383	RADEON_TV_DAC_BDACPD \|
		2384	RADEON_TV_DAC_BGADJ_MASK \|
		2385	RADEON_TV_DAC_DACADJ_MASK);
		2386	tv_dac_cntl \|= (RADEON_TV_DAC_NBLANK \|
		2387	RADEON_TV_DAC_NHOLD \|
		2388	RADEON_TV_DAC_STD_PS2 \|
		2389	(0x58 << 16));
		2390
		2391	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		2392	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		2393	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		2394	}
1963	serge	2395
		2396	/* switch PM block to ACPI mode */
		2397	tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
		2398	tmp &= ~RADEON_PM_MODE_SEL;
		2399	WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
		2400
1321	serge	2401	}
1117	serge	2402
		2403	/*
		2404	* VRAM info
		2405	*/
		2406	static void r100_vram_get_type(struct radeon_device *rdev)
		2407	{
		2408	uint32_t tmp;
		2409
		2410	rdev->mc.vram_is_ddr = false;
		2411	if (rdev->flags & RADEON_IS_IGP)
		2412	rdev->mc.vram_is_ddr = true;
		2413	else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
		2414	rdev->mc.vram_is_ddr = true;
		2415	if ((rdev->family == CHIP_RV100) \|\|
		2416	(rdev->family == CHIP_RS100) \|\|
		2417	(rdev->family == CHIP_RS200)) {
		2418	tmp = RREG32(RADEON_MEM_CNTL);
		2419	if (tmp & RV100_HALF_MODE) {
		2420	rdev->mc.vram_width = 32;
		2421	} else {
		2422	rdev->mc.vram_width = 64;
		2423	}
		2424	if (rdev->flags & RADEON_SINGLE_CRTC) {
		2425	rdev->mc.vram_width /= 4;
		2426	rdev->mc.vram_is_ddr = true;
		2427	}
		2428	} else if (rdev->family <= CHIP_RV280) {
		2429	tmp = RREG32(RADEON_MEM_CNTL);
		2430	if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
		2431	rdev->mc.vram_width = 128;
		2432	} else {
		2433	rdev->mc.vram_width = 64;
		2434	}
		2435	} else {
		2436	/* newer IGPs */
		2437	rdev->mc.vram_width = 128;
		2438	}
		2439	}
		2440
1179	serge	2441	static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1117	serge	2442	{
1179	serge	2443	u32 aper_size;
		2444	u8 byte;
1117	serge	2445
1179	serge	2446	aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
		2447
		2448	/* Set HDP_APER_CNTL only on cards that are known not to be broken,
		2449	* that is has the 2nd generation multifunction PCI interface
		2450	*/
		2451	if (rdev->family == CHIP_RV280 \|\|
		2452	rdev->family >= CHIP_RV350) {
		2453	WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
		2454	~RADEON_HDP_APER_CNTL);
		2455	DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
		2456	return aper_size * 2;
		2457	}
		2458
		2459	/* Older cards have all sorts of funny issues to deal with. First
		2460	* check if it's a multifunction card by reading the PCI config
		2461	* header type... Limit those to one aperture size
		2462	*/
		2463	// pci_read_config_byte(rdev->pdev, 0xe, &byte);
		2464	// if (byte & 0x80) {
		2465	// DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
		2466	// DRM_INFO("Limiting VRAM to one aperture\n");
		2467	// return aper_size;
		2468	// }
		2469
		2470	/* Single function older card. We read HDP_APER_CNTL to see how the BIOS
		2471	* have set it up. We don't write this as it's broken on some ASICs but
		2472	* we expect the BIOS to have done the right thing (might be too optimistic...)
		2473	*/
		2474	if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
		2475	return aper_size * 2;
		2476	return aper_size;
		2477	}
		2478
		2479	void r100_vram_init_sizes(struct radeon_device *rdev)
		2480	{
		2481	u64 config_aper_size;
		2482
1430	serge	2483	/* work out accessible VRAM */
1963	serge	2484	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
		2485	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1430	serge	2486	rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
		2487	/* FIXME we don't use the second aperture yet when we could use it */
		2488	if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
		2489	rdev->mc.visible_vram_size = rdev->mc.aper_size;
1179	serge	2490	config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1117	serge	2491	if (rdev->flags & RADEON_IS_IGP) {
		2492	uint32_t tom;
		2493	/* read NB_TOM to get the amount of ram stolen for the GPU */
		2494	tom = RREG32(RADEON_NB_TOM);
1179	serge	2495	rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
		2496	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
		2497	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	2498	} else {
1179	serge	2499	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1117	serge	2500	/* Some production boards of m6 will report 0
		2501	* if it's 8 MB
		2502	*/
1179	serge	2503	if (rdev->mc.real_vram_size == 0) {
		2504	rdev->mc.real_vram_size = 8192 * 1024;
		2505	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1117	serge	2506	}
1179	serge	2507	/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1430	serge	2508	* Novell bug 204882 + along with lots of ubuntu ones
		2509	*/
1963	serge	2510	if (rdev->mc.aper_size > config_aper_size)
		2511	config_aper_size = rdev->mc.aper_size;
		2512
1179	serge	2513	if (config_aper_size > rdev->mc.real_vram_size)
		2514	rdev->mc.mc_vram_size = config_aper_size;
		2515	else
		2516	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	2517	}
		2518	}
		2519
1179	serge	2520	void r100_vga_set_state(struct radeon_device *rdev, bool state)
		2521	{
		2522	uint32_t temp;
		2523
		2524	temp = RREG32(RADEON_CONFIG_CNTL);
		2525	if (state == false) {
1963	serge	2526	temp &= ~RADEON_CFG_VGA_RAM_EN;
		2527	temp \|= RADEON_CFG_VGA_IO_DIS;
1179	serge	2528	} else {
1963	serge	2529	temp &= ~RADEON_CFG_VGA_IO_DIS;
1179	serge	2530	}
		2531	WREG32(RADEON_CONFIG_CNTL, temp);
		2532	}
		2533
2997	Serge	2534	static void r100_mc_init(struct radeon_device *rdev)
1179	serge	2535	{
1430	serge	2536	u64 base;
		2537
1179	serge	2538	r100_vram_get_type(rdev);
		2539	r100_vram_init_sizes(rdev);
1430	serge	2540	base = rdev->mc.aper_base;
		2541	if (rdev->flags & RADEON_IS_IGP)
		2542	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
		2543	radeon_vram_location(rdev, &rdev->mc, base);
1963	serge	2544	rdev->mc.gtt_base_align = 0;
1430	serge	2545	if (!(rdev->flags & RADEON_IS_AGP))
		2546	radeon_gtt_location(rdev, &rdev->mc);
1963	serge	2547	radeon_update_bandwidth_info(rdev);
1179	serge	2548	}
		2549
		2550
1117	serge	2551	/*
		2552	* Indirect registers accessor
		2553	*/
		2554	void r100_pll_errata_after_index(struct radeon_device *rdev)
		2555	{
1963	serge	2556	if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
1117	serge	2557	(void)RREG32(RADEON_CLOCK_CNTL_DATA);
		2558	(void)RREG32(RADEON_CRTC_GEN_CNTL);
1963	serge	2559	}
1117	serge	2560	}
		2561
		2562	static void r100_pll_errata_after_data(struct radeon_device *rdev)
		2563	{
		2564	/* This workarounds is necessary on RV100, RS100 and RS200 chips
		2565	* or the chip could hang on a subsequent access
		2566	*/
		2567	if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2997	Serge	2568	mdelay(5);
1117	serge	2569	}
		2570
		2571	/* This function is required to workaround a hardware bug in some (all?)
		2572	* revisions of the R300. This workaround should be called after every
		2573	* CLOCK_CNTL_INDEX register access. If not, register reads afterward
		2574	* may not be correct.
		2575	*/
		2576	if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
		2577	uint32_t save, tmp;
		2578
		2579	save = RREG32(RADEON_CLOCK_CNTL_INDEX);
		2580	tmp = save & ~(0x3f \| RADEON_PLL_WR_EN);
		2581	WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
		2582	tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
		2583	WREG32(RADEON_CLOCK_CNTL_INDEX, save);
		2584	}
		2585	}
		2586
		2587	uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
		2588	{
		2589	uint32_t data;
		2590
		2591	WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
		2592	r100_pll_errata_after_index(rdev);
		2593	data = RREG32(RADEON_CLOCK_CNTL_DATA);
		2594	r100_pll_errata_after_data(rdev);
		2595	return data;
		2596	}
		2597
		2598	void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		2599	{
		2600	WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) \| RADEON_PLL_WR_EN));
		2601	r100_pll_errata_after_index(rdev);
		2602	WREG32(RADEON_CLOCK_CNTL_DATA, v);
		2603	r100_pll_errata_after_data(rdev);
		2604	}
		2605
2997	Serge	2606	static void r100_set_safe_registers(struct radeon_device *rdev)
1117	serge	2607	{
1179	serge	2608	if (ASIC_IS_RN50(rdev)) {
		2609	rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
		2610	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
		2611	} else if (rdev->family < CHIP_R200) {
		2612	rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
		2613	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
		2614	} else {
1221	serge	2615	r200_set_safe_registers(rdev);
1117	serge	2616	}
		2617	}
		2618
1129	serge	2619	/*
		2620	* Debugfs info
		2621	*/
		2622	#if defined(CONFIG_DEBUG_FS)
		2623	static int r100_debugfs_rbbm_info(struct seq_file m, void data)
		2624	{
		2625	struct drm_info_node node = (struct drm_info_node ) m->private;
		2626	struct drm_device *dev = node->minor->dev;
		2627	struct radeon_device *rdev = dev->dev_private;
		2628	uint32_t reg, value;
		2629	unsigned i;
		2630
		2631	seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
		2632	seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
		2633	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2634	for (i = 0; i < 64; i++) {
		2635	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i \| 0x100);
		2636	reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
		2637	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
		2638	value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
		2639	seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
		2640	}
		2641	return 0;
		2642	}
		2643
		2644	static int r100_debugfs_cp_ring_info(struct seq_file m, void data)
		2645	{
		2646	struct drm_info_node node = (struct drm_info_node ) m->private;
		2647	struct drm_device *dev = node->minor->dev;
		2648	struct radeon_device *rdev = dev->dev_private;
2997	Serge	2649	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1129	serge	2650	uint32_t rdp, wdp;
		2651	unsigned count, i, j;
		2652
2997	Serge	2653	radeon_ring_free_size(rdev, ring);
1129	serge	2654	rdp = RREG32(RADEON_CP_RB_RPTR);
		2655	wdp = RREG32(RADEON_CP_RB_WPTR);
2997	Serge	2656	count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
1129	serge	2657	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2658	seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
		2659	seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2997	Serge	2660	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
1129	serge	2661	seq_printf(m, "%u dwords in ring\n", count);
		2662	for (j = 0; j <= count; j++) {
2997	Serge	2663	i = (rdp + j) & ring->ptr_mask;
		2664	seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
1129	serge	2665	}
		2666	return 0;
		2667	}
		2668
		2669
		2670	static int r100_debugfs_cp_csq_fifo(struct seq_file m, void data)
		2671	{
		2672	struct drm_info_node node = (struct drm_info_node ) m->private;
		2673	struct drm_device *dev = node->minor->dev;
		2674	struct radeon_device *rdev = dev->dev_private;
		2675	uint32_t csq_stat, csq2_stat, tmp;
		2676	unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
		2677	unsigned i;
		2678
		2679	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2680	seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
		2681	csq_stat = RREG32(RADEON_CP_CSQ_STAT);
		2682	csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
		2683	r_rptr = (csq_stat >> 0) & 0x3ff;
		2684	r_wptr = (csq_stat >> 10) & 0x3ff;
		2685	ib1_rptr = (csq_stat >> 20) & 0x3ff;
		2686	ib1_wptr = (csq2_stat >> 0) & 0x3ff;
		2687	ib2_rptr = (csq2_stat >> 10) & 0x3ff;
		2688	ib2_wptr = (csq2_stat >> 20) & 0x3ff;
		2689	seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
		2690	seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
		2691	seq_printf(m, "Ring rptr %u\n", r_rptr);
		2692	seq_printf(m, "Ring wptr %u\n", r_wptr);
		2693	seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
		2694	seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
		2695	seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
		2696	seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
		2697	/* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
		2698	* 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
		2699	seq_printf(m, "Ring fifo:\n");
		2700	for (i = 0; i < 256; i++) {
		2701	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2702	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2703	seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
		2704	}
		2705	seq_printf(m, "Indirect1 fifo:\n");
		2706	for (i = 256; i <= 512; i++) {
		2707	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2708	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2709	seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
		2710	}
		2711	seq_printf(m, "Indirect2 fifo:\n");
		2712	for (i = 640; i < ib1_wptr; i++) {
		2713	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2714	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2715	seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
		2716	}
		2717	return 0;
		2718	}
		2719
		2720	static int r100_debugfs_mc_info(struct seq_file m, void data)
		2721	{
		2722	struct drm_info_node node = (struct drm_info_node ) m->private;
		2723	struct drm_device *dev = node->minor->dev;
		2724	struct radeon_device *rdev = dev->dev_private;
		2725	uint32_t tmp;
		2726
		2727	tmp = RREG32(RADEON_CONFIG_MEMSIZE);
		2728	seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
		2729	tmp = RREG32(RADEON_MC_FB_LOCATION);
		2730	seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
		2731	tmp = RREG32(RADEON_BUS_CNTL);
		2732	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
		2733	tmp = RREG32(RADEON_MC_AGP_LOCATION);
		2734	seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
		2735	tmp = RREG32(RADEON_AGP_BASE);
		2736	seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
		2737	tmp = RREG32(RADEON_HOST_PATH_CNTL);
		2738	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
		2739	tmp = RREG32(0x01D0);
		2740	seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
		2741	tmp = RREG32(RADEON_AIC_LO_ADDR);
		2742	seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
		2743	tmp = RREG32(RADEON_AIC_HI_ADDR);
		2744	seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
		2745	tmp = RREG32(0x01E4);
		2746	seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
		2747	return 0;
		2748	}
		2749
		2750	static struct drm_info_list r100_debugfs_rbbm_list[] = {
		2751	{"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
		2752	};
		2753
		2754	static struct drm_info_list r100_debugfs_cp_list[] = {
		2755	{"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
		2756	{"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
		2757	};
		2758
		2759	static struct drm_info_list r100_debugfs_mc_info_list[] = {
		2760	{"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
		2761	};
		2762	#endif
		2763
		2764	int r100_debugfs_rbbm_init(struct radeon_device *rdev)
		2765	{
		2766	#if defined(CONFIG_DEBUG_FS)
		2767	return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
		2768	#else
		2769	return 0;
		2770	#endif
		2771	}
		2772
		2773	int r100_debugfs_cp_init(struct radeon_device *rdev)
		2774	{
		2775	#if defined(CONFIG_DEBUG_FS)
		2776	return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
		2777	#else
		2778	return 0;
		2779	#endif
		2780	}
		2781
		2782	int r100_debugfs_mc_info_init(struct radeon_device *rdev)
		2783	{
		2784	#if defined(CONFIG_DEBUG_FS)
		2785	return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
		2786	#else
		2787	return 0;
		2788	#endif
		2789	}
1179	serge	2790
		2791	int r100_set_surface_reg(struct radeon_device *rdev, int reg,
		2792	uint32_t tiling_flags, uint32_t pitch,
		2793	uint32_t offset, uint32_t obj_size)
		2794	{
		2795	int surf_index = reg * 16;
		2796	int flags = 0;
		2797
		2798	if (rdev->family <= CHIP_RS200) {
		2799	if ((tiling_flags & (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		2800	== (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		2801	flags \|= RADEON_SURF_TILE_COLOR_BOTH;
		2802	if (tiling_flags & RADEON_TILING_MACRO)
		2803	flags \|= RADEON_SURF_TILE_COLOR_MACRO;
		2804	} else if (rdev->family <= CHIP_RV280) {
		2805	if (tiling_flags & (RADEON_TILING_MACRO))
		2806	flags \|= R200_SURF_TILE_COLOR_MACRO;
		2807	if (tiling_flags & RADEON_TILING_MICRO)
		2808	flags \|= R200_SURF_TILE_COLOR_MICRO;
		2809	} else {
		2810	if (tiling_flags & RADEON_TILING_MACRO)
		2811	flags \|= R300_SURF_TILE_MACRO;
		2812	if (tiling_flags & RADEON_TILING_MICRO)
		2813	flags \|= R300_SURF_TILE_MICRO;
		2814	}
		2815
		2816	if (tiling_flags & RADEON_TILING_SWAP_16BIT)
		2817	flags \|= RADEON_SURF_AP0_SWP_16BPP \| RADEON_SURF_AP1_SWP_16BPP;
		2818	if (tiling_flags & RADEON_TILING_SWAP_32BIT)
		2819	flags \|= RADEON_SURF_AP0_SWP_32BPP \| RADEON_SURF_AP1_SWP_32BPP;
		2820
1963	serge	2821	/* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
		2822	if (tiling_flags & (RADEON_TILING_SWAP_16BIT \| RADEON_TILING_SWAP_32BIT)) {
		2823	if (!(tiling_flags & (RADEON_TILING_MACRO \| RADEON_TILING_MICRO)))
		2824	if (ASIC_IS_RN50(rdev))
		2825	pitch /= 16;
		2826	}
		2827
		2828	/* r100/r200 divide by 16 */
		2829	if (rdev->family < CHIP_R300)
		2830	flags \|= pitch / 16;
		2831	else
		2832	flags \|= pitch / 8;
		2833
		2834
		2835	DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
1179	serge	2836	WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
		2837	WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
		2838	WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
		2839	return 0;
		2840	}
		2841
		2842	void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
		2843	{
		2844	int surf_index = reg * 16;
		2845	WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
		2846	}
		2847
		2848	void r100_bandwidth_update(struct radeon_device *rdev)
		2849	{
		2850	fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
		2851	fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
		2852	fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
		2853	uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
		2854	fixed20_12 memtcas_ff[8] = {
1963	serge	2855	dfixed_init(1),
		2856	dfixed_init(2),
		2857	dfixed_init(3),
		2858	dfixed_init(0),
		2859	dfixed_init_half(1),
		2860	dfixed_init_half(2),
		2861	dfixed_init(0),
1179	serge	2862	};
		2863	fixed20_12 memtcas_rs480_ff[8] = {
1963	serge	2864	dfixed_init(0),
		2865	dfixed_init(1),
		2866	dfixed_init(2),
		2867	dfixed_init(3),
		2868	dfixed_init(0),
		2869	dfixed_init_half(1),
		2870	dfixed_init_half(2),
		2871	dfixed_init_half(3),
1179	serge	2872	};
		2873	fixed20_12 memtcas2_ff[8] = {
1963	serge	2874	dfixed_init(0),
		2875	dfixed_init(1),
		2876	dfixed_init(2),
		2877	dfixed_init(3),
		2878	dfixed_init(4),
		2879	dfixed_init(5),
		2880	dfixed_init(6),
		2881	dfixed_init(7),
1179	serge	2882	};
		2883	fixed20_12 memtrbs[8] = {
1963	serge	2884	dfixed_init(1),
		2885	dfixed_init_half(1),
		2886	dfixed_init(2),
		2887	dfixed_init_half(2),
		2888	dfixed_init(3),
		2889	dfixed_init_half(3),
		2890	dfixed_init(4),
		2891	dfixed_init_half(4)
1179	serge	2892	};
		2893	fixed20_12 memtrbs_r4xx[8] = {
1963	serge	2894	dfixed_init(4),
		2895	dfixed_init(5),
		2896	dfixed_init(6),
		2897	dfixed_init(7),
		2898	dfixed_init(8),
		2899	dfixed_init(9),
		2900	dfixed_init(10),
		2901	dfixed_init(11)
1179	serge	2902	};
		2903	fixed20_12 min_mem_eff;
		2904	fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
		2905	fixed20_12 cur_latency_mclk, cur_latency_sclk;
		2906	fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
		2907	disp_drain_rate2, read_return_rate;
		2908	fixed20_12 time_disp1_drop_priority;
		2909	int c;
		2910	int cur_size = 16; /* in octawords */
		2911	int critical_point = 0, critical_point2;
		2912	/* uint32_t read_return_rate, time_disp1_drop_priority; */
		2913	int stop_req, max_stop_req;
		2914	struct drm_display_mode *mode1 = NULL;
		2915	struct drm_display_mode *mode2 = NULL;
		2916	uint32_t pixel_bytes1 = 0;
		2917	uint32_t pixel_bytes2 = 0;
		2918
1963	serge	2919	radeon_update_display_priority(rdev);
		2920
1179	serge	2921	if (rdev->mode_info.crtcs[0]->base.enabled) {
		2922	mode1 = &rdev->mode_info.crtcs[0]->base.mode;
		2923	pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
		2924	}
1221	serge	2925	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
1179	serge	2926	if (rdev->mode_info.crtcs[1]->base.enabled) {
		2927	mode2 = &rdev->mode_info.crtcs[1]->base.mode;
		2928	pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
		2929	}
1221	serge	2930	}
1179	serge	2931
1963	serge	2932	min_mem_eff.full = dfixed_const_8(0);
1179	serge	2933	/* get modes */
		2934	if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
		2935	uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
		2936	mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
		2937	mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
		2938	/* check crtc enables */
		2939	if (mode2)
		2940	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
		2941	if (mode1)
		2942	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
		2943	WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
		2944	}
		2945
		2946	/*
		2947	* determine is there is enough bw for current mode
		2948	*/
1963	serge	2949	sclk_ff = rdev->pm.sclk;
		2950	mclk_ff = rdev->pm.mclk;
1179	serge	2951
		2952	temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
1963	serge	2953	temp_ff.full = dfixed_const(temp);
		2954	mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
1179	serge	2955
		2956	pix_clk.full = 0;
		2957	pix_clk2.full = 0;
		2958	peak_disp_bw.full = 0;
		2959	if (mode1) {
1963	serge	2960	temp_ff.full = dfixed_const(1000);
		2961	pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
		2962	pix_clk.full = dfixed_div(pix_clk, temp_ff);
		2963	temp_ff.full = dfixed_const(pixel_bytes1);
		2964	peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
1179	serge	2965	}
		2966	if (mode2) {
1963	serge	2967	temp_ff.full = dfixed_const(1000);
		2968	pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
		2969	pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
		2970	temp_ff.full = dfixed_const(pixel_bytes2);
		2971	peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
1179	serge	2972	}
		2973
1963	serge	2974	mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
1179	serge	2975	if (peak_disp_bw.full >= mem_bw.full) {
		2976	DRM_ERROR("You may not have enough display bandwidth for current mode\n"
		2977	"If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
		2978	}
		2979
		2980	/* Get values from the EXT_MEM_CNTL register...converting its contents. */
		2981	temp = RREG32(RADEON_MEM_TIMING_CNTL);
		2982	if ((rdev->family == CHIP_RV100) \|\| (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
		2983	mem_trcd = ((temp >> 2) & 0x3) + 1;
		2984	mem_trp = ((temp & 0x3)) + 1;
		2985	mem_tras = ((temp & 0x70) >> 4) + 1;
		2986	} else if (rdev->family == CHIP_R300 \|\|
		2987	rdev->family == CHIP_R350) { /* r300, r350 */
		2988	mem_trcd = (temp & 0x7) + 1;
		2989	mem_trp = ((temp >> 8) & 0x7) + 1;
		2990	mem_tras = ((temp >> 11) & 0xf) + 4;
		2991	} else if (rdev->family == CHIP_RV350 \|\|
		2992	rdev->family <= CHIP_RV380) {
		2993	/* rv3x0 */
		2994	mem_trcd = (temp & 0x7) + 3;
		2995	mem_trp = ((temp >> 8) & 0x7) + 3;
		2996	mem_tras = ((temp >> 11) & 0xf) + 6;
		2997	} else if (rdev->family == CHIP_R420 \|\|
		2998	rdev->family == CHIP_R423 \|\|
		2999	rdev->family == CHIP_RV410) {
		3000	/* r4xx */
		3001	mem_trcd = (temp & 0xf) + 3;
		3002	if (mem_trcd > 15)
		3003	mem_trcd = 15;
		3004	mem_trp = ((temp >> 8) & 0xf) + 3;
		3005	if (mem_trp > 15)
		3006	mem_trp = 15;
		3007	mem_tras = ((temp >> 12) & 0x1f) + 6;
		3008	if (mem_tras > 31)
		3009	mem_tras = 31;
		3010	} else { /* RV200, R200 */
		3011	mem_trcd = (temp & 0x7) + 1;
		3012	mem_trp = ((temp >> 8) & 0x7) + 1;
		3013	mem_tras = ((temp >> 12) & 0xf) + 4;
		3014	}
		3015	/* convert to FF */
1963	serge	3016	trcd_ff.full = dfixed_const(mem_trcd);
		3017	trp_ff.full = dfixed_const(mem_trp);
		3018	tras_ff.full = dfixed_const(mem_tras);
1179	serge	3019
		3020	/* Get values from the MEM_SDRAM_MODE_REG register...converting its */
		3021	temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		3022	data = (temp & (7 << 20)) >> 20;
		3023	if ((rdev->family == CHIP_RV100) \|\| rdev->flags & RADEON_IS_IGP) {
		3024	if (rdev->family == CHIP_RS480) /* don't think rs400 */
		3025	tcas_ff = memtcas_rs480_ff[data];
		3026	else
		3027	tcas_ff = memtcas_ff[data];
		3028	} else
		3029	tcas_ff = memtcas2_ff[data];
		3030
		3031	if (rdev->family == CHIP_RS400 \|\|
		3032	rdev->family == CHIP_RS480) {
		3033	/* extra cas latency stored in bits 23-25 0-4 clocks */
		3034	data = (temp >> 23) & 0x7;
		3035	if (data < 5)
1963	serge	3036	tcas_ff.full += dfixed_const(data);
1179	serge	3037	}
		3038
		3039	if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
		3040	/* on the R300, Tcas is included in Trbs.
		3041	*/
		3042	temp = RREG32(RADEON_MEM_CNTL);
		3043	data = (R300_MEM_NUM_CHANNELS_MASK & temp);
		3044	if (data == 1) {
		3045	if (R300_MEM_USE_CD_CH_ONLY & temp) {
		3046	temp = RREG32(R300_MC_IND_INDEX);
		3047	temp &= ~R300_MC_IND_ADDR_MASK;
		3048	temp \|= R300_MC_READ_CNTL_CD_mcind;
		3049	WREG32(R300_MC_IND_INDEX, temp);
		3050	temp = RREG32(R300_MC_IND_DATA);
		3051	data = (R300_MEM_RBS_POSITION_C_MASK & temp);
		3052	} else {
		3053	temp = RREG32(R300_MC_READ_CNTL_AB);
		3054	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		3055	}
		3056	} else {
		3057	temp = RREG32(R300_MC_READ_CNTL_AB);
		3058	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		3059	}
		3060	if (rdev->family == CHIP_RV410 \|\|
		3061	rdev->family == CHIP_R420 \|\|
		3062	rdev->family == CHIP_R423)
		3063	trbs_ff = memtrbs_r4xx[data];
		3064	else
		3065	trbs_ff = memtrbs[data];
		3066	tcas_ff.full += trbs_ff.full;
		3067	}
		3068
		3069	sclk_eff_ff.full = sclk_ff.full;
		3070
		3071	if (rdev->flags & RADEON_IS_AGP) {
		3072	fixed20_12 agpmode_ff;
1963	serge	3073	agpmode_ff.full = dfixed_const(radeon_agpmode);
		3074	temp_ff.full = dfixed_const_666(16);
		3075	sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
1179	serge	3076	}
		3077	/* TODO PCIE lanes may affect this - agpmode == 16?? */
		3078
		3079	if (ASIC_IS_R300(rdev)) {
1963	serge	3080	sclk_delay_ff.full = dfixed_const(250);
1179	serge	3081	} else {
		3082	if ((rdev->family == CHIP_RV100) \|\|
		3083	rdev->flags & RADEON_IS_IGP) {
		3084	if (rdev->mc.vram_is_ddr)
1963	serge	3085	sclk_delay_ff.full = dfixed_const(41);
1179	serge	3086	else
1963	serge	3087	sclk_delay_ff.full = dfixed_const(33);
1179	serge	3088	} else {
		3089	if (rdev->mc.vram_width == 128)
1963	serge	3090	sclk_delay_ff.full = dfixed_const(57);
1179	serge	3091	else
1963	serge	3092	sclk_delay_ff.full = dfixed_const(41);
1179	serge	3093	}
		3094	}
		3095
1963	serge	3096	mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
1179	serge	3097
		3098	if (rdev->mc.vram_is_ddr) {
		3099	if (rdev->mc.vram_width == 32) {
1963	serge	3100	k1.full = dfixed_const(40);
1179	serge	3101	c = 3;
		3102	} else {
1963	serge	3103	k1.full = dfixed_const(20);
1179	serge	3104	c = 1;
		3105	}
		3106	} else {
1963	serge	3107	k1.full = dfixed_const(40);
1179	serge	3108	c = 3;
		3109	}
		3110
1963	serge	3111	temp_ff.full = dfixed_const(2);
		3112	mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
		3113	temp_ff.full = dfixed_const(c);
		3114	mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
		3115	temp_ff.full = dfixed_const(4);
		3116	mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
		3117	mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
1179	serge	3118	mc_latency_mclk.full += k1.full;
		3119
1963	serge	3120	mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
		3121	mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
1179	serge	3122
		3123	/*
		3124	HW cursor time assuming worst case of full size colour cursor.
		3125	*/
1963	serge	3126	temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
1179	serge	3127	temp_ff.full += trcd_ff.full;
		3128	if (temp_ff.full < tras_ff.full)
		3129	temp_ff.full = tras_ff.full;
1963	serge	3130	cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
1179	serge	3131
1963	serge	3132	temp_ff.full = dfixed_const(cur_size);
		3133	cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
1179	serge	3134	/*
		3135	Find the total latency for the display data.
		3136	*/
1963	serge	3137	disp_latency_overhead.full = dfixed_const(8);
		3138	disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
1179	serge	3139	mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
		3140	mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
		3141
		3142	if (mc_latency_mclk.full > mc_latency_sclk.full)
		3143	disp_latency.full = mc_latency_mclk.full;
		3144	else
		3145	disp_latency.full = mc_latency_sclk.full;
		3146
		3147	/* setup Max GRPH_STOP_REQ default value */
		3148	if (ASIC_IS_RV100(rdev))
		3149	max_stop_req = 0x5c;
		3150	else
		3151	max_stop_req = 0x7c;
		3152
		3153	if (mode1) {
		3154	/* CRTC1
		3155	Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
		3156	GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
		3157	*/
		3158	stop_req = mode1->hdisplay * pixel_bytes1 / 16;
		3159
		3160	if (stop_req > max_stop_req)
		3161	stop_req = max_stop_req;
		3162
		3163	/*
		3164	Find the drain rate of the display buffer.
		3165	*/
1963	serge	3166	temp_ff.full = dfixed_const((16/pixel_bytes1));
		3167	disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
1179	serge	3168
		3169	/*
		3170	Find the critical point of the display buffer.
		3171	*/
1963	serge	3172	crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
		3173	crit_point_ff.full += dfixed_const_half(0);
1179	serge	3174
1963	serge	3175	critical_point = dfixed_trunc(crit_point_ff);
1179	serge	3176
		3177	if (rdev->disp_priority == 2) {
		3178	critical_point = 0;
		3179	}
		3180
		3181	/*
		3182	The critical point should never be above max_stop_req-4. Setting
		3183	GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
		3184	*/
		3185	if (max_stop_req - critical_point < 4)
		3186	critical_point = 0;
		3187
		3188	if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
		3189	/* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
		3190	critical_point = 0x10;
		3191	}
		3192
		3193	temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
		3194	temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
		3195	temp \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		3196	temp &= ~(RADEON_GRPH_START_REQ_MASK);
		3197	if ((rdev->family == CHIP_R350) &&
		3198	(stop_req > 0x15)) {
		3199	stop_req -= 0x10;
		3200	}
		3201	temp \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		3202	temp \|= RADEON_GRPH_BUFFER_SIZE;
		3203	temp &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		3204	RADEON_GRPH_CRITICAL_AT_SOF \|
		3205	RADEON_GRPH_STOP_CNTL);
		3206	/*
		3207	Write the result into the register.
		3208	*/
		3209	WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		3210	(critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		3211
		3212	#if 0
		3213	if ((rdev->family == CHIP_RS400) \|\|
		3214	(rdev->family == CHIP_RS480)) {
		3215	/* attempt to program RS400 disp regs correctly ??? */
		3216	temp = RREG32(RS400_DISP1_REG_CNTL);
		3217	temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK \|
		3218	RS400_DISP1_STOP_REQ_LEVEL_MASK);
		3219	WREG32(RS400_DISP1_REQ_CNTL1, (temp \|
		3220	(critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		3221	(critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		3222	temp = RREG32(RS400_DMIF_MEM_CNTL1);
		3223	temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK \|
		3224	RS400_DISP1_CRITICAL_POINT_STOP_MASK);
		3225	WREG32(RS400_DMIF_MEM_CNTL1, (temp \|
		3226	(critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) \|
		3227	(critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
		3228	}
		3229	#endif
		3230
1963	serge	3231	DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
1179	serge	3232	/* (unsigned int)info->SavedReg->grph_buffer_cntl, */
		3233	(unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
		3234	}
		3235
		3236	if (mode2) {
		3237	u32 grph2_cntl;
		3238	stop_req = mode2->hdisplay * pixel_bytes2 / 16;
		3239
		3240	if (stop_req > max_stop_req)
		3241	stop_req = max_stop_req;
		3242
		3243	/*
		3244	Find the drain rate of the display buffer.
		3245	*/
1963	serge	3246	temp_ff.full = dfixed_const((16/pixel_bytes2));
		3247	disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
1179	serge	3248
		3249	grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
		3250	grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
		3251	grph2_cntl \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		3252	grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
		3253	if ((rdev->family == CHIP_R350) &&
		3254	(stop_req > 0x15)) {
		3255	stop_req -= 0x10;
		3256	}
		3257	grph2_cntl \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		3258	grph2_cntl \|= RADEON_GRPH_BUFFER_SIZE;
		3259	grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		3260	RADEON_GRPH_CRITICAL_AT_SOF \|
		3261	RADEON_GRPH_STOP_CNTL);
		3262
		3263	if ((rdev->family == CHIP_RS100) \|\|
		3264	(rdev->family == CHIP_RS200))
		3265	critical_point2 = 0;
		3266	else {
		3267	temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
1963	serge	3268	temp_ff.full = dfixed_const(temp);
		3269	temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
1179	serge	3270	if (sclk_ff.full < temp_ff.full)
		3271	temp_ff.full = sclk_ff.full;
		3272
		3273	read_return_rate.full = temp_ff.full;
		3274
		3275	if (mode1) {
		3276	temp_ff.full = read_return_rate.full - disp_drain_rate.full;
1963	serge	3277	time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
1179	serge	3278	} else {
		3279	time_disp1_drop_priority.full = 0;
		3280	}
		3281	crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
1963	serge	3282	crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
		3283	crit_point_ff.full += dfixed_const_half(0);
1179	serge	3284
1963	serge	3285	critical_point2 = dfixed_trunc(crit_point_ff);
1179	serge	3286
		3287	if (rdev->disp_priority == 2) {
		3288	critical_point2 = 0;
		3289	}
		3290
		3291	if (max_stop_req - critical_point2 < 4)
		3292	critical_point2 = 0;
		3293
		3294	}
		3295
		3296	if (critical_point2 == 0 && rdev->family == CHIP_R300) {
		3297	/* some R300 cards have problem with this set to 0 */
		3298	critical_point2 = 0x10;
		3299	}
		3300
		3301	WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		3302	(critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		3303
		3304	if ((rdev->family == CHIP_RS400) \|\|
		3305	(rdev->family == CHIP_RS480)) {
		3306	#if 0
		3307	/* attempt to program RS400 disp2 regs correctly ??? */
		3308	temp = RREG32(RS400_DISP2_REQ_CNTL1);
		3309	temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK \|
		3310	RS400_DISP2_STOP_REQ_LEVEL_MASK);
		3311	WREG32(RS400_DISP2_REQ_CNTL1, (temp \|
		3312	(critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		3313	(critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		3314	temp = RREG32(RS400_DISP2_REQ_CNTL2);
		3315	temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK \|
		3316	RS400_DISP2_CRITICAL_POINT_STOP_MASK);
		3317	WREG32(RS400_DISP2_REQ_CNTL2, (temp \|
		3318	(critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) \|
		3319	(critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
		3320	#endif
		3321	WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
		3322	WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
		3323	WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
		3324	WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
		3325	}
		3326
1963	serge	3327	DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
1179	serge	3328	(unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
		3329	}
		3330	}
		3331
2997	Serge	3332	int r100_ring_test(struct radeon_device rdev, struct radeon_ring ring)
1963	serge	3333	{
1412	serge	3334	uint32_t scratch;
		3335	uint32_t tmp = 0;
		3336	unsigned i;
		3337	int r;
1179	serge	3338
1412	serge	3339	r = radeon_scratch_get(rdev, &scratch);
		3340	if (r) {
		3341	DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
		3342	return r;
		3343	}
		3344	WREG32(scratch, 0xCAFEDEAD);
2997	Serge	3345	r = radeon_ring_lock(rdev, ring, 2);
1412	serge	3346	if (r) {
		3347	DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
		3348	radeon_scratch_free(rdev, scratch);
		3349	return r;
		3350	}
2997	Serge	3351	radeon_ring_write(ring, PACKET0(scratch, 0));
		3352	radeon_ring_write(ring, 0xDEADBEEF);
		3353	radeon_ring_unlock_commit(rdev, ring);
1412	serge	3354	for (i = 0; i < rdev->usec_timeout; i++) {
		3355	tmp = RREG32(scratch);
		3356	if (tmp == 0xDEADBEEF) {
		3357	break;
		3358	}
		3359	DRM_UDELAY(1);
		3360	}
		3361	if (i < rdev->usec_timeout) {
		3362	DRM_INFO("ring test succeeded in %d usecs\n", i);
		3363	} else {
1963	serge	3364	DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1412	serge	3365	scratch, tmp);
		3366	r = -EINVAL;
		3367	}
		3368	radeon_scratch_free(rdev, scratch);
		3369	return r;
		3370	}
		3371
1963	serge	3372	void r100_ring_ib_execute(struct radeon_device rdev, struct radeon_ib ib)
		3373	{
2997	Serge	3374	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
		3375
		3376	if (ring->rptr_save_reg) {
		3377	u32 next_rptr = ring->wptr + 2 + 3;
		3378	radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
		3379	radeon_ring_write(ring, next_rptr);
		3380	}
		3381
		3382	radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
		3383	radeon_ring_write(ring, ib->gpu_addr);
		3384	radeon_ring_write(ring, ib->length_dw);
1963	serge	3385	}
		3386
2997	Serge	3387	int r100_ib_test(struct radeon_device rdev, struct radeon_ring ring)
1963	serge	3388	{
2997	Serge	3389	struct radeon_ib ib;
1963	serge	3390	uint32_t scratch;
		3391	uint32_t tmp = 0;
		3392	unsigned i;
		3393	int r;
		3394
		3395	r = radeon_scratch_get(rdev, &scratch);
		3396	if (r) {
		3397	DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
		3398	return r;
		3399	}
		3400	WREG32(scratch, 0xCAFEDEAD);
2997	Serge	3401	r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
1963	serge	3402	if (r) {
2997	Serge	3403	DRM_ERROR("radeon: failed to get ib (%d).\n", r);
		3404	goto free_scratch;
1963	serge	3405	}
2997	Serge	3406	ib.ptr[0] = PACKET0(scratch, 0);
		3407	ib.ptr[1] = 0xDEADBEEF;
		3408	ib.ptr[2] = PACKET2(0);
		3409	ib.ptr[3] = PACKET2(0);
		3410	ib.ptr[4] = PACKET2(0);
		3411	ib.ptr[5] = PACKET2(0);
		3412	ib.ptr[6] = PACKET2(0);
		3413	ib.ptr[7] = PACKET2(0);
		3414	ib.length_dw = 8;
		3415	r = radeon_ib_schedule(rdev, &ib, NULL);
1963	serge	3416	if (r) {
2997	Serge	3417	DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
		3418	goto free_ib;
1963	serge	3419	}
2997	Serge	3420	r = radeon_fence_wait(ib.fence, false);
1963	serge	3421	if (r) {
2997	Serge	3422	DRM_ERROR("radeon: fence wait failed (%d).\n", r);
		3423	goto free_ib;
1963	serge	3424	}
		3425	for (i = 0; i < rdev->usec_timeout; i++) {
		3426	tmp = RREG32(scratch);
		3427	if (tmp == 0xDEADBEEF) {
		3428	break;
		3429	}
		3430	DRM_UDELAY(1);
		3431	}
		3432	if (i < rdev->usec_timeout) {
		3433	DRM_INFO("ib test succeeded in %u usecs\n", i);
		3434	} else {
		3435	DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
		3436	scratch, tmp);
		3437	r = -EINVAL;
		3438	}
2997	Serge	3439	free_ib:
		3440	radeon_ib_free(rdev, &ib);
		3441	free_scratch:
1963	serge	3442	radeon_scratch_free(rdev, scratch);
		3443	return r;
		3444	}
		3445
1179	serge	3446	void r100_mc_stop(struct radeon_device rdev, struct r100_mc_save save)
		3447	{
		3448	/* Shutdown CP we shouldn't need to do that but better be safe than
		3449	* sorry
		3450	*/
2997	Serge	3451	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1179	serge	3452	WREG32(R_000740_CP_CSQ_CNTL, 0);
		3453
		3454	/* Save few CRTC registers */
1221	serge	3455	save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
1179	serge	3456	save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
		3457	save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
		3458	save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
		3459	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3460	save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
		3461	save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
		3462	}
		3463
		3464	/* Disable VGA aperture access */
1221	serge	3465	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
1179	serge	3466	/* Disable cursor, overlay, crtc */
		3467	WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET \| S_000260_CUR_LOCK(1));
		3468	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL \|
		3469	S_000054_CRTC_DISPLAY_DIS(1));
		3470	WREG32(R_000050_CRTC_GEN_CNTL,
		3471	(C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) \|
		3472	S_000050_CRTC_DISP_REQ_EN_B(1));
		3473	WREG32(R_000420_OV0_SCALE_CNTL,
		3474	C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
		3475	WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
		3476	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3477	WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET \|
		3478	S_000360_CUR2_LOCK(1));
		3479	WREG32(R_0003F8_CRTC2_GEN_CNTL,
		3480	(C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) \|
		3481	S_0003F8_CRTC2_DISPLAY_DIS(1) \|
		3482	S_0003F8_CRTC2_DISP_REQ_EN_B(1));
		3483	WREG32(R_000360_CUR2_OFFSET,
		3484	C_000360_CUR2_LOCK & save->CUR2_OFFSET);
		3485	}
		3486	}
		3487
		3488	void r100_mc_resume(struct radeon_device rdev, struct r100_mc_save save)
		3489	{
		3490	/* Update base address for crtc */
1430	serge	3491	WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
1179	serge	3492	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
1430	serge	3493	WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
1179	serge	3494	}
		3495	/* Restore CRTC registers */
1221	serge	3496	WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
1179	serge	3497	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
		3498	WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
		3499	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3500	WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
		3501	}
		3502	}
		3503
1221	serge	3504	void r100_vga_render_disable(struct radeon_device *rdev)
		3505	{
		3506	u32 tmp;
		3507
		3508	tmp = RREG8(R_0003C2_GENMO_WT);
		3509	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
		3510	}
		3511
		3512	static void r100_debugfs(struct radeon_device *rdev)
		3513	{
		3514	int r;
		3515
		3516	r = r100_debugfs_mc_info_init(rdev);
		3517	if (r)
		3518	dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		3519	}
		3520
		3521	static void r100_mc_program(struct radeon_device *rdev)
		3522	{
		3523	struct r100_mc_save save;
		3524
		3525	/* Stops all mc clients */
		3526	r100_mc_stop(rdev, &save);
		3527	if (rdev->flags & RADEON_IS_AGP) {
		3528	WREG32(R_00014C_MC_AGP_LOCATION,
		3529	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		3530	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		3531	WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		3532	if (rdev->family > CHIP_RV200)
		3533	WREG32(R_00015C_AGP_BASE_2,
		3534	upper_32_bits(rdev->mc.agp_base) & 0xff);
		3535	} else {
		3536	WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		3537	WREG32(R_000170_AGP_BASE, 0);
		3538	if (rdev->family > CHIP_RV200)
		3539	WREG32(R_00015C_AGP_BASE_2, 0);
		3540	}
		3541	/* Wait for mc idle */
		3542	if (r100_mc_wait_for_idle(rdev))
		3543	dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
		3544	/* Program MC, should be a 32bits limited address space */
		3545	WREG32(R_000148_MC_FB_LOCATION,
		3546	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		3547	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		3548	r100_mc_resume(rdev, &save);
		3549	}
		3550
2997	Serge	3551	static void r100_clock_startup(struct radeon_device *rdev)
1221	serge	3552	{
		3553	u32 tmp;
		3554
		3555	if (radeon_dynclks != -1 && radeon_dynclks)
		3556	radeon_legacy_set_clock_gating(rdev, 1);
		3557	/* We need to force on some of the block */
		3558	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
		3559	tmp \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		3560	if ((rdev->family == CHIP_RV250) \|\| (rdev->family == CHIP_RV280))
		3561	tmp \|= S_00000D_FORCE_DISP1(1) \| S_00000D_FORCE_DISP2(1);
		3562	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
		3563	}
		3564
		3565	static int r100_startup(struct radeon_device *rdev)
		3566	{
		3567	int r;
		3568
1321	serge	3569	/* set common regs */
		3570	r100_set_common_regs(rdev);
		3571	/* program mc */
1221	serge	3572	r100_mc_program(rdev);
		3573	/* Resume clock */
		3574	r100_clock_startup(rdev);
		3575	/* Initialize GART (initialize after TTM so we can allocate
		3576	* memory through TTM but finalize after TTM) */
1321	serge	3577	r100_enable_bm(rdev);
1221	serge	3578	if (rdev->flags & RADEON_IS_PCI) {
		3579	r = r100_pci_gart_enable(rdev);
		3580	if (r)
		3581	return r;
		3582	}
2005	serge	3583
		3584	/* allocate wb buffer */
		3585	r = radeon_wb_init(rdev);
		3586	if (r)
		3587	return r;
		3588
3120	serge	3589	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
		3590	if (r) {
		3591	dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
		3592	return r;
		3593	}
		3594
1221	serge	3595	/* Enable IRQ */
2005	serge	3596	r100_irq_set(rdev);
1404	serge	3597	rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1221	serge	3598	/* 1M ring buffer */
1412	serge	3599	r = r100_cp_init(rdev, 1024 * 1024);
		3600	if (r) {
1963	serge	3601	dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1412	serge	3602	return r;
		3603	}
2997	Serge	3604
		3605	r = radeon_ib_pool_init(rdev);
2005	serge	3606	if (r) {
2997	Serge	3607	dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2005	serge	3608	return r;
		3609	}
3120	serge	3610
1221	serge	3611	return 0;
		3612	}
		3613
1963	serge	3614	/*
		3615	* Due to how kexec works, it can leave the hw fully initialised when it
		3616	* boots the new kernel. However doing our init sequence with the CP and
		3617	* WB stuff setup causes GPU hangs on the RN50 at least. So at startup
		3618	* do some quick sanity checks and restore sane values to avoid this
		3619	* problem.
		3620	*/
		3621	void r100_restore_sanity(struct radeon_device *rdev)
		3622	{
		3623	u32 tmp;
1221	serge	3624
1963	serge	3625	tmp = RREG32(RADEON_CP_CSQ_CNTL);
		3626	if (tmp) {
		3627	WREG32(RADEON_CP_CSQ_CNTL, 0);
		3628	}
		3629	tmp = RREG32(RADEON_CP_RB_CNTL);
		3630	if (tmp) {
		3631	WREG32(RADEON_CP_RB_CNTL, 0);
		3632	}
		3633	tmp = RREG32(RADEON_SCRATCH_UMSK);
		3634	if (tmp) {
		3635	WREG32(RADEON_SCRATCH_UMSK, 0);
		3636	}
		3637	}
1221	serge	3638
		3639	int r100_init(struct radeon_device *rdev)
		3640	{
		3641	int r;
		3642
		3643	/* Register debugfs file specific to this group of asics */
		3644	r100_debugfs(rdev);
		3645	/* Disable VGA */
		3646	r100_vga_render_disable(rdev);
		3647	/* Initialize scratch registers */
		3648	radeon_scratch_init(rdev);
		3649	/* Initialize surface registers */
		3650	radeon_surface_init(rdev);
1963	serge	3651	/* sanity check some register to avoid hangs like after kexec */
		3652	r100_restore_sanity(rdev);
1221	serge	3653	/* TODO: disable VGA need to use VGA request */
		3654	/* BIOS*/
		3655	if (!radeon_get_bios(rdev)) {
		3656	if (ASIC_IS_AVIVO(rdev))
		3657	return -EINVAL;
		3658	}
		3659	if (rdev->is_atom_bios) {
		3660	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		3661	return -EINVAL;
		3662	} else {
		3663	r = radeon_combios_init(rdev);
		3664	if (r)
		3665	return r;
		3666	}
		3667	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
1963	serge	3668	if (radeon_asic_reset(rdev)) {
1221	serge	3669	dev_warn(rdev->dev,
		3670	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		3671	RREG32(R_000E40_RBBM_STATUS),
		3672	RREG32(R_0007C0_CP_STAT));
		3673	}
		3674	/* check if cards are posted or not */
1321	serge	3675	if (radeon_boot_test_post_card(rdev) == false)
		3676	return -EINVAL;
1221	serge	3677	/* Set asic errata */
		3678	r100_errata(rdev);
		3679	/* Initialize clocks */
		3680	radeon_get_clock_info(rdev->ddev);
1430	serge	3681	/* initialize AGP */
		3682	if (rdev->flags & RADEON_IS_AGP) {
		3683	r = radeon_agp_init(rdev);
		3684	if (r) {
		3685	radeon_agp_disable(rdev);
		3686	}
		3687	}
		3688	/* initialize VRAM */
		3689	r100_mc_init(rdev);
1221	serge	3690	/* Fence driver */
2005	serge	3691	r = radeon_fence_driver_init(rdev);
		3692	if (r)
		3693	return r;
		3694	r = radeon_irq_kms_init(rdev);
		3695	if (r)
		3696	return r;
1221	serge	3697	/* Memory manager */
1321	serge	3698	r = radeon_bo_init(rdev);
1221	serge	3699	if (r)
		3700	return r;
		3701	if (rdev->flags & RADEON_IS_PCI) {
		3702	r = r100_pci_gart_init(rdev);
		3703	if (r)
		3704	return r;
		3705	}
		3706	r100_set_safe_registers(rdev);
2997	Serge	3707
1221	serge	3708	rdev->accel_working = true;
		3709	r = r100_startup(rdev);
		3710	if (r) {
		3711	/* Somethings want wront with the accel init stop accel */
		3712	dev_err(rdev->dev, "Disabling GPU acceleration\n");
		3713	if (rdev->flags & RADEON_IS_PCI)
		3714	r100_pci_gart_fini(rdev);
		3715	rdev->accel_working = false;
		3716	}
		3717	return 0;
		3718	}
2997	Serge	3719
3192	Serge	3720	uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
		3721	bool always_indirect)
2997	Serge	3722	{
3192	Serge	3723	if (reg < rdev->rmmio_size && !always_indirect)
2997	Serge	3724	return readl(((void __iomem *)rdev->rmmio) + reg);
		3725	else {
3192	Serge	3726	unsigned long flags;
		3727	uint32_t ret;
		3728
		3729	spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2997	Serge	3730	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
3192	Serge	3731	ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
		3732	spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
		3733
		3734	return ret;
2997	Serge	3735	}
		3736	}
		3737
3192	Serge	3738	void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
		3739	bool always_indirect)
2997	Serge	3740	{
3192	Serge	3741	if (reg < rdev->rmmio_size && !always_indirect)
2997	Serge	3742	writel(v, ((void __iomem *)rdev->rmmio) + reg);
		3743	else {
3192	Serge	3744	unsigned long flags;
		3745
		3746	spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2997	Serge	3747	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		3748	writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
3192	Serge	3749	spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2997	Serge	3750	}
		3751	}
		3752
		3753	u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
		3754	{
		3755	if (reg < rdev->rio_mem_size)
		3756	return ioread32(rdev->rio_mem + reg);
		3757	else {
		3758	iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
		3759	return ioread32(rdev->rio_mem + RADEON_MM_DATA);
		3760	}
		3761	}
		3762
		3763	void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		3764	{
		3765	if (reg < rdev->rio_mem_size)
		3766	iowrite32(v, rdev->rio_mem + reg);
		3767	else {
		3768	iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
		3769	iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
		3770	}
		3771	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r100.c – Rev 3192