WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r100.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1179	serge	28	#include
1963	serge	29	#include
2997	Serge	30	#include
		31	#include
1117	serge	32	#include "radeon_reg.h"
		33	#include "radeon.h"
1963	serge	34	#include "radeon_asic.h"
1179	serge	35	#include "r100d.h"
1221	serge	36	#include "rs100d.h"
		37	#include "rv200d.h"
		38	#include "rv250d.h"
1963	serge	39	#include "atom.h"
1117	serge	40
1221	serge	41	#include
2997	Serge	42	#include
1221	serge	43
1179	serge	44	#include "r100_reg_safe.h"
		45	#include "rn50_reg_safe.h"
1221	serge	46
		47	/* Firmware Names */
		48	#define FIRMWARE_R100 "radeon/R100_cp.bin"
		49	#define FIRMWARE_R200 "radeon/R200_cp.bin"
		50	#define FIRMWARE_R300 "radeon/R300_cp.bin"
		51	#define FIRMWARE_R420 "radeon/R420_cp.bin"
		52	#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
		53	#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
		54	#define FIRMWARE_R520 "radeon/R520_cp.bin"
		55
		56	MODULE_FIRMWARE(FIRMWARE_R100);
		57	MODULE_FIRMWARE(FIRMWARE_R200);
		58	MODULE_FIRMWARE(FIRMWARE_R300);
		59	MODULE_FIRMWARE(FIRMWARE_R420);
		60	MODULE_FIRMWARE(FIRMWARE_RS690);
		61	MODULE_FIRMWARE(FIRMWARE_RS600);
		62	MODULE_FIRMWARE(FIRMWARE_R520);
		63
		64
1117	serge	65	/* This files gather functions specifics to:
		66	* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
2997	Serge	67	* and others in some cases.
1117	serge	68	*/
		69
2997	Serge	70	/**
		71	* r100_wait_for_vblank - vblank wait asic callback.
		72	*
		73	* @rdev: radeon_device pointer
		74	* @crtc: crtc to wait for vblank on
		75	*
		76	* Wait for vblank on the requested crtc (r1xx-r4xx).
		77	*/
		78	void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
		79	{
		80	int i;
		81
		82	if (crtc >= rdev->num_crtc)
		83	return;
		84
		85	if (crtc == 0) {
		86	if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
		87	for (i = 0; i < rdev->usec_timeout; i++) {
		88	if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
		89	break;
		90	udelay(1);
		91	}
		92	for (i = 0; i < rdev->usec_timeout; i++) {
		93	if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
		94	break;
		95	udelay(1);
		96	}
		97	}
		98	} else {
		99	if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
		100	for (i = 0; i < rdev->usec_timeout; i++) {
		101	if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
		102	break;
		103	udelay(1);
		104	}
		105	for (i = 0; i < rdev->usec_timeout; i++) {
		106	if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
		107	break;
		108	udelay(1);
		109	}
		110	}
		111	}
		112	}
1963	serge	113	u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
		114	{
		115	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
		116	u32 tmp = ((u32)crtc_base) \| RADEON_CRTC_OFFSET__OFFSET_LOCK;
2997	Serge	117	int i;
1963	serge	118
		119	/* Lock the graphics update lock */
		120	/* update the scanout addresses */
		121	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
		122
		123	/* Wait for update_pending to go high. */
2997	Serge	124	for (i = 0; i < rdev->usec_timeout; i++) {
		125	if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
		126	break;
		127	udelay(1);
		128	}
1963	serge	129	DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
		130
		131	/* Unlock the lock, so double-buffering can take place inside vblank */
		132	tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
		133	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
		134
		135	/* Return current update_pending status: */
		136	return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
		137	}
		138	bool r100_gui_idle(struct radeon_device *rdev)
		139	{
		140	if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
		141	return false;
		142	else
		143	return true;
		144	}
		145
1321	serge	146	/* hpd for digital panel detect/disconnect */
2997	Serge	147	/**
		148	* r100_hpd_sense - hpd sense callback.
		149	*
		150	* @rdev: radeon_device pointer
		151	* @hpd: hpd (hotplug detect) pin
		152	*
		153	* Checks if a digital monitor is connected (r1xx-r4xx).
		154	* Returns true if connected, false if not connected.
		155	*/
1321	serge	156	bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
		157	{
		158	bool connected = false;
		159
		160	switch (hpd) {
		161	case RADEON_HPD_1:
		162	if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
		163	connected = true;
		164	break;
		165	case RADEON_HPD_2:
		166	if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
		167	connected = true;
		168	break;
		169	default:
		170	break;
		171	}
		172	return connected;
		173	}
		174
2997	Serge	175	/**
		176	* r100_hpd_set_polarity - hpd set polarity callback.
		177	*
		178	* @rdev: radeon_device pointer
		179	* @hpd: hpd (hotplug detect) pin
		180	*
		181	* Set the polarity of the hpd pin (r1xx-r4xx).
		182	*/
1321	serge	183	void r100_hpd_set_polarity(struct radeon_device *rdev,
		184	enum radeon_hpd_id hpd)
		185	{
		186	u32 tmp;
		187	bool connected = r100_hpd_sense(rdev, hpd);
		188
		189	switch (hpd) {
		190	case RADEON_HPD_1:
		191	tmp = RREG32(RADEON_FP_GEN_CNTL);
		192	if (connected)
		193	tmp &= ~RADEON_FP_DETECT_INT_POL;
		194	else
		195	tmp \|= RADEON_FP_DETECT_INT_POL;
		196	WREG32(RADEON_FP_GEN_CNTL, tmp);
		197	break;
		198	case RADEON_HPD_2:
		199	tmp = RREG32(RADEON_FP2_GEN_CNTL);
		200	if (connected)
		201	tmp &= ~RADEON_FP2_DETECT_INT_POL;
		202	else
		203	tmp \|= RADEON_FP2_DETECT_INT_POL;
		204	WREG32(RADEON_FP2_GEN_CNTL, tmp);
		205	break;
		206	default:
		207	break;
		208	}
		209	}
		210
2997	Serge	211	/**
		212	* r100_hpd_init - hpd setup callback.
		213	*
		214	* @rdev: radeon_device pointer
		215	*
		216	* Setup the hpd pins used by the card (r1xx-r4xx).
		217	* Set the polarity, and enable the hpd interrupts.
		218	*/
1321	serge	219	void r100_hpd_init(struct radeon_device *rdev)
		220	{
		221	struct drm_device *dev = rdev->ddev;
		222	struct drm_connector *connector;
2997	Serge	223	unsigned enable = 0;
1321	serge	224
		225	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		226	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2997	Serge	227	enable \|= 1 << radeon_connector->hpd.hpd;
		228	radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
1321	serge	229	}
2997	Serge	230	// radeon_irq_kms_enable_hpd(rdev, enable);
1321	serge	231	}
		232
2997	Serge	233	/**
		234	* r100_hpd_fini - hpd tear down callback.
		235	*
		236	* @rdev: radeon_device pointer
		237	*
		238	* Tear down the hpd pins used by the card (r1xx-r4xx).
		239	* Disable the hpd interrupts.
		240	*/
1321	serge	241	void r100_hpd_fini(struct radeon_device *rdev)
		242	{
		243	struct drm_device *dev = rdev->ddev;
		244	struct drm_connector *connector;
2997	Serge	245	unsigned disable = 0;
1321	serge	246
		247	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		248	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2997	Serge	249	disable \|= 1 << radeon_connector->hpd.hpd;
1321	serge	250	}
2997	Serge	251	// radeon_irq_kms_disable_hpd(rdev, disable);
1321	serge	252	}
		253
1117	serge	254	/*
		255	* PCI GART
		256	*/
		257	void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
		258	{
		259	/* TODO: can we do somethings here ? */
		260	/* It seems hw only cache one entry so we should discard this
		261	* entry otherwise if first GPU GART read hit this entry it
		262	* could end up in wrong address. */
		263	}
		264
1179	serge	265	int r100_pci_gart_init(struct radeon_device *rdev)
1117	serge	266	{
		267	int r;
		268
2997	Serge	269	if (rdev->gart.ptr) {
1963	serge	270	WARN(1, "R100 PCI GART already initialized\n");
1179	serge	271	return 0;
		272	}
1117	serge	273	/* Initialize common gart structure */
		274	r = radeon_gart_init(rdev);
1179	serge	275	if (r)
1117	serge	276	return r;
1268	serge	277	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
2997	Serge	278	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
		279	rdev->asic->gart.set_page = &r100_pci_gart_set_page;
1179	serge	280	return radeon_gart_table_ram_alloc(rdev);
		281	}
		282
		283	int r100_pci_gart_enable(struct radeon_device *rdev)
		284	{
		285	uint32_t tmp;
		286
1430	serge	287	radeon_gart_restore(rdev);
1117	serge	288	/* discard memory request outside of configured range */
		289	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		290	WREG32(RADEON_AIC_CNTL, tmp);
		291	/* set address range for PCI address translate */
1430	serge	292	WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
		293	WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
1117	serge	294	/* set PCI GART page-table base address */
		295	WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
		296	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_PCIGART_TRANSLATE_EN;
		297	WREG32(RADEON_AIC_CNTL, tmp);
		298	r100_pci_gart_tlb_flush(rdev);
2997	Serge	299	DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
		300	(unsigned)(rdev->mc.gtt_size >> 20),
		301	(unsigned long long)rdev->gart.table_addr);
1117	serge	302	rdev->gart.ready = true;
		303	return 0;
		304	}
		305
		306	void r100_pci_gart_disable(struct radeon_device *rdev)
		307	{
		308	uint32_t tmp;
		309
		310	/* discard memory request outside of configured range */
		311	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		312	WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
		313	WREG32(RADEON_AIC_LO_ADDR, 0);
		314	WREG32(RADEON_AIC_HI_ADDR, 0);
		315	}
		316
		317	int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
		318	{
2997	Serge	319	u32 *gtt = rdev->gart.ptr;
		320
1117	serge	321	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
		322	return -EINVAL;
		323	}
2997	Serge	324	gtt[i] = cpu_to_le32(lower_32_bits(addr));
1117	serge	325	return 0;
		326	}
		327
1179	serge	328	void r100_pci_gart_fini(struct radeon_device *rdev)
1117	serge	329	{
1963	serge	330	radeon_gart_fini(rdev);
1117	serge	331	r100_pci_gart_disable(rdev);
1179	serge	332	radeon_gart_table_ram_free(rdev);
1117	serge	333	}
		334
2005	serge	335	int r100_irq_set(struct radeon_device *rdev)
		336	{
		337	uint32_t tmp = 0;
1117	serge	338
2005	serge	339	if (!rdev->irq.installed) {
		340	WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
		341	WREG32(R_000040_GEN_INT_CNTL, 0);
		342	return -EINVAL;
		343	}
2997	Serge	344	if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2005	serge	345	tmp \|= RADEON_SW_INT_ENABLE;
		346	}
		347	if (rdev->irq.crtc_vblank_int[0] \|\|
2997	Serge	348	atomic_read(&rdev->irq.pflip[0])) {
2005	serge	349	tmp \|= RADEON_CRTC_VBLANK_MASK;
		350	}
		351	if (rdev->irq.crtc_vblank_int[1] \|\|
2997	Serge	352	atomic_read(&rdev->irq.pflip[1])) {
2005	serge	353	tmp \|= RADEON_CRTC2_VBLANK_MASK;
		354	}
		355	if (rdev->irq.hpd[0]) {
		356	tmp \|= RADEON_FP_DETECT_MASK;
		357	}
		358	if (rdev->irq.hpd[1]) {
		359	tmp \|= RADEON_FP2_DETECT_MASK;
		360	}
		361	WREG32(RADEON_GEN_INT_CNTL, tmp);
		362	return 0;
		363	}
		364
1221	serge	365	void r100_irq_disable(struct radeon_device *rdev)
1117	serge	366	{
1221	serge	367	u32 tmp;
1117	serge	368
1221	serge	369	WREG32(R_000040_GEN_INT_CNTL, 0);
		370	/* Wait and acknowledge irq */
		371	mdelay(1);
		372	tmp = RREG32(R_000044_GEN_INT_STATUS);
		373	WREG32(R_000044_GEN_INT_STATUS, tmp);
1117	serge	374	}
		375
2997	Serge	376	static uint32_t r100_irq_ack(struct radeon_device *rdev)
1117	serge	377	{
1221	serge	378	uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
1321	serge	379	uint32_t irq_mask = RADEON_SW_INT_TEST \|
		380	RADEON_CRTC_VBLANK_STAT \| RADEON_CRTC2_VBLANK_STAT \|
		381	RADEON_FP_DETECT_STAT \| RADEON_FP2_DETECT_STAT;
1117	serge	382
1221	serge	383	if (irqs) {
		384	WREG32(RADEON_GEN_INT_STATUS, irqs);
1129	serge	385	}
1221	serge	386	return irqs & irq_mask;
1117	serge	387	}
		388
2005	serge	389	int r100_irq_process(struct radeon_device *rdev)
		390	{
		391	uint32_t status, msi_rearm;
		392	bool queue_hotplug = false;
1117	serge	393
3120	serge	394
2005	serge	395	status = r100_irq_ack(rdev);
		396	if (!status) {
		397	return IRQ_NONE;
		398	}
		399	if (rdev->shutdown) {
		400	return IRQ_NONE;
		401	}
		402	while (status) {
		403	/* SW interrupt */
		404	if (status & RADEON_SW_INT_TEST) {
2997	Serge	405	radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
2005	serge	406	}
		407	/* Vertical blank interrupts */
		408	if (status & RADEON_CRTC_VBLANK_STAT) {
		409	if (rdev->irq.crtc_vblank_int[0]) {
		410	// drm_handle_vblank(rdev->ddev, 0);
		411	rdev->pm.vblank_sync = true;
		412	// wake_up(&rdev->irq.vblank_queue);
		413	}
		414	// if (rdev->irq.pflip[0])
		415	// radeon_crtc_handle_flip(rdev, 0);
		416	}
		417	if (status & RADEON_CRTC2_VBLANK_STAT) {
		418	if (rdev->irq.crtc_vblank_int[1]) {
		419	// drm_handle_vblank(rdev->ddev, 1);
		420	rdev->pm.vblank_sync = true;
		421	// wake_up(&rdev->irq.vblank_queue);
		422	}
		423	// if (rdev->irq.pflip[1])
		424	// radeon_crtc_handle_flip(rdev, 1);
		425	}
		426	if (status & RADEON_FP_DETECT_STAT) {
		427	queue_hotplug = true;
		428	DRM_DEBUG("HPD1\n");
		429	}
		430	if (status & RADEON_FP2_DETECT_STAT) {
		431	queue_hotplug = true;
		432	DRM_DEBUG("HPD2\n");
		433	}
		434	status = r100_irq_ack(rdev);
		435	}
		436	// if (queue_hotplug)
		437	// schedule_work(&rdev->hotplug_work);
		438	if (rdev->msi_enabled) {
		439	switch (rdev->family) {
		440	case CHIP_RS400:
		441	case CHIP_RS480:
		442	msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
		443	WREG32(RADEON_AIC_CNTL, msi_rearm);
		444	WREG32(RADEON_AIC_CNTL, msi_rearm \| RS400_MSI_REARM);
		445	break;
		446	default:
2997	Serge	447	WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
2005	serge	448	break;
		449	}
		450	}
		451	return IRQ_HANDLED;
		452	}
		453
1403	serge	454	u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
		455	{
		456	if (crtc == 0)
		457	return RREG32(RADEON_CRTC_CRNT_FRAME);
		458	else
		459	return RREG32(RADEON_CRTC2_CRNT_FRAME);
		460	}
1117	serge	461
1404	serge	462	/* Who ever call radeon_fence_emit should call ring_lock and ask
		463	* for enough space (today caller are ib schedule and buffer move) */
1117	serge	464	void r100_fence_ring_emit(struct radeon_device *rdev,
		465	struct radeon_fence *fence)
		466	{
2997	Serge	467	struct radeon_ring *ring = &rdev->ring[fence->ring];
		468
1404	serge	469	/* We have to make sure that caches are flushed before
		470	* CPU might read something from VRAM. */
2997	Serge	471	radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
		472	radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
		473	radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
		474	radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
1117	serge	475	/* Wait until IDLE & CLEAN */
2997	Serge	476	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
		477	radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN \| RADEON_WAIT_3D_IDLECLEAN);
		478	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		479	radeon_ring_write(ring, rdev->config.r100.hdp_cntl \|
1403	serge	480	RADEON_HDP_READ_BUFFER_INVALIDATE);
2997	Serge	481	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		482	radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
1117	serge	483	/* Emit fence sequence & fire IRQ */
2997	Serge	484	radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
		485	radeon_ring_write(ring, fence->seq);
		486	radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
		487	radeon_ring_write(ring, RADEON_SW_INT_FIRE);
1117	serge	488	}
		489
2997	Serge	490	void r100_semaphore_ring_emit(struct radeon_device *rdev,
		491	struct radeon_ring *ring,
		492	struct radeon_semaphore *semaphore,
		493	bool emit_wait)
		494	{
		495	/* Unused on older asics, since we don't have semaphores or multiple rings */
		496	BUG();
		497	}
		498
1117	serge	499	int r100_copy_blit(struct radeon_device *rdev,
		500	uint64_t src_offset,
		501	uint64_t dst_offset,
2997	Serge	502	unsigned num_gpu_pages,
		503	struct radeon_fence **fence)
1117	serge	504	{
2997	Serge	505	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1117	serge	506	uint32_t cur_pages;
2997	Serge	507	uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
1117	serge	508	uint32_t pitch;
		509	uint32_t stride_pixels;
		510	unsigned ndw;
		511	int num_loops;
		512	int r = 0;
		513
		514	/* radeon limited to 16k stride */
		515	stride_bytes &= 0x3fff;
		516	/* radeon pitch is /64 */
		517	pitch = stride_bytes / 64;
		518	stride_pixels = stride_bytes / 4;
2997	Serge	519	num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
1117	serge	520
		521	/* Ask for enough room for blit + flush + fence */
		522	ndw = 64 + (10 * num_loops);
2997	Serge	523	r = radeon_ring_lock(rdev, ring, ndw);
1117	serge	524	if (r) {
		525	DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
		526	return -EINVAL;
		527	}
2997	Serge	528	while (num_gpu_pages > 0) {
		529	cur_pages = num_gpu_pages;
1117	serge	530	if (cur_pages > 8191) {
		531	cur_pages = 8191;
		532	}
2997	Serge	533	num_gpu_pages -= cur_pages;
1117	serge	534
		535	/* pages are in Y direction - height
		536	page width in X direction - width */
2997	Serge	537	radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
		538	radeon_ring_write(ring,
1117	serge	539	RADEON_GMC_SRC_PITCH_OFFSET_CNTL \|
		540	RADEON_GMC_DST_PITCH_OFFSET_CNTL \|
		541	RADEON_GMC_SRC_CLIPPING \|
		542	RADEON_GMC_DST_CLIPPING \|
		543	RADEON_GMC_BRUSH_NONE \|
		544	(RADEON_COLOR_FORMAT_ARGB8888 << 8) \|
		545	RADEON_GMC_SRC_DATATYPE_COLOR \|
		546	RADEON_ROP3_S \|
		547	RADEON_DP_SRC_SOURCE_MEMORY \|
		548	RADEON_GMC_CLR_CMP_CNTL_DIS \|
		549	RADEON_GMC_WR_MSK_DIS);
2997	Serge	550	radeon_ring_write(ring, (pitch << 22) \| (src_offset >> 10));
		551	radeon_ring_write(ring, (pitch << 22) \| (dst_offset >> 10));
		552	radeon_ring_write(ring, (0x1fff) \| (0x1fff << 16));
		553	radeon_ring_write(ring, 0);
		554	radeon_ring_write(ring, (0x1fff) \| (0x1fff << 16));
		555	radeon_ring_write(ring, num_gpu_pages);
		556	radeon_ring_write(ring, num_gpu_pages);
		557	radeon_ring_write(ring, cur_pages \| (stride_pixels << 16));
1117	serge	558	}
2997	Serge	559	radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
		560	radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
		561	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
		562	radeon_ring_write(ring,
1117	serge	563	RADEON_WAIT_2D_IDLECLEAN \|
		564	RADEON_WAIT_HOST_IDLECLEAN \|
		565	RADEON_WAIT_DMA_GUI_IDLE);
		566	if (fence) {
2997	Serge	567	r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
1117	serge	568	}
2997	Serge	569	radeon_ring_unlock_commit(rdev, ring);
1117	serge	570	return r;
		571	}
		572
1179	serge	573	static int r100_cp_wait_for_idle(struct radeon_device *rdev)
		574	{
		575	unsigned i;
		576	u32 tmp;
		577
		578	for (i = 0; i < rdev->usec_timeout; i++) {
		579	tmp = RREG32(R_000E40_RBBM_STATUS);
		580	if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
		581	return 0;
		582	}
		583	udelay(1);
		584	}
		585	return -1;
		586	}
		587
2997	Serge	588	void r100_ring_start(struct radeon_device rdev, struct radeon_ring ring)
1117	serge	589	{
		590	int r;
		591
2997	Serge	592	r = radeon_ring_lock(rdev, ring, 2);
1117	serge	593	if (r) {
		594	return;
		595	}
2997	Serge	596	radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
		597	radeon_ring_write(ring,
1117	serge	598	RADEON_ISYNC_ANY2D_IDLE3D \|
		599	RADEON_ISYNC_ANY3D_IDLE2D \|
		600	RADEON_ISYNC_WAIT_IDLEGUI \|
		601	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
2997	Serge	602	radeon_ring_unlock_commit(rdev, ring);
1117	serge	603	}
		604
1221	serge	605
		606	/* Load the microcode for the CP */
		607	static int r100_cp_init_microcode(struct radeon_device *rdev)
1117	serge	608	{
1221	serge	609	struct platform_device *pdev;
		610	const char *fw_name = NULL;
		611	int err;
1117	serge	612
1963	serge	613	DRM_DEBUG_KMS("\n");
1117	serge	614
1412	serge	615	pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
		616	err = IS_ERR(pdev);
		617	if (err) {
		618	printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
		619	return -EINVAL;
		620	}
1117	serge	621	if ((rdev->family == CHIP_R100) \|\| (rdev->family == CHIP_RV100) \|\|
		622	(rdev->family == CHIP_RV200) \|\| (rdev->family == CHIP_RS100) \|\|
		623	(rdev->family == CHIP_RS200)) {
		624	DRM_INFO("Loading R100 Microcode\n");
1221	serge	625	fw_name = FIRMWARE_R100;
1117	serge	626	} else if ((rdev->family == CHIP_R200) \|\|
		627	(rdev->family == CHIP_RV250) \|\|
		628	(rdev->family == CHIP_RV280) \|\|
		629	(rdev->family == CHIP_RS300)) {
		630	DRM_INFO("Loading R200 Microcode\n");
1221	serge	631	fw_name = FIRMWARE_R200;
1117	serge	632	} else if ((rdev->family == CHIP_R300) \|\|
		633	(rdev->family == CHIP_R350) \|\|
		634	(rdev->family == CHIP_RV350) \|\|
		635	(rdev->family == CHIP_RV380) \|\|
		636	(rdev->family == CHIP_RS400) \|\|
		637	(rdev->family == CHIP_RS480)) {
		638	DRM_INFO("Loading R300 Microcode\n");
1221	serge	639	fw_name = FIRMWARE_R300;
1117	serge	640	} else if ((rdev->family == CHIP_R420) \|\|
		641	(rdev->family == CHIP_R423) \|\|
		642	(rdev->family == CHIP_RV410)) {
		643	DRM_INFO("Loading R400 Microcode\n");
1221	serge	644	fw_name = FIRMWARE_R420;
1117	serge	645	} else if ((rdev->family == CHIP_RS690) \|\|
		646	(rdev->family == CHIP_RS740)) {
		647	DRM_INFO("Loading RS690/RS740 Microcode\n");
1221	serge	648	fw_name = FIRMWARE_RS690;
1117	serge	649	} else if (rdev->family == CHIP_RS600) {
		650	DRM_INFO("Loading RS600 Microcode\n");
1221	serge	651	fw_name = FIRMWARE_RS600;
1117	serge	652	} else if ((rdev->family == CHIP_RV515) \|\|
		653	(rdev->family == CHIP_R520) \|\|
		654	(rdev->family == CHIP_RV530) \|\|
		655	(rdev->family == CHIP_R580) \|\|
		656	(rdev->family == CHIP_RV560) \|\|
		657	(rdev->family == CHIP_RV570)) {
		658	DRM_INFO("Loading R500 Microcode\n");
1221	serge	659	fw_name = FIRMWARE_R520;
1117	serge	660	}
1221	serge	661
1412	serge	662	err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
		663	platform_device_unregister(pdev);
1221	serge	664	if (err) {
		665	printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
		666	fw_name);
		667	} else if (rdev->me_fw->size % 8) {
		668	printk(KERN_ERR
		669	"radeon_cp: Bogus length %zu in firmware \"%s\"\n",
		670	rdev->me_fw->size, fw_name);
		671	err = -EINVAL;
		672	release_firmware(rdev->me_fw);
		673	rdev->me_fw = NULL;
1117	serge	674	}
1221	serge	675	return err;
1117	serge	676	}
		677
1221	serge	678	static void r100_cp_load_microcode(struct radeon_device *rdev)
		679	{
		680	const __be32 *fw_data;
		681	int i, size;
		682
		683	if (r100_gui_wait_for_idle(rdev)) {
		684	printk(KERN_WARNING "Failed to wait GUI idle while "
		685	"programming pipes. Bad things might happen.\n");
		686	}
		687
		688	if (rdev->me_fw) {
		689	size = rdev->me_fw->size / 4;
		690	fw_data = (const __be32 *)&rdev->me_fw->data[0];
		691	WREG32(RADEON_CP_ME_RAM_ADDR, 0);
		692	for (i = 0; i < size; i += 2) {
		693	WREG32(RADEON_CP_ME_RAM_DATAH,
		694	be32_to_cpup(&fw_data[i]));
		695	WREG32(RADEON_CP_ME_RAM_DATAL,
		696	be32_to_cpup(&fw_data[i + 1]));
		697	}
		698	}
		699	}
		700
1117	serge	701	int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
		702	{
2997	Serge	703	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1117	serge	704	unsigned rb_bufsz;
		705	unsigned rb_blksz;
		706	unsigned max_fetch;
		707	unsigned pre_write_timer;
		708	unsigned pre_write_limit;
		709	unsigned indirect2_start;
		710	unsigned indirect1_start;
		711	uint32_t tmp;
		712	int r;
		713
1129	serge	714	if (r100_debugfs_cp_init(rdev)) {
		715	DRM_ERROR("Failed to register debugfs file for CP !\n");
		716	}
1179	serge	717	if (!rdev->me_fw) {
		718	r = r100_cp_init_microcode(rdev);
		719	if (r) {
		720	DRM_ERROR("Failed to load firmware!\n");
		721	return r;
		722	}
		723	}
		724
1117	serge	725	/* Align ring size */
		726	rb_bufsz = drm_order(ring_size / 8);
		727	ring_size = (1 << (rb_bufsz + 1)) * 4;
		728	r100_cp_load_microcode(rdev);
2997	Serge	729	r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
		730	RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
		731	0, 0x7fffff, RADEON_CP_PACKET2);
1117	serge	732	if (r) {
		733	return r;
		734	}
		735	/* Each time the cp read 1024 bytes (16 dword/quadword) update
		736	* the rptr copy in system ram */
		737	rb_blksz = 9;
		738	/* cp will read 128bytes at a time (4 dwords) */
		739	max_fetch = 1;
2997	Serge	740	ring->align_mask = 16 - 1;
1117	serge	741	/* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
		742	pre_write_timer = 64;
		743	/* Force CP_RB_WPTR write if written more than one time before the
		744	* delay expire
		745	*/
		746	pre_write_limit = 0;
		747	/* Setup the cp cache like this (cache size is 96 dwords) :
		748	* RING 0 to 15
		749	* INDIRECT1 16 to 79
		750	* INDIRECT2 80 to 95
		751	* So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		752	* indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
		753	* indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		754	* Idea being that most of the gpu cmd will be through indirect1 buffer
		755	* so it gets the bigger cache.
		756	*/
		757	indirect2_start = 80;
		758	indirect1_start = 16;
		759	/* cp setup */
		760	WREG32(0x718, pre_write_timer \| (pre_write_limit << 28));
1268	serge	761	tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) \|
1117	serge	762	REG_SET(RADEON_RB_BLKSZ, rb_blksz) \|
1963	serge	763	REG_SET(RADEON_MAX_FETCH, max_fetch));
1268	serge	764	#ifdef __BIG_ENDIAN
		765	tmp \|= RADEON_BUF_SWAP_32BIT;
		766	#endif
1963	serge	767	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_NO_UPDATE);
1268	serge	768
1117	serge	769	/* Set ring address */
2997	Serge	770	DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
		771	WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1117	serge	772	/* Force read & write ptr to 0 */
1963	serge	773	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA \| RADEON_RB_NO_UPDATE);
1117	serge	774	WREG32(RADEON_CP_RB_RPTR_WR, 0);
2997	Serge	775	ring->wptr = 0;
		776	WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1963	serge	777
		778	/* set the wb address whether it's enabled or not */
		779	WREG32(R_00070C_CP_RB_RPTR_ADDR,
		780	S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
		781	WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
		782
		783	if (rdev->wb.enabled)
		784	WREG32(R_000770_SCRATCH_UMSK, 0xff);
		785	else {
		786	tmp \|= RADEON_RB_NO_UPDATE;
		787	WREG32(R_000770_SCRATCH_UMSK, 0);
		788	}
		789
1117	serge	790	WREG32(RADEON_CP_RB_CNTL, tmp);
		791	udelay(10);
2997	Serge	792	ring->rptr = RREG32(RADEON_CP_RB_RPTR);
1117	serge	793	/* Set cp mode to bus mastering & enable cp*/
		794	WREG32(RADEON_CP_CSQ_MODE,
		795	REG_SET(RADEON_INDIRECT2_START, indirect2_start) \|
		796	REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1963	serge	797	WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
		798	WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1117	serge	799	WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
2997	Serge	800	radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
		801	r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1117	serge	802	if (r) {
		803	DRM_ERROR("radeon: cp isn't working (%d).\n", r);
		804	return r;
		805	}
2997	Serge	806	ring->ready = true;
		807	// radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1117	serge	808	return 0;
		809	}
		810
		811	void r100_cp_fini(struct radeon_device *rdev)
		812	{
1179	serge	813	if (r100_cp_wait_for_idle(rdev)) {
		814	DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
		815	}
1117	serge	816	/* Disable ring */
1179	serge	817	r100_cp_disable(rdev);
2997	Serge	818	radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1117	serge	819	DRM_INFO("radeon: cp finalized\n");
		820	}
		821
		822	void r100_cp_disable(struct radeon_device *rdev)
		823	{
		824	/* Disable ring */
2997	Serge	825	// radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
		826	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1117	serge	827	WREG32(RADEON_CP_CSQ_MODE, 0);
		828	WREG32(RADEON_CP_CSQ_CNTL, 0);
1963	serge	829	WREG32(R_000770_SCRATCH_UMSK, 0);
1117	serge	830	if (r100_gui_wait_for_idle(rdev)) {
		831	printk(KERN_WARNING "Failed to wait GUI idle while "
		832	"programming pipes. Bad things might happen.\n");
		833	}
		834	}
		835
2997	Serge	836	#if 0
		837	/*
		838	* CS functions
		839	*/
		840	int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
		841	struct radeon_cs_packet *pkt,
		842	unsigned idx,
		843	unsigned reg)
1179	serge	844	{
2997	Serge	845	int r;
		846	u32 tile_flags = 0;
		847	u32 tmp;
		848	struct radeon_cs_reloc *reloc;
		849	u32 value;
		850
		851	r = r100_cs_packet_next_reloc(p, &reloc);
		852	if (r) {
		853	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		854	idx, reg);
		855	r100_cs_dump_packet(p, pkt);
		856	return r;
		857	}
		858
		859	value = radeon_get_ib_value(p, idx);
		860	tmp = value & 0x003fffff;
		861	tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
		862
		863	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
		864	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		865	tile_flags \|= RADEON_DST_TILE_MACRO;
		866	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
		867	if (reg == RADEON_SRC_PITCH_OFFSET) {
		868	DRM_ERROR("Cannot src blit from microtiled surface\n");
		869	r100_cs_dump_packet(p, pkt);
		870	return -EINVAL;
		871	}
		872	tile_flags \|= RADEON_DST_TILE_MICRO;
		873	}
		874
		875	tmp \|= tile_flags;
		876	p->ib.ptr[idx] = (value & 0x3fc00000) \| tmp;
		877	} else
		878	p->ib.ptr[idx] = (value & 0xffc00000) \| tmp;
		879	return 0;
1179	serge	880	}
		881
2997	Serge	882	int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
		883	struct radeon_cs_packet *pkt,
		884	int idx)
		885	{
		886	unsigned c, i;
		887	struct radeon_cs_reloc *reloc;
		888	struct r100_cs_track *track;
		889	int r = 0;
		890	volatile uint32_t *ib;
		891	u32 idx_value;
1179	serge	892
2997	Serge	893	ib = p->ib.ptr;
		894	track = (struct r100_cs_track *)p->track;
		895	c = radeon_get_ib_value(p, idx++) & 0x1F;
		896	if (c > 16) {
		897	DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
		898	pkt->opcode);
		899	r100_cs_dump_packet(p, pkt);
		900	return -EINVAL;
		901	}
		902	track->num_arrays = c;
		903	for (i = 0; i < (c - 1); i+=2, idx+=3) {
		904	r = r100_cs_packet_next_reloc(p, &reloc);
		905	if (r) {
		906	DRM_ERROR("No reloc for packet3 %d\n",
		907	pkt->opcode);
		908	r100_cs_dump_packet(p, pkt);
		909	return r;
		910	}
		911	idx_value = radeon_get_ib_value(p, idx);
		912	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
		913
		914	track->arrays[i + 0].esize = idx_value >> 8;
		915	track->arrays[i + 0].robj = reloc->robj;
		916	track->arrays[i + 0].esize &= 0x7F;
		917	r = r100_cs_packet_next_reloc(p, &reloc);
		918	if (r) {
		919	DRM_ERROR("No reloc for packet3 %d\n",
		920	pkt->opcode);
		921	r100_cs_dump_packet(p, pkt);
		922	return r;
		923	}
		924	ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
		925	track->arrays[i + 1].robj = reloc->robj;
		926	track->arrays[i + 1].esize = idx_value >> 24;
		927	track->arrays[i + 1].esize &= 0x7F;
		928	}
		929	if (c & 1) {
		930	r = r100_cs_packet_next_reloc(p, &reloc);
		931	if (r) {
		932	DRM_ERROR("No reloc for packet3 %d\n",
		933	pkt->opcode);
		934	r100_cs_dump_packet(p, pkt);
		935	return r;
		936	}
		937	idx_value = radeon_get_ib_value(p, idx);
		938	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
		939	track->arrays[i + 0].robj = reloc->robj;
		940	track->arrays[i + 0].esize = idx_value >> 8;
		941	track->arrays[i + 0].esize &= 0x7F;
		942	}
		943	return r;
		944	}
		945
1117	serge	946	int r100_cs_parse_packet0(struct radeon_cs_parser *p,
		947	struct radeon_cs_packet *pkt,
		948	const unsigned *auth, unsigned n,
		949	radeon_packet0_check_t check)
		950	{
		951	unsigned reg;
		952	unsigned i, j, m;
		953	unsigned idx;
		954	int r;
		955
		956	idx = pkt->idx + 1;
		957	reg = pkt->reg;
		958	/* Check that register fall into register range
		959	* determined by the number of entry (n) in the
		960	* safe register bitmap.
		961	*/
		962	if (pkt->one_reg_wr) {
		963	if ((reg >> 7) > n) {
		964	return -EINVAL;
		965	}
		966	} else {
		967	if (((reg + (pkt->count << 2)) >> 7) > n) {
		968	return -EINVAL;
		969	}
		970	}
		971	for (i = 0; i <= pkt->count; i++, idx++) {
		972	j = (reg >> 7);
		973	m = 1 << ((reg >> 2) & 31);
		974	if (auth[j] & m) {
		975	r = check(p, pkt, idx, reg);
		976	if (r) {
		977	return r;
		978	}
		979	}
		980	if (pkt->one_reg_wr) {
		981	if (!(auth[j] & m)) {
		982	break;
		983	}
		984	} else {
		985	reg += 4;
		986	}
		987	}
		988	return 0;
		989	}
		990
		991	void r100_cs_dump_packet(struct radeon_cs_parser *p,
		992	struct radeon_cs_packet *pkt)
		993	{
		994	volatile uint32_t *ib;
		995	unsigned i;
		996	unsigned idx;
		997
2997	Serge	998	ib = p->ib.ptr;
1117	serge	999	idx = pkt->idx;
		1000	for (i = 0; i <= (pkt->count + 1); i++, idx++) {
		1001	DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
		1002	}
		1003	}
		1004
		1005	/**
		1006	* r100_cs_packet_parse() - parse cp packet and point ib index to next packet
		1007	* @parser: parser structure holding parsing context.
		1008	* @pkt: where to store packet informations
		1009	*
		1010	* Assume that chunk_ib_index is properly set. Will return -EINVAL
		1011	* if packet is bigger than remaining ib size. or if packets is unknown.
		1012	**/
		1013	int r100_cs_packet_parse(struct radeon_cs_parser *p,
		1014	struct radeon_cs_packet *pkt,
		1015	unsigned idx)
		1016	{
		1017	struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1179	serge	1018	uint32_t header;
1117	serge	1019
		1020	if (idx >= ib_chunk->length_dw) {
		1021	DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
		1022	idx, ib_chunk->length_dw);
		1023	return -EINVAL;
		1024	}
1221	serge	1025	header = radeon_get_ib_value(p, idx);
1117	serge	1026	pkt->idx = idx;
		1027	pkt->type = CP_PACKET_GET_TYPE(header);
		1028	pkt->count = CP_PACKET_GET_COUNT(header);
		1029	switch (pkt->type) {
		1030	case PACKET_TYPE0:
		1031	pkt->reg = CP_PACKET0_GET_REG(header);
		1032	pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
		1033	break;
		1034	case PACKET_TYPE3:
		1035	pkt->opcode = CP_PACKET3_GET_OPCODE(header);
		1036	break;
		1037	case PACKET_TYPE2:
		1038	pkt->count = -1;
		1039	break;
		1040	default:
		1041	DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
		1042	return -EINVAL;
		1043	}
		1044	if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
		1045	DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
		1046	pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
		1047	return -EINVAL;
		1048	}
		1049	return 0;
		1050	}
		1051
		1052	/**
1179	serge	1053	* r100_cs_packet_next_vline() - parse userspace VLINE packet
		1054	* @parser: parser structure holding parsing context.
		1055	*
		1056	* Userspace sends a special sequence for VLINE waits.
		1057	* PACKET0 - VLINE_START_END + value
		1058	* PACKET0 - WAIT_UNTIL +_value
		1059	* RELOC (P3) - crtc_id in reloc.
		1060	*
		1061	* This function parses this and relocates the VLINE START END
		1062	* and WAIT UNTIL packets to the correct crtc.
		1063	* It also detects a switched off crtc and nulls out the
		1064	* wait in that case.
		1065	*/
		1066	int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
		1067	{
		1068	struct drm_mode_object *obj;
		1069	struct drm_crtc *crtc;
		1070	struct radeon_crtc *radeon_crtc;
		1071	struct radeon_cs_packet p3reloc, waitreloc;
		1072	int crtc_id;
		1073	int r;
		1074	uint32_t header, h_idx, reg;
1221	serge	1075	volatile uint32_t *ib;
1179	serge	1076
2997	Serge	1077	ib = p->ib.ptr;
1179	serge	1078
		1079	/* parse the wait until */
		1080	r = r100_cs_packet_parse(p, &waitreloc, p->idx);
		1081	if (r)
		1082	return r;
		1083
		1084	/* check its a wait until and only 1 count */
		1085	if (waitreloc.reg != RADEON_WAIT_UNTIL \|\|
		1086	waitreloc.count != 0) {
		1087	DRM_ERROR("vline wait had illegal wait until segment\n");
1963	serge	1088	return -EINVAL;
1179	serge	1089	}
		1090
1221	serge	1091	if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1179	serge	1092	DRM_ERROR("vline wait had illegal wait until\n");
1963	serge	1093	return -EINVAL;
1179	serge	1094	}
		1095
		1096	/* jump over the NOP */
1221	serge	1097	r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1179	serge	1098	if (r)
		1099	return r;
		1100
		1101	h_idx = p->idx - 2;
1221	serge	1102	p->idx += waitreloc.count + 2;
		1103	p->idx += p3reloc.count + 2;
1179	serge	1104
1221	serge	1105	header = radeon_get_ib_value(p, h_idx);
		1106	crtc_id = radeon_get_ib_value(p, h_idx + 5);
		1107	reg = CP_PACKET0_GET_REG(header);
1179	serge	1108	obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
		1109	if (!obj) {
		1110	DRM_ERROR("cannot find crtc %d\n", crtc_id);
1963	serge	1111	return -EINVAL;
1179	serge	1112	}
		1113	crtc = obj_to_crtc(obj);
		1114	radeon_crtc = to_radeon_crtc(crtc);
		1115	crtc_id = radeon_crtc->crtc_id;
		1116
		1117	if (!crtc->enabled) {
		1118	/* if the CRTC isn't enabled - we need to nop out the wait until */
1221	serge	1119	ib[h_idx + 2] = PACKET2(0);
		1120	ib[h_idx + 3] = PACKET2(0);
1179	serge	1121	} else if (crtc_id == 1) {
		1122	switch (reg) {
		1123	case AVIVO_D1MODE_VLINE_START_END:
1221	serge	1124	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	1125	header \|= AVIVO_D2MODE_VLINE_START_END >> 2;
		1126	break;
		1127	case RADEON_CRTC_GUI_TRIG_VLINE:
1221	serge	1128	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	1129	header \|= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
		1130	break;
		1131	default:
		1132	DRM_ERROR("unknown crtc reloc\n");
1963	serge	1133	return -EINVAL;
1179	serge	1134	}
1221	serge	1135	ib[h_idx] = header;
		1136	ib[h_idx + 3] \|= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1179	serge	1137	}
1963	serge	1138
		1139	return 0;
1179	serge	1140	}
		1141
		1142	/**
1117	serge	1143	* r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
		1144	* @parser: parser structure holding parsing context.
		1145	* @data: pointer to relocation data
		1146	* @offset_start: starting offset
		1147	* @offset_mask: offset mask (to align start offset on)
		1148	* @reloc: reloc informations
		1149	*
		1150	* Check next packet is relocation packet3, do bo validation and compute
		1151	* GPU offset using the provided start.
		1152	**/
		1153	int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
		1154	struct radeon_cs_reloc **cs_reloc)
		1155	{
		1156	struct radeon_cs_chunk *relocs_chunk;
		1157	struct radeon_cs_packet p3reloc;
		1158	unsigned idx;
		1159	int r;
		1160
		1161	if (p->chunk_relocs_idx == -1) {
		1162	DRM_ERROR("No relocation chunk !\n");
		1163	return -EINVAL;
		1164	}
		1165	*cs_reloc = NULL;
		1166	relocs_chunk = &p->chunks[p->chunk_relocs_idx];
		1167	r = r100_cs_packet_parse(p, &p3reloc, p->idx);
		1168	if (r) {
		1169	return r;
		1170	}
		1171	p->idx += p3reloc.count + 2;
		1172	if (p3reloc.type != PACKET_TYPE3 \|\| p3reloc.opcode != PACKET3_NOP) {
		1173	DRM_ERROR("No packet3 for relocation for packet at %d.\n",
		1174	p3reloc.idx);
		1175	r100_cs_dump_packet(p, &p3reloc);
		1176	return -EINVAL;
		1177	}
1221	serge	1178	idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1117	serge	1179	if (idx >= relocs_chunk->length_dw) {
		1180	DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
		1181	idx, relocs_chunk->length_dw);
		1182	r100_cs_dump_packet(p, &p3reloc);
		1183	return -EINVAL;
		1184	}
		1185	/* FIXME: we assume reloc size is 4 dwords */
		1186	*cs_reloc = p->relocs_ptr[(idx / 4)];
		1187	return 0;
		1188	}
		1189
1179	serge	1190	static int r100_get_vtx_size(uint32_t vtx_fmt)
		1191	{
		1192	int vtx_size;
		1193	vtx_size = 2;
		1194	/* ordered according to bits in spec */
		1195	if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
		1196	vtx_size++;
		1197	if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
		1198	vtx_size += 3;
		1199	if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
		1200	vtx_size++;
		1201	if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
		1202	vtx_size++;
		1203	if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
		1204	vtx_size += 3;
		1205	if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
		1206	vtx_size++;
		1207	if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
		1208	vtx_size++;
		1209	if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
		1210	vtx_size += 2;
		1211	if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
		1212	vtx_size += 2;
		1213	if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
		1214	vtx_size++;
		1215	if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
		1216	vtx_size += 2;
		1217	if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
		1218	vtx_size++;
		1219	if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
		1220	vtx_size += 2;
		1221	if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
		1222	vtx_size++;
		1223	if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
		1224	vtx_size++;
		1225	/* blend weight */
		1226	if (vtx_fmt & (0x7 << 15))
		1227	vtx_size += (vtx_fmt >> 15) & 0x7;
		1228	if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
		1229	vtx_size += 3;
		1230	if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
		1231	vtx_size += 2;
		1232	if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
		1233	vtx_size++;
		1234	if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
		1235	vtx_size++;
		1236	if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
		1237	vtx_size++;
		1238	if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
		1239	vtx_size++;
		1240	return vtx_size;
		1241	}
		1242
1117	serge	1243	static int r100_packet0_check(struct radeon_cs_parser *p,
1179	serge	1244	struct radeon_cs_packet *pkt,
		1245	unsigned idx, unsigned reg)
1117	serge	1246	{
		1247	struct radeon_cs_reloc *reloc;
1179	serge	1248	struct r100_cs_track *track;
1117	serge	1249	volatile uint32_t *ib;
		1250	uint32_t tmp;
		1251	int r;
1179	serge	1252	int i, face;
		1253	u32 tile_flags = 0;
1221	serge	1254	u32 idx_value;
1117	serge	1255
2997	Serge	1256	ib = p->ib.ptr;
1179	serge	1257	track = (struct r100_cs_track *)p->track;
		1258
1221	serge	1259	idx_value = radeon_get_ib_value(p, idx);
		1260
1117	serge	1261	switch (reg) {
1179	serge	1262	case RADEON_CRTC_GUI_TRIG_VLINE:
		1263	r = r100_cs_packet_parse_vline(p);
		1264	if (r) {
		1265	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1266	idx, reg);
		1267	r100_cs_dump_packet(p, pkt);
		1268	return r;
		1269	}
		1270	break;
1117	serge	1271	/* FIXME: only allow PACKET3 blit? easier to check for out of
		1272	* range access */
		1273	case RADEON_DST_PITCH_OFFSET:
		1274	case RADEON_SRC_PITCH_OFFSET:
1179	serge	1275	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		1276	if (r)
		1277	return r;
		1278	break;
		1279	case RADEON_RB3D_DEPTHOFFSET:
1117	serge	1280	r = r100_cs_packet_next_reloc(p, &reloc);
		1281	if (r) {
		1282	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1283	idx, reg);
		1284	r100_cs_dump_packet(p, pkt);
		1285	return r;
		1286	}
1179	serge	1287	track->zb.robj = reloc->robj;
1221	serge	1288	track->zb.offset = idx_value;
1963	serge	1289	track->zb_dirty = true;
1221	serge	1290	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1117	serge	1291	break;
		1292	case RADEON_RB3D_COLOROFFSET:
1179	serge	1293	r = r100_cs_packet_next_reloc(p, &reloc);
		1294	if (r) {
		1295	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1296	idx, reg);
		1297	r100_cs_dump_packet(p, pkt);
		1298	return r;
		1299	}
		1300	track->cb[0].robj = reloc->robj;
1221	serge	1301	track->cb[0].offset = idx_value;
1963	serge	1302	track->cb_dirty = true;
1221	serge	1303	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1304	break;
1117	serge	1305	case RADEON_PP_TXOFFSET_0:
		1306	case RADEON_PP_TXOFFSET_1:
		1307	case RADEON_PP_TXOFFSET_2:
1179	serge	1308	i = (reg - RADEON_PP_TXOFFSET_0) / 24;
		1309	r = r100_cs_packet_next_reloc(p, &reloc);
		1310	if (r) {
		1311	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1312	idx, reg);
		1313	r100_cs_dump_packet(p, pkt);
		1314	return r;
		1315	}
2997	Serge	1316	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
		1317	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		1318	tile_flags \|= RADEON_TXO_MACRO_TILE;
		1319	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		1320	tile_flags \|= RADEON_TXO_MICRO_TILE_X2;
		1321
		1322	tmp = idx_value & ~(0x7 << 2);
		1323	tmp \|= tile_flags;
		1324	ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
		1325	} else
1221	serge	1326	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1327	track->textures[i].robj = reloc->robj;
1963	serge	1328	track->tex_dirty = true;
1179	serge	1329	break;
		1330	case RADEON_PP_CUBIC_OFFSET_T0_0:
		1331	case RADEON_PP_CUBIC_OFFSET_T0_1:
		1332	case RADEON_PP_CUBIC_OFFSET_T0_2:
		1333	case RADEON_PP_CUBIC_OFFSET_T0_3:
		1334	case RADEON_PP_CUBIC_OFFSET_T0_4:
		1335	i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
		1336	r = r100_cs_packet_next_reloc(p, &reloc);
		1337	if (r) {
		1338	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1339	idx, reg);
		1340	r100_cs_dump_packet(p, pkt);
		1341	return r;
		1342	}
1221	serge	1343	track->textures[0].cube_info[i].offset = idx_value;
		1344	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1345	track->textures[0].cube_info[i].robj = reloc->robj;
1963	serge	1346	track->tex_dirty = true;
1179	serge	1347	break;
		1348	case RADEON_PP_CUBIC_OFFSET_T1_0:
		1349	case RADEON_PP_CUBIC_OFFSET_T1_1:
		1350	case RADEON_PP_CUBIC_OFFSET_T1_2:
		1351	case RADEON_PP_CUBIC_OFFSET_T1_3:
		1352	case RADEON_PP_CUBIC_OFFSET_T1_4:
		1353	i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
		1354	r = r100_cs_packet_next_reloc(p, &reloc);
		1355	if (r) {
		1356	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1357	idx, reg);
		1358	r100_cs_dump_packet(p, pkt);
		1359	return r;
		1360	}
1221	serge	1361	track->textures[1].cube_info[i].offset = idx_value;
		1362	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1363	track->textures[1].cube_info[i].robj = reloc->robj;
1963	serge	1364	track->tex_dirty = true;
1179	serge	1365	break;
		1366	case RADEON_PP_CUBIC_OFFSET_T2_0:
		1367	case RADEON_PP_CUBIC_OFFSET_T2_1:
		1368	case RADEON_PP_CUBIC_OFFSET_T2_2:
		1369	case RADEON_PP_CUBIC_OFFSET_T2_3:
		1370	case RADEON_PP_CUBIC_OFFSET_T2_4:
		1371	i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1117	serge	1372	r = r100_cs_packet_next_reloc(p, &reloc);
		1373	if (r) {
		1374	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1375	idx, reg);
		1376	r100_cs_dump_packet(p, pkt);
		1377	return r;
		1378	}
1221	serge	1379	track->textures[2].cube_info[i].offset = idx_value;
		1380	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1381	track->textures[2].cube_info[i].robj = reloc->robj;
1963	serge	1382	track->tex_dirty = true;
1179	serge	1383	break;
		1384	case RADEON_RE_WIDTH_HEIGHT:
1221	serge	1385	track->maxy = ((idx_value >> 16) & 0x7FF);
1963	serge	1386	track->cb_dirty = true;
		1387	track->zb_dirty = true;
1117	serge	1388	break;
1179	serge	1389	case RADEON_RB3D_COLORPITCH:
		1390	r = r100_cs_packet_next_reloc(p, &reloc);
		1391	if (r) {
		1392	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1393	idx, reg);
		1394	r100_cs_dump_packet(p, pkt);
		1395	return r;
		1396	}
2997	Serge	1397	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1179	serge	1398	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		1399	tile_flags \|= RADEON_COLOR_TILE_ENABLE;
		1400	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		1401	tile_flags \|= RADEON_COLOR_MICROTILE_ENABLE;
		1402
1221	serge	1403	tmp = idx_value & ~(0x7 << 16);
1179	serge	1404	tmp \|= tile_flags;
		1405	ib[idx] = tmp;
2997	Serge	1406	} else
		1407	ib[idx] = idx_value;
1179	serge	1408
1221	serge	1409	track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1963	serge	1410	track->cb_dirty = true;
1179	serge	1411	break;
		1412	case RADEON_RB3D_DEPTHPITCH:
1221	serge	1413	track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1963	serge	1414	track->zb_dirty = true;
1179	serge	1415	break;
		1416	case RADEON_RB3D_CNTL:
1221	serge	1417	switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1179	serge	1418	case 7:
		1419	case 8:
		1420	case 9:
		1421	case 11:
		1422	case 12:
		1423	track->cb[0].cpp = 1;
		1424	break;
		1425	case 3:
		1426	case 4:
		1427	case 15:
		1428	track->cb[0].cpp = 2;
		1429	break;
		1430	case 6:
		1431	track->cb[0].cpp = 4;
		1432	break;
1117	serge	1433	default:
1179	serge	1434	DRM_ERROR("Invalid color buffer format (%d) !\n",
1221	serge	1435	((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1179	serge	1436	return -EINVAL;
		1437	}
1221	serge	1438	track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1963	serge	1439	track->cb_dirty = true;
		1440	track->zb_dirty = true;
1179	serge	1441	break;
		1442	case RADEON_RB3D_ZSTENCILCNTL:
1221	serge	1443	switch (idx_value & 0xf) {
1179	serge	1444	case 0:
		1445	track->zb.cpp = 2;
1117	serge	1446	break;
1179	serge	1447	case 2:
		1448	case 3:
		1449	case 4:
		1450	case 5:
		1451	case 9:
		1452	case 11:
		1453	track->zb.cpp = 4;
		1454	break;
		1455	default:
		1456	break;
1117	serge	1457	}
1963	serge	1458	track->zb_dirty = true;
1117	serge	1459	break;
1179	serge	1460	case RADEON_RB3D_ZPASS_ADDR:
		1461	r = r100_cs_packet_next_reloc(p, &reloc);
		1462	if (r) {
		1463	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1464	idx, reg);
		1465	r100_cs_dump_packet(p, pkt);
		1466	return r;
		1467	}
1221	serge	1468	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1469	break;
		1470	case RADEON_PP_CNTL:
		1471	{
1221	serge	1472	uint32_t temp = idx_value >> 4;
1179	serge	1473	for (i = 0; i < track->num_texture; i++)
		1474	track->textures[i].enabled = !!(temp & (1 << i));
1963	serge	1475	track->tex_dirty = true;
1117	serge	1476	}
1179	serge	1477	break;
		1478	case RADEON_SE_VF_CNTL:
1221	serge	1479	track->vap_vf_cntl = idx_value;
1179	serge	1480	break;
		1481	case RADEON_SE_VTX_FMT:
1221	serge	1482	track->vtx_size = r100_get_vtx_size(idx_value);
1179	serge	1483	break;
		1484	case RADEON_PP_TEX_SIZE_0:
		1485	case RADEON_PP_TEX_SIZE_1:
		1486	case RADEON_PP_TEX_SIZE_2:
		1487	i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1221	serge	1488	track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
		1489	track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1963	serge	1490	track->tex_dirty = true;
1179	serge	1491	break;
		1492	case RADEON_PP_TEX_PITCH_0:
		1493	case RADEON_PP_TEX_PITCH_1:
		1494	case RADEON_PP_TEX_PITCH_2:
		1495	i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1221	serge	1496	track->textures[i].pitch = idx_value + 32;
1963	serge	1497	track->tex_dirty = true;
1179	serge	1498	break;
		1499	case RADEON_PP_TXFILTER_0:
		1500	case RADEON_PP_TXFILTER_1:
		1501	case RADEON_PP_TXFILTER_2:
		1502	i = (reg - RADEON_PP_TXFILTER_0) / 24;
1221	serge	1503	track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1179	serge	1504	>> RADEON_MAX_MIP_LEVEL_SHIFT);
1221	serge	1505	tmp = (idx_value >> 23) & 0x7;
1179	serge	1506	if (tmp == 2 \|\| tmp == 6)
		1507	track->textures[i].roundup_w = false;
1221	serge	1508	tmp = (idx_value >> 27) & 0x7;
1179	serge	1509	if (tmp == 2 \|\| tmp == 6)
		1510	track->textures[i].roundup_h = false;
1963	serge	1511	track->tex_dirty = true;
1179	serge	1512	break;
		1513	case RADEON_PP_TXFORMAT_0:
		1514	case RADEON_PP_TXFORMAT_1:
		1515	case RADEON_PP_TXFORMAT_2:
		1516	i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1221	serge	1517	if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1179	serge	1518	track->textures[i].use_pitch = 1;
		1519	} else {
		1520	track->textures[i].use_pitch = 0;
1221	serge	1521	track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
		1522	track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1179	serge	1523	}
1221	serge	1524	if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1179	serge	1525	track->textures[i].tex_coord_type = 2;
1221	serge	1526	switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1179	serge	1527	case RADEON_TXFORMAT_I8:
		1528	case RADEON_TXFORMAT_RGB332:
		1529	case RADEON_TXFORMAT_Y8:
		1530	track->textures[i].cpp = 1;
1963	serge	1531	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1532	break;
		1533	case RADEON_TXFORMAT_AI88:
		1534	case RADEON_TXFORMAT_ARGB1555:
		1535	case RADEON_TXFORMAT_RGB565:
		1536	case RADEON_TXFORMAT_ARGB4444:
		1537	case RADEON_TXFORMAT_VYUY422:
		1538	case RADEON_TXFORMAT_YVYU422:
		1539	case RADEON_TXFORMAT_SHADOW16:
		1540	case RADEON_TXFORMAT_LDUDV655:
		1541	case RADEON_TXFORMAT_DUDV88:
		1542	track->textures[i].cpp = 2;
1963	serge	1543	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1544	break;
		1545	case RADEON_TXFORMAT_ARGB8888:
		1546	case RADEON_TXFORMAT_RGBA8888:
		1547	case RADEON_TXFORMAT_SHADOW32:
		1548	case RADEON_TXFORMAT_LDUDUV8888:
		1549	track->textures[i].cpp = 4;
1963	serge	1550	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1551	break;
1403	serge	1552	case RADEON_TXFORMAT_DXT1:
		1553	track->textures[i].cpp = 1;
		1554	track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
		1555	break;
		1556	case RADEON_TXFORMAT_DXT23:
		1557	case RADEON_TXFORMAT_DXT45:
		1558	track->textures[i].cpp = 1;
		1559	track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
		1560	break;
1179	serge	1561	}
1221	serge	1562	track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
		1563	track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1963	serge	1564	track->tex_dirty = true;
1179	serge	1565	break;
		1566	case RADEON_PP_CUBIC_FACES_0:
		1567	case RADEON_PP_CUBIC_FACES_1:
		1568	case RADEON_PP_CUBIC_FACES_2:
1221	serge	1569	tmp = idx_value;
1179	serge	1570	i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
		1571	for (face = 0; face < 4; face++) {
		1572	track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
		1573	track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
		1574	}
1963	serge	1575	track->tex_dirty = true;
1179	serge	1576	break;
		1577	default:
		1578	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
		1579	reg, idx);
		1580	return -EINVAL;
1117	serge	1581	}
		1582	return 0;
		1583	}
		1584
		1585	int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
		1586	struct radeon_cs_packet *pkt,
1321	serge	1587	struct radeon_bo *robj)
1117	serge	1588	{
		1589	unsigned idx;
1221	serge	1590	u32 value;
1117	serge	1591	idx = pkt->idx + 1;
1221	serge	1592	value = radeon_get_ib_value(p, idx + 2);
1321	serge	1593	if ((value + 1) > radeon_bo_size(robj)) {
1117	serge	1594	DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
		1595	"(need %u have %lu) !\n",
1221	serge	1596	value + 1,
1321	serge	1597	radeon_bo_size(robj));
1117	serge	1598	return -EINVAL;
		1599	}
		1600	return 0;
		1601	}
		1602
		1603	static int r100_packet3_check(struct radeon_cs_parser *p,
		1604	struct radeon_cs_packet *pkt)
		1605	{
		1606	struct radeon_cs_reloc *reloc;
1179	serge	1607	struct r100_cs_track *track;
1117	serge	1608	unsigned idx;
		1609	volatile uint32_t *ib;
		1610	int r;
		1611
2997	Serge	1612	ib = p->ib.ptr;
1117	serge	1613	idx = pkt->idx + 1;
1179	serge	1614	track = (struct r100_cs_track *)p->track;
1117	serge	1615	switch (pkt->opcode) {
		1616	case PACKET3_3D_LOAD_VBPNTR:
1221	serge	1617	r = r100_packet3_load_vbpntr(p, pkt, idx);
		1618	if (r)
1117	serge	1619	return r;
		1620	break;
		1621	case PACKET3_INDX_BUFFER:
		1622	r = r100_cs_packet_next_reloc(p, &reloc);
		1623	if (r) {
		1624	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1625	r100_cs_dump_packet(p, pkt);
		1626	return r;
		1627	}
1221	serge	1628	ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1117	serge	1629	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		1630	if (r) {
		1631	return r;
		1632	}
		1633	break;
		1634	case 0x23:
		1635	/* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
		1636	r = r100_cs_packet_next_reloc(p, &reloc);
		1637	if (r) {
		1638	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1639	r100_cs_dump_packet(p, pkt);
		1640	return r;
		1641	}
1221	serge	1642	ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1179	serge	1643	track->num_arrays = 1;
1221	serge	1644	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1179	serge	1645
		1646	track->arrays[0].robj = reloc->robj;
		1647	track->arrays[0].esize = track->vtx_size;
		1648
1221	serge	1649	track->max_indx = radeon_get_ib_value(p, idx+1);
1179	serge	1650
1221	serge	1651	track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1179	serge	1652	track->immd_dwords = pkt->count - 1;
		1653	r = r100_cs_track_check(p->rdev, track);
		1654	if (r)
		1655	return r;
1117	serge	1656	break;
		1657	case PACKET3_3D_DRAW_IMMD:
1221	serge	1658	if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1179	serge	1659	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1660	return -EINVAL;
		1661	}
1403	serge	1662	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1221	serge	1663	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1664	track->immd_dwords = pkt->count - 1;
		1665	r = r100_cs_track_check(p->rdev, track);
		1666	if (r)
		1667	return r;
		1668	break;
1117	serge	1669	/* triggers drawing using in-packet vertex data */
		1670	case PACKET3_3D_DRAW_IMMD_2:
1221	serge	1671	if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1179	serge	1672	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1673	return -EINVAL;
		1674	}
1221	serge	1675	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1676	track->immd_dwords = pkt->count;
		1677	r = r100_cs_track_check(p->rdev, track);
		1678	if (r)
		1679	return r;
		1680	break;
1117	serge	1681	/* triggers drawing using in-packet vertex data */
		1682	case PACKET3_3D_DRAW_VBUF_2:
1221	serge	1683	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1684	r = r100_cs_track_check(p->rdev, track);
		1685	if (r)
		1686	return r;
		1687	break;
1117	serge	1688	/* triggers drawing of vertex buffers setup elsewhere */
		1689	case PACKET3_3D_DRAW_INDX_2:
1221	serge	1690	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1691	r = r100_cs_track_check(p->rdev, track);
		1692	if (r)
		1693	return r;
		1694	break;
1117	serge	1695	/* triggers drawing using indices to vertex buffer */
		1696	case PACKET3_3D_DRAW_VBUF:
1221	serge	1697	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1698	r = r100_cs_track_check(p->rdev, track);
		1699	if (r)
		1700	return r;
		1701	break;
1117	serge	1702	/* triggers drawing of vertex buffers setup elsewhere */
		1703	case PACKET3_3D_DRAW_INDX:
1221	serge	1704	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1705	r = r100_cs_track_check(p->rdev, track);
		1706	if (r)
		1707	return r;
		1708	break;
1117	serge	1709	/* triggers drawing using indices to vertex buffer */
1963	serge	1710	case PACKET3_3D_CLEAR_HIZ:
		1711	case PACKET3_3D_CLEAR_ZMASK:
		1712	if (p->rdev->hyperz_filp != p->filp)
		1713	return -EINVAL;
		1714	break;
1117	serge	1715	case PACKET3_NOP:
		1716	break;
		1717	default:
		1718	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		1719	return -EINVAL;
		1720	}
		1721	return 0;
		1722	}
		1723
		1724	int r100_cs_parse(struct radeon_cs_parser *p)
		1725	{
		1726	struct radeon_cs_packet pkt;
1179	serge	1727	struct r100_cs_track *track;
1117	serge	1728	int r;
		1729
1179	serge	1730	track = kzalloc(sizeof(*track), GFP_KERNEL);
2997	Serge	1731	if (!track)
		1732	return -ENOMEM;
1179	serge	1733	r100_cs_track_clear(p->rdev, track);
		1734	p->track = track;
1117	serge	1735	do {
		1736	r = r100_cs_packet_parse(p, &pkt, p->idx);
		1737	if (r) {
		1738	return r;
		1739	}
		1740	p->idx += pkt.count + 2;
		1741	switch (pkt.type) {
		1742	case PACKET_TYPE0:
1179	serge	1743	if (p->rdev->family >= CHIP_R200)
		1744	r = r100_cs_parse_packet0(p, &pkt,
		1745	p->rdev->config.r100.reg_safe_bm,
		1746	p->rdev->config.r100.reg_safe_bm_size,
		1747	&r200_packet0_check);
		1748	else
		1749	r = r100_cs_parse_packet0(p, &pkt,
		1750	p->rdev->config.r100.reg_safe_bm,
		1751	p->rdev->config.r100.reg_safe_bm_size,
		1752	&r100_packet0_check);
1117	serge	1753	break;
		1754	case PACKET_TYPE2:
		1755	break;
		1756	case PACKET_TYPE3:
		1757	r = r100_packet3_check(p, &pkt);
		1758	break;
		1759	default:
		1760	DRM_ERROR("Unknown packet type %d !\n",
		1761	pkt.type);
		1762	return -EINVAL;
		1763	}
		1764	if (r) {
		1765	return r;
		1766	}
		1767	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
		1768	return 0;
		1769	}
		1770
2997	Serge	1771	static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
		1772	{
		1773	DRM_ERROR("pitch %d\n", t->pitch);
		1774	DRM_ERROR("use_pitch %d\n", t->use_pitch);
		1775	DRM_ERROR("width %d\n", t->width);
		1776	DRM_ERROR("width_11 %d\n", t->width_11);
		1777	DRM_ERROR("height %d\n", t->height);
		1778	DRM_ERROR("height_11 %d\n", t->height_11);
		1779	DRM_ERROR("num levels %d\n", t->num_levels);
		1780	DRM_ERROR("depth %d\n", t->txdepth);
		1781	DRM_ERROR("bpp %d\n", t->cpp);
		1782	DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
		1783	DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
		1784	DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
		1785	DRM_ERROR("compress format %d\n", t->compress_format);
		1786	}
1117	serge	1787
2997	Serge	1788	static int r100_track_compress_size(int compress_format, int w, int h)
1117	serge	1789	{
2997	Serge	1790	int block_width, block_height, block_bytes;
		1791	int wblocks, hblocks;
		1792	int min_wblocks;
		1793	int sz;
1117	serge	1794
2997	Serge	1795	block_width = 4;
		1796	block_height = 4;
		1797
		1798	switch (compress_format) {
		1799	case R100_TRACK_COMP_DXT1:
		1800	block_bytes = 8;
		1801	min_wblocks = 4;
		1802	break;
		1803	default:
		1804	case R100_TRACK_COMP_DXT35:
		1805	block_bytes = 16;
		1806	min_wblocks = 2;
		1807	break;
1117	serge	1808	}
		1809
2997	Serge	1810	hblocks = (h + block_height - 1) / block_height;
		1811	wblocks = (w + block_width - 1) / block_width;
		1812	if (wblocks < min_wblocks)
		1813	wblocks = min_wblocks;
		1814	sz = wblocks * hblocks * block_bytes;
		1815	return sz;
		1816	}
		1817
		1818	static int r100_cs_track_cube(struct radeon_device *rdev,
		1819	struct r100_cs_track *track, unsigned idx)
		1820	{
		1821	unsigned face, w, h;
		1822	struct radeon_bo *cube_robj;
		1823	unsigned long size;
		1824	unsigned compress_format = track->textures[idx].compress_format;
		1825
		1826	for (face = 0; face < 5; face++) {
		1827	cube_robj = track->textures[idx].cube_info[face].robj;
		1828	w = track->textures[idx].cube_info[face].width;
		1829	h = track->textures[idx].cube_info[face].height;
		1830
		1831	if (compress_format) {
		1832	size = r100_track_compress_size(compress_format, w, h);
		1833	} else
		1834	size = w * h;
		1835	size *= track->textures[idx].cpp;
		1836
		1837	size += track->textures[idx].cube_info[face].offset;
		1838
		1839	if (size > radeon_bo_size(cube_robj)) {
		1840	DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
		1841	size, radeon_bo_size(cube_robj));
		1842	r100_cs_track_texture_print(&track->textures[idx]);
		1843	return -1;
		1844	}
1117	serge	1845	}
2997	Serge	1846	return 0;
1117	serge	1847	}
		1848
2997	Serge	1849	static int r100_cs_track_texture_check(struct radeon_device *rdev,
		1850	struct r100_cs_track *track)
1117	serge	1851	{
2997	Serge	1852	struct radeon_bo *robj;
		1853	unsigned long size;
		1854	unsigned u, i, w, h, d;
		1855	int ret;
1117	serge	1856
2997	Serge	1857	for (u = 0; u < track->num_texture; u++) {
		1858	if (!track->textures[u].enabled)
		1859	continue;
		1860	if (track->textures[u].lookup_disable)
		1861	continue;
		1862	robj = track->textures[u].robj;
		1863	if (robj == NULL) {
		1864	DRM_ERROR("No texture bound to unit %u\n", u);
		1865	return -EINVAL;
		1866	}
		1867	size = 0;
		1868	for (i = 0; i <= track->textures[u].num_levels; i++) {
		1869	if (track->textures[u].use_pitch) {
		1870	if (rdev->family < CHIP_R300)
		1871	w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
		1872	else
		1873	w = track->textures[u].pitch / (1 << i);
		1874	} else {
		1875	w = track->textures[u].width;
		1876	if (rdev->family >= CHIP_RV515)
		1877	w \|= track->textures[u].width_11;
		1878	w = w / (1 << i);
		1879	if (track->textures[u].roundup_w)
		1880	w = roundup_pow_of_two(w);
		1881	}
		1882	h = track->textures[u].height;
		1883	if (rdev->family >= CHIP_RV515)
		1884	h \|= track->textures[u].height_11;
		1885	h = h / (1 << i);
		1886	if (track->textures[u].roundup_h)
		1887	h = roundup_pow_of_two(h);
		1888	if (track->textures[u].tex_coord_type == 1) {
		1889	d = (1 << track->textures[u].txdepth) / (1 << i);
		1890	if (!d)
		1891	d = 1;
		1892	} else {
		1893	d = 1;
		1894	}
		1895	if (track->textures[u].compress_format) {
		1896
		1897	size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
		1898	/* compressed textures are block based */
		1899	} else
		1900	size += w * h * d;
		1901	}
		1902	size *= track->textures[u].cpp;
		1903
		1904	switch (track->textures[u].tex_coord_type) {
		1905	case 0:
		1906	case 1:
		1907	break;
		1908	case 2:
		1909	if (track->separate_cube) {
		1910	ret = r100_cs_track_cube(rdev, track, u);
		1911	if (ret)
		1912	return ret;
		1913	} else
		1914	size *= 6;
		1915	break;
		1916	default:
		1917	DRM_ERROR("Invalid texture coordinate type %u for unit "
		1918	"%u\n", track->textures[u].tex_coord_type, u);
		1919	return -EINVAL;
		1920	}
		1921	if (size > radeon_bo_size(robj)) {
		1922	DRM_ERROR("Texture of unit %u needs %lu bytes but is "
		1923	"%lu\n", u, size, radeon_bo_size(robj));
		1924	r100_cs_track_texture_print(&track->textures[u]);
		1925	return -EINVAL;
		1926	}
1117	serge	1927	}
2997	Serge	1928	return 0;
		1929	}
		1930
		1931	int r100_cs_track_check(struct radeon_device rdev, struct r100_cs_track track)
		1932	{
		1933	unsigned i;
		1934	unsigned long size;
		1935	unsigned prim_walk;
		1936	unsigned nverts;
		1937	unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
		1938
		1939	if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
		1940	!track->blend_read_enable)
		1941	num_cb = 0;
		1942
		1943	for (i = 0; i < num_cb; i++) {
		1944	if (track->cb[i].robj == NULL) {
		1945	DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
		1946	return -EINVAL;
1117	serge	1947	}
2997	Serge	1948	size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
		1949	size += track->cb[i].offset;
		1950	if (size > radeon_bo_size(track->cb[i].robj)) {
		1951	DRM_ERROR("[drm] Buffer too small for color buffer %d "
		1952	"(need %lu have %lu) !\n", i, size,
		1953	radeon_bo_size(track->cb[i].robj));
		1954	DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
		1955	i, track->cb[i].pitch, track->cb[i].cpp,
		1956	track->cb[i].offset, track->maxy);
		1957	return -EINVAL;
		1958	}
1117	serge	1959	}
2997	Serge	1960	track->cb_dirty = false;
		1961
		1962	if (track->zb_dirty && track->z_enabled) {
		1963	if (track->zb.robj == NULL) {
		1964	DRM_ERROR("[drm] No buffer for z buffer !\n");
		1965	return -EINVAL;
		1966	}
		1967	size = track->zb.pitch * track->zb.cpp * track->maxy;
		1968	size += track->zb.offset;
		1969	if (size > radeon_bo_size(track->zb.robj)) {
		1970	DRM_ERROR("[drm] Buffer too small for z buffer "
		1971	"(need %lu have %lu) !\n", size,
		1972	radeon_bo_size(track->zb.robj));
		1973	DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
		1974	track->zb.pitch, track->zb.cpp,
		1975	track->zb.offset, track->maxy);
		1976	return -EINVAL;
		1977	}
		1978	}
		1979	track->zb_dirty = false;
		1980
		1981	if (track->aa_dirty && track->aaresolve) {
		1982	if (track->aa.robj == NULL) {
		1983	DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
		1984	return -EINVAL;
		1985	}
		1986	/* I believe the format comes from colorbuffer0. */
		1987	size = track->aa.pitch * track->cb[0].cpp * track->maxy;
		1988	size += track->aa.offset;
		1989	if (size > radeon_bo_size(track->aa.robj)) {
		1990	DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
		1991	"(need %lu have %lu) !\n", i, size,
		1992	radeon_bo_size(track->aa.robj));
		1993	DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
		1994	i, track->aa.pitch, track->cb[0].cpp,
		1995	track->aa.offset, track->maxy);
		1996	return -EINVAL;
		1997	}
		1998	}
		1999	track->aa_dirty = false;
		2000
		2001	prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
		2002	if (track->vap_vf_cntl & (1 << 14)) {
		2003	nverts = track->vap_alt_nverts;
		2004	} else {
		2005	nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
		2006	}
		2007	switch (prim_walk) {
		2008	case 1:
		2009	for (i = 0; i < track->num_arrays; i++) {
		2010	size = track->arrays[i].esize * track->max_indx * 4;
		2011	if (track->arrays[i].robj == NULL) {
		2012	DRM_ERROR("(PW %u) Vertex array %u no buffer "
		2013	"bound\n", prim_walk, i);
		2014	return -EINVAL;
		2015	}
		2016	if (size > radeon_bo_size(track->arrays[i].robj)) {
		2017	dev_err(rdev->dev, "(PW %u) Vertex array %u "
		2018	"need %lu dwords have %lu dwords\n",
		2019	prim_walk, i, size >> 2,
		2020	radeon_bo_size(track->arrays[i].robj)
		2021	>> 2);
		2022	DRM_ERROR("Max indices %u\n", track->max_indx);
		2023	return -EINVAL;
		2024	}
		2025	}
		2026	break;
		2027	case 2:
		2028	for (i = 0; i < track->num_arrays; i++) {
		2029	size = track->arrays[i].esize * (nverts - 1) * 4;
		2030	if (track->arrays[i].robj == NULL) {
		2031	DRM_ERROR("(PW %u) Vertex array %u no buffer "
		2032	"bound\n", prim_walk, i);
		2033	return -EINVAL;
		2034	}
		2035	if (size > radeon_bo_size(track->arrays[i].robj)) {
		2036	dev_err(rdev->dev, "(PW %u) Vertex array %u "
		2037	"need %lu dwords have %lu dwords\n",
		2038	prim_walk, i, size >> 2,
		2039	radeon_bo_size(track->arrays[i].robj)
		2040	>> 2);
		2041	return -EINVAL;
		2042	}
		2043	}
		2044	break;
		2045	case 3:
		2046	size = track->vtx_size * nverts;
		2047	if (size != track->immd_dwords) {
		2048	DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
		2049	track->immd_dwords, size);
		2050	DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
		2051	nverts, track->vtx_size);
		2052	return -EINVAL;
		2053	}
		2054	break;
		2055	default:
		2056	DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
		2057	prim_walk);
		2058	return -EINVAL;
		2059	}
		2060
		2061	if (track->tex_dirty) {
		2062	track->tex_dirty = false;
		2063	return r100_cs_track_texture_check(rdev, track);
		2064	}
		2065	return 0;
1117	serge	2066	}
		2067
2997	Serge	2068	void r100_cs_track_clear(struct radeon_device rdev, struct r100_cs_track track)
1117	serge	2069	{
2997	Serge	2070	unsigned i, face;
1117	serge	2071
2997	Serge	2072	track->cb_dirty = true;
		2073	track->zb_dirty = true;
		2074	track->tex_dirty = true;
		2075	track->aa_dirty = true;
1117	serge	2076
2997	Serge	2077	if (rdev->family < CHIP_R300) {
		2078	track->num_cb = 1;
		2079	if (rdev->family <= CHIP_RS200)
		2080	track->num_texture = 3;
		2081	else
		2082	track->num_texture = 6;
		2083	track->maxy = 2048;
		2084	track->separate_cube = 1;
		2085	} else {
		2086	track->num_cb = 4;
		2087	track->num_texture = 16;
		2088	track->maxy = 4096;
		2089	track->separate_cube = 0;
		2090	track->aaresolve = false;
		2091	track->aa.robj = NULL;
		2092	}
		2093
		2094	for (i = 0; i < track->num_cb; i++) {
		2095	track->cb[i].robj = NULL;
		2096	track->cb[i].pitch = 8192;
		2097	track->cb[i].cpp = 16;
		2098	track->cb[i].offset = 0;
		2099	}
		2100	track->z_enabled = true;
		2101	track->zb.robj = NULL;
		2102	track->zb.pitch = 8192;
		2103	track->zb.cpp = 4;
		2104	track->zb.offset = 0;
		2105	track->vtx_size = 0x7F;
		2106	track->immd_dwords = 0xFFFFFFFFUL;
		2107	track->num_arrays = 11;
		2108	track->max_indx = 0x00FFFFFFUL;
		2109	for (i = 0; i < track->num_arrays; i++) {
		2110	track->arrays[i].robj = NULL;
		2111	track->arrays[i].esize = 0x7F;
		2112	}
		2113	for (i = 0; i < track->num_texture; i++) {
		2114	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
		2115	track->textures[i].pitch = 16536;
		2116	track->textures[i].width = 16536;
		2117	track->textures[i].height = 16536;
		2118	track->textures[i].width_11 = 1 << 11;
		2119	track->textures[i].height_11 = 1 << 11;
		2120	track->textures[i].num_levels = 12;
		2121	if (rdev->family <= CHIP_RS200) {
		2122	track->textures[i].tex_coord_type = 0;
		2123	track->textures[i].txdepth = 0;
		2124	} else {
		2125	track->textures[i].txdepth = 16;
		2126	track->textures[i].tex_coord_type = 1;
1117	serge	2127	}
2997	Serge	2128	track->textures[i].cpp = 64;
		2129	track->textures[i].robj = NULL;
		2130	/* CS IB emission code makes sure texture unit are disabled */
		2131	track->textures[i].enabled = false;
		2132	track->textures[i].lookup_disable = false;
		2133	track->textures[i].roundup_w = true;
		2134	track->textures[i].roundup_h = true;
		2135	if (track->separate_cube)
		2136	for (face = 0; face < 5; face++) {
		2137	track->textures[i].cube_info[face].robj = NULL;
		2138	track->textures[i].cube_info[face].width = 16536;
		2139	track->textures[i].cube_info[face].height = 16536;
		2140	track->textures[i].cube_info[face].offset = 0;
		2141	}
1117	serge	2142	}
		2143	}
2997	Serge	2144	#endif
1117	serge	2145
2997	Serge	2146	/*
		2147	* Global GPU functions
		2148	*/
		2149	static void r100_errata(struct radeon_device *rdev)
1117	serge	2150	{
2997	Serge	2151	rdev->pll_errata = 0;
		2152
		2153	if (rdev->family == CHIP_RV200 \|\| rdev->family == CHIP_RS200) {
		2154	rdev->pll_errata \|= CHIP_ERRATA_PLL_DUMMYREADS;
		2155	}
		2156
		2157	if (rdev->family == CHIP_RV100 \|\|
		2158	rdev->family == CHIP_RS100 \|\|
		2159	rdev->family == CHIP_RS200) {
		2160	rdev->pll_errata \|= CHIP_ERRATA_PLL_DELAY;
		2161	}
		2162	}
		2163
		2164	static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
		2165	{
1117	serge	2166	unsigned i;
		2167	uint32_t tmp;
		2168
		2169	for (i = 0; i < rdev->usec_timeout; i++) {
		2170	tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
		2171	if (tmp >= n) {
		2172	return 0;
		2173	}
		2174	DRM_UDELAY(1);
		2175	}
		2176	return -1;
		2177	}
		2178
		2179	int r100_gui_wait_for_idle(struct radeon_device *rdev)
		2180	{
		2181	unsigned i;
		2182	uint32_t tmp;
		2183
		2184	if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
		2185	printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
		2186	" Bad things might happen.\n");
		2187	}
		2188	for (i = 0; i < rdev->usec_timeout; i++) {
		2189	tmp = RREG32(RADEON_RBBM_STATUS);
1430	serge	2190	if (!(tmp & RADEON_RBBM_ACTIVE)) {
1117	serge	2191	return 0;
		2192	}
		2193	DRM_UDELAY(1);
		2194	}
		2195	return -1;
		2196	}
		2197
		2198	int r100_mc_wait_for_idle(struct radeon_device *rdev)
		2199	{
		2200	unsigned i;
		2201	uint32_t tmp;
		2202
		2203	for (i = 0; i < rdev->usec_timeout; i++) {
		2204	/* read MC_STATUS */
1430	serge	2205	tmp = RREG32(RADEON_MC_STATUS);
		2206	if (tmp & RADEON_MC_IDLE) {
1117	serge	2207	return 0;
		2208	}
		2209	DRM_UDELAY(1);
		2210	}
		2211	return -1;
		2212	}
		2213
2997	Serge	2214	bool r100_gpu_is_lockup(struct radeon_device rdev, struct radeon_ring ring)
1117	serge	2215	{
1963	serge	2216	u32 rbbm_status;
1117	serge	2217
1963	serge	2218	rbbm_status = RREG32(R_000E40_RBBM_STATUS);
		2219	if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2997	Serge	2220	radeon_ring_lockup_update(ring);
1963	serge	2221	return false;
1117	serge	2222	}
1963	serge	2223	/* force CP activities */
2997	Serge	2224	radeon_ring_force_activity(rdev, ring);
		2225	return radeon_ring_test_lockup(rdev, ring);
1117	serge	2226	}
		2227
2997	Serge	2228	/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
		2229	void r100_enable_bm(struct radeon_device *rdev)
		2230	{
		2231	uint32_t tmp;
		2232	/* Enable bus mastering */
		2233	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
		2234	WREG32(RADEON_BUS_CNTL, tmp);
		2235	}
		2236
1963	serge	2237	void r100_bm_disable(struct radeon_device *rdev)
1117	serge	2238	{
1963	serge	2239	u32 tmp;
1117	serge	2240
1963	serge	2241	/* disable bus mastering */
		2242	tmp = RREG32(R_000030_BUS_CNTL);
		2243	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000044);
		2244	mdelay(1);
		2245	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000042);
		2246	mdelay(1);
		2247	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000040);
		2248	tmp = RREG32(RADEON_BUS_CNTL);
		2249	mdelay(1);
2997	Serge	2250	pci_clear_master(rdev->pdev);
1963	serge	2251	mdelay(1);
		2252	}
		2253
		2254	int r100_asic_reset(struct radeon_device *rdev)
		2255	{
		2256	struct r100_mc_save save;
		2257	u32 status, tmp;
		2258	int ret = 0;
		2259
		2260	status = RREG32(R_000E40_RBBM_STATUS);
		2261	if (!G_000E40_GUI_ACTIVE(status)) {
		2262	return 0;
1117	serge	2263	}
1963	serge	2264	r100_mc_stop(rdev, &save);
		2265	status = RREG32(R_000E40_RBBM_STATUS);
		2266	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		2267	/* stop CP */
		2268	WREG32(RADEON_CP_CSQ_CNTL, 0);
		2269	tmp = RREG32(RADEON_CP_RB_CNTL);
		2270	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);
		2271	WREG32(RADEON_CP_RB_RPTR_WR, 0);
		2272	WREG32(RADEON_CP_RB_WPTR, 0);
		2273	WREG32(RADEON_CP_RB_CNTL, tmp);
		2274	/* save PCI state */
		2275	// pci_save_state(rdev->pdev);
		2276	/* disable bus mastering */
		2277	r100_bm_disable(rdev);
		2278	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) \|
		2279	S_0000F0_SOFT_RESET_RE(1) \|
		2280	S_0000F0_SOFT_RESET_PP(1) \|
		2281	S_0000F0_SOFT_RESET_RB(1));
		2282	RREG32(R_0000F0_RBBM_SOFT_RESET);
		2283	mdelay(500);
		2284	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		2285	mdelay(1);
		2286	status = RREG32(R_000E40_RBBM_STATUS);
		2287	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
1117	serge	2288	/* reset CP */
1963	serge	2289	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
		2290	RREG32(R_0000F0_RBBM_SOFT_RESET);
		2291	mdelay(500);
		2292	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		2293	mdelay(1);
		2294	status = RREG32(R_000E40_RBBM_STATUS);
		2295	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		2296	/* restore PCI & busmastering */
		2297	// pci_restore_state(rdev->pdev);
		2298	r100_enable_bm(rdev);
1117	serge	2299	/* Check if GPU is idle */
1963	serge	2300	if (G_000E40_SE_BUSY(status) \|\| G_000E40_RE_BUSY(status) \|\|
		2301	G_000E40_TAM_BUSY(status) \|\| G_000E40_PB_BUSY(status)) {
		2302	dev_err(rdev->dev, "failed to reset GPU\n");
		2303	ret = -1;
		2304	} else
		2305	dev_info(rdev->dev, "GPU reset succeed\n");
		2306	r100_mc_resume(rdev, &save);
		2307	return ret;
1117	serge	2308	}
		2309
1321	serge	2310	void r100_set_common_regs(struct radeon_device *rdev)
		2311	{
1430	serge	2312	struct drm_device *dev = rdev->ddev;
		2313	bool force_dac2 = false;
1963	serge	2314	u32 tmp;
1430	serge	2315
1321	serge	2316	/* set these so they don't interfere with anything */
		2317	WREG32(RADEON_OV0_SCALE_CNTL, 0);
		2318	WREG32(RADEON_SUBPIC_CNTL, 0);
		2319	WREG32(RADEON_VIPH_CONTROL, 0);
		2320	WREG32(RADEON_I2C_CNTL_1, 0);
		2321	WREG32(RADEON_DVI_I2C_CNTL_1, 0);
		2322	WREG32(RADEON_CAP0_TRIG_CNTL, 0);
		2323	WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1430	serge	2324
		2325	/* always set up dac2 on rn50 and some rv100 as lots
		2326	* of servers seem to wire it up to a VGA port but
		2327	* don't report it in the bios connector
		2328	* table.
		2329	*/
		2330	switch (dev->pdev->device) {
		2331	/* RN50 */
		2332	case 0x515e:
		2333	case 0x5969:
		2334	force_dac2 = true;
		2335	break;
		2336	/* RV100*/
		2337	case 0x5159:
		2338	case 0x515a:
		2339	/* DELL triple head servers */
		2340	if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
		2341	((dev->pdev->subsystem_device == 0x016c) \|\|
		2342	(dev->pdev->subsystem_device == 0x016d) \|\|
		2343	(dev->pdev->subsystem_device == 0x016e) \|\|
		2344	(dev->pdev->subsystem_device == 0x016f) \|\|
		2345	(dev->pdev->subsystem_device == 0x0170) \|\|
		2346	(dev->pdev->subsystem_device == 0x017d) \|\|
		2347	(dev->pdev->subsystem_device == 0x017e) \|\|
		2348	(dev->pdev->subsystem_device == 0x0183) \|\|
		2349	(dev->pdev->subsystem_device == 0x018a) \|\|
		2350	(dev->pdev->subsystem_device == 0x019a)))
		2351	force_dac2 = true;
		2352	break;
		2353	}
		2354
		2355	if (force_dac2) {
		2356	u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
		2357	u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		2358	u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
		2359
		2360	/* For CRT on DAC2, don't turn it on if BIOS didn't
		2361	enable it, even it's detected.
		2362	*/
		2363
		2364	/* force it to crtc0 */
		2365	dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
		2366	dac2_cntl \|= RADEON_DAC2_DAC2_CLK_SEL;
		2367	disp_hw_debug \|= RADEON_CRT2_DISP1_SEL;
		2368
		2369	/* set up the TV DAC */
		2370	tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL \|
		2371	RADEON_TV_DAC_STD_MASK \|
		2372	RADEON_TV_DAC_RDACPD \|
		2373	RADEON_TV_DAC_GDACPD \|
		2374	RADEON_TV_DAC_BDACPD \|
		2375	RADEON_TV_DAC_BGADJ_MASK \|
		2376	RADEON_TV_DAC_DACADJ_MASK);
		2377	tv_dac_cntl \|= (RADEON_TV_DAC_NBLANK \|
		2378	RADEON_TV_DAC_NHOLD \|
		2379	RADEON_TV_DAC_STD_PS2 \|
		2380	(0x58 << 16));
		2381
		2382	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		2383	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		2384	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		2385	}
1963	serge	2386
		2387	/* switch PM block to ACPI mode */
		2388	tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
		2389	tmp &= ~RADEON_PM_MODE_SEL;
		2390	WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
		2391
1321	serge	2392	}
1117	serge	2393
		2394	/*
		2395	* VRAM info
		2396	*/
		2397	static void r100_vram_get_type(struct radeon_device *rdev)
		2398	{
		2399	uint32_t tmp;
		2400
		2401	rdev->mc.vram_is_ddr = false;
		2402	if (rdev->flags & RADEON_IS_IGP)
		2403	rdev->mc.vram_is_ddr = true;
		2404	else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
		2405	rdev->mc.vram_is_ddr = true;
		2406	if ((rdev->family == CHIP_RV100) \|\|
		2407	(rdev->family == CHIP_RS100) \|\|
		2408	(rdev->family == CHIP_RS200)) {
		2409	tmp = RREG32(RADEON_MEM_CNTL);
		2410	if (tmp & RV100_HALF_MODE) {
		2411	rdev->mc.vram_width = 32;
		2412	} else {
		2413	rdev->mc.vram_width = 64;
		2414	}
		2415	if (rdev->flags & RADEON_SINGLE_CRTC) {
		2416	rdev->mc.vram_width /= 4;
		2417	rdev->mc.vram_is_ddr = true;
		2418	}
		2419	} else if (rdev->family <= CHIP_RV280) {
		2420	tmp = RREG32(RADEON_MEM_CNTL);
		2421	if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
		2422	rdev->mc.vram_width = 128;
		2423	} else {
		2424	rdev->mc.vram_width = 64;
		2425	}
		2426	} else {
		2427	/* newer IGPs */
		2428	rdev->mc.vram_width = 128;
		2429	}
		2430	}
		2431
1179	serge	2432	static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1117	serge	2433	{
1179	serge	2434	u32 aper_size;
		2435	u8 byte;
1117	serge	2436
1179	serge	2437	aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
		2438
		2439	/* Set HDP_APER_CNTL only on cards that are known not to be broken,
		2440	* that is has the 2nd generation multifunction PCI interface
		2441	*/
		2442	if (rdev->family == CHIP_RV280 \|\|
		2443	rdev->family >= CHIP_RV350) {
		2444	WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
		2445	~RADEON_HDP_APER_CNTL);
		2446	DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
		2447	return aper_size * 2;
		2448	}
		2449
		2450	/* Older cards have all sorts of funny issues to deal with. First
		2451	* check if it's a multifunction card by reading the PCI config
		2452	* header type... Limit those to one aperture size
		2453	*/
		2454	// pci_read_config_byte(rdev->pdev, 0xe, &byte);
		2455	// if (byte & 0x80) {
		2456	// DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
		2457	// DRM_INFO("Limiting VRAM to one aperture\n");
		2458	// return aper_size;
		2459	// }
		2460
		2461	/* Single function older card. We read HDP_APER_CNTL to see how the BIOS
		2462	* have set it up. We don't write this as it's broken on some ASICs but
		2463	* we expect the BIOS to have done the right thing (might be too optimistic...)
		2464	*/
		2465	if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
		2466	return aper_size * 2;
		2467	return aper_size;
		2468	}
		2469
		2470	void r100_vram_init_sizes(struct radeon_device *rdev)
		2471	{
		2472	u64 config_aper_size;
		2473
1430	serge	2474	/* work out accessible VRAM */
1963	serge	2475	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
		2476	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1430	serge	2477	rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
		2478	/* FIXME we don't use the second aperture yet when we could use it */
		2479	if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
		2480	rdev->mc.visible_vram_size = rdev->mc.aper_size;
1179	serge	2481	config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1117	serge	2482	if (rdev->flags & RADEON_IS_IGP) {
		2483	uint32_t tom;
		2484	/* read NB_TOM to get the amount of ram stolen for the GPU */
		2485	tom = RREG32(RADEON_NB_TOM);
1179	serge	2486	rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
		2487	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
		2488	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	2489	} else {
1179	serge	2490	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1117	serge	2491	/* Some production boards of m6 will report 0
		2492	* if it's 8 MB
		2493	*/
1179	serge	2494	if (rdev->mc.real_vram_size == 0) {
		2495	rdev->mc.real_vram_size = 8192 * 1024;
		2496	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1117	serge	2497	}
1179	serge	2498	/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1430	serge	2499	* Novell bug 204882 + along with lots of ubuntu ones
		2500	*/
1963	serge	2501	if (rdev->mc.aper_size > config_aper_size)
		2502	config_aper_size = rdev->mc.aper_size;
		2503
1179	serge	2504	if (config_aper_size > rdev->mc.real_vram_size)
		2505	rdev->mc.mc_vram_size = config_aper_size;
		2506	else
		2507	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	2508	}
		2509	}
		2510
1179	serge	2511	void r100_vga_set_state(struct radeon_device *rdev, bool state)
		2512	{
		2513	uint32_t temp;
		2514
		2515	temp = RREG32(RADEON_CONFIG_CNTL);
		2516	if (state == false) {
1963	serge	2517	temp &= ~RADEON_CFG_VGA_RAM_EN;
		2518	temp \|= RADEON_CFG_VGA_IO_DIS;
1179	serge	2519	} else {
1963	serge	2520	temp &= ~RADEON_CFG_VGA_IO_DIS;
1179	serge	2521	}
		2522	WREG32(RADEON_CONFIG_CNTL, temp);
		2523	}
		2524
2997	Serge	2525	static void r100_mc_init(struct radeon_device *rdev)
1179	serge	2526	{
1430	serge	2527	u64 base;
		2528
1179	serge	2529	r100_vram_get_type(rdev);
		2530	r100_vram_init_sizes(rdev);
1430	serge	2531	base = rdev->mc.aper_base;
		2532	if (rdev->flags & RADEON_IS_IGP)
		2533	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
		2534	radeon_vram_location(rdev, &rdev->mc, base);
1963	serge	2535	rdev->mc.gtt_base_align = 0;
1430	serge	2536	if (!(rdev->flags & RADEON_IS_AGP))
		2537	radeon_gtt_location(rdev, &rdev->mc);
1963	serge	2538	radeon_update_bandwidth_info(rdev);
1179	serge	2539	}
		2540
		2541
1117	serge	2542	/*
		2543	* Indirect registers accessor
		2544	*/
		2545	void r100_pll_errata_after_index(struct radeon_device *rdev)
		2546	{
1963	serge	2547	if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
1117	serge	2548	(void)RREG32(RADEON_CLOCK_CNTL_DATA);
		2549	(void)RREG32(RADEON_CRTC_GEN_CNTL);
1963	serge	2550	}
1117	serge	2551	}
		2552
		2553	static void r100_pll_errata_after_data(struct radeon_device *rdev)
		2554	{
		2555	/* This workarounds is necessary on RV100, RS100 and RS200 chips
		2556	* or the chip could hang on a subsequent access
		2557	*/
		2558	if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2997	Serge	2559	mdelay(5);
1117	serge	2560	}
		2561
		2562	/* This function is required to workaround a hardware bug in some (all?)
		2563	* revisions of the R300. This workaround should be called after every
		2564	* CLOCK_CNTL_INDEX register access. If not, register reads afterward
		2565	* may not be correct.
		2566	*/
		2567	if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
		2568	uint32_t save, tmp;
		2569
		2570	save = RREG32(RADEON_CLOCK_CNTL_INDEX);
		2571	tmp = save & ~(0x3f \| RADEON_PLL_WR_EN);
		2572	WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
		2573	tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
		2574	WREG32(RADEON_CLOCK_CNTL_INDEX, save);
		2575	}
		2576	}
		2577
		2578	uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
		2579	{
		2580	uint32_t data;
		2581
		2582	WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
		2583	r100_pll_errata_after_index(rdev);
		2584	data = RREG32(RADEON_CLOCK_CNTL_DATA);
		2585	r100_pll_errata_after_data(rdev);
		2586	return data;
		2587	}
		2588
		2589	void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		2590	{
		2591	WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) \| RADEON_PLL_WR_EN));
		2592	r100_pll_errata_after_index(rdev);
		2593	WREG32(RADEON_CLOCK_CNTL_DATA, v);
		2594	r100_pll_errata_after_data(rdev);
		2595	}
		2596
2997	Serge	2597	static void r100_set_safe_registers(struct radeon_device *rdev)
1117	serge	2598	{
1179	serge	2599	if (ASIC_IS_RN50(rdev)) {
		2600	rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
		2601	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
		2602	} else if (rdev->family < CHIP_R200) {
		2603	rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
		2604	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
		2605	} else {
1221	serge	2606	r200_set_safe_registers(rdev);
1117	serge	2607	}
		2608	}
		2609
1129	serge	2610	/*
		2611	* Debugfs info
		2612	*/
		2613	#if defined(CONFIG_DEBUG_FS)
		2614	static int r100_debugfs_rbbm_info(struct seq_file m, void data)
		2615	{
		2616	struct drm_info_node node = (struct drm_info_node ) m->private;
		2617	struct drm_device *dev = node->minor->dev;
		2618	struct radeon_device *rdev = dev->dev_private;
		2619	uint32_t reg, value;
		2620	unsigned i;
		2621
		2622	seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
		2623	seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
		2624	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2625	for (i = 0; i < 64; i++) {
		2626	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i \| 0x100);
		2627	reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
		2628	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
		2629	value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
		2630	seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
		2631	}
		2632	return 0;
		2633	}
		2634
		2635	static int r100_debugfs_cp_ring_info(struct seq_file m, void data)
		2636	{
		2637	struct drm_info_node node = (struct drm_info_node ) m->private;
		2638	struct drm_device *dev = node->minor->dev;
		2639	struct radeon_device *rdev = dev->dev_private;
2997	Serge	2640	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1129	serge	2641	uint32_t rdp, wdp;
		2642	unsigned count, i, j;
		2643
2997	Serge	2644	radeon_ring_free_size(rdev, ring);
1129	serge	2645	rdp = RREG32(RADEON_CP_RB_RPTR);
		2646	wdp = RREG32(RADEON_CP_RB_WPTR);
2997	Serge	2647	count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
1129	serge	2648	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2649	seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
		2650	seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2997	Serge	2651	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
1129	serge	2652	seq_printf(m, "%u dwords in ring\n", count);
		2653	for (j = 0; j <= count; j++) {
2997	Serge	2654	i = (rdp + j) & ring->ptr_mask;
		2655	seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
1129	serge	2656	}
		2657	return 0;
		2658	}
		2659
		2660
		2661	static int r100_debugfs_cp_csq_fifo(struct seq_file m, void data)
		2662	{
		2663	struct drm_info_node node = (struct drm_info_node ) m->private;
		2664	struct drm_device *dev = node->minor->dev;
		2665	struct radeon_device *rdev = dev->dev_private;
		2666	uint32_t csq_stat, csq2_stat, tmp;
		2667	unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
		2668	unsigned i;
		2669
		2670	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2671	seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
		2672	csq_stat = RREG32(RADEON_CP_CSQ_STAT);
		2673	csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
		2674	r_rptr = (csq_stat >> 0) & 0x3ff;
		2675	r_wptr = (csq_stat >> 10) & 0x3ff;
		2676	ib1_rptr = (csq_stat >> 20) & 0x3ff;
		2677	ib1_wptr = (csq2_stat >> 0) & 0x3ff;
		2678	ib2_rptr = (csq2_stat >> 10) & 0x3ff;
		2679	ib2_wptr = (csq2_stat >> 20) & 0x3ff;
		2680	seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
		2681	seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
		2682	seq_printf(m, "Ring rptr %u\n", r_rptr);
		2683	seq_printf(m, "Ring wptr %u\n", r_wptr);
		2684	seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
		2685	seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
		2686	seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
		2687	seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
		2688	/* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
		2689	* 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
		2690	seq_printf(m, "Ring fifo:\n");
		2691	for (i = 0; i < 256; i++) {
		2692	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2693	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2694	seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
		2695	}
		2696	seq_printf(m, "Indirect1 fifo:\n");
		2697	for (i = 256; i <= 512; i++) {
		2698	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2699	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2700	seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
		2701	}
		2702	seq_printf(m, "Indirect2 fifo:\n");
		2703	for (i = 640; i < ib1_wptr; i++) {
		2704	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2705	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2706	seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
		2707	}
		2708	return 0;
		2709	}
		2710
		2711	static int r100_debugfs_mc_info(struct seq_file m, void data)
		2712	{
		2713	struct drm_info_node node = (struct drm_info_node ) m->private;
		2714	struct drm_device *dev = node->minor->dev;
		2715	struct radeon_device *rdev = dev->dev_private;
		2716	uint32_t tmp;
		2717
		2718	tmp = RREG32(RADEON_CONFIG_MEMSIZE);
		2719	seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
		2720	tmp = RREG32(RADEON_MC_FB_LOCATION);
		2721	seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
		2722	tmp = RREG32(RADEON_BUS_CNTL);
		2723	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
		2724	tmp = RREG32(RADEON_MC_AGP_LOCATION);
		2725	seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
		2726	tmp = RREG32(RADEON_AGP_BASE);
		2727	seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
		2728	tmp = RREG32(RADEON_HOST_PATH_CNTL);
		2729	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
		2730	tmp = RREG32(0x01D0);
		2731	seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
		2732	tmp = RREG32(RADEON_AIC_LO_ADDR);
		2733	seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
		2734	tmp = RREG32(RADEON_AIC_HI_ADDR);
		2735	seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
		2736	tmp = RREG32(0x01E4);
		2737	seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
		2738	return 0;
		2739	}
		2740
		2741	static struct drm_info_list r100_debugfs_rbbm_list[] = {
		2742	{"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
		2743	};
		2744
		2745	static struct drm_info_list r100_debugfs_cp_list[] = {
		2746	{"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
		2747	{"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
		2748	};
		2749
		2750	static struct drm_info_list r100_debugfs_mc_info_list[] = {
		2751	{"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
		2752	};
		2753	#endif
		2754
		2755	int r100_debugfs_rbbm_init(struct radeon_device *rdev)
		2756	{
		2757	#if defined(CONFIG_DEBUG_FS)
		2758	return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
		2759	#else
		2760	return 0;
		2761	#endif
		2762	}
		2763
		2764	int r100_debugfs_cp_init(struct radeon_device *rdev)
		2765	{
		2766	#if defined(CONFIG_DEBUG_FS)
		2767	return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
		2768	#else
		2769	return 0;
		2770	#endif
		2771	}
		2772
		2773	int r100_debugfs_mc_info_init(struct radeon_device *rdev)
		2774	{
		2775	#if defined(CONFIG_DEBUG_FS)
		2776	return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
		2777	#else
		2778	return 0;
		2779	#endif
		2780	}
1179	serge	2781
		2782	int r100_set_surface_reg(struct radeon_device *rdev, int reg,
		2783	uint32_t tiling_flags, uint32_t pitch,
		2784	uint32_t offset, uint32_t obj_size)
		2785	{
		2786	int surf_index = reg * 16;
		2787	int flags = 0;
		2788
		2789	if (rdev->family <= CHIP_RS200) {
		2790	if ((tiling_flags & (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		2791	== (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		2792	flags \|= RADEON_SURF_TILE_COLOR_BOTH;
		2793	if (tiling_flags & RADEON_TILING_MACRO)
		2794	flags \|= RADEON_SURF_TILE_COLOR_MACRO;
		2795	} else if (rdev->family <= CHIP_RV280) {
		2796	if (tiling_flags & (RADEON_TILING_MACRO))
		2797	flags \|= R200_SURF_TILE_COLOR_MACRO;
		2798	if (tiling_flags & RADEON_TILING_MICRO)
		2799	flags \|= R200_SURF_TILE_COLOR_MICRO;
		2800	} else {
		2801	if (tiling_flags & RADEON_TILING_MACRO)
		2802	flags \|= R300_SURF_TILE_MACRO;
		2803	if (tiling_flags & RADEON_TILING_MICRO)
		2804	flags \|= R300_SURF_TILE_MICRO;
		2805	}
		2806
		2807	if (tiling_flags & RADEON_TILING_SWAP_16BIT)
		2808	flags \|= RADEON_SURF_AP0_SWP_16BPP \| RADEON_SURF_AP1_SWP_16BPP;
		2809	if (tiling_flags & RADEON_TILING_SWAP_32BIT)
		2810	flags \|= RADEON_SURF_AP0_SWP_32BPP \| RADEON_SURF_AP1_SWP_32BPP;
		2811
1963	serge	2812	/* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
		2813	if (tiling_flags & (RADEON_TILING_SWAP_16BIT \| RADEON_TILING_SWAP_32BIT)) {
		2814	if (!(tiling_flags & (RADEON_TILING_MACRO \| RADEON_TILING_MICRO)))
		2815	if (ASIC_IS_RN50(rdev))
		2816	pitch /= 16;
		2817	}
		2818
		2819	/* r100/r200 divide by 16 */
		2820	if (rdev->family < CHIP_R300)
		2821	flags \|= pitch / 16;
		2822	else
		2823	flags \|= pitch / 8;
		2824
		2825
		2826	DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
1179	serge	2827	WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
		2828	WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
		2829	WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
		2830	return 0;
		2831	}
		2832
		2833	void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
		2834	{
		2835	int surf_index = reg * 16;
		2836	WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
		2837	}
		2838
		2839	void r100_bandwidth_update(struct radeon_device *rdev)
		2840	{
		2841	fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
		2842	fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
		2843	fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
		2844	uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
		2845	fixed20_12 memtcas_ff[8] = {
1963	serge	2846	dfixed_init(1),
		2847	dfixed_init(2),
		2848	dfixed_init(3),
		2849	dfixed_init(0),
		2850	dfixed_init_half(1),
		2851	dfixed_init_half(2),
		2852	dfixed_init(0),
1179	serge	2853	};
		2854	fixed20_12 memtcas_rs480_ff[8] = {
1963	serge	2855	dfixed_init(0),
		2856	dfixed_init(1),
		2857	dfixed_init(2),
		2858	dfixed_init(3),
		2859	dfixed_init(0),
		2860	dfixed_init_half(1),
		2861	dfixed_init_half(2),
		2862	dfixed_init_half(3),
1179	serge	2863	};
		2864	fixed20_12 memtcas2_ff[8] = {
1963	serge	2865	dfixed_init(0),
		2866	dfixed_init(1),
		2867	dfixed_init(2),
		2868	dfixed_init(3),
		2869	dfixed_init(4),
		2870	dfixed_init(5),
		2871	dfixed_init(6),
		2872	dfixed_init(7),
1179	serge	2873	};
		2874	fixed20_12 memtrbs[8] = {
1963	serge	2875	dfixed_init(1),
		2876	dfixed_init_half(1),
		2877	dfixed_init(2),
		2878	dfixed_init_half(2),
		2879	dfixed_init(3),
		2880	dfixed_init_half(3),
		2881	dfixed_init(4),
		2882	dfixed_init_half(4)
1179	serge	2883	};
		2884	fixed20_12 memtrbs_r4xx[8] = {
1963	serge	2885	dfixed_init(4),
		2886	dfixed_init(5),
		2887	dfixed_init(6),
		2888	dfixed_init(7),
		2889	dfixed_init(8),
		2890	dfixed_init(9),
		2891	dfixed_init(10),
		2892	dfixed_init(11)
1179	serge	2893	};
		2894	fixed20_12 min_mem_eff;
		2895	fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
		2896	fixed20_12 cur_latency_mclk, cur_latency_sclk;
		2897	fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
		2898	disp_drain_rate2, read_return_rate;
		2899	fixed20_12 time_disp1_drop_priority;
		2900	int c;
		2901	int cur_size = 16; /* in octawords */
		2902	int critical_point = 0, critical_point2;
		2903	/* uint32_t read_return_rate, time_disp1_drop_priority; */
		2904	int stop_req, max_stop_req;
		2905	struct drm_display_mode *mode1 = NULL;
		2906	struct drm_display_mode *mode2 = NULL;
		2907	uint32_t pixel_bytes1 = 0;
		2908	uint32_t pixel_bytes2 = 0;
		2909
1963	serge	2910	radeon_update_display_priority(rdev);
		2911
1179	serge	2912	if (rdev->mode_info.crtcs[0]->base.enabled) {
		2913	mode1 = &rdev->mode_info.crtcs[0]->base.mode;
		2914	pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
		2915	}
1221	serge	2916	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
1179	serge	2917	if (rdev->mode_info.crtcs[1]->base.enabled) {
		2918	mode2 = &rdev->mode_info.crtcs[1]->base.mode;
		2919	pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
		2920	}
1221	serge	2921	}
1179	serge	2922
1963	serge	2923	min_mem_eff.full = dfixed_const_8(0);
1179	serge	2924	/* get modes */
		2925	if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
		2926	uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
		2927	mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
		2928	mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
		2929	/* check crtc enables */
		2930	if (mode2)
		2931	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
		2932	if (mode1)
		2933	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
		2934	WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
		2935	}
		2936
		2937	/*
		2938	* determine is there is enough bw for current mode
		2939	*/
1963	serge	2940	sclk_ff = rdev->pm.sclk;
		2941	mclk_ff = rdev->pm.mclk;
1179	serge	2942
		2943	temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
1963	serge	2944	temp_ff.full = dfixed_const(temp);
		2945	mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
1179	serge	2946
		2947	pix_clk.full = 0;
		2948	pix_clk2.full = 0;
		2949	peak_disp_bw.full = 0;
		2950	if (mode1) {
1963	serge	2951	temp_ff.full = dfixed_const(1000);
		2952	pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
		2953	pix_clk.full = dfixed_div(pix_clk, temp_ff);
		2954	temp_ff.full = dfixed_const(pixel_bytes1);
		2955	peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
1179	serge	2956	}
		2957	if (mode2) {
1963	serge	2958	temp_ff.full = dfixed_const(1000);
		2959	pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
		2960	pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
		2961	temp_ff.full = dfixed_const(pixel_bytes2);
		2962	peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
1179	serge	2963	}
		2964
1963	serge	2965	mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
1179	serge	2966	if (peak_disp_bw.full >= mem_bw.full) {
		2967	DRM_ERROR("You may not have enough display bandwidth for current mode\n"
		2968	"If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
		2969	}
		2970
		2971	/* Get values from the EXT_MEM_CNTL register...converting its contents. */
		2972	temp = RREG32(RADEON_MEM_TIMING_CNTL);
		2973	if ((rdev->family == CHIP_RV100) \|\| (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
		2974	mem_trcd = ((temp >> 2) & 0x3) + 1;
		2975	mem_trp = ((temp & 0x3)) + 1;
		2976	mem_tras = ((temp & 0x70) >> 4) + 1;
		2977	} else if (rdev->family == CHIP_R300 \|\|
		2978	rdev->family == CHIP_R350) { /* r300, r350 */
		2979	mem_trcd = (temp & 0x7) + 1;
		2980	mem_trp = ((temp >> 8) & 0x7) + 1;
		2981	mem_tras = ((temp >> 11) & 0xf) + 4;
		2982	} else if (rdev->family == CHIP_RV350 \|\|
		2983	rdev->family <= CHIP_RV380) {
		2984	/* rv3x0 */
		2985	mem_trcd = (temp & 0x7) + 3;
		2986	mem_trp = ((temp >> 8) & 0x7) + 3;
		2987	mem_tras = ((temp >> 11) & 0xf) + 6;
		2988	} else if (rdev->family == CHIP_R420 \|\|
		2989	rdev->family == CHIP_R423 \|\|
		2990	rdev->family == CHIP_RV410) {
		2991	/* r4xx */
		2992	mem_trcd = (temp & 0xf) + 3;
		2993	if (mem_trcd > 15)
		2994	mem_trcd = 15;
		2995	mem_trp = ((temp >> 8) & 0xf) + 3;
		2996	if (mem_trp > 15)
		2997	mem_trp = 15;
		2998	mem_tras = ((temp >> 12) & 0x1f) + 6;
		2999	if (mem_tras > 31)
		3000	mem_tras = 31;
		3001	} else { /* RV200, R200 */
		3002	mem_trcd = (temp & 0x7) + 1;
		3003	mem_trp = ((temp >> 8) & 0x7) + 1;
		3004	mem_tras = ((temp >> 12) & 0xf) + 4;
		3005	}
		3006	/* convert to FF */
1963	serge	3007	trcd_ff.full = dfixed_const(mem_trcd);
		3008	trp_ff.full = dfixed_const(mem_trp);
		3009	tras_ff.full = dfixed_const(mem_tras);
1179	serge	3010
		3011	/* Get values from the MEM_SDRAM_MODE_REG register...converting its */
		3012	temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		3013	data = (temp & (7 << 20)) >> 20;
		3014	if ((rdev->family == CHIP_RV100) \|\| rdev->flags & RADEON_IS_IGP) {
		3015	if (rdev->family == CHIP_RS480) /* don't think rs400 */
		3016	tcas_ff = memtcas_rs480_ff[data];
		3017	else
		3018	tcas_ff = memtcas_ff[data];
		3019	} else
		3020	tcas_ff = memtcas2_ff[data];
		3021
		3022	if (rdev->family == CHIP_RS400 \|\|
		3023	rdev->family == CHIP_RS480) {
		3024	/* extra cas latency stored in bits 23-25 0-4 clocks */
		3025	data = (temp >> 23) & 0x7;
		3026	if (data < 5)
1963	serge	3027	tcas_ff.full += dfixed_const(data);
1179	serge	3028	}
		3029
		3030	if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
		3031	/* on the R300, Tcas is included in Trbs.
		3032	*/
		3033	temp = RREG32(RADEON_MEM_CNTL);
		3034	data = (R300_MEM_NUM_CHANNELS_MASK & temp);
		3035	if (data == 1) {
		3036	if (R300_MEM_USE_CD_CH_ONLY & temp) {
		3037	temp = RREG32(R300_MC_IND_INDEX);
		3038	temp &= ~R300_MC_IND_ADDR_MASK;
		3039	temp \|= R300_MC_READ_CNTL_CD_mcind;
		3040	WREG32(R300_MC_IND_INDEX, temp);
		3041	temp = RREG32(R300_MC_IND_DATA);
		3042	data = (R300_MEM_RBS_POSITION_C_MASK & temp);
		3043	} else {
		3044	temp = RREG32(R300_MC_READ_CNTL_AB);
		3045	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		3046	}
		3047	} else {
		3048	temp = RREG32(R300_MC_READ_CNTL_AB);
		3049	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		3050	}
		3051	if (rdev->family == CHIP_RV410 \|\|
		3052	rdev->family == CHIP_R420 \|\|
		3053	rdev->family == CHIP_R423)
		3054	trbs_ff = memtrbs_r4xx[data];
		3055	else
		3056	trbs_ff = memtrbs[data];
		3057	tcas_ff.full += trbs_ff.full;
		3058	}
		3059
		3060	sclk_eff_ff.full = sclk_ff.full;
		3061
		3062	if (rdev->flags & RADEON_IS_AGP) {
		3063	fixed20_12 agpmode_ff;
1963	serge	3064	agpmode_ff.full = dfixed_const(radeon_agpmode);
		3065	temp_ff.full = dfixed_const_666(16);
		3066	sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
1179	serge	3067	}
		3068	/* TODO PCIE lanes may affect this - agpmode == 16?? */
		3069
		3070	if (ASIC_IS_R300(rdev)) {
1963	serge	3071	sclk_delay_ff.full = dfixed_const(250);
1179	serge	3072	} else {
		3073	if ((rdev->family == CHIP_RV100) \|\|
		3074	rdev->flags & RADEON_IS_IGP) {
		3075	if (rdev->mc.vram_is_ddr)
1963	serge	3076	sclk_delay_ff.full = dfixed_const(41);
1179	serge	3077	else
1963	serge	3078	sclk_delay_ff.full = dfixed_const(33);
1179	serge	3079	} else {
		3080	if (rdev->mc.vram_width == 128)
1963	serge	3081	sclk_delay_ff.full = dfixed_const(57);
1179	serge	3082	else
1963	serge	3083	sclk_delay_ff.full = dfixed_const(41);
1179	serge	3084	}
		3085	}
		3086
1963	serge	3087	mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
1179	serge	3088
		3089	if (rdev->mc.vram_is_ddr) {
		3090	if (rdev->mc.vram_width == 32) {
1963	serge	3091	k1.full = dfixed_const(40);
1179	serge	3092	c = 3;
		3093	} else {
1963	serge	3094	k1.full = dfixed_const(20);
1179	serge	3095	c = 1;
		3096	}
		3097	} else {
1963	serge	3098	k1.full = dfixed_const(40);
1179	serge	3099	c = 3;
		3100	}
		3101
1963	serge	3102	temp_ff.full = dfixed_const(2);
		3103	mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
		3104	temp_ff.full = dfixed_const(c);
		3105	mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
		3106	temp_ff.full = dfixed_const(4);
		3107	mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
		3108	mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
1179	serge	3109	mc_latency_mclk.full += k1.full;
		3110
1963	serge	3111	mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
		3112	mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
1179	serge	3113
		3114	/*
		3115	HW cursor time assuming worst case of full size colour cursor.
		3116	*/
1963	serge	3117	temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
1179	serge	3118	temp_ff.full += trcd_ff.full;
		3119	if (temp_ff.full < tras_ff.full)
		3120	temp_ff.full = tras_ff.full;
1963	serge	3121	cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
1179	serge	3122
1963	serge	3123	temp_ff.full = dfixed_const(cur_size);
		3124	cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
1179	serge	3125	/*
		3126	Find the total latency for the display data.
		3127	*/
1963	serge	3128	disp_latency_overhead.full = dfixed_const(8);
		3129	disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
1179	serge	3130	mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
		3131	mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
		3132
		3133	if (mc_latency_mclk.full > mc_latency_sclk.full)
		3134	disp_latency.full = mc_latency_mclk.full;
		3135	else
		3136	disp_latency.full = mc_latency_sclk.full;
		3137
		3138	/* setup Max GRPH_STOP_REQ default value */
		3139	if (ASIC_IS_RV100(rdev))
		3140	max_stop_req = 0x5c;
		3141	else
		3142	max_stop_req = 0x7c;
		3143
		3144	if (mode1) {
		3145	/* CRTC1
		3146	Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
		3147	GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
		3148	*/
		3149	stop_req = mode1->hdisplay * pixel_bytes1 / 16;
		3150
		3151	if (stop_req > max_stop_req)
		3152	stop_req = max_stop_req;
		3153
		3154	/*
		3155	Find the drain rate of the display buffer.
		3156	*/
1963	serge	3157	temp_ff.full = dfixed_const((16/pixel_bytes1));
		3158	disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
1179	serge	3159
		3160	/*
		3161	Find the critical point of the display buffer.
		3162	*/
1963	serge	3163	crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
		3164	crit_point_ff.full += dfixed_const_half(0);
1179	serge	3165
1963	serge	3166	critical_point = dfixed_trunc(crit_point_ff);
1179	serge	3167
		3168	if (rdev->disp_priority == 2) {
		3169	critical_point = 0;
		3170	}
		3171
		3172	/*
		3173	The critical point should never be above max_stop_req-4. Setting
		3174	GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
		3175	*/
		3176	if (max_stop_req - critical_point < 4)
		3177	critical_point = 0;
		3178
		3179	if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
		3180	/* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
		3181	critical_point = 0x10;
		3182	}
		3183
		3184	temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
		3185	temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
		3186	temp \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		3187	temp &= ~(RADEON_GRPH_START_REQ_MASK);
		3188	if ((rdev->family == CHIP_R350) &&
		3189	(stop_req > 0x15)) {
		3190	stop_req -= 0x10;
		3191	}
		3192	temp \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		3193	temp \|= RADEON_GRPH_BUFFER_SIZE;
		3194	temp &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		3195	RADEON_GRPH_CRITICAL_AT_SOF \|
		3196	RADEON_GRPH_STOP_CNTL);
		3197	/*
		3198	Write the result into the register.
		3199	*/
		3200	WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		3201	(critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		3202
		3203	#if 0
		3204	if ((rdev->family == CHIP_RS400) \|\|
		3205	(rdev->family == CHIP_RS480)) {
		3206	/* attempt to program RS400 disp regs correctly ??? */
		3207	temp = RREG32(RS400_DISP1_REG_CNTL);
		3208	temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK \|
		3209	RS400_DISP1_STOP_REQ_LEVEL_MASK);
		3210	WREG32(RS400_DISP1_REQ_CNTL1, (temp \|
		3211	(critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		3212	(critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		3213	temp = RREG32(RS400_DMIF_MEM_CNTL1);
		3214	temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK \|
		3215	RS400_DISP1_CRITICAL_POINT_STOP_MASK);
		3216	WREG32(RS400_DMIF_MEM_CNTL1, (temp \|
		3217	(critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) \|
		3218	(critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
		3219	}
		3220	#endif
		3221
1963	serge	3222	DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
1179	serge	3223	/* (unsigned int)info->SavedReg->grph_buffer_cntl, */
		3224	(unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
		3225	}
		3226
		3227	if (mode2) {
		3228	u32 grph2_cntl;
		3229	stop_req = mode2->hdisplay * pixel_bytes2 / 16;
		3230
		3231	if (stop_req > max_stop_req)
		3232	stop_req = max_stop_req;
		3233
		3234	/*
		3235	Find the drain rate of the display buffer.
		3236	*/
1963	serge	3237	temp_ff.full = dfixed_const((16/pixel_bytes2));
		3238	disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
1179	serge	3239
		3240	grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
		3241	grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
		3242	grph2_cntl \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		3243	grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
		3244	if ((rdev->family == CHIP_R350) &&
		3245	(stop_req > 0x15)) {
		3246	stop_req -= 0x10;
		3247	}
		3248	grph2_cntl \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		3249	grph2_cntl \|= RADEON_GRPH_BUFFER_SIZE;
		3250	grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		3251	RADEON_GRPH_CRITICAL_AT_SOF \|
		3252	RADEON_GRPH_STOP_CNTL);
		3253
		3254	if ((rdev->family == CHIP_RS100) \|\|
		3255	(rdev->family == CHIP_RS200))
		3256	critical_point2 = 0;
		3257	else {
		3258	temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
1963	serge	3259	temp_ff.full = dfixed_const(temp);
		3260	temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
1179	serge	3261	if (sclk_ff.full < temp_ff.full)
		3262	temp_ff.full = sclk_ff.full;
		3263
		3264	read_return_rate.full = temp_ff.full;
		3265
		3266	if (mode1) {
		3267	temp_ff.full = read_return_rate.full - disp_drain_rate.full;
1963	serge	3268	time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
1179	serge	3269	} else {
		3270	time_disp1_drop_priority.full = 0;
		3271	}
		3272	crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
1963	serge	3273	crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
		3274	crit_point_ff.full += dfixed_const_half(0);
1179	serge	3275
1963	serge	3276	critical_point2 = dfixed_trunc(crit_point_ff);
1179	serge	3277
		3278	if (rdev->disp_priority == 2) {
		3279	critical_point2 = 0;
		3280	}
		3281
		3282	if (max_stop_req - critical_point2 < 4)
		3283	critical_point2 = 0;
		3284
		3285	}
		3286
		3287	if (critical_point2 == 0 && rdev->family == CHIP_R300) {
		3288	/* some R300 cards have problem with this set to 0 */
		3289	critical_point2 = 0x10;
		3290	}
		3291
		3292	WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		3293	(critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		3294
		3295	if ((rdev->family == CHIP_RS400) \|\|
		3296	(rdev->family == CHIP_RS480)) {
		3297	#if 0
		3298	/* attempt to program RS400 disp2 regs correctly ??? */
		3299	temp = RREG32(RS400_DISP2_REQ_CNTL1);
		3300	temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK \|
		3301	RS400_DISP2_STOP_REQ_LEVEL_MASK);
		3302	WREG32(RS400_DISP2_REQ_CNTL1, (temp \|
		3303	(critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		3304	(critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		3305	temp = RREG32(RS400_DISP2_REQ_CNTL2);
		3306	temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK \|
		3307	RS400_DISP2_CRITICAL_POINT_STOP_MASK);
		3308	WREG32(RS400_DISP2_REQ_CNTL2, (temp \|
		3309	(critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) \|
		3310	(critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
		3311	#endif
		3312	WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
		3313	WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
		3314	WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
		3315	WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
		3316	}
		3317
1963	serge	3318	DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
1179	serge	3319	(unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
		3320	}
		3321	}
		3322
2997	Serge	3323	int r100_ring_test(struct radeon_device rdev, struct radeon_ring ring)
1963	serge	3324	{
1412	serge	3325	uint32_t scratch;
		3326	uint32_t tmp = 0;
		3327	unsigned i;
		3328	int r;
1179	serge	3329
1412	serge	3330	r = radeon_scratch_get(rdev, &scratch);
		3331	if (r) {
		3332	DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
		3333	return r;
		3334	}
		3335	WREG32(scratch, 0xCAFEDEAD);
2997	Serge	3336	r = radeon_ring_lock(rdev, ring, 2);
1412	serge	3337	if (r) {
		3338	DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
		3339	radeon_scratch_free(rdev, scratch);
		3340	return r;
		3341	}
2997	Serge	3342	radeon_ring_write(ring, PACKET0(scratch, 0));
		3343	radeon_ring_write(ring, 0xDEADBEEF);
		3344	radeon_ring_unlock_commit(rdev, ring);
1412	serge	3345	for (i = 0; i < rdev->usec_timeout; i++) {
		3346	tmp = RREG32(scratch);
		3347	if (tmp == 0xDEADBEEF) {
		3348	break;
		3349	}
		3350	DRM_UDELAY(1);
		3351	}
		3352	if (i < rdev->usec_timeout) {
		3353	DRM_INFO("ring test succeeded in %d usecs\n", i);
		3354	} else {
1963	serge	3355	DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1412	serge	3356	scratch, tmp);
		3357	r = -EINVAL;
		3358	}
		3359	radeon_scratch_free(rdev, scratch);
		3360	return r;
		3361	}
		3362
1963	serge	3363	void r100_ring_ib_execute(struct radeon_device rdev, struct radeon_ib ib)
		3364	{
2997	Serge	3365	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
		3366
		3367	if (ring->rptr_save_reg) {
		3368	u32 next_rptr = ring->wptr + 2 + 3;
		3369	radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
		3370	radeon_ring_write(ring, next_rptr);
		3371	}
		3372
		3373	radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
		3374	radeon_ring_write(ring, ib->gpu_addr);
		3375	radeon_ring_write(ring, ib->length_dw);
1963	serge	3376	}
		3377
2997	Serge	3378	int r100_ib_test(struct radeon_device rdev, struct radeon_ring ring)
1963	serge	3379	{
2997	Serge	3380	struct radeon_ib ib;
1963	serge	3381	uint32_t scratch;
		3382	uint32_t tmp = 0;
		3383	unsigned i;
		3384	int r;
		3385
		3386	r = radeon_scratch_get(rdev, &scratch);
		3387	if (r) {
		3388	DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
		3389	return r;
		3390	}
		3391	WREG32(scratch, 0xCAFEDEAD);
2997	Serge	3392	r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
1963	serge	3393	if (r) {
2997	Serge	3394	DRM_ERROR("radeon: failed to get ib (%d).\n", r);
		3395	goto free_scratch;
1963	serge	3396	}
2997	Serge	3397	ib.ptr[0] = PACKET0(scratch, 0);
		3398	ib.ptr[1] = 0xDEADBEEF;
		3399	ib.ptr[2] = PACKET2(0);
		3400	ib.ptr[3] = PACKET2(0);
		3401	ib.ptr[4] = PACKET2(0);
		3402	ib.ptr[5] = PACKET2(0);
		3403	ib.ptr[6] = PACKET2(0);
		3404	ib.ptr[7] = PACKET2(0);
		3405	ib.length_dw = 8;
		3406	r = radeon_ib_schedule(rdev, &ib, NULL);
1963	serge	3407	if (r) {
2997	Serge	3408	DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
		3409	goto free_ib;
1963	serge	3410	}
2997	Serge	3411	r = radeon_fence_wait(ib.fence, false);
1963	serge	3412	if (r) {
2997	Serge	3413	DRM_ERROR("radeon: fence wait failed (%d).\n", r);
		3414	goto free_ib;
1963	serge	3415	}
		3416	for (i = 0; i < rdev->usec_timeout; i++) {
		3417	tmp = RREG32(scratch);
		3418	if (tmp == 0xDEADBEEF) {
		3419	break;
		3420	}
		3421	DRM_UDELAY(1);
		3422	}
		3423	if (i < rdev->usec_timeout) {
		3424	DRM_INFO("ib test succeeded in %u usecs\n", i);
		3425	} else {
		3426	DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
		3427	scratch, tmp);
		3428	r = -EINVAL;
		3429	}
2997	Serge	3430	free_ib:
		3431	radeon_ib_free(rdev, &ib);
		3432	free_scratch:
1963	serge	3433	radeon_scratch_free(rdev, scratch);
		3434	return r;
		3435	}
		3436
1179	serge	3437	void r100_mc_stop(struct radeon_device rdev, struct r100_mc_save save)
		3438	{
		3439	/* Shutdown CP we shouldn't need to do that but better be safe than
		3440	* sorry
		3441	*/
2997	Serge	3442	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1179	serge	3443	WREG32(R_000740_CP_CSQ_CNTL, 0);
		3444
		3445	/* Save few CRTC registers */
1221	serge	3446	save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
1179	serge	3447	save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
		3448	save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
		3449	save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
		3450	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3451	save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
		3452	save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
		3453	}
		3454
		3455	/* Disable VGA aperture access */
1221	serge	3456	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
1179	serge	3457	/* Disable cursor, overlay, crtc */
		3458	WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET \| S_000260_CUR_LOCK(1));
		3459	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL \|
		3460	S_000054_CRTC_DISPLAY_DIS(1));
		3461	WREG32(R_000050_CRTC_GEN_CNTL,
		3462	(C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) \|
		3463	S_000050_CRTC_DISP_REQ_EN_B(1));
		3464	WREG32(R_000420_OV0_SCALE_CNTL,
		3465	C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
		3466	WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
		3467	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3468	WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET \|
		3469	S_000360_CUR2_LOCK(1));
		3470	WREG32(R_0003F8_CRTC2_GEN_CNTL,
		3471	(C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) \|
		3472	S_0003F8_CRTC2_DISPLAY_DIS(1) \|
		3473	S_0003F8_CRTC2_DISP_REQ_EN_B(1));
		3474	WREG32(R_000360_CUR2_OFFSET,
		3475	C_000360_CUR2_LOCK & save->CUR2_OFFSET);
		3476	}
		3477	}
		3478
		3479	void r100_mc_resume(struct radeon_device rdev, struct r100_mc_save save)
		3480	{
		3481	/* Update base address for crtc */
1430	serge	3482	WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
1179	serge	3483	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
1430	serge	3484	WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
1179	serge	3485	}
		3486	/* Restore CRTC registers */
1221	serge	3487	WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
1179	serge	3488	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
		3489	WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
		3490	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3491	WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
		3492	}
		3493	}
		3494
1221	serge	3495	void r100_vga_render_disable(struct radeon_device *rdev)
		3496	{
		3497	u32 tmp;
		3498
		3499	tmp = RREG8(R_0003C2_GENMO_WT);
		3500	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
		3501	}
		3502
		3503	static void r100_debugfs(struct radeon_device *rdev)
		3504	{
		3505	int r;
		3506
		3507	r = r100_debugfs_mc_info_init(rdev);
		3508	if (r)
		3509	dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		3510	}
		3511
		3512	static void r100_mc_program(struct radeon_device *rdev)
		3513	{
		3514	struct r100_mc_save save;
		3515
		3516	/* Stops all mc clients */
		3517	r100_mc_stop(rdev, &save);
		3518	if (rdev->flags & RADEON_IS_AGP) {
		3519	WREG32(R_00014C_MC_AGP_LOCATION,
		3520	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		3521	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		3522	WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		3523	if (rdev->family > CHIP_RV200)
		3524	WREG32(R_00015C_AGP_BASE_2,
		3525	upper_32_bits(rdev->mc.agp_base) & 0xff);
		3526	} else {
		3527	WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		3528	WREG32(R_000170_AGP_BASE, 0);
		3529	if (rdev->family > CHIP_RV200)
		3530	WREG32(R_00015C_AGP_BASE_2, 0);
		3531	}
		3532	/* Wait for mc idle */
		3533	if (r100_mc_wait_for_idle(rdev))
		3534	dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
		3535	/* Program MC, should be a 32bits limited address space */
		3536	WREG32(R_000148_MC_FB_LOCATION,
		3537	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		3538	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		3539	r100_mc_resume(rdev, &save);
		3540	}
		3541
2997	Serge	3542	static void r100_clock_startup(struct radeon_device *rdev)
1221	serge	3543	{
		3544	u32 tmp;
		3545
		3546	if (radeon_dynclks != -1 && radeon_dynclks)
		3547	radeon_legacy_set_clock_gating(rdev, 1);
		3548	/* We need to force on some of the block */
		3549	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
		3550	tmp \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		3551	if ((rdev->family == CHIP_RV250) \|\| (rdev->family == CHIP_RV280))
		3552	tmp \|= S_00000D_FORCE_DISP1(1) \| S_00000D_FORCE_DISP2(1);
		3553	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
		3554	}
		3555
		3556	static int r100_startup(struct radeon_device *rdev)
		3557	{
		3558	int r;
		3559
1321	serge	3560	/* set common regs */
		3561	r100_set_common_regs(rdev);
		3562	/* program mc */
1221	serge	3563	r100_mc_program(rdev);
		3564	/* Resume clock */
		3565	r100_clock_startup(rdev);
		3566	/* Initialize GART (initialize after TTM so we can allocate
		3567	* memory through TTM but finalize after TTM) */
1321	serge	3568	r100_enable_bm(rdev);
1221	serge	3569	if (rdev->flags & RADEON_IS_PCI) {
		3570	r = r100_pci_gart_enable(rdev);
		3571	if (r)
		3572	return r;
		3573	}
2005	serge	3574
		3575	/* allocate wb buffer */
		3576	r = radeon_wb_init(rdev);
		3577	if (r)
		3578	return r;
		3579
3120	serge	3580	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
		3581	if (r) {
		3582	dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
		3583	return r;
		3584	}
		3585
1221	serge	3586	/* Enable IRQ */
2005	serge	3587	r100_irq_set(rdev);
1404	serge	3588	rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1221	serge	3589	/* 1M ring buffer */
1412	serge	3590	r = r100_cp_init(rdev, 1024 * 1024);
		3591	if (r) {
1963	serge	3592	dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1412	serge	3593	return r;
		3594	}
2997	Serge	3595
		3596	r = radeon_ib_pool_init(rdev);
2005	serge	3597	if (r) {
2997	Serge	3598	dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2005	serge	3599	return r;
		3600	}
3120	serge	3601
1221	serge	3602	return 0;
		3603	}
		3604
1963	serge	3605	/*
		3606	* Due to how kexec works, it can leave the hw fully initialised when it
		3607	* boots the new kernel. However doing our init sequence with the CP and
		3608	* WB stuff setup causes GPU hangs on the RN50 at least. So at startup
		3609	* do some quick sanity checks and restore sane values to avoid this
		3610	* problem.
		3611	*/
		3612	void r100_restore_sanity(struct radeon_device *rdev)
		3613	{
		3614	u32 tmp;
1221	serge	3615
1963	serge	3616	tmp = RREG32(RADEON_CP_CSQ_CNTL);
		3617	if (tmp) {
		3618	WREG32(RADEON_CP_CSQ_CNTL, 0);
		3619	}
		3620	tmp = RREG32(RADEON_CP_RB_CNTL);
		3621	if (tmp) {
		3622	WREG32(RADEON_CP_RB_CNTL, 0);
		3623	}
		3624	tmp = RREG32(RADEON_SCRATCH_UMSK);
		3625	if (tmp) {
		3626	WREG32(RADEON_SCRATCH_UMSK, 0);
		3627	}
		3628	}
1221	serge	3629
		3630	int r100_init(struct radeon_device *rdev)
		3631	{
		3632	int r;
		3633
		3634	/* Register debugfs file specific to this group of asics */
		3635	r100_debugfs(rdev);
		3636	/* Disable VGA */
		3637	r100_vga_render_disable(rdev);
		3638	/* Initialize scratch registers */
		3639	radeon_scratch_init(rdev);
		3640	/* Initialize surface registers */
		3641	radeon_surface_init(rdev);
1963	serge	3642	/* sanity check some register to avoid hangs like after kexec */
		3643	r100_restore_sanity(rdev);
1221	serge	3644	/* TODO: disable VGA need to use VGA request */
		3645	/* BIOS*/
		3646	if (!radeon_get_bios(rdev)) {
		3647	if (ASIC_IS_AVIVO(rdev))
		3648	return -EINVAL;
		3649	}
		3650	if (rdev->is_atom_bios) {
		3651	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		3652	return -EINVAL;
		3653	} else {
		3654	r = radeon_combios_init(rdev);
		3655	if (r)
		3656	return r;
		3657	}
		3658	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
1963	serge	3659	if (radeon_asic_reset(rdev)) {
1221	serge	3660	dev_warn(rdev->dev,
		3661	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		3662	RREG32(R_000E40_RBBM_STATUS),
		3663	RREG32(R_0007C0_CP_STAT));
		3664	}
		3665	/* check if cards are posted or not */
1321	serge	3666	if (radeon_boot_test_post_card(rdev) == false)
		3667	return -EINVAL;
1221	serge	3668	/* Set asic errata */
		3669	r100_errata(rdev);
		3670	/* Initialize clocks */
		3671	radeon_get_clock_info(rdev->ddev);
1430	serge	3672	/* initialize AGP */
		3673	if (rdev->flags & RADEON_IS_AGP) {
		3674	r = radeon_agp_init(rdev);
		3675	if (r) {
		3676	radeon_agp_disable(rdev);
		3677	}
		3678	}
		3679	/* initialize VRAM */
		3680	r100_mc_init(rdev);
1221	serge	3681	/* Fence driver */
2005	serge	3682	r = radeon_fence_driver_init(rdev);
		3683	if (r)
		3684	return r;
		3685	r = radeon_irq_kms_init(rdev);
		3686	if (r)
		3687	return r;
1221	serge	3688	/* Memory manager */
1321	serge	3689	r = radeon_bo_init(rdev);
1221	serge	3690	if (r)
		3691	return r;
		3692	if (rdev->flags & RADEON_IS_PCI) {
		3693	r = r100_pci_gart_init(rdev);
		3694	if (r)
		3695	return r;
		3696	}
		3697	r100_set_safe_registers(rdev);
2997	Serge	3698
1221	serge	3699	rdev->accel_working = true;
		3700	r = r100_startup(rdev);
		3701	if (r) {
		3702	/* Somethings want wront with the accel init stop accel */
		3703	dev_err(rdev->dev, "Disabling GPU acceleration\n");
		3704	if (rdev->flags & RADEON_IS_PCI)
		3705	r100_pci_gart_fini(rdev);
		3706	rdev->accel_working = false;
		3707	}
		3708	return 0;
		3709	}
2997	Serge	3710
		3711	uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
		3712	{
		3713	if (reg < rdev->rmmio_size)
		3714	return readl(((void __iomem *)rdev->rmmio) + reg);
		3715	else {
		3716	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		3717	return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
		3718	}
		3719	}
		3720
		3721	void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		3722	{
		3723	if (reg < rdev->rmmio_size)
		3724	writel(v, ((void __iomem *)rdev->rmmio) + reg);
		3725	else {
		3726	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		3727	writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
		3728	}
		3729	}
		3730
		3731	u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
		3732	{
		3733	if (reg < rdev->rio_mem_size)
		3734	return ioread32(rdev->rio_mem + reg);
		3735	else {
		3736	iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
		3737	return ioread32(rdev->rio_mem + RADEON_MM_DATA);
		3738	}
		3739	}
		3740
		3741	void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		3742	{
		3743	if (reg < rdev->rio_mem_size)
		3744	iowrite32(v, rdev->rio_mem + reg);
		3745	else {
		3746	iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
		3747	iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
		3748	}
		3749	}

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(root)/drivers/video/drm/radeon/r100.c @ 3764 – Rev 3120