WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r100.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1179	serge	28	#include
1963	serge	29	#include
1125	serge	30	#include "drmP.h"
		31	#include "drm.h"
1117	serge	32	#include "radeon_drm.h"
		33	#include "radeon_reg.h"
		34	#include "radeon.h"
1963	serge	35	#include "radeon_asic.h"
1179	serge	36	#include "r100d.h"
1221	serge	37	#include "rs100d.h"
		38	#include "rv200d.h"
		39	#include "rv250d.h"
1963	serge	40	#include "atom.h"
1117	serge	41
1221	serge	42	#include
		43
1179	serge	44	#include "r100_reg_safe.h"
		45	#include "rn50_reg_safe.h"
1221	serge	46
		47	/* Firmware Names */
		48	#define FIRMWARE_R100 "radeon/R100_cp.bin"
		49	#define FIRMWARE_R200 "radeon/R200_cp.bin"
		50	#define FIRMWARE_R300 "radeon/R300_cp.bin"
		51	#define FIRMWARE_R420 "radeon/R420_cp.bin"
		52	#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
		53	#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
		54	#define FIRMWARE_R520 "radeon/R520_cp.bin"
		55
		56	MODULE_FIRMWARE(FIRMWARE_R100);
		57	MODULE_FIRMWARE(FIRMWARE_R200);
		58	MODULE_FIRMWARE(FIRMWARE_R300);
		59	MODULE_FIRMWARE(FIRMWARE_R420);
		60	MODULE_FIRMWARE(FIRMWARE_RS690);
		61	MODULE_FIRMWARE(FIRMWARE_RS600);
		62	MODULE_FIRMWARE(FIRMWARE_R520);
		63
		64
1117	serge	65	/* This files gather functions specifics to:
		66	* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
		67	*/
		68
1963	serge	69	u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
		70	{
		71	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
		72	u32 tmp = ((u32)crtc_base) \| RADEON_CRTC_OFFSET__OFFSET_LOCK;
		73
		74	/* Lock the graphics update lock */
		75	/* update the scanout addresses */
		76	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
		77
		78	/* Wait for update_pending to go high. */
		79	while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET));
		80	DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
		81
		82	/* Unlock the lock, so double-buffering can take place inside vblank */
		83	tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
		84	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
		85
		86	/* Return current update_pending status: */
		87	return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
		88	}
		89	bool r100_gui_idle(struct radeon_device *rdev)
		90	{
		91	if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
		92	return false;
		93	else
		94	return true;
		95	}
		96
1321	serge	97	/* hpd for digital panel detect/disconnect */
		98	bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
		99	{
		100	bool connected = false;
		101
		102	switch (hpd) {
		103	case RADEON_HPD_1:
		104	if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
		105	connected = true;
		106	break;
		107	case RADEON_HPD_2:
		108	if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
		109	connected = true;
		110	break;
		111	default:
		112	break;
		113	}
		114	return connected;
		115	}
		116
		117	void r100_hpd_set_polarity(struct radeon_device *rdev,
		118	enum radeon_hpd_id hpd)
		119	{
		120	u32 tmp;
		121	bool connected = r100_hpd_sense(rdev, hpd);
		122
		123	switch (hpd) {
		124	case RADEON_HPD_1:
		125	tmp = RREG32(RADEON_FP_GEN_CNTL);
		126	if (connected)
		127	tmp &= ~RADEON_FP_DETECT_INT_POL;
		128	else
		129	tmp \|= RADEON_FP_DETECT_INT_POL;
		130	WREG32(RADEON_FP_GEN_CNTL, tmp);
		131	break;
		132	case RADEON_HPD_2:
		133	tmp = RREG32(RADEON_FP2_GEN_CNTL);
		134	if (connected)
		135	tmp &= ~RADEON_FP2_DETECT_INT_POL;
		136	else
		137	tmp \|= RADEON_FP2_DETECT_INT_POL;
		138	WREG32(RADEON_FP2_GEN_CNTL, tmp);
		139	break;
		140	default:
		141	break;
		142	}
		143	}
		144
		145	void r100_hpd_init(struct radeon_device *rdev)
		146	{
		147	struct drm_device *dev = rdev->ddev;
		148	struct drm_connector *connector;
		149
		150	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		151	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		152	switch (radeon_connector->hpd.hpd) {
		153	case RADEON_HPD_1:
1403	serge	154	// rdev->irq.hpd[0] = true;
1321	serge	155	break;
		156	case RADEON_HPD_2:
1403	serge	157	// rdev->irq.hpd[1] = true;
1321	serge	158	break;
		159	default:
		160	break;
		161	}
		162	}
1403	serge	163	// if (rdev->irq.installed)
		164	// r100_irq_set(rdev);
1321	serge	165	}
		166
		167	void r100_hpd_fini(struct radeon_device *rdev)
		168	{
		169	struct drm_device *dev = rdev->ddev;
		170	struct drm_connector *connector;
		171
		172	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		173	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		174	switch (radeon_connector->hpd.hpd) {
		175	case RADEON_HPD_1:
1403	serge	176	// rdev->irq.hpd[0] = false;
1321	serge	177	break;
		178	case RADEON_HPD_2:
1403	serge	179	// rdev->irq.hpd[1] = false;
1321	serge	180	break;
		181	default:
		182	break;
		183	}
		184	}
		185	}
		186
1117	serge	187	/*
		188	* PCI GART
		189	*/
		190	void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
		191	{
		192	/* TODO: can we do somethings here ? */
		193	/* It seems hw only cache one entry so we should discard this
		194	* entry otherwise if first GPU GART read hit this entry it
		195	* could end up in wrong address. */
		196	}
		197
1179	serge	198	int r100_pci_gart_init(struct radeon_device *rdev)
1117	serge	199	{
		200	int r;
		201
1179	serge	202	if (rdev->gart.table.ram.ptr) {
1963	serge	203	WARN(1, "R100 PCI GART already initialized\n");
1179	serge	204	return 0;
		205	}
1117	serge	206	/* Initialize common gart structure */
		207	r = radeon_gart_init(rdev);
1179	serge	208	if (r)
1117	serge	209	return r;
1268	serge	210	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
1179	serge	211	rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
		212	rdev->asic->gart_set_page = &r100_pci_gart_set_page;
		213	return radeon_gart_table_ram_alloc(rdev);
		214	}
		215
1321	serge	216	/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
		217	void r100_enable_bm(struct radeon_device *rdev)
		218	{
		219	uint32_t tmp;
		220	/* Enable bus mastering */
		221	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
		222	WREG32(RADEON_BUS_CNTL, tmp);
		223	}
		224
1179	serge	225	int r100_pci_gart_enable(struct radeon_device *rdev)
		226	{
		227	uint32_t tmp;
		228
1430	serge	229	radeon_gart_restore(rdev);
1117	serge	230	/* discard memory request outside of configured range */
		231	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		232	WREG32(RADEON_AIC_CNTL, tmp);
		233	/* set address range for PCI address translate */
1430	serge	234	WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
		235	WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
1117	serge	236	/* set PCI GART page-table base address */
		237	WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
		238	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_PCIGART_TRANSLATE_EN;
		239	WREG32(RADEON_AIC_CNTL, tmp);
		240	r100_pci_gart_tlb_flush(rdev);
		241	rdev->gart.ready = true;
		242	return 0;
		243	}
		244
		245	void r100_pci_gart_disable(struct radeon_device *rdev)
		246	{
		247	uint32_t tmp;
		248
		249	/* discard memory request outside of configured range */
		250	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		251	WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
		252	WREG32(RADEON_AIC_LO_ADDR, 0);
		253	WREG32(RADEON_AIC_HI_ADDR, 0);
		254	}
		255
		256	int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
		257	{
		258	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
		259	return -EINVAL;
		260	}
1179	serge	261	rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
1117	serge	262	return 0;
		263	}
		264
1179	serge	265	void r100_pci_gart_fini(struct radeon_device *rdev)
1117	serge	266	{
1963	serge	267	radeon_gart_fini(rdev);
1117	serge	268	r100_pci_gart_disable(rdev);
1179	serge	269	radeon_gart_table_ram_free(rdev);
1117	serge	270	}
		271
		272
1221	serge	273	void r100_irq_disable(struct radeon_device *rdev)
1117	serge	274	{
1221	serge	275	u32 tmp;
1117	serge	276
1221	serge	277	WREG32(R_000040_GEN_INT_CNTL, 0);
		278	/* Wait and acknowledge irq */
		279	mdelay(1);
		280	tmp = RREG32(R_000044_GEN_INT_STATUS);
		281	WREG32(R_000044_GEN_INT_STATUS, tmp);
1117	serge	282	}
		283
1963	serge	284	#if 0
1221	serge	285	static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
1117	serge	286	{
1221	serge	287	uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
1321	serge	288	uint32_t irq_mask = RADEON_SW_INT_TEST \|
		289	RADEON_CRTC_VBLANK_STAT \| RADEON_CRTC2_VBLANK_STAT \|
		290	RADEON_FP_DETECT_STAT \| RADEON_FP2_DETECT_STAT;
1117	serge	291
1963	serge	292	/* the interrupt works, but the status bit is permanently asserted */
		293	if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
		294	if (!rdev->irq.gui_idle_acked)
		295	irq_mask \|= RADEON_GUI_IDLE_STAT;
		296	}
		297
1221	serge	298	if (irqs) {
		299	WREG32(RADEON_GEN_INT_STATUS, irqs);
1129	serge	300	}
1221	serge	301	return irqs & irq_mask;
1117	serge	302	}
		303
1963	serge	304	#endif
1117	serge	305
1963	serge	306
1403	serge	307	u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
		308	{
		309	if (crtc == 0)
		310	return RREG32(RADEON_CRTC_CRNT_FRAME);
		311	else
		312	return RREG32(RADEON_CRTC2_CRNT_FRAME);
		313	}
1117	serge	314
1404	serge	315	/* Who ever call radeon_fence_emit should call ring_lock and ask
		316	* for enough space (today caller are ib schedule and buffer move) */
1117	serge	317	void r100_fence_ring_emit(struct radeon_device *rdev,
		318	struct radeon_fence *fence)
		319	{
1404	serge	320	/* We have to make sure that caches are flushed before
		321	* CPU might read something from VRAM. */
		322	radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
		323	radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
		324	radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
		325	radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
1117	serge	326	/* Wait until IDLE & CLEAN */
1430	serge	327	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		328	radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN \| RADEON_WAIT_3D_IDLECLEAN);
1403	serge	329	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		330	radeon_ring_write(rdev, rdev->config.r100.hdp_cntl \|
		331	RADEON_HDP_READ_BUFFER_INVALIDATE);
		332	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		333	radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
1117	serge	334	/* Emit fence sequence & fire IRQ */
		335	radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
		336	radeon_ring_write(rdev, fence->seq);
		337	radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
		338	radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
		339	}
		340
1128	serge	341	#if 0
1117	serge	342
		343	int r100_copy_blit(struct radeon_device *rdev,
		344	uint64_t src_offset,
		345	uint64_t dst_offset,
		346	unsigned num_pages,
		347	struct radeon_fence *fence)
		348	{
		349	uint32_t cur_pages;
		350	uint32_t stride_bytes = PAGE_SIZE;
		351	uint32_t pitch;
		352	uint32_t stride_pixels;
		353	unsigned ndw;
		354	int num_loops;
		355	int r = 0;
		356
		357	/* radeon limited to 16k stride */
		358	stride_bytes &= 0x3fff;
		359	/* radeon pitch is /64 */
		360	pitch = stride_bytes / 64;
		361	stride_pixels = stride_bytes / 4;
		362	num_loops = DIV_ROUND_UP(num_pages, 8191);
		363
		364	/* Ask for enough room for blit + flush + fence */
		365	ndw = 64 + (10 * num_loops);
		366	r = radeon_ring_lock(rdev, ndw);
		367	if (r) {
		368	DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
		369	return -EINVAL;
		370	}
		371	while (num_pages > 0) {
		372	cur_pages = num_pages;
		373	if (cur_pages > 8191) {
		374	cur_pages = 8191;
		375	}
		376	num_pages -= cur_pages;
		377
		378	/* pages are in Y direction - height
		379	page width in X direction - width */
		380	radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
		381	radeon_ring_write(rdev,
		382	RADEON_GMC_SRC_PITCH_OFFSET_CNTL \|
		383	RADEON_GMC_DST_PITCH_OFFSET_CNTL \|
		384	RADEON_GMC_SRC_CLIPPING \|
		385	RADEON_GMC_DST_CLIPPING \|
		386	RADEON_GMC_BRUSH_NONE \|
		387	(RADEON_COLOR_FORMAT_ARGB8888 << 8) \|
		388	RADEON_GMC_SRC_DATATYPE_COLOR \|
		389	RADEON_ROP3_S \|
		390	RADEON_DP_SRC_SOURCE_MEMORY \|
		391	RADEON_GMC_CLR_CMP_CNTL_DIS \|
		392	RADEON_GMC_WR_MSK_DIS);
		393	radeon_ring_write(rdev, (pitch << 22) \| (src_offset >> 10));
		394	radeon_ring_write(rdev, (pitch << 22) \| (dst_offset >> 10));
		395	radeon_ring_write(rdev, (0x1fff) \| (0x1fff << 16));
		396	radeon_ring_write(rdev, 0);
		397	radeon_ring_write(rdev, (0x1fff) \| (0x1fff << 16));
		398	radeon_ring_write(rdev, num_pages);
		399	radeon_ring_write(rdev, num_pages);
		400	radeon_ring_write(rdev, cur_pages \| (stride_pixels << 16));
		401	}
		402	radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
		403	radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
		404	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		405	radeon_ring_write(rdev,
		406	RADEON_WAIT_2D_IDLECLEAN \|
		407	RADEON_WAIT_HOST_IDLECLEAN \|
		408	RADEON_WAIT_DMA_GUI_IDLE);
		409	if (fence) {
		410	r = radeon_fence_emit(rdev, fence);
		411	}
		412	radeon_ring_unlock_commit(rdev);
		413	return r;
		414	}
		415
1128	serge	416	#endif
1117	serge	417
1221	serge	418
1179	serge	419	static int r100_cp_wait_for_idle(struct radeon_device *rdev)
		420	{
		421	unsigned i;
		422	u32 tmp;
		423
		424	for (i = 0; i < rdev->usec_timeout; i++) {
		425	tmp = RREG32(R_000E40_RBBM_STATUS);
		426	if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
		427	return 0;
		428	}
		429	udelay(1);
		430	}
		431	return -1;
		432	}
		433
1117	serge	434	void r100_ring_start(struct radeon_device *rdev)
		435	{
		436	int r;
		437
		438	r = radeon_ring_lock(rdev, 2);
		439	if (r) {
		440	return;
		441	}
		442	radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
		443	radeon_ring_write(rdev,
		444	RADEON_ISYNC_ANY2D_IDLE3D \|
		445	RADEON_ISYNC_ANY3D_IDLE2D \|
		446	RADEON_ISYNC_WAIT_IDLEGUI \|
		447	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
		448	radeon_ring_unlock_commit(rdev);
		449	}
		450
1221	serge	451
		452	/* Load the microcode for the CP */
		453	static int r100_cp_init_microcode(struct radeon_device *rdev)
1117	serge	454	{
1221	serge	455	struct platform_device *pdev;
		456	const char *fw_name = NULL;
		457	int err;
1117	serge	458
1963	serge	459	DRM_DEBUG_KMS("\n");
1117	serge	460
1412	serge	461	pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
		462	err = IS_ERR(pdev);
		463	if (err) {
		464	printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
		465	return -EINVAL;
		466	}
1117	serge	467	if ((rdev->family == CHIP_R100) \|\| (rdev->family == CHIP_RV100) \|\|
		468	(rdev->family == CHIP_RV200) \|\| (rdev->family == CHIP_RS100) \|\|
		469	(rdev->family == CHIP_RS200)) {
		470	DRM_INFO("Loading R100 Microcode\n");
1221	serge	471	fw_name = FIRMWARE_R100;
1117	serge	472	} else if ((rdev->family == CHIP_R200) \|\|
		473	(rdev->family == CHIP_RV250) \|\|
		474	(rdev->family == CHIP_RV280) \|\|
		475	(rdev->family == CHIP_RS300)) {
		476	DRM_INFO("Loading R200 Microcode\n");
1221	serge	477	fw_name = FIRMWARE_R200;
1117	serge	478	} else if ((rdev->family == CHIP_R300) \|\|
		479	(rdev->family == CHIP_R350) \|\|
		480	(rdev->family == CHIP_RV350) \|\|
		481	(rdev->family == CHIP_RV380) \|\|
		482	(rdev->family == CHIP_RS400) \|\|
		483	(rdev->family == CHIP_RS480)) {
		484	DRM_INFO("Loading R300 Microcode\n");
1221	serge	485	fw_name = FIRMWARE_R300;
1117	serge	486	} else if ((rdev->family == CHIP_R420) \|\|
		487	(rdev->family == CHIP_R423) \|\|
		488	(rdev->family == CHIP_RV410)) {
		489	DRM_INFO("Loading R400 Microcode\n");
1221	serge	490	fw_name = FIRMWARE_R420;
1117	serge	491	} else if ((rdev->family == CHIP_RS690) \|\|
		492	(rdev->family == CHIP_RS740)) {
		493	DRM_INFO("Loading RS690/RS740 Microcode\n");
1221	serge	494	fw_name = FIRMWARE_RS690;
1117	serge	495	} else if (rdev->family == CHIP_RS600) {
		496	DRM_INFO("Loading RS600 Microcode\n");
1221	serge	497	fw_name = FIRMWARE_RS600;
1117	serge	498	} else if ((rdev->family == CHIP_RV515) \|\|
		499	(rdev->family == CHIP_R520) \|\|
		500	(rdev->family == CHIP_RV530) \|\|
		501	(rdev->family == CHIP_R580) \|\|
		502	(rdev->family == CHIP_RV560) \|\|
		503	(rdev->family == CHIP_RV570)) {
		504	DRM_INFO("Loading R500 Microcode\n");
1221	serge	505	fw_name = FIRMWARE_R520;
1117	serge	506	}
1221	serge	507
1412	serge	508	err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
		509	platform_device_unregister(pdev);
1221	serge	510	if (err) {
		511	printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
		512	fw_name);
		513	} else if (rdev->me_fw->size % 8) {
		514	printk(KERN_ERR
		515	"radeon_cp: Bogus length %zu in firmware \"%s\"\n",
		516	rdev->me_fw->size, fw_name);
		517	err = -EINVAL;
		518	release_firmware(rdev->me_fw);
		519	rdev->me_fw = NULL;
1117	serge	520	}
1221	serge	521	return err;
1117	serge	522	}
		523
1221	serge	524	static void r100_cp_load_microcode(struct radeon_device *rdev)
		525	{
		526	const __be32 *fw_data;
		527	int i, size;
		528
		529	if (r100_gui_wait_for_idle(rdev)) {
		530	printk(KERN_WARNING "Failed to wait GUI idle while "
		531	"programming pipes. Bad things might happen.\n");
		532	}
		533
		534	if (rdev->me_fw) {
		535	size = rdev->me_fw->size / 4;
		536	fw_data = (const __be32 *)&rdev->me_fw->data[0];
		537	WREG32(RADEON_CP_ME_RAM_ADDR, 0);
		538	for (i = 0; i < size; i += 2) {
		539	WREG32(RADEON_CP_ME_RAM_DATAH,
		540	be32_to_cpup(&fw_data[i]));
		541	WREG32(RADEON_CP_ME_RAM_DATAL,
		542	be32_to_cpup(&fw_data[i + 1]));
		543	}
		544	}
		545	}
		546
1117	serge	547	int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
		548	{
		549	unsigned rb_bufsz;
		550	unsigned rb_blksz;
		551	unsigned max_fetch;
		552	unsigned pre_write_timer;
		553	unsigned pre_write_limit;
		554	unsigned indirect2_start;
		555	unsigned indirect1_start;
		556	uint32_t tmp;
		557	int r;
		558
1129	serge	559	if (r100_debugfs_cp_init(rdev)) {
		560	DRM_ERROR("Failed to register debugfs file for CP !\n");
		561	}
1179	serge	562	if (!rdev->me_fw) {
		563	r = r100_cp_init_microcode(rdev);
		564	if (r) {
		565	DRM_ERROR("Failed to load firmware!\n");
		566	return r;
		567	}
		568	}
		569
1117	serge	570	/* Align ring size */
		571	rb_bufsz = drm_order(ring_size / 8);
		572	ring_size = (1 << (rb_bufsz + 1)) * 4;
		573	r100_cp_load_microcode(rdev);
		574	r = radeon_ring_init(rdev, ring_size);
		575	if (r) {
		576	return r;
		577	}
		578	/* Each time the cp read 1024 bytes (16 dword/quadword) update
		579	* the rptr copy in system ram */
		580	rb_blksz = 9;
		581	/* cp will read 128bytes at a time (4 dwords) */
		582	max_fetch = 1;
		583	rdev->cp.align_mask = 16 - 1;
		584	/* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
		585	pre_write_timer = 64;
		586	/* Force CP_RB_WPTR write if written more than one time before the
		587	* delay expire
		588	*/
		589	pre_write_limit = 0;
		590	/* Setup the cp cache like this (cache size is 96 dwords) :
		591	* RING 0 to 15
		592	* INDIRECT1 16 to 79
		593	* INDIRECT2 80 to 95
		594	* So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		595	* indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
		596	* indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		597	* Idea being that most of the gpu cmd will be through indirect1 buffer
		598	* so it gets the bigger cache.
		599	*/
		600	indirect2_start = 80;
		601	indirect1_start = 16;
		602	/* cp setup */
		603	WREG32(0x718, pre_write_timer \| (pre_write_limit << 28));
1268	serge	604	tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) \|
1117	serge	605	REG_SET(RADEON_RB_BLKSZ, rb_blksz) \|
1963	serge	606	REG_SET(RADEON_MAX_FETCH, max_fetch));
1268	serge	607	#ifdef __BIG_ENDIAN
		608	tmp \|= RADEON_BUF_SWAP_32BIT;
		609	#endif
1963	serge	610	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_NO_UPDATE);
1268	serge	611
1117	serge	612	/* Set ring address */
		613	DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
		614	WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
		615	/* Force read & write ptr to 0 */
1963	serge	616	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA \| RADEON_RB_NO_UPDATE);
1117	serge	617	WREG32(RADEON_CP_RB_RPTR_WR, 0);
		618	WREG32(RADEON_CP_RB_WPTR, 0);
1963	serge	619
		620	/* set the wb address whether it's enabled or not */
		621	WREG32(R_00070C_CP_RB_RPTR_ADDR,
		622	S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
		623	WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
		624
		625	if (rdev->wb.enabled)
		626	WREG32(R_000770_SCRATCH_UMSK, 0xff);
		627	else {
		628	tmp \|= RADEON_RB_NO_UPDATE;
		629	WREG32(R_000770_SCRATCH_UMSK, 0);
		630	}
		631
1117	serge	632	WREG32(RADEON_CP_RB_CNTL, tmp);
		633	udelay(10);
		634	rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
		635	rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
1963	serge	636	/* protect against crazy HW on resume */
		637	rdev->cp.wptr &= rdev->cp.ptr_mask;
1117	serge	638	/* Set cp mode to bus mastering & enable cp*/
		639	WREG32(RADEON_CP_CSQ_MODE,
		640	REG_SET(RADEON_INDIRECT2_START, indirect2_start) \|
		641	REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1963	serge	642	WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
		643	WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1117	serge	644	WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
		645	radeon_ring_start(rdev);
		646	r = radeon_ring_test(rdev);
		647	if (r) {
		648	DRM_ERROR("radeon: cp isn't working (%d).\n", r);
		649	return r;
		650	}
		651	rdev->cp.ready = true;
1963	serge	652	// radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1117	serge	653	return 0;
		654	}
		655
		656	void r100_cp_fini(struct radeon_device *rdev)
		657	{
1179	serge	658	if (r100_cp_wait_for_idle(rdev)) {
		659	DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
		660	}
1117	serge	661	/* Disable ring */
1179	serge	662	r100_cp_disable(rdev);
1117	serge	663	radeon_ring_fini(rdev);
		664	DRM_INFO("radeon: cp finalized\n");
		665	}
		666
		667	void r100_cp_disable(struct radeon_device *rdev)
		668	{
		669	/* Disable ring */
1963	serge	670	// radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1117	serge	671	rdev->cp.ready = false;
		672	WREG32(RADEON_CP_CSQ_MODE, 0);
		673	WREG32(RADEON_CP_CSQ_CNTL, 0);
1963	serge	674	WREG32(R_000770_SCRATCH_UMSK, 0);
1117	serge	675	if (r100_gui_wait_for_idle(rdev)) {
		676	printk(KERN_WARNING "Failed to wait GUI idle while "
		677	"programming pipes. Bad things might happen.\n");
		678	}
		679	}
		680
1179	serge	681	void r100_cp_commit(struct radeon_device *rdev)
		682	{
		683	WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
		684	(void)RREG32(RADEON_CP_RB_WPTR);
		685	}
		686
		687
1117	serge	688	#if 0
		689	/*
		690	* CS functions
		691	*/
		692	int r100_cs_parse_packet0(struct radeon_cs_parser *p,
		693	struct radeon_cs_packet *pkt,
		694	const unsigned *auth, unsigned n,
		695	radeon_packet0_check_t check)
		696	{
		697	unsigned reg;
		698	unsigned i, j, m;
		699	unsigned idx;
		700	int r;
		701
		702	idx = pkt->idx + 1;
		703	reg = pkt->reg;
		704	/* Check that register fall into register range
		705	* determined by the number of entry (n) in the
		706	* safe register bitmap.
		707	*/
		708	if (pkt->one_reg_wr) {
		709	if ((reg >> 7) > n) {
		710	return -EINVAL;
		711	}
		712	} else {
		713	if (((reg + (pkt->count << 2)) >> 7) > n) {
		714	return -EINVAL;
		715	}
		716	}
		717	for (i = 0; i <= pkt->count; i++, idx++) {
		718	j = (reg >> 7);
		719	m = 1 << ((reg >> 2) & 31);
		720	if (auth[j] & m) {
		721	r = check(p, pkt, idx, reg);
		722	if (r) {
		723	return r;
		724	}
		725	}
		726	if (pkt->one_reg_wr) {
		727	if (!(auth[j] & m)) {
		728	break;
		729	}
		730	} else {
		731	reg += 4;
		732	}
		733	}
		734	return 0;
		735	}
		736
		737	void r100_cs_dump_packet(struct radeon_cs_parser *p,
		738	struct radeon_cs_packet *pkt)
		739	{
		740	volatile uint32_t *ib;
		741	unsigned i;
		742	unsigned idx;
		743
		744	ib = p->ib->ptr;
		745	idx = pkt->idx;
		746	for (i = 0; i <= (pkt->count + 1); i++, idx++) {
		747	DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
		748	}
		749	}
		750
		751	/**
		752	* r100_cs_packet_parse() - parse cp packet and point ib index to next packet
		753	* @parser: parser structure holding parsing context.
		754	* @pkt: where to store packet informations
		755	*
		756	* Assume that chunk_ib_index is properly set. Will return -EINVAL
		757	* if packet is bigger than remaining ib size. or if packets is unknown.
		758	**/
		759	int r100_cs_packet_parse(struct radeon_cs_parser *p,
		760	struct radeon_cs_packet *pkt,
		761	unsigned idx)
		762	{
		763	struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1179	serge	764	uint32_t header;
1117	serge	765
		766	if (idx >= ib_chunk->length_dw) {
		767	DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
		768	idx, ib_chunk->length_dw);
		769	return -EINVAL;
		770	}
1221	serge	771	header = radeon_get_ib_value(p, idx);
1117	serge	772	pkt->idx = idx;
		773	pkt->type = CP_PACKET_GET_TYPE(header);
		774	pkt->count = CP_PACKET_GET_COUNT(header);
		775	switch (pkt->type) {
		776	case PACKET_TYPE0:
		777	pkt->reg = CP_PACKET0_GET_REG(header);
		778	pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
		779	break;
		780	case PACKET_TYPE3:
		781	pkt->opcode = CP_PACKET3_GET_OPCODE(header);
		782	break;
		783	case PACKET_TYPE2:
		784	pkt->count = -1;
		785	break;
		786	default:
		787	DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
		788	return -EINVAL;
		789	}
		790	if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
		791	DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
		792	pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
		793	return -EINVAL;
		794	}
		795	return 0;
		796	}
		797
		798	/**
1179	serge	799	* r100_cs_packet_next_vline() - parse userspace VLINE packet
		800	* @parser: parser structure holding parsing context.
		801	*
		802	* Userspace sends a special sequence for VLINE waits.
		803	* PACKET0 - VLINE_START_END + value
		804	* PACKET0 - WAIT_UNTIL +_value
		805	* RELOC (P3) - crtc_id in reloc.
		806	*
		807	* This function parses this and relocates the VLINE START END
		808	* and WAIT UNTIL packets to the correct crtc.
		809	* It also detects a switched off crtc and nulls out the
		810	* wait in that case.
		811	*/
		812	int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
		813	{
		814	struct drm_mode_object *obj;
		815	struct drm_crtc *crtc;
		816	struct radeon_crtc *radeon_crtc;
		817	struct radeon_cs_packet p3reloc, waitreloc;
		818	int crtc_id;
		819	int r;
		820	uint32_t header, h_idx, reg;
1221	serge	821	volatile uint32_t *ib;
1179	serge	822
1221	serge	823	ib = p->ib->ptr;
1179	serge	824
		825	/* parse the wait until */
		826	r = r100_cs_packet_parse(p, &waitreloc, p->idx);
		827	if (r)
		828	return r;
		829
		830	/* check its a wait until and only 1 count */
		831	if (waitreloc.reg != RADEON_WAIT_UNTIL \|\|
		832	waitreloc.count != 0) {
		833	DRM_ERROR("vline wait had illegal wait until segment\n");
1963	serge	834	return -EINVAL;
1179	serge	835	}
		836
1221	serge	837	if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1179	serge	838	DRM_ERROR("vline wait had illegal wait until\n");
1963	serge	839	return -EINVAL;
1179	serge	840	}
		841
		842	/* jump over the NOP */
1221	serge	843	r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1179	serge	844	if (r)
		845	return r;
		846
		847	h_idx = p->idx - 2;
1221	serge	848	p->idx += waitreloc.count + 2;
		849	p->idx += p3reloc.count + 2;
1179	serge	850
1221	serge	851	header = radeon_get_ib_value(p, h_idx);
		852	crtc_id = radeon_get_ib_value(p, h_idx + 5);
		853	reg = CP_PACKET0_GET_REG(header);
1179	serge	854	obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
		855	if (!obj) {
		856	DRM_ERROR("cannot find crtc %d\n", crtc_id);
1963	serge	857	return -EINVAL;
1179	serge	858	}
		859	crtc = obj_to_crtc(obj);
		860	radeon_crtc = to_radeon_crtc(crtc);
		861	crtc_id = radeon_crtc->crtc_id;
		862
		863	if (!crtc->enabled) {
		864	/* if the CRTC isn't enabled - we need to nop out the wait until */
1221	serge	865	ib[h_idx + 2] = PACKET2(0);
		866	ib[h_idx + 3] = PACKET2(0);
1179	serge	867	} else if (crtc_id == 1) {
		868	switch (reg) {
		869	case AVIVO_D1MODE_VLINE_START_END:
1221	serge	870	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	871	header \|= AVIVO_D2MODE_VLINE_START_END >> 2;
		872	break;
		873	case RADEON_CRTC_GUI_TRIG_VLINE:
1221	serge	874	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	875	header \|= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
		876	break;
		877	default:
		878	DRM_ERROR("unknown crtc reloc\n");
1963	serge	879	return -EINVAL;
1179	serge	880	}
1221	serge	881	ib[h_idx] = header;
		882	ib[h_idx + 3] \|= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1179	serge	883	}
1963	serge	884
		885	return 0;
1179	serge	886	}
		887
		888	/**
1117	serge	889	* r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
		890	* @parser: parser structure holding parsing context.
		891	* @data: pointer to relocation data
		892	* @offset_start: starting offset
		893	* @offset_mask: offset mask (to align start offset on)
		894	* @reloc: reloc informations
		895	*
		896	* Check next packet is relocation packet3, do bo validation and compute
		897	* GPU offset using the provided start.
		898	**/
		899	int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
		900	struct radeon_cs_reloc **cs_reloc)
		901	{
		902	struct radeon_cs_chunk *relocs_chunk;
		903	struct radeon_cs_packet p3reloc;
		904	unsigned idx;
		905	int r;
		906
		907	if (p->chunk_relocs_idx == -1) {
		908	DRM_ERROR("No relocation chunk !\n");
		909	return -EINVAL;
		910	}
		911	*cs_reloc = NULL;
		912	relocs_chunk = &p->chunks[p->chunk_relocs_idx];
		913	r = r100_cs_packet_parse(p, &p3reloc, p->idx);
		914	if (r) {
		915	return r;
		916	}
		917	p->idx += p3reloc.count + 2;
		918	if (p3reloc.type != PACKET_TYPE3 \|\| p3reloc.opcode != PACKET3_NOP) {
		919	DRM_ERROR("No packet3 for relocation for packet at %d.\n",
		920	p3reloc.idx);
		921	r100_cs_dump_packet(p, &p3reloc);
		922	return -EINVAL;
		923	}
1221	serge	924	idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1117	serge	925	if (idx >= relocs_chunk->length_dw) {
		926	DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
		927	idx, relocs_chunk->length_dw);
		928	r100_cs_dump_packet(p, &p3reloc);
		929	return -EINVAL;
		930	}
		931	/* FIXME: we assume reloc size is 4 dwords */
		932	*cs_reloc = p->relocs_ptr[(idx / 4)];
		933	return 0;
		934	}
		935
1179	serge	936	static int r100_get_vtx_size(uint32_t vtx_fmt)
		937	{
		938	int vtx_size;
		939	vtx_size = 2;
		940	/* ordered according to bits in spec */
		941	if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
		942	vtx_size++;
		943	if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
		944	vtx_size += 3;
		945	if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
		946	vtx_size++;
		947	if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
		948	vtx_size++;
		949	if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
		950	vtx_size += 3;
		951	if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
		952	vtx_size++;
		953	if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
		954	vtx_size++;
		955	if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
		956	vtx_size += 2;
		957	if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
		958	vtx_size += 2;
		959	if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
		960	vtx_size++;
		961	if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
		962	vtx_size += 2;
		963	if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
		964	vtx_size++;
		965	if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
		966	vtx_size += 2;
		967	if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
		968	vtx_size++;
		969	if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
		970	vtx_size++;
		971	/* blend weight */
		972	if (vtx_fmt & (0x7 << 15))
		973	vtx_size += (vtx_fmt >> 15) & 0x7;
		974	if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
		975	vtx_size += 3;
		976	if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
		977	vtx_size += 2;
		978	if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
		979	vtx_size++;
		980	if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
		981	vtx_size++;
		982	if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
		983	vtx_size++;
		984	if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
		985	vtx_size++;
		986	return vtx_size;
		987	}
		988
1117	serge	989	static int r100_packet0_check(struct radeon_cs_parser *p,
1179	serge	990	struct radeon_cs_packet *pkt,
		991	unsigned idx, unsigned reg)
1117	serge	992	{
		993	struct radeon_cs_reloc *reloc;
1179	serge	994	struct r100_cs_track *track;
1117	serge	995	volatile uint32_t *ib;
		996	uint32_t tmp;
		997	int r;
1179	serge	998	int i, face;
		999	u32 tile_flags = 0;
1221	serge	1000	u32 idx_value;
1117	serge	1001
		1002	ib = p->ib->ptr;
1179	serge	1003	track = (struct r100_cs_track *)p->track;
		1004
1221	serge	1005	idx_value = radeon_get_ib_value(p, idx);
		1006
1117	serge	1007	switch (reg) {
1179	serge	1008	case RADEON_CRTC_GUI_TRIG_VLINE:
		1009	r = r100_cs_packet_parse_vline(p);
		1010	if (r) {
		1011	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1012	idx, reg);
		1013	r100_cs_dump_packet(p, pkt);
		1014	return r;
		1015	}
		1016	break;
1117	serge	1017	/* FIXME: only allow PACKET3 blit? easier to check for out of
		1018	* range access */
		1019	case RADEON_DST_PITCH_OFFSET:
		1020	case RADEON_SRC_PITCH_OFFSET:
1179	serge	1021	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		1022	if (r)
		1023	return r;
		1024	break;
		1025	case RADEON_RB3D_DEPTHOFFSET:
1117	serge	1026	r = r100_cs_packet_next_reloc(p, &reloc);
		1027	if (r) {
		1028	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1029	idx, reg);
		1030	r100_cs_dump_packet(p, pkt);
		1031	return r;
		1032	}
1179	serge	1033	track->zb.robj = reloc->robj;
1221	serge	1034	track->zb.offset = idx_value;
1963	serge	1035	track->zb_dirty = true;
1221	serge	1036	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1117	serge	1037	break;
		1038	case RADEON_RB3D_COLOROFFSET:
1179	serge	1039	r = r100_cs_packet_next_reloc(p, &reloc);
		1040	if (r) {
		1041	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1042	idx, reg);
		1043	r100_cs_dump_packet(p, pkt);
		1044	return r;
		1045	}
		1046	track->cb[0].robj = reloc->robj;
1221	serge	1047	track->cb[0].offset = idx_value;
1963	serge	1048	track->cb_dirty = true;
1221	serge	1049	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1050	break;
1117	serge	1051	case RADEON_PP_TXOFFSET_0:
		1052	case RADEON_PP_TXOFFSET_1:
		1053	case RADEON_PP_TXOFFSET_2:
1179	serge	1054	i = (reg - RADEON_PP_TXOFFSET_0) / 24;
		1055	r = r100_cs_packet_next_reloc(p, &reloc);
		1056	if (r) {
		1057	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1058	idx, reg);
		1059	r100_cs_dump_packet(p, pkt);
		1060	return r;
		1061	}
1221	serge	1062	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1063	track->textures[i].robj = reloc->robj;
1963	serge	1064	track->tex_dirty = true;
1179	serge	1065	break;
		1066	case RADEON_PP_CUBIC_OFFSET_T0_0:
		1067	case RADEON_PP_CUBIC_OFFSET_T0_1:
		1068	case RADEON_PP_CUBIC_OFFSET_T0_2:
		1069	case RADEON_PP_CUBIC_OFFSET_T0_3:
		1070	case RADEON_PP_CUBIC_OFFSET_T0_4:
		1071	i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
		1072	r = r100_cs_packet_next_reloc(p, &reloc);
		1073	if (r) {
		1074	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1075	idx, reg);
		1076	r100_cs_dump_packet(p, pkt);
		1077	return r;
		1078	}
1221	serge	1079	track->textures[0].cube_info[i].offset = idx_value;
		1080	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1081	track->textures[0].cube_info[i].robj = reloc->robj;
1963	serge	1082	track->tex_dirty = true;
1179	serge	1083	break;
		1084	case RADEON_PP_CUBIC_OFFSET_T1_0:
		1085	case RADEON_PP_CUBIC_OFFSET_T1_1:
		1086	case RADEON_PP_CUBIC_OFFSET_T1_2:
		1087	case RADEON_PP_CUBIC_OFFSET_T1_3:
		1088	case RADEON_PP_CUBIC_OFFSET_T1_4:
		1089	i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
		1090	r = r100_cs_packet_next_reloc(p, &reloc);
		1091	if (r) {
		1092	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1093	idx, reg);
		1094	r100_cs_dump_packet(p, pkt);
		1095	return r;
		1096	}
1221	serge	1097	track->textures[1].cube_info[i].offset = idx_value;
		1098	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1099	track->textures[1].cube_info[i].robj = reloc->robj;
1963	serge	1100	track->tex_dirty = true;
1179	serge	1101	break;
		1102	case RADEON_PP_CUBIC_OFFSET_T2_0:
		1103	case RADEON_PP_CUBIC_OFFSET_T2_1:
		1104	case RADEON_PP_CUBIC_OFFSET_T2_2:
		1105	case RADEON_PP_CUBIC_OFFSET_T2_3:
		1106	case RADEON_PP_CUBIC_OFFSET_T2_4:
		1107	i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1117	serge	1108	r = r100_cs_packet_next_reloc(p, &reloc);
		1109	if (r) {
		1110	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1111	idx, reg);
		1112	r100_cs_dump_packet(p, pkt);
		1113	return r;
		1114	}
1221	serge	1115	track->textures[2].cube_info[i].offset = idx_value;
		1116	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1117	track->textures[2].cube_info[i].robj = reloc->robj;
1963	serge	1118	track->tex_dirty = true;
1179	serge	1119	break;
		1120	case RADEON_RE_WIDTH_HEIGHT:
1221	serge	1121	track->maxy = ((idx_value >> 16) & 0x7FF);
1963	serge	1122	track->cb_dirty = true;
		1123	track->zb_dirty = true;
1117	serge	1124	break;
1179	serge	1125	case RADEON_RB3D_COLORPITCH:
		1126	r = r100_cs_packet_next_reloc(p, &reloc);
		1127	if (r) {
		1128	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1129	idx, reg);
		1130	r100_cs_dump_packet(p, pkt);
		1131	return r;
		1132	}
		1133
		1134	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		1135	tile_flags \|= RADEON_COLOR_TILE_ENABLE;
		1136	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		1137	tile_flags \|= RADEON_COLOR_MICROTILE_ENABLE;
		1138
1221	serge	1139	tmp = idx_value & ~(0x7 << 16);
1179	serge	1140	tmp \|= tile_flags;
		1141	ib[idx] = tmp;
		1142
1221	serge	1143	track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1963	serge	1144	track->cb_dirty = true;
1179	serge	1145	break;
		1146	case RADEON_RB3D_DEPTHPITCH:
1221	serge	1147	track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1963	serge	1148	track->zb_dirty = true;
1179	serge	1149	break;
		1150	case RADEON_RB3D_CNTL:
1221	serge	1151	switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1179	serge	1152	case 7:
		1153	case 8:
		1154	case 9:
		1155	case 11:
		1156	case 12:
		1157	track->cb[0].cpp = 1;
		1158	break;
		1159	case 3:
		1160	case 4:
		1161	case 15:
		1162	track->cb[0].cpp = 2;
		1163	break;
		1164	case 6:
		1165	track->cb[0].cpp = 4;
		1166	break;
1117	serge	1167	default:
1179	serge	1168	DRM_ERROR("Invalid color buffer format (%d) !\n",
1221	serge	1169	((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1179	serge	1170	return -EINVAL;
		1171	}
1221	serge	1172	track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1963	serge	1173	track->cb_dirty = true;
		1174	track->zb_dirty = true;
1179	serge	1175	break;
		1176	case RADEON_RB3D_ZSTENCILCNTL:
1221	serge	1177	switch (idx_value & 0xf) {
1179	serge	1178	case 0:
		1179	track->zb.cpp = 2;
1117	serge	1180	break;
1179	serge	1181	case 2:
		1182	case 3:
		1183	case 4:
		1184	case 5:
		1185	case 9:
		1186	case 11:
		1187	track->zb.cpp = 4;
		1188	break;
		1189	default:
		1190	break;
1117	serge	1191	}
1963	serge	1192	track->zb_dirty = true;
1117	serge	1193	break;
1179	serge	1194	case RADEON_RB3D_ZPASS_ADDR:
		1195	r = r100_cs_packet_next_reloc(p, &reloc);
		1196	if (r) {
		1197	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1198	idx, reg);
		1199	r100_cs_dump_packet(p, pkt);
		1200	return r;
		1201	}
1221	serge	1202	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1203	break;
		1204	case RADEON_PP_CNTL:
		1205	{
1221	serge	1206	uint32_t temp = idx_value >> 4;
1179	serge	1207	for (i = 0; i < track->num_texture; i++)
		1208	track->textures[i].enabled = !!(temp & (1 << i));
1963	serge	1209	track->tex_dirty = true;
1117	serge	1210	}
1179	serge	1211	break;
		1212	case RADEON_SE_VF_CNTL:
1221	serge	1213	track->vap_vf_cntl = idx_value;
1179	serge	1214	break;
		1215	case RADEON_SE_VTX_FMT:
1221	serge	1216	track->vtx_size = r100_get_vtx_size(idx_value);
1179	serge	1217	break;
		1218	case RADEON_PP_TEX_SIZE_0:
		1219	case RADEON_PP_TEX_SIZE_1:
		1220	case RADEON_PP_TEX_SIZE_2:
		1221	i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1221	serge	1222	track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
		1223	track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1963	serge	1224	track->tex_dirty = true;
1179	serge	1225	break;
		1226	case RADEON_PP_TEX_PITCH_0:
		1227	case RADEON_PP_TEX_PITCH_1:
		1228	case RADEON_PP_TEX_PITCH_2:
		1229	i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1221	serge	1230	track->textures[i].pitch = idx_value + 32;
1963	serge	1231	track->tex_dirty = true;
1179	serge	1232	break;
		1233	case RADEON_PP_TXFILTER_0:
		1234	case RADEON_PP_TXFILTER_1:
		1235	case RADEON_PP_TXFILTER_2:
		1236	i = (reg - RADEON_PP_TXFILTER_0) / 24;
1221	serge	1237	track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1179	serge	1238	>> RADEON_MAX_MIP_LEVEL_SHIFT);
1221	serge	1239	tmp = (idx_value >> 23) & 0x7;
1179	serge	1240	if (tmp == 2 \|\| tmp == 6)
		1241	track->textures[i].roundup_w = false;
1221	serge	1242	tmp = (idx_value >> 27) & 0x7;
1179	serge	1243	if (tmp == 2 \|\| tmp == 6)
		1244	track->textures[i].roundup_h = false;
1963	serge	1245	track->tex_dirty = true;
1179	serge	1246	break;
		1247	case RADEON_PP_TXFORMAT_0:
		1248	case RADEON_PP_TXFORMAT_1:
		1249	case RADEON_PP_TXFORMAT_2:
		1250	i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1221	serge	1251	if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1179	serge	1252	track->textures[i].use_pitch = 1;
		1253	} else {
		1254	track->textures[i].use_pitch = 0;
1221	serge	1255	track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
		1256	track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1179	serge	1257	}
1221	serge	1258	if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1179	serge	1259	track->textures[i].tex_coord_type = 2;
1221	serge	1260	switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1179	serge	1261	case RADEON_TXFORMAT_I8:
		1262	case RADEON_TXFORMAT_RGB332:
		1263	case RADEON_TXFORMAT_Y8:
		1264	track->textures[i].cpp = 1;
1963	serge	1265	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1266	break;
		1267	case RADEON_TXFORMAT_AI88:
		1268	case RADEON_TXFORMAT_ARGB1555:
		1269	case RADEON_TXFORMAT_RGB565:
		1270	case RADEON_TXFORMAT_ARGB4444:
		1271	case RADEON_TXFORMAT_VYUY422:
		1272	case RADEON_TXFORMAT_YVYU422:
		1273	case RADEON_TXFORMAT_SHADOW16:
		1274	case RADEON_TXFORMAT_LDUDV655:
		1275	case RADEON_TXFORMAT_DUDV88:
		1276	track->textures[i].cpp = 2;
1963	serge	1277	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1278	break;
		1279	case RADEON_TXFORMAT_ARGB8888:
		1280	case RADEON_TXFORMAT_RGBA8888:
		1281	case RADEON_TXFORMAT_SHADOW32:
		1282	case RADEON_TXFORMAT_LDUDUV8888:
		1283	track->textures[i].cpp = 4;
1963	serge	1284	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1285	break;
1403	serge	1286	case RADEON_TXFORMAT_DXT1:
		1287	track->textures[i].cpp = 1;
		1288	track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
		1289	break;
		1290	case RADEON_TXFORMAT_DXT23:
		1291	case RADEON_TXFORMAT_DXT45:
		1292	track->textures[i].cpp = 1;
		1293	track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
		1294	break;
1179	serge	1295	}
1221	serge	1296	track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
		1297	track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1963	serge	1298	track->tex_dirty = true;
1179	serge	1299	break;
		1300	case RADEON_PP_CUBIC_FACES_0:
		1301	case RADEON_PP_CUBIC_FACES_1:
		1302	case RADEON_PP_CUBIC_FACES_2:
1221	serge	1303	tmp = idx_value;
1179	serge	1304	i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
		1305	for (face = 0; face < 4; face++) {
		1306	track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
		1307	track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
		1308	}
1963	serge	1309	track->tex_dirty = true;
1179	serge	1310	break;
		1311	default:
		1312	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
		1313	reg, idx);
		1314	return -EINVAL;
1117	serge	1315	}
		1316	return 0;
		1317	}
		1318
		1319	int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
		1320	struct radeon_cs_packet *pkt,
1321	serge	1321	struct radeon_bo *robj)
1117	serge	1322	{
		1323	unsigned idx;
1221	serge	1324	u32 value;
1117	serge	1325	idx = pkt->idx + 1;
1221	serge	1326	value = radeon_get_ib_value(p, idx + 2);
1321	serge	1327	if ((value + 1) > radeon_bo_size(robj)) {
1117	serge	1328	DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
		1329	"(need %u have %lu) !\n",
1221	serge	1330	value + 1,
1321	serge	1331	radeon_bo_size(robj));
1117	serge	1332	return -EINVAL;
		1333	}
		1334	return 0;
		1335	}
		1336
		1337	static int r100_packet3_check(struct radeon_cs_parser *p,
		1338	struct radeon_cs_packet *pkt)
		1339	{
		1340	struct radeon_cs_reloc *reloc;
1179	serge	1341	struct r100_cs_track *track;
1117	serge	1342	unsigned idx;
		1343	volatile uint32_t *ib;
		1344	int r;
		1345
		1346	ib = p->ib->ptr;
		1347	idx = pkt->idx + 1;
1179	serge	1348	track = (struct r100_cs_track *)p->track;
1117	serge	1349	switch (pkt->opcode) {
		1350	case PACKET3_3D_LOAD_VBPNTR:
1221	serge	1351	r = r100_packet3_load_vbpntr(p, pkt, idx);
		1352	if (r)
1117	serge	1353	return r;
		1354	break;
		1355	case PACKET3_INDX_BUFFER:
		1356	r = r100_cs_packet_next_reloc(p, &reloc);
		1357	if (r) {
		1358	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1359	r100_cs_dump_packet(p, pkt);
		1360	return r;
		1361	}
1221	serge	1362	ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1117	serge	1363	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		1364	if (r) {
		1365	return r;
		1366	}
		1367	break;
		1368	case 0x23:
		1369	/* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
		1370	r = r100_cs_packet_next_reloc(p, &reloc);
		1371	if (r) {
		1372	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1373	r100_cs_dump_packet(p, pkt);
		1374	return r;
		1375	}
1221	serge	1376	ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1179	serge	1377	track->num_arrays = 1;
1221	serge	1378	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1179	serge	1379
		1380	track->arrays[0].robj = reloc->robj;
		1381	track->arrays[0].esize = track->vtx_size;
		1382
1221	serge	1383	track->max_indx = radeon_get_ib_value(p, idx+1);
1179	serge	1384
1221	serge	1385	track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1179	serge	1386	track->immd_dwords = pkt->count - 1;
		1387	r = r100_cs_track_check(p->rdev, track);
		1388	if (r)
		1389	return r;
1117	serge	1390	break;
		1391	case PACKET3_3D_DRAW_IMMD:
1221	serge	1392	if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1179	serge	1393	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1394	return -EINVAL;
		1395	}
1403	serge	1396	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1221	serge	1397	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1398	track->immd_dwords = pkt->count - 1;
		1399	r = r100_cs_track_check(p->rdev, track);
		1400	if (r)
		1401	return r;
		1402	break;
1117	serge	1403	/* triggers drawing using in-packet vertex data */
		1404	case PACKET3_3D_DRAW_IMMD_2:
1221	serge	1405	if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1179	serge	1406	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1407	return -EINVAL;
		1408	}
1221	serge	1409	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1410	track->immd_dwords = pkt->count;
		1411	r = r100_cs_track_check(p->rdev, track);
		1412	if (r)
		1413	return r;
		1414	break;
1117	serge	1415	/* triggers drawing using in-packet vertex data */
		1416	case PACKET3_3D_DRAW_VBUF_2:
1221	serge	1417	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1418	r = r100_cs_track_check(p->rdev, track);
		1419	if (r)
		1420	return r;
		1421	break;
1117	serge	1422	/* triggers drawing of vertex buffers setup elsewhere */
		1423	case PACKET3_3D_DRAW_INDX_2:
1221	serge	1424	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1425	r = r100_cs_track_check(p->rdev, track);
		1426	if (r)
		1427	return r;
		1428	break;
1117	serge	1429	/* triggers drawing using indices to vertex buffer */
		1430	case PACKET3_3D_DRAW_VBUF:
1221	serge	1431	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1432	r = r100_cs_track_check(p->rdev, track);
		1433	if (r)
		1434	return r;
		1435	break;
1117	serge	1436	/* triggers drawing of vertex buffers setup elsewhere */
		1437	case PACKET3_3D_DRAW_INDX:
1221	serge	1438	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1439	r = r100_cs_track_check(p->rdev, track);
		1440	if (r)
		1441	return r;
		1442	break;
1117	serge	1443	/* triggers drawing using indices to vertex buffer */
1963	serge	1444	case PACKET3_3D_CLEAR_HIZ:
		1445	case PACKET3_3D_CLEAR_ZMASK:
		1446	if (p->rdev->hyperz_filp != p->filp)
		1447	return -EINVAL;
		1448	break;
1117	serge	1449	case PACKET3_NOP:
		1450	break;
		1451	default:
		1452	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		1453	return -EINVAL;
		1454	}
		1455	return 0;
		1456	}
		1457
		1458	int r100_cs_parse(struct radeon_cs_parser *p)
		1459	{
		1460	struct radeon_cs_packet pkt;
1179	serge	1461	struct r100_cs_track *track;
1117	serge	1462	int r;
		1463
1179	serge	1464	track = kzalloc(sizeof(*track), GFP_KERNEL);
		1465	r100_cs_track_clear(p->rdev, track);
		1466	p->track = track;
1117	serge	1467	do {
		1468	r = r100_cs_packet_parse(p, &pkt, p->idx);
		1469	if (r) {
		1470	return r;
		1471	}
		1472	p->idx += pkt.count + 2;
		1473	switch (pkt.type) {
		1474	case PACKET_TYPE0:
1179	serge	1475	if (p->rdev->family >= CHIP_R200)
		1476	r = r100_cs_parse_packet0(p, &pkt,
		1477	p->rdev->config.r100.reg_safe_bm,
		1478	p->rdev->config.r100.reg_safe_bm_size,
		1479	&r200_packet0_check);
		1480	else
		1481	r = r100_cs_parse_packet0(p, &pkt,
		1482	p->rdev->config.r100.reg_safe_bm,
		1483	p->rdev->config.r100.reg_safe_bm_size,
		1484	&r100_packet0_check);
1117	serge	1485	break;
		1486	case PACKET_TYPE2:
		1487	break;
		1488	case PACKET_TYPE3:
		1489	r = r100_packet3_check(p, &pkt);
		1490	break;
		1491	default:
		1492	DRM_ERROR("Unknown packet type %d !\n",
		1493	pkt.type);
		1494	return -EINVAL;
		1495	}
		1496	if (r) {
		1497	return r;
		1498	}
		1499	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
		1500	return 0;
		1501	}
		1502
1128	serge	1503	#endif
1117	serge	1504
		1505	/*
		1506	* Global GPU functions
		1507	*/
		1508	void r100_errata(struct radeon_device *rdev)
		1509	{
		1510	rdev->pll_errata = 0;
		1511
		1512	if (rdev->family == CHIP_RV200 \|\| rdev->family == CHIP_RS200) {
		1513	rdev->pll_errata \|= CHIP_ERRATA_PLL_DUMMYREADS;
		1514	}
		1515
		1516	if (rdev->family == CHIP_RV100 \|\|
		1517	rdev->family == CHIP_RS100 \|\|
		1518	rdev->family == CHIP_RS200) {
		1519	rdev->pll_errata \|= CHIP_ERRATA_PLL_DELAY;
		1520	}
		1521	}
		1522
		1523	/* Wait for vertical sync on primary CRTC */
		1524	void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
		1525	{
		1526	uint32_t crtc_gen_cntl, tmp;
		1527	int i;
		1528
		1529	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
		1530	if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) \|\|
		1531	!(crtc_gen_cntl & RADEON_CRTC_EN)) {
		1532	return;
		1533	}
		1534	/* Clear the CRTC_VBLANK_SAVE bit */
		1535	WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
		1536	for (i = 0; i < rdev->usec_timeout; i++) {
		1537	tmp = RREG32(RADEON_CRTC_STATUS);
		1538	if (tmp & RADEON_CRTC_VBLANK_SAVE) {
		1539	return;
		1540	}
		1541	DRM_UDELAY(1);
		1542	}
		1543	}
		1544
		1545	/* Wait for vertical sync on secondary CRTC */
		1546	void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
		1547	{
		1548	uint32_t crtc2_gen_cntl, tmp;
		1549	int i;
		1550
		1551	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1552	if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) \|\|
		1553	!(crtc2_gen_cntl & RADEON_CRTC2_EN))
		1554	return;
		1555
		1556	/* Clear the CRTC_VBLANK_SAVE bit */
		1557	WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
		1558	for (i = 0; i < rdev->usec_timeout; i++) {
		1559	tmp = RREG32(RADEON_CRTC2_STATUS);
		1560	if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
		1561	return;
		1562	}
		1563	DRM_UDELAY(1);
		1564	}
		1565	}
		1566
		1567	int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
		1568	{
		1569	unsigned i;
		1570	uint32_t tmp;
		1571
		1572	for (i = 0; i < rdev->usec_timeout; i++) {
		1573	tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
		1574	if (tmp >= n) {
		1575	return 0;
		1576	}
		1577	DRM_UDELAY(1);
		1578	}
		1579	return -1;
		1580	}
		1581
		1582	int r100_gui_wait_for_idle(struct radeon_device *rdev)
		1583	{
		1584	unsigned i;
		1585	uint32_t tmp;
		1586
		1587	if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
		1588	printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
		1589	" Bad things might happen.\n");
		1590	}
		1591	for (i = 0; i < rdev->usec_timeout; i++) {
		1592	tmp = RREG32(RADEON_RBBM_STATUS);
1430	serge	1593	if (!(tmp & RADEON_RBBM_ACTIVE)) {
1117	serge	1594	return 0;
		1595	}
		1596	DRM_UDELAY(1);
		1597	}
		1598	return -1;
		1599	}
		1600
		1601	int r100_mc_wait_for_idle(struct radeon_device *rdev)
		1602	{
		1603	unsigned i;
		1604	uint32_t tmp;
		1605
		1606	for (i = 0; i < rdev->usec_timeout; i++) {
		1607	/* read MC_STATUS */
1430	serge	1608	tmp = RREG32(RADEON_MC_STATUS);
		1609	if (tmp & RADEON_MC_IDLE) {
1117	serge	1610	return 0;
		1611	}
		1612	DRM_UDELAY(1);
		1613	}
		1614	return -1;
		1615	}
		1616
1963	serge	1617	void r100_gpu_lockup_update(struct r100_gpu_lockup lockup, struct radeon_cp cp)
1117	serge	1618	{
1963	serge	1619	lockup->last_cp_rptr = cp->rptr;
		1620	lockup->last_jiffies = 0; //jiffies;
1117	serge	1621	}
		1622
1963	serge	1623	/**
		1624	* r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
		1625	* @rdev: radeon device structure
		1626	* @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
		1627	* @cp: radeon_cp structure holding CP information
		1628	*
		1629	* We don't need to initialize the lockup tracking information as we will either
		1630	* have CP rptr to a different value of jiffies wrap around which will force
		1631	* initialization of the lockup tracking informations.
		1632	*
		1633	* A possible false positivie is if we get call after while and last_cp_rptr ==
		1634	* the current CP rptr, even if it's unlikely it might happen. To avoid this
		1635	* if the elapsed time since last call is bigger than 2 second than we return
		1636	* false and update the tracking information. Due to this the caller must call
		1637	* r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
		1638	* the fencing code should be cautious about that.
		1639	*
		1640	* Caller should write to the ring to force CP to do something so we don't get
		1641	* false positive when CP is just gived nothing to do.
		1642	*
		1643	**/
		1644	bool r100_gpu_cp_is_lockup(struct radeon_device rdev, struct r100_gpu_lockup lockup, struct radeon_cp *cp)
1117	serge	1645	{
1963	serge	1646	unsigned long cjiffies, elapsed;
1117	serge	1647
1963	serge	1648	#if 0
		1649	cjiffies = jiffies;
		1650	if (!time_after(cjiffies, lockup->last_jiffies)) {
		1651	/* likely a wrap around */
		1652	lockup->last_cp_rptr = cp->rptr;
		1653	lockup->last_jiffies = jiffies;
		1654	return false;
		1655	}
		1656	if (cp->rptr != lockup->last_cp_rptr) {
		1657	/* CP is still working no lockup */
		1658	lockup->last_cp_rptr = cp->rptr;
		1659	lockup->last_jiffies = jiffies;
		1660	return false;
		1661	}
		1662	elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
		1663	if (elapsed >= 10000) {
		1664	dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
		1665	return true;
		1666	}
		1667	#endif
		1668
		1669	/* give a chance to the GPU ... */
		1670	return false;
1117	serge	1671	}
		1672
1963	serge	1673	bool r100_gpu_is_lockup(struct radeon_device *rdev)
1117	serge	1674	{
1963	serge	1675	u32 rbbm_status;
		1676	int r;
1117	serge	1677
1963	serge	1678	rbbm_status = RREG32(R_000E40_RBBM_STATUS);
		1679	if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
		1680	r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
		1681	return false;
1117	serge	1682	}
1963	serge	1683	/* force CP activities */
		1684	r = radeon_ring_lock(rdev, 2);
		1685	if (!r) {
		1686	/* PACKET2 NOP */
		1687	radeon_ring_write(rdev, 0x80000000);
		1688	radeon_ring_write(rdev, 0x80000000);
		1689	radeon_ring_unlock_commit(rdev);
1117	serge	1690	}
1963	serge	1691	rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
		1692	return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
1117	serge	1693	}
		1694
1963	serge	1695	void r100_bm_disable(struct radeon_device *rdev)
1117	serge	1696	{
1963	serge	1697	u32 tmp;
1117	serge	1698
1963	serge	1699	/* disable bus mastering */
		1700	tmp = RREG32(R_000030_BUS_CNTL);
		1701	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000044);
		1702	mdelay(1);
		1703	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000042);
		1704	mdelay(1);
		1705	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000040);
		1706	tmp = RREG32(RADEON_BUS_CNTL);
		1707	mdelay(1);
		1708	tmp = PciRead16(rdev->pdev->bus, rdev->pdev->devfn, 0x4);
		1709	PciWrite16(rdev->pdev->bus, rdev->pdev->devfn, 0x4, tmp & 0xFFFB);
		1710	mdelay(1);
		1711	}
		1712
		1713	int r100_asic_reset(struct radeon_device *rdev)
		1714	{
		1715	struct r100_mc_save save;
		1716	u32 status, tmp;
		1717	int ret = 0;
		1718
		1719	status = RREG32(R_000E40_RBBM_STATUS);
		1720	if (!G_000E40_GUI_ACTIVE(status)) {
		1721	return 0;
1117	serge	1722	}
1963	serge	1723	r100_mc_stop(rdev, &save);
		1724	status = RREG32(R_000E40_RBBM_STATUS);
		1725	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		1726	/* stop CP */
		1727	WREG32(RADEON_CP_CSQ_CNTL, 0);
		1728	tmp = RREG32(RADEON_CP_RB_CNTL);
		1729	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);
		1730	WREG32(RADEON_CP_RB_RPTR_WR, 0);
		1731	WREG32(RADEON_CP_RB_WPTR, 0);
		1732	WREG32(RADEON_CP_RB_CNTL, tmp);
		1733	/* save PCI state */
		1734	// pci_save_state(rdev->pdev);
		1735	/* disable bus mastering */
		1736	r100_bm_disable(rdev);
		1737	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) \|
		1738	S_0000F0_SOFT_RESET_RE(1) \|
		1739	S_0000F0_SOFT_RESET_PP(1) \|
		1740	S_0000F0_SOFT_RESET_RB(1));
		1741	RREG32(R_0000F0_RBBM_SOFT_RESET);
		1742	mdelay(500);
		1743	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		1744	mdelay(1);
		1745	status = RREG32(R_000E40_RBBM_STATUS);
		1746	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
1117	serge	1747	/* reset CP */
1963	serge	1748	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
		1749	RREG32(R_0000F0_RBBM_SOFT_RESET);
		1750	mdelay(500);
		1751	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		1752	mdelay(1);
		1753	status = RREG32(R_000E40_RBBM_STATUS);
		1754	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		1755	/* restore PCI & busmastering */
		1756	// pci_restore_state(rdev->pdev);
		1757	r100_enable_bm(rdev);
1117	serge	1758	/* Check if GPU is idle */
1963	serge	1759	if (G_000E40_SE_BUSY(status) \|\| G_000E40_RE_BUSY(status) \|\|
		1760	G_000E40_TAM_BUSY(status) \|\| G_000E40_PB_BUSY(status)) {
		1761	dev_err(rdev->dev, "failed to reset GPU\n");
		1762	rdev->gpu_lockup = true;
		1763	ret = -1;
		1764	} else
		1765	dev_info(rdev->dev, "GPU reset succeed\n");
		1766	r100_mc_resume(rdev, &save);
		1767	return ret;
1117	serge	1768	}
		1769
1321	serge	1770	void r100_set_common_regs(struct radeon_device *rdev)
		1771	{
1430	serge	1772	struct drm_device *dev = rdev->ddev;
		1773	bool force_dac2 = false;
1963	serge	1774	u32 tmp;
1430	serge	1775
1321	serge	1776	/* set these so they don't interfere with anything */
		1777	WREG32(RADEON_OV0_SCALE_CNTL, 0);
		1778	WREG32(RADEON_SUBPIC_CNTL, 0);
		1779	WREG32(RADEON_VIPH_CONTROL, 0);
		1780	WREG32(RADEON_I2C_CNTL_1, 0);
		1781	WREG32(RADEON_DVI_I2C_CNTL_1, 0);
		1782	WREG32(RADEON_CAP0_TRIG_CNTL, 0);
		1783	WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1430	serge	1784
		1785	/* always set up dac2 on rn50 and some rv100 as lots
		1786	* of servers seem to wire it up to a VGA port but
		1787	* don't report it in the bios connector
		1788	* table.
		1789	*/
		1790	switch (dev->pdev->device) {
		1791	/* RN50 */
		1792	case 0x515e:
		1793	case 0x5969:
		1794	force_dac2 = true;
		1795	break;
		1796	/* RV100*/
		1797	case 0x5159:
		1798	case 0x515a:
		1799	/* DELL triple head servers */
		1800	if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
		1801	((dev->pdev->subsystem_device == 0x016c) \|\|
		1802	(dev->pdev->subsystem_device == 0x016d) \|\|
		1803	(dev->pdev->subsystem_device == 0x016e) \|\|
		1804	(dev->pdev->subsystem_device == 0x016f) \|\|
		1805	(dev->pdev->subsystem_device == 0x0170) \|\|
		1806	(dev->pdev->subsystem_device == 0x017d) \|\|
		1807	(dev->pdev->subsystem_device == 0x017e) \|\|
		1808	(dev->pdev->subsystem_device == 0x0183) \|\|
		1809	(dev->pdev->subsystem_device == 0x018a) \|\|
		1810	(dev->pdev->subsystem_device == 0x019a)))
		1811	force_dac2 = true;
		1812	break;
		1813	}
		1814
		1815	if (force_dac2) {
		1816	u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
		1817	u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1818	u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
		1819
		1820	/* For CRT on DAC2, don't turn it on if BIOS didn't
		1821	enable it, even it's detected.
		1822	*/
		1823
		1824	/* force it to crtc0 */
		1825	dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
		1826	dac2_cntl \|= RADEON_DAC2_DAC2_CLK_SEL;
		1827	disp_hw_debug \|= RADEON_CRT2_DISP1_SEL;
		1828
		1829	/* set up the TV DAC */
		1830	tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL \|
		1831	RADEON_TV_DAC_STD_MASK \|
		1832	RADEON_TV_DAC_RDACPD \|
		1833	RADEON_TV_DAC_GDACPD \|
		1834	RADEON_TV_DAC_BDACPD \|
		1835	RADEON_TV_DAC_BGADJ_MASK \|
		1836	RADEON_TV_DAC_DACADJ_MASK);
		1837	tv_dac_cntl \|= (RADEON_TV_DAC_NBLANK \|
		1838	RADEON_TV_DAC_NHOLD \|
		1839	RADEON_TV_DAC_STD_PS2 \|
		1840	(0x58 << 16));
		1841
		1842	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1843	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		1844	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		1845	}
1963	serge	1846
		1847	/* switch PM block to ACPI mode */
		1848	tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
		1849	tmp &= ~RADEON_PM_MODE_SEL;
		1850	WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
		1851
1321	serge	1852	}
1117	serge	1853
		1854	/*
		1855	* VRAM info
		1856	*/
		1857	static void r100_vram_get_type(struct radeon_device *rdev)
		1858	{
		1859	uint32_t tmp;
		1860
		1861	rdev->mc.vram_is_ddr = false;
		1862	if (rdev->flags & RADEON_IS_IGP)
		1863	rdev->mc.vram_is_ddr = true;
		1864	else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
		1865	rdev->mc.vram_is_ddr = true;
		1866	if ((rdev->family == CHIP_RV100) \|\|
		1867	(rdev->family == CHIP_RS100) \|\|
		1868	(rdev->family == CHIP_RS200)) {
		1869	tmp = RREG32(RADEON_MEM_CNTL);
		1870	if (tmp & RV100_HALF_MODE) {
		1871	rdev->mc.vram_width = 32;
		1872	} else {
		1873	rdev->mc.vram_width = 64;
		1874	}
		1875	if (rdev->flags & RADEON_SINGLE_CRTC) {
		1876	rdev->mc.vram_width /= 4;
		1877	rdev->mc.vram_is_ddr = true;
		1878	}
		1879	} else if (rdev->family <= CHIP_RV280) {
		1880	tmp = RREG32(RADEON_MEM_CNTL);
		1881	if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
		1882	rdev->mc.vram_width = 128;
		1883	} else {
		1884	rdev->mc.vram_width = 64;
		1885	}
		1886	} else {
		1887	/* newer IGPs */
		1888	rdev->mc.vram_width = 128;
		1889	}
		1890	}
		1891
1179	serge	1892	static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1117	serge	1893	{
1179	serge	1894	u32 aper_size;
		1895	u8 byte;
1117	serge	1896
1179	serge	1897	aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
		1898
		1899	/* Set HDP_APER_CNTL only on cards that are known not to be broken,
		1900	* that is has the 2nd generation multifunction PCI interface
		1901	*/
		1902	if (rdev->family == CHIP_RV280 \|\|
		1903	rdev->family >= CHIP_RV350) {
		1904	WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
		1905	~RADEON_HDP_APER_CNTL);
		1906	DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
		1907	return aper_size * 2;
		1908	}
		1909
		1910	/* Older cards have all sorts of funny issues to deal with. First
		1911	* check if it's a multifunction card by reading the PCI config
		1912	* header type... Limit those to one aperture size
		1913	*/
		1914	// pci_read_config_byte(rdev->pdev, 0xe, &byte);
		1915	// if (byte & 0x80) {
		1916	// DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
		1917	// DRM_INFO("Limiting VRAM to one aperture\n");
		1918	// return aper_size;
		1919	// }
		1920
		1921	/* Single function older card. We read HDP_APER_CNTL to see how the BIOS
		1922	* have set it up. We don't write this as it's broken on some ASICs but
		1923	* we expect the BIOS to have done the right thing (might be too optimistic...)
		1924	*/
		1925	if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
		1926	return aper_size * 2;
		1927	return aper_size;
		1928	}
		1929
		1930	void r100_vram_init_sizes(struct radeon_device *rdev)
		1931	{
		1932	u64 config_aper_size;
		1933
1430	serge	1934	/* work out accessible VRAM */
1963	serge	1935	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
		1936	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1430	serge	1937	rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
		1938	/* FIXME we don't use the second aperture yet when we could use it */
		1939	if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
		1940	rdev->mc.visible_vram_size = rdev->mc.aper_size;
1179	serge	1941	config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1117	serge	1942	if (rdev->flags & RADEON_IS_IGP) {
		1943	uint32_t tom;
		1944	/* read NB_TOM to get the amount of ram stolen for the GPU */
		1945	tom = RREG32(RADEON_NB_TOM);
1179	serge	1946	rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
		1947	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
		1948	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	1949	} else {
1179	serge	1950	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1117	serge	1951	/* Some production boards of m6 will report 0
		1952	* if it's 8 MB
		1953	*/
1179	serge	1954	if (rdev->mc.real_vram_size == 0) {
		1955	rdev->mc.real_vram_size = 8192 * 1024;
		1956	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1117	serge	1957	}
1179	serge	1958	/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1430	serge	1959	* Novell bug 204882 + along with lots of ubuntu ones
		1960	*/
1963	serge	1961	if (rdev->mc.aper_size > config_aper_size)
		1962	config_aper_size = rdev->mc.aper_size;
		1963
1179	serge	1964	if (config_aper_size > rdev->mc.real_vram_size)
		1965	rdev->mc.mc_vram_size = config_aper_size;
		1966	else
		1967	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	1968	}
		1969	}
		1970
1179	serge	1971	void r100_vga_set_state(struct radeon_device *rdev, bool state)
		1972	{
		1973	uint32_t temp;
		1974
		1975	temp = RREG32(RADEON_CONFIG_CNTL);
		1976	if (state == false) {
1963	serge	1977	temp &= ~RADEON_CFG_VGA_RAM_EN;
		1978	temp \|= RADEON_CFG_VGA_IO_DIS;
1179	serge	1979	} else {
1963	serge	1980	temp &= ~RADEON_CFG_VGA_IO_DIS;
1179	serge	1981	}
		1982	WREG32(RADEON_CONFIG_CNTL, temp);
		1983	}
		1984
1430	serge	1985	void r100_mc_init(struct radeon_device *rdev)
1179	serge	1986	{
1430	serge	1987	u64 base;
		1988
1179	serge	1989	r100_vram_get_type(rdev);
		1990	r100_vram_init_sizes(rdev);
1430	serge	1991	base = rdev->mc.aper_base;
		1992	if (rdev->flags & RADEON_IS_IGP)
		1993	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
		1994	radeon_vram_location(rdev, &rdev->mc, base);
1963	serge	1995	rdev->mc.gtt_base_align = 0;
1430	serge	1996	if (!(rdev->flags & RADEON_IS_AGP))
		1997	radeon_gtt_location(rdev, &rdev->mc);
1963	serge	1998	radeon_update_bandwidth_info(rdev);
1179	serge	1999	}
		2000
		2001
1117	serge	2002	/*
		2003	* Indirect registers accessor
		2004	*/
		2005	void r100_pll_errata_after_index(struct radeon_device *rdev)
		2006	{
1963	serge	2007	if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
1117	serge	2008	(void)RREG32(RADEON_CLOCK_CNTL_DATA);
		2009	(void)RREG32(RADEON_CRTC_GEN_CNTL);
1963	serge	2010	}
1117	serge	2011	}
		2012
		2013	static void r100_pll_errata_after_data(struct radeon_device *rdev)
		2014	{
		2015	/* This workarounds is necessary on RV100, RS100 and RS200 chips
		2016	* or the chip could hang on a subsequent access
		2017	*/
		2018	if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
		2019	udelay(5000);
		2020	}
		2021
		2022	/* This function is required to workaround a hardware bug in some (all?)
		2023	* revisions of the R300. This workaround should be called after every
		2024	* CLOCK_CNTL_INDEX register access. If not, register reads afterward
		2025	* may not be correct.
		2026	*/
		2027	if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
		2028	uint32_t save, tmp;
		2029
		2030	save = RREG32(RADEON_CLOCK_CNTL_INDEX);
		2031	tmp = save & ~(0x3f \| RADEON_PLL_WR_EN);
		2032	WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
		2033	tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
		2034	WREG32(RADEON_CLOCK_CNTL_INDEX, save);
		2035	}
		2036	}
		2037
		2038	uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
		2039	{
		2040	uint32_t data;
		2041
		2042	WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
		2043	r100_pll_errata_after_index(rdev);
		2044	data = RREG32(RADEON_CLOCK_CNTL_DATA);
		2045	r100_pll_errata_after_data(rdev);
		2046	return data;
		2047	}
		2048
		2049	void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		2050	{
		2051	WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) \| RADEON_PLL_WR_EN));
		2052	r100_pll_errata_after_index(rdev);
		2053	WREG32(RADEON_CLOCK_CNTL_DATA, v);
		2054	r100_pll_errata_after_data(rdev);
		2055	}
		2056
1221	serge	2057	void r100_set_safe_registers(struct radeon_device *rdev)
1117	serge	2058	{
1179	serge	2059	if (ASIC_IS_RN50(rdev)) {
		2060	rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
		2061	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
		2062	} else if (rdev->family < CHIP_R200) {
		2063	rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
		2064	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
		2065	} else {
1221	serge	2066	r200_set_safe_registers(rdev);
1117	serge	2067	}
		2068	}
		2069
1129	serge	2070	/*
		2071	* Debugfs info
		2072	*/
		2073	#if defined(CONFIG_DEBUG_FS)
		2074	static int r100_debugfs_rbbm_info(struct seq_file m, void data)
		2075	{
		2076	struct drm_info_node node = (struct drm_info_node ) m->private;
		2077	struct drm_device *dev = node->minor->dev;
		2078	struct radeon_device *rdev = dev->dev_private;
		2079	uint32_t reg, value;
		2080	unsigned i;
		2081
		2082	seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
		2083	seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
		2084	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2085	for (i = 0; i < 64; i++) {
		2086	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i \| 0x100);
		2087	reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
		2088	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
		2089	value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
		2090	seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
		2091	}
		2092	return 0;
		2093	}
		2094
		2095	static int r100_debugfs_cp_ring_info(struct seq_file m, void data)
		2096	{
		2097	struct drm_info_node node = (struct drm_info_node ) m->private;
		2098	struct drm_device *dev = node->minor->dev;
		2099	struct radeon_device *rdev = dev->dev_private;
		2100	uint32_t rdp, wdp;
		2101	unsigned count, i, j;
		2102
		2103	radeon_ring_free_size(rdev);
		2104	rdp = RREG32(RADEON_CP_RB_RPTR);
		2105	wdp = RREG32(RADEON_CP_RB_WPTR);
		2106	count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
		2107	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2108	seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
		2109	seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
		2110	seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
		2111	seq_printf(m, "%u dwords in ring\n", count);
		2112	for (j = 0; j <= count; j++) {
		2113	i = (rdp + j) & rdev->cp.ptr_mask;
		2114	seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
		2115	}
		2116	return 0;
		2117	}
		2118
		2119
		2120	static int r100_debugfs_cp_csq_fifo(struct seq_file m, void data)
		2121	{
		2122	struct drm_info_node node = (struct drm_info_node ) m->private;
		2123	struct drm_device *dev = node->minor->dev;
		2124	struct radeon_device *rdev = dev->dev_private;
		2125	uint32_t csq_stat, csq2_stat, tmp;
		2126	unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
		2127	unsigned i;
		2128
		2129	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2130	seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
		2131	csq_stat = RREG32(RADEON_CP_CSQ_STAT);
		2132	csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
		2133	r_rptr = (csq_stat >> 0) & 0x3ff;
		2134	r_wptr = (csq_stat >> 10) & 0x3ff;
		2135	ib1_rptr = (csq_stat >> 20) & 0x3ff;
		2136	ib1_wptr = (csq2_stat >> 0) & 0x3ff;
		2137	ib2_rptr = (csq2_stat >> 10) & 0x3ff;
		2138	ib2_wptr = (csq2_stat >> 20) & 0x3ff;
		2139	seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
		2140	seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
		2141	seq_printf(m, "Ring rptr %u\n", r_rptr);
		2142	seq_printf(m, "Ring wptr %u\n", r_wptr);
		2143	seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
		2144	seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
		2145	seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
		2146	seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
		2147	/* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
		2148	* 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
		2149	seq_printf(m, "Ring fifo:\n");
		2150	for (i = 0; i < 256; i++) {
		2151	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2152	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2153	seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
		2154	}
		2155	seq_printf(m, "Indirect1 fifo:\n");
		2156	for (i = 256; i <= 512; i++) {
		2157	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2158	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2159	seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
		2160	}
		2161	seq_printf(m, "Indirect2 fifo:\n");
		2162	for (i = 640; i < ib1_wptr; i++) {
		2163	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2164	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2165	seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
		2166	}
		2167	return 0;
		2168	}
		2169
		2170	static int r100_debugfs_mc_info(struct seq_file m, void data)
		2171	{
		2172	struct drm_info_node node = (struct drm_info_node ) m->private;
		2173	struct drm_device *dev = node->minor->dev;
		2174	struct radeon_device *rdev = dev->dev_private;
		2175	uint32_t tmp;
		2176
		2177	tmp = RREG32(RADEON_CONFIG_MEMSIZE);
		2178	seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
		2179	tmp = RREG32(RADEON_MC_FB_LOCATION);
		2180	seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
		2181	tmp = RREG32(RADEON_BUS_CNTL);
		2182	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
		2183	tmp = RREG32(RADEON_MC_AGP_LOCATION);
		2184	seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
		2185	tmp = RREG32(RADEON_AGP_BASE);
		2186	seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
		2187	tmp = RREG32(RADEON_HOST_PATH_CNTL);
		2188	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
		2189	tmp = RREG32(0x01D0);
		2190	seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
		2191	tmp = RREG32(RADEON_AIC_LO_ADDR);
		2192	seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
		2193	tmp = RREG32(RADEON_AIC_HI_ADDR);
		2194	seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
		2195	tmp = RREG32(0x01E4);
		2196	seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
		2197	return 0;
		2198	}
		2199
		2200	static struct drm_info_list r100_debugfs_rbbm_list[] = {
		2201	{"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
		2202	};
		2203
		2204	static struct drm_info_list r100_debugfs_cp_list[] = {
		2205	{"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
		2206	{"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
		2207	};
		2208
		2209	static struct drm_info_list r100_debugfs_mc_info_list[] = {
		2210	{"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
		2211	};
		2212	#endif
		2213
		2214	int r100_debugfs_rbbm_init(struct radeon_device *rdev)
		2215	{
		2216	#if defined(CONFIG_DEBUG_FS)
		2217	return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
		2218	#else
		2219	return 0;
		2220	#endif
		2221	}
		2222
		2223	int r100_debugfs_cp_init(struct radeon_device *rdev)
		2224	{
		2225	#if defined(CONFIG_DEBUG_FS)
		2226	return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
		2227	#else
		2228	return 0;
		2229	#endif
		2230	}
		2231
		2232	int r100_debugfs_mc_info_init(struct radeon_device *rdev)
		2233	{
		2234	#if defined(CONFIG_DEBUG_FS)
		2235	return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
		2236	#else
		2237	return 0;
		2238	#endif
		2239	}
1179	serge	2240
		2241	int r100_set_surface_reg(struct radeon_device *rdev, int reg,
		2242	uint32_t tiling_flags, uint32_t pitch,
		2243	uint32_t offset, uint32_t obj_size)
		2244	{
		2245	int surf_index = reg * 16;
		2246	int flags = 0;
		2247
		2248	if (rdev->family <= CHIP_RS200) {
		2249	if ((tiling_flags & (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		2250	== (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		2251	flags \|= RADEON_SURF_TILE_COLOR_BOTH;
		2252	if (tiling_flags & RADEON_TILING_MACRO)
		2253	flags \|= RADEON_SURF_TILE_COLOR_MACRO;
		2254	} else if (rdev->family <= CHIP_RV280) {
		2255	if (tiling_flags & (RADEON_TILING_MACRO))
		2256	flags \|= R200_SURF_TILE_COLOR_MACRO;
		2257	if (tiling_flags & RADEON_TILING_MICRO)
		2258	flags \|= R200_SURF_TILE_COLOR_MICRO;
		2259	} else {
		2260	if (tiling_flags & RADEON_TILING_MACRO)
		2261	flags \|= R300_SURF_TILE_MACRO;
		2262	if (tiling_flags & RADEON_TILING_MICRO)
		2263	flags \|= R300_SURF_TILE_MICRO;
		2264	}
		2265
		2266	if (tiling_flags & RADEON_TILING_SWAP_16BIT)
		2267	flags \|= RADEON_SURF_AP0_SWP_16BPP \| RADEON_SURF_AP1_SWP_16BPP;
		2268	if (tiling_flags & RADEON_TILING_SWAP_32BIT)
		2269	flags \|= RADEON_SURF_AP0_SWP_32BPP \| RADEON_SURF_AP1_SWP_32BPP;
		2270
1963	serge	2271	/* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
		2272	if (tiling_flags & (RADEON_TILING_SWAP_16BIT \| RADEON_TILING_SWAP_32BIT)) {
		2273	if (!(tiling_flags & (RADEON_TILING_MACRO \| RADEON_TILING_MICRO)))
		2274	if (ASIC_IS_RN50(rdev))
		2275	pitch /= 16;
		2276	}
		2277
		2278	/* r100/r200 divide by 16 */
		2279	if (rdev->family < CHIP_R300)
		2280	flags \|= pitch / 16;
		2281	else
		2282	flags \|= pitch / 8;
		2283
		2284
		2285	DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
1179	serge	2286	WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
		2287	WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
		2288	WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
		2289	return 0;
		2290	}
		2291
		2292	void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
		2293	{
		2294	int surf_index = reg * 16;
		2295	WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
		2296	}
		2297
		2298	void r100_bandwidth_update(struct radeon_device *rdev)
		2299	{
		2300	fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
		2301	fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
		2302	fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
		2303	uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
		2304	fixed20_12 memtcas_ff[8] = {
1963	serge	2305	dfixed_init(1),
		2306	dfixed_init(2),
		2307	dfixed_init(3),
		2308	dfixed_init(0),
		2309	dfixed_init_half(1),
		2310	dfixed_init_half(2),
		2311	dfixed_init(0),
1179	serge	2312	};
		2313	fixed20_12 memtcas_rs480_ff[8] = {
1963	serge	2314	dfixed_init(0),
		2315	dfixed_init(1),
		2316	dfixed_init(2),
		2317	dfixed_init(3),
		2318	dfixed_init(0),
		2319	dfixed_init_half(1),
		2320	dfixed_init_half(2),
		2321	dfixed_init_half(3),
1179	serge	2322	};
		2323	fixed20_12 memtcas2_ff[8] = {
1963	serge	2324	dfixed_init(0),
		2325	dfixed_init(1),
		2326	dfixed_init(2),
		2327	dfixed_init(3),
		2328	dfixed_init(4),
		2329	dfixed_init(5),
		2330	dfixed_init(6),
		2331	dfixed_init(7),
1179	serge	2332	};
		2333	fixed20_12 memtrbs[8] = {
1963	serge	2334	dfixed_init(1),
		2335	dfixed_init_half(1),
		2336	dfixed_init(2),
		2337	dfixed_init_half(2),
		2338	dfixed_init(3),
		2339	dfixed_init_half(3),
		2340	dfixed_init(4),
		2341	dfixed_init_half(4)
1179	serge	2342	};
		2343	fixed20_12 memtrbs_r4xx[8] = {
1963	serge	2344	dfixed_init(4),
		2345	dfixed_init(5),
		2346	dfixed_init(6),
		2347	dfixed_init(7),
		2348	dfixed_init(8),
		2349	dfixed_init(9),
		2350	dfixed_init(10),
		2351	dfixed_init(11)
1179	serge	2352	};
		2353	fixed20_12 min_mem_eff;
		2354	fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
		2355	fixed20_12 cur_latency_mclk, cur_latency_sclk;
		2356	fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
		2357	disp_drain_rate2, read_return_rate;
		2358	fixed20_12 time_disp1_drop_priority;
		2359	int c;
		2360	int cur_size = 16; /* in octawords */
		2361	int critical_point = 0, critical_point2;
		2362	/* uint32_t read_return_rate, time_disp1_drop_priority; */
		2363	int stop_req, max_stop_req;
		2364	struct drm_display_mode *mode1 = NULL;
		2365	struct drm_display_mode *mode2 = NULL;
		2366	uint32_t pixel_bytes1 = 0;
		2367	uint32_t pixel_bytes2 = 0;
		2368
1963	serge	2369	radeon_update_display_priority(rdev);
		2370
1179	serge	2371	if (rdev->mode_info.crtcs[0]->base.enabled) {
		2372	mode1 = &rdev->mode_info.crtcs[0]->base.mode;
		2373	pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
		2374	}
1221	serge	2375	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
1179	serge	2376	if (rdev->mode_info.crtcs[1]->base.enabled) {
		2377	mode2 = &rdev->mode_info.crtcs[1]->base.mode;
		2378	pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
		2379	}
1221	serge	2380	}
1179	serge	2381
1963	serge	2382	min_mem_eff.full = dfixed_const_8(0);
1179	serge	2383	/* get modes */
		2384	if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
		2385	uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
		2386	mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
		2387	mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
		2388	/* check crtc enables */
		2389	if (mode2)
		2390	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
		2391	if (mode1)
		2392	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
		2393	WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
		2394	}
		2395
		2396	/*
		2397	* determine is there is enough bw for current mode
		2398	*/
1963	serge	2399	sclk_ff = rdev->pm.sclk;
		2400	mclk_ff = rdev->pm.mclk;
1179	serge	2401
		2402	temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
1963	serge	2403	temp_ff.full = dfixed_const(temp);
		2404	mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
1179	serge	2405
		2406	pix_clk.full = 0;
		2407	pix_clk2.full = 0;
		2408	peak_disp_bw.full = 0;
		2409	if (mode1) {
1963	serge	2410	temp_ff.full = dfixed_const(1000);
		2411	pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
		2412	pix_clk.full = dfixed_div(pix_clk, temp_ff);
		2413	temp_ff.full = dfixed_const(pixel_bytes1);
		2414	peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
1179	serge	2415	}
		2416	if (mode2) {
1963	serge	2417	temp_ff.full = dfixed_const(1000);
		2418	pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
		2419	pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
		2420	temp_ff.full = dfixed_const(pixel_bytes2);
		2421	peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
1179	serge	2422	}
		2423
1963	serge	2424	mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
1179	serge	2425	if (peak_disp_bw.full >= mem_bw.full) {
		2426	DRM_ERROR("You may not have enough display bandwidth for current mode\n"
		2427	"If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
		2428	}
		2429
		2430	/* Get values from the EXT_MEM_CNTL register...converting its contents. */
		2431	temp = RREG32(RADEON_MEM_TIMING_CNTL);
		2432	if ((rdev->family == CHIP_RV100) \|\| (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
		2433	mem_trcd = ((temp >> 2) & 0x3) + 1;
		2434	mem_trp = ((temp & 0x3)) + 1;
		2435	mem_tras = ((temp & 0x70) >> 4) + 1;
		2436	} else if (rdev->family == CHIP_R300 \|\|
		2437	rdev->family == CHIP_R350) { /* r300, r350 */
		2438	mem_trcd = (temp & 0x7) + 1;
		2439	mem_trp = ((temp >> 8) & 0x7) + 1;
		2440	mem_tras = ((temp >> 11) & 0xf) + 4;
		2441	} else if (rdev->family == CHIP_RV350 \|\|
		2442	rdev->family <= CHIP_RV380) {
		2443	/* rv3x0 */
		2444	mem_trcd = (temp & 0x7) + 3;
		2445	mem_trp = ((temp >> 8) & 0x7) + 3;
		2446	mem_tras = ((temp >> 11) & 0xf) + 6;
		2447	} else if (rdev->family == CHIP_R420 \|\|
		2448	rdev->family == CHIP_R423 \|\|
		2449	rdev->family == CHIP_RV410) {
		2450	/* r4xx */
		2451	mem_trcd = (temp & 0xf) + 3;
		2452	if (mem_trcd > 15)
		2453	mem_trcd = 15;
		2454	mem_trp = ((temp >> 8) & 0xf) + 3;
		2455	if (mem_trp > 15)
		2456	mem_trp = 15;
		2457	mem_tras = ((temp >> 12) & 0x1f) + 6;
		2458	if (mem_tras > 31)
		2459	mem_tras = 31;
		2460	} else { /* RV200, R200 */
		2461	mem_trcd = (temp & 0x7) + 1;
		2462	mem_trp = ((temp >> 8) & 0x7) + 1;
		2463	mem_tras = ((temp >> 12) & 0xf) + 4;
		2464	}
		2465	/* convert to FF */
1963	serge	2466	trcd_ff.full = dfixed_const(mem_trcd);
		2467	trp_ff.full = dfixed_const(mem_trp);
		2468	tras_ff.full = dfixed_const(mem_tras);
1179	serge	2469
		2470	/* Get values from the MEM_SDRAM_MODE_REG register...converting its */
		2471	temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		2472	data = (temp & (7 << 20)) >> 20;
		2473	if ((rdev->family == CHIP_RV100) \|\| rdev->flags & RADEON_IS_IGP) {
		2474	if (rdev->family == CHIP_RS480) /* don't think rs400 */
		2475	tcas_ff = memtcas_rs480_ff[data];
		2476	else
		2477	tcas_ff = memtcas_ff[data];
		2478	} else
		2479	tcas_ff = memtcas2_ff[data];
		2480
		2481	if (rdev->family == CHIP_RS400 \|\|
		2482	rdev->family == CHIP_RS480) {
		2483	/* extra cas latency stored in bits 23-25 0-4 clocks */
		2484	data = (temp >> 23) & 0x7;
		2485	if (data < 5)
1963	serge	2486	tcas_ff.full += dfixed_const(data);
1179	serge	2487	}
		2488
		2489	if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
		2490	/* on the R300, Tcas is included in Trbs.
		2491	*/
		2492	temp = RREG32(RADEON_MEM_CNTL);
		2493	data = (R300_MEM_NUM_CHANNELS_MASK & temp);
		2494	if (data == 1) {
		2495	if (R300_MEM_USE_CD_CH_ONLY & temp) {
		2496	temp = RREG32(R300_MC_IND_INDEX);
		2497	temp &= ~R300_MC_IND_ADDR_MASK;
		2498	temp \|= R300_MC_READ_CNTL_CD_mcind;
		2499	WREG32(R300_MC_IND_INDEX, temp);
		2500	temp = RREG32(R300_MC_IND_DATA);
		2501	data = (R300_MEM_RBS_POSITION_C_MASK & temp);
		2502	} else {
		2503	temp = RREG32(R300_MC_READ_CNTL_AB);
		2504	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		2505	}
		2506	} else {
		2507	temp = RREG32(R300_MC_READ_CNTL_AB);
		2508	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		2509	}
		2510	if (rdev->family == CHIP_RV410 \|\|
		2511	rdev->family == CHIP_R420 \|\|
		2512	rdev->family == CHIP_R423)
		2513	trbs_ff = memtrbs_r4xx[data];
		2514	else
		2515	trbs_ff = memtrbs[data];
		2516	tcas_ff.full += trbs_ff.full;
		2517	}
		2518
		2519	sclk_eff_ff.full = sclk_ff.full;
		2520
		2521	if (rdev->flags & RADEON_IS_AGP) {
		2522	fixed20_12 agpmode_ff;
1963	serge	2523	agpmode_ff.full = dfixed_const(radeon_agpmode);
		2524	temp_ff.full = dfixed_const_666(16);
		2525	sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
1179	serge	2526	}
		2527	/* TODO PCIE lanes may affect this - agpmode == 16?? */
		2528
		2529	if (ASIC_IS_R300(rdev)) {
1963	serge	2530	sclk_delay_ff.full = dfixed_const(250);
1179	serge	2531	} else {
		2532	if ((rdev->family == CHIP_RV100) \|\|
		2533	rdev->flags & RADEON_IS_IGP) {
		2534	if (rdev->mc.vram_is_ddr)
1963	serge	2535	sclk_delay_ff.full = dfixed_const(41);
1179	serge	2536	else
1963	serge	2537	sclk_delay_ff.full = dfixed_const(33);
1179	serge	2538	} else {
		2539	if (rdev->mc.vram_width == 128)
1963	serge	2540	sclk_delay_ff.full = dfixed_const(57);
1179	serge	2541	else
1963	serge	2542	sclk_delay_ff.full = dfixed_const(41);
1179	serge	2543	}
		2544	}
		2545
1963	serge	2546	mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
1179	serge	2547
		2548	if (rdev->mc.vram_is_ddr) {
		2549	if (rdev->mc.vram_width == 32) {
1963	serge	2550	k1.full = dfixed_const(40);
1179	serge	2551	c = 3;
		2552	} else {
1963	serge	2553	k1.full = dfixed_const(20);
1179	serge	2554	c = 1;
		2555	}
		2556	} else {
1963	serge	2557	k1.full = dfixed_const(40);
1179	serge	2558	c = 3;
		2559	}
		2560
1963	serge	2561	temp_ff.full = dfixed_const(2);
		2562	mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
		2563	temp_ff.full = dfixed_const(c);
		2564	mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
		2565	temp_ff.full = dfixed_const(4);
		2566	mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
		2567	mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
1179	serge	2568	mc_latency_mclk.full += k1.full;
		2569
1963	serge	2570	mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
		2571	mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
1179	serge	2572
		2573	/*
		2574	HW cursor time assuming worst case of full size colour cursor.
		2575	*/
1963	serge	2576	temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
1179	serge	2577	temp_ff.full += trcd_ff.full;
		2578	if (temp_ff.full < tras_ff.full)
		2579	temp_ff.full = tras_ff.full;
1963	serge	2580	cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
1179	serge	2581
1963	serge	2582	temp_ff.full = dfixed_const(cur_size);
		2583	cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
1179	serge	2584	/*
		2585	Find the total latency for the display data.
		2586	*/
1963	serge	2587	disp_latency_overhead.full = dfixed_const(8);
		2588	disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
1179	serge	2589	mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
		2590	mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
		2591
		2592	if (mc_latency_mclk.full > mc_latency_sclk.full)
		2593	disp_latency.full = mc_latency_mclk.full;
		2594	else
		2595	disp_latency.full = mc_latency_sclk.full;
		2596
		2597	/* setup Max GRPH_STOP_REQ default value */
		2598	if (ASIC_IS_RV100(rdev))
		2599	max_stop_req = 0x5c;
		2600	else
		2601	max_stop_req = 0x7c;
		2602
		2603	if (mode1) {
		2604	/* CRTC1
		2605	Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
		2606	GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
		2607	*/
		2608	stop_req = mode1->hdisplay * pixel_bytes1 / 16;
		2609
		2610	if (stop_req > max_stop_req)
		2611	stop_req = max_stop_req;
		2612
		2613	/*
		2614	Find the drain rate of the display buffer.
		2615	*/
1963	serge	2616	temp_ff.full = dfixed_const((16/pixel_bytes1));
		2617	disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
1179	serge	2618
		2619	/*
		2620	Find the critical point of the display buffer.
		2621	*/
1963	serge	2622	crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
		2623	crit_point_ff.full += dfixed_const_half(0);
1179	serge	2624
1963	serge	2625	critical_point = dfixed_trunc(crit_point_ff);
1179	serge	2626
		2627	if (rdev->disp_priority == 2) {
		2628	critical_point = 0;
		2629	}
		2630
		2631	/*
		2632	The critical point should never be above max_stop_req-4. Setting
		2633	GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
		2634	*/
		2635	if (max_stop_req - critical_point < 4)
		2636	critical_point = 0;
		2637
		2638	if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
		2639	/* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
		2640	critical_point = 0x10;
		2641	}
		2642
		2643	temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
		2644	temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
		2645	temp \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		2646	temp &= ~(RADEON_GRPH_START_REQ_MASK);
		2647	if ((rdev->family == CHIP_R350) &&
		2648	(stop_req > 0x15)) {
		2649	stop_req -= 0x10;
		2650	}
		2651	temp \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		2652	temp \|= RADEON_GRPH_BUFFER_SIZE;
		2653	temp &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		2654	RADEON_GRPH_CRITICAL_AT_SOF \|
		2655	RADEON_GRPH_STOP_CNTL);
		2656	/*
		2657	Write the result into the register.
		2658	*/
		2659	WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		2660	(critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		2661
		2662	#if 0
		2663	if ((rdev->family == CHIP_RS400) \|\|
		2664	(rdev->family == CHIP_RS480)) {
		2665	/* attempt to program RS400 disp regs correctly ??? */
		2666	temp = RREG32(RS400_DISP1_REG_CNTL);
		2667	temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK \|
		2668	RS400_DISP1_STOP_REQ_LEVEL_MASK);
		2669	WREG32(RS400_DISP1_REQ_CNTL1, (temp \|
		2670	(critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		2671	(critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		2672	temp = RREG32(RS400_DMIF_MEM_CNTL1);
		2673	temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK \|
		2674	RS400_DISP1_CRITICAL_POINT_STOP_MASK);
		2675	WREG32(RS400_DMIF_MEM_CNTL1, (temp \|
		2676	(critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) \|
		2677	(critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
		2678	}
		2679	#endif
		2680
1963	serge	2681	DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
1179	serge	2682	/* (unsigned int)info->SavedReg->grph_buffer_cntl, */
		2683	(unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
		2684	}
		2685
		2686	if (mode2) {
		2687	u32 grph2_cntl;
		2688	stop_req = mode2->hdisplay * pixel_bytes2 / 16;
		2689
		2690	if (stop_req > max_stop_req)
		2691	stop_req = max_stop_req;
		2692
		2693	/*
		2694	Find the drain rate of the display buffer.
		2695	*/
1963	serge	2696	temp_ff.full = dfixed_const((16/pixel_bytes2));
		2697	disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
1179	serge	2698
		2699	grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
		2700	grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
		2701	grph2_cntl \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		2702	grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
		2703	if ((rdev->family == CHIP_R350) &&
		2704	(stop_req > 0x15)) {
		2705	stop_req -= 0x10;
		2706	}
		2707	grph2_cntl \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		2708	grph2_cntl \|= RADEON_GRPH_BUFFER_SIZE;
		2709	grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		2710	RADEON_GRPH_CRITICAL_AT_SOF \|
		2711	RADEON_GRPH_STOP_CNTL);
		2712
		2713	if ((rdev->family == CHIP_RS100) \|\|
		2714	(rdev->family == CHIP_RS200))
		2715	critical_point2 = 0;
		2716	else {
		2717	temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
1963	serge	2718	temp_ff.full = dfixed_const(temp);
		2719	temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
1179	serge	2720	if (sclk_ff.full < temp_ff.full)
		2721	temp_ff.full = sclk_ff.full;
		2722
		2723	read_return_rate.full = temp_ff.full;
		2724
		2725	if (mode1) {
		2726	temp_ff.full = read_return_rate.full - disp_drain_rate.full;
1963	serge	2727	time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
1179	serge	2728	} else {
		2729	time_disp1_drop_priority.full = 0;
		2730	}
		2731	crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
1963	serge	2732	crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
		2733	crit_point_ff.full += dfixed_const_half(0);
1179	serge	2734
1963	serge	2735	critical_point2 = dfixed_trunc(crit_point_ff);
1179	serge	2736
		2737	if (rdev->disp_priority == 2) {
		2738	critical_point2 = 0;
		2739	}
		2740
		2741	if (max_stop_req - critical_point2 < 4)
		2742	critical_point2 = 0;
		2743
		2744	}
		2745
		2746	if (critical_point2 == 0 && rdev->family == CHIP_R300) {
		2747	/* some R300 cards have problem with this set to 0 */
		2748	critical_point2 = 0x10;
		2749	}
		2750
		2751	WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		2752	(critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		2753
		2754	if ((rdev->family == CHIP_RS400) \|\|
		2755	(rdev->family == CHIP_RS480)) {
		2756	#if 0
		2757	/* attempt to program RS400 disp2 regs correctly ??? */
		2758	temp = RREG32(RS400_DISP2_REQ_CNTL1);
		2759	temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK \|
		2760	RS400_DISP2_STOP_REQ_LEVEL_MASK);
		2761	WREG32(RS400_DISP2_REQ_CNTL1, (temp \|
		2762	(critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		2763	(critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		2764	temp = RREG32(RS400_DISP2_REQ_CNTL2);
		2765	temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK \|
		2766	RS400_DISP2_CRITICAL_POINT_STOP_MASK);
		2767	WREG32(RS400_DISP2_REQ_CNTL2, (temp \|
		2768	(critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) \|
		2769	(critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
		2770	#endif
		2771	WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
		2772	WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
		2773	WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
		2774	WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
		2775	}
		2776
1963	serge	2777	DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
1179	serge	2778	(unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
		2779	}
		2780	}
		2781
1963	serge	2782	#if 0
		2783	static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
		2784	{
		2785	DRM_ERROR("pitch %d\n", t->pitch);
		2786	DRM_ERROR("use_pitch %d\n", t->use_pitch);
		2787	DRM_ERROR("width %d\n", t->width);
		2788	DRM_ERROR("width_11 %d\n", t->width_11);
		2789	DRM_ERROR("height %d\n", t->height);
		2790	DRM_ERROR("height_11 %d\n", t->height_11);
		2791	DRM_ERROR("num levels %d\n", t->num_levels);
		2792	DRM_ERROR("depth %d\n", t->txdepth);
		2793	DRM_ERROR("bpp %d\n", t->cpp);
		2794	DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
		2795	DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
		2796	DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
		2797	DRM_ERROR("compress format %d\n", t->compress_format);
		2798	}
1179	serge	2799
1963	serge	2800	static int r100_track_compress_size(int compress_format, int w, int h)
		2801	{
		2802	int block_width, block_height, block_bytes;
		2803	int wblocks, hblocks;
		2804	int min_wblocks;
		2805	int sz;
1179	serge	2806
1963	serge	2807	block_width = 4;
		2808	block_height = 4;
		2809
		2810	switch (compress_format) {
		2811	case R100_TRACK_COMP_DXT1:
		2812	block_bytes = 8;
		2813	min_wblocks = 4;
		2814	break;
		2815	default:
		2816	case R100_TRACK_COMP_DXT35:
		2817	block_bytes = 16;
		2818	min_wblocks = 2;
		2819	break;
		2820	}
		2821
		2822	hblocks = (h + block_height - 1) / block_height;
		2823	wblocks = (w + block_width - 1) / block_width;
		2824	if (wblocks < min_wblocks)
		2825	wblocks = min_wblocks;
		2826	sz = wblocks * hblocks * block_bytes;
		2827	return sz;
		2828	}
		2829
		2830	static int r100_cs_track_cube(struct radeon_device *rdev,
		2831	struct r100_cs_track *track, unsigned idx)
		2832	{
		2833	unsigned face, w, h;
		2834	struct radeon_bo *cube_robj;
		2835	unsigned long size;
		2836	unsigned compress_format = track->textures[idx].compress_format;
		2837
		2838	for (face = 0; face < 5; face++) {
		2839	cube_robj = track->textures[idx].cube_info[face].robj;
		2840	w = track->textures[idx].cube_info[face].width;
		2841	h = track->textures[idx].cube_info[face].height;
		2842
		2843	if (compress_format) {
		2844	size = r100_track_compress_size(compress_format, w, h);
		2845	} else
		2846	size = w * h;
		2847	size *= track->textures[idx].cpp;
		2848
		2849	size += track->textures[idx].cube_info[face].offset;
		2850
		2851	if (size > radeon_bo_size(cube_robj)) {
		2852	DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
		2853	size, radeon_bo_size(cube_robj));
		2854	r100_cs_track_texture_print(&track->textures[idx]);
		2855	return -1;
		2856	}
		2857	}
		2858	return 0;
		2859	}
		2860
		2861	static int r100_cs_track_texture_check(struct radeon_device *rdev,
		2862	struct r100_cs_track *track)
		2863	{
		2864	struct radeon_bo *robj;
		2865	unsigned long size;
		2866	unsigned u, i, w, h, d;
		2867	int ret;
		2868
		2869	for (u = 0; u < track->num_texture; u++) {
		2870	if (!track->textures[u].enabled)
		2871	continue;
		2872	if (track->textures[u].lookup_disable)
		2873	continue;
		2874	robj = track->textures[u].robj;
		2875	if (robj == NULL) {
		2876	DRM_ERROR("No texture bound to unit %u\n", u);
		2877	return -EINVAL;
		2878	}
		2879	size = 0;
		2880	for (i = 0; i <= track->textures[u].num_levels; i++) {
		2881	if (track->textures[u].use_pitch) {
		2882	if (rdev->family < CHIP_R300)
		2883	w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
		2884	else
		2885	w = track->textures[u].pitch / (1 << i);
		2886	} else {
		2887	w = track->textures[u].width;
		2888	if (rdev->family >= CHIP_RV515)
		2889	w \|= track->textures[u].width_11;
		2890	w = w / (1 << i);
		2891	if (track->textures[u].roundup_w)
		2892	w = roundup_pow_of_two(w);
		2893	}
		2894	h = track->textures[u].height;
		2895	if (rdev->family >= CHIP_RV515)
		2896	h \|= track->textures[u].height_11;
		2897	h = h / (1 << i);
		2898	if (track->textures[u].roundup_h)
		2899	h = roundup_pow_of_two(h);
		2900	if (track->textures[u].tex_coord_type == 1) {
		2901	d = (1 << track->textures[u].txdepth) / (1 << i);
		2902	if (!d)
		2903	d = 1;
		2904	} else {
		2905	d = 1;
		2906	}
		2907	if (track->textures[u].compress_format) {
		2908
		2909	size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
		2910	/* compressed textures are block based */
		2911	} else
		2912	size += w * h * d;
		2913	}
		2914	size *= track->textures[u].cpp;
		2915
		2916	switch (track->textures[u].tex_coord_type) {
		2917	case 0:
		2918	case 1:
		2919	break;
		2920	case 2:
		2921	if (track->separate_cube) {
		2922	ret = r100_cs_track_cube(rdev, track, u);
		2923	if (ret)
		2924	return ret;
		2925	} else
		2926	size *= 6;
		2927	break;
		2928	default:
		2929	DRM_ERROR("Invalid texture coordinate type %u for unit "
		2930	"%u\n", track->textures[u].tex_coord_type, u);
		2931	return -EINVAL;
		2932	}
		2933	if (size > radeon_bo_size(robj)) {
		2934	DRM_ERROR("Texture of unit %u needs %lu bytes but is "
		2935	"%lu\n", u, size, radeon_bo_size(robj));
		2936	r100_cs_track_texture_print(&track->textures[u]);
		2937	return -EINVAL;
		2938	}
		2939	}
		2940	return 0;
		2941	}
		2942
		2943	int r100_cs_track_check(struct radeon_device rdev, struct r100_cs_track track)
		2944	{
		2945	unsigned i;
		2946	unsigned long size;
		2947	unsigned prim_walk;
		2948	unsigned nverts;
		2949	unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
		2950
		2951	if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
		2952	!track->blend_read_enable)
		2953	num_cb = 0;
		2954
		2955	for (i = 0; i < num_cb; i++) {
		2956	if (track->cb[i].robj == NULL) {
		2957	DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
		2958	return -EINVAL;
		2959	}
		2960	size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
		2961	size += track->cb[i].offset;
		2962	if (size > radeon_bo_size(track->cb[i].robj)) {
		2963	DRM_ERROR("[drm] Buffer too small for color buffer %d "
		2964	"(need %lu have %lu) !\n", i, size,
		2965	radeon_bo_size(track->cb[i].robj));
		2966	DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
		2967	i, track->cb[i].pitch, track->cb[i].cpp,
		2968	track->cb[i].offset, track->maxy);
		2969	return -EINVAL;
		2970	}
		2971	}
		2972	track->cb_dirty = false;
		2973
		2974	if (track->zb_dirty && track->z_enabled) {
		2975	if (track->zb.robj == NULL) {
		2976	DRM_ERROR("[drm] No buffer for z buffer !\n");
		2977	return -EINVAL;
		2978	}
		2979	size = track->zb.pitch * track->zb.cpp * track->maxy;
		2980	size += track->zb.offset;
		2981	if (size > radeon_bo_size(track->zb.robj)) {
		2982	DRM_ERROR("[drm] Buffer too small for z buffer "
		2983	"(need %lu have %lu) !\n", size,
		2984	radeon_bo_size(track->zb.robj));
		2985	DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
		2986	track->zb.pitch, track->zb.cpp,
		2987	track->zb.offset, track->maxy);
		2988	return -EINVAL;
		2989	}
		2990	}
		2991	track->zb_dirty = false;
		2992
		2993	if (track->aa_dirty && track->aaresolve) {
		2994	if (track->aa.robj == NULL) {
		2995	DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
		2996	return -EINVAL;
		2997	}
		2998	/* I believe the format comes from colorbuffer0. */
		2999	size = track->aa.pitch * track->cb[0].cpp * track->maxy;
		3000	size += track->aa.offset;
		3001	if (size > radeon_bo_size(track->aa.robj)) {
		3002	DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
		3003	"(need %lu have %lu) !\n", i, size,
		3004	radeon_bo_size(track->aa.robj));
		3005	DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
		3006	i, track->aa.pitch, track->cb[0].cpp,
		3007	track->aa.offset, track->maxy);
		3008	return -EINVAL;
		3009	}
		3010	}
		3011	track->aa_dirty = false;
		3012
		3013	prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
		3014	if (track->vap_vf_cntl & (1 << 14)) {
		3015	nverts = track->vap_alt_nverts;
		3016	} else {
		3017	nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
		3018	}
		3019	switch (prim_walk) {
		3020	case 1:
		3021	for (i = 0; i < track->num_arrays; i++) {
		3022	size = track->arrays[i].esize * track->max_indx * 4;
		3023	if (track->arrays[i].robj == NULL) {
		3024	DRM_ERROR("(PW %u) Vertex array %u no buffer "
		3025	"bound\n", prim_walk, i);
		3026	return -EINVAL;
		3027	}
		3028	if (size > radeon_bo_size(track->arrays[i].robj)) {
		3029	dev_err(rdev->dev, "(PW %u) Vertex array %u "
		3030	"need %lu dwords have %lu dwords\n",
		3031	prim_walk, i, size >> 2,
		3032	radeon_bo_size(track->arrays[i].robj)
		3033	>> 2);
		3034	DRM_ERROR("Max indices %u\n", track->max_indx);
		3035	return -EINVAL;
		3036	}
		3037	}
		3038	break;
		3039	case 2:
		3040	for (i = 0; i < track->num_arrays; i++) {
		3041	size = track->arrays[i].esize * (nverts - 1) * 4;
		3042	if (track->arrays[i].robj == NULL) {
		3043	DRM_ERROR("(PW %u) Vertex array %u no buffer "
		3044	"bound\n", prim_walk, i);
		3045	return -EINVAL;
		3046	}
		3047	if (size > radeon_bo_size(track->arrays[i].robj)) {
		3048	dev_err(rdev->dev, "(PW %u) Vertex array %u "
		3049	"need %lu dwords have %lu dwords\n",
		3050	prim_walk, i, size >> 2,
		3051	radeon_bo_size(track->arrays[i].robj)
		3052	>> 2);
		3053	return -EINVAL;
		3054	}
		3055	}
		3056	break;
		3057	case 3:
		3058	size = track->vtx_size * nverts;
		3059	if (size != track->immd_dwords) {
		3060	DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
		3061	track->immd_dwords, size);
		3062	DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
		3063	nverts, track->vtx_size);
		3064	return -EINVAL;
		3065	}
		3066	break;
		3067	default:
		3068	DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
		3069	prim_walk);
		3070	return -EINVAL;
		3071	}
		3072
		3073	if (track->tex_dirty) {
		3074	track->tex_dirty = false;
		3075	return r100_cs_track_texture_check(rdev, track);
		3076	}
		3077	return 0;
		3078	}
		3079
		3080	void r100_cs_track_clear(struct radeon_device rdev, struct r100_cs_track track)
		3081	{
		3082	unsigned i, face;
		3083
		3084	track->cb_dirty = true;
		3085	track->zb_dirty = true;
		3086	track->tex_dirty = true;
		3087	track->aa_dirty = true;
		3088
		3089	if (rdev->family < CHIP_R300) {
		3090	track->num_cb = 1;
		3091	if (rdev->family <= CHIP_RS200)
		3092	track->num_texture = 3;
		3093	else
		3094	track->num_texture = 6;
		3095	track->maxy = 2048;
		3096	track->separate_cube = 1;
		3097	} else {
		3098	track->num_cb = 4;
		3099	track->num_texture = 16;
		3100	track->maxy = 4096;
		3101	track->separate_cube = 0;
		3102	track->aaresolve = false;
		3103	track->aa.robj = NULL;
		3104	}
		3105
		3106	for (i = 0; i < track->num_cb; i++) {
		3107	track->cb[i].robj = NULL;
		3108	track->cb[i].pitch = 8192;
		3109	track->cb[i].cpp = 16;
		3110	track->cb[i].offset = 0;
		3111	}
		3112	track->z_enabled = true;
		3113	track->zb.robj = NULL;
		3114	track->zb.pitch = 8192;
		3115	track->zb.cpp = 4;
		3116	track->zb.offset = 0;
		3117	track->vtx_size = 0x7F;
		3118	track->immd_dwords = 0xFFFFFFFFUL;
		3119	track->num_arrays = 11;
		3120	track->max_indx = 0x00FFFFFFUL;
		3121	for (i = 0; i < track->num_arrays; i++) {
		3122	track->arrays[i].robj = NULL;
		3123	track->arrays[i].esize = 0x7F;
		3124	}
		3125	for (i = 0; i < track->num_texture; i++) {
		3126	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
		3127	track->textures[i].pitch = 16536;
		3128	track->textures[i].width = 16536;
		3129	track->textures[i].height = 16536;
		3130	track->textures[i].width_11 = 1 << 11;
		3131	track->textures[i].height_11 = 1 << 11;
		3132	track->textures[i].num_levels = 12;
		3133	if (rdev->family <= CHIP_RS200) {
		3134	track->textures[i].tex_coord_type = 0;
		3135	track->textures[i].txdepth = 0;
		3136	} else {
		3137	track->textures[i].txdepth = 16;
		3138	track->textures[i].tex_coord_type = 1;
		3139	}
		3140	track->textures[i].cpp = 64;
		3141	track->textures[i].robj = NULL;
		3142	/* CS IB emission code makes sure texture unit are disabled */
		3143	track->textures[i].enabled = false;
		3144	track->textures[i].lookup_disable = false;
		3145	track->textures[i].roundup_w = true;
		3146	track->textures[i].roundup_h = true;
		3147	if (track->separate_cube)
		3148	for (face = 0; face < 5; face++) {
		3149	track->textures[i].cube_info[face].robj = NULL;
		3150	track->textures[i].cube_info[face].width = 16536;
		3151	track->textures[i].cube_info[face].height = 16536;
		3152	track->textures[i].cube_info[face].offset = 0;
		3153	}
		3154	}
		3155	}
		3156	#endif
		3157
1412	serge	3158	int r100_ring_test(struct radeon_device *rdev)
		3159	{
		3160	uint32_t scratch;
		3161	uint32_t tmp = 0;
		3162	unsigned i;
		3163	int r;
1179	serge	3164
1412	serge	3165	r = radeon_scratch_get(rdev, &scratch);
		3166	if (r) {
		3167	DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
		3168	return r;
		3169	}
		3170	WREG32(scratch, 0xCAFEDEAD);
		3171	r = radeon_ring_lock(rdev, 2);
		3172	if (r) {
		3173	DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
		3174	radeon_scratch_free(rdev, scratch);
		3175	return r;
		3176	}
		3177	radeon_ring_write(rdev, PACKET0(scratch, 0));
		3178	radeon_ring_write(rdev, 0xDEADBEEF);
		3179	radeon_ring_unlock_commit(rdev);
		3180	for (i = 0; i < rdev->usec_timeout; i++) {
		3181	tmp = RREG32(scratch);
		3182	if (tmp == 0xDEADBEEF) {
		3183	break;
		3184	}
		3185	DRM_UDELAY(1);
		3186	}
		3187	if (i < rdev->usec_timeout) {
		3188	DRM_INFO("ring test succeeded in %d usecs\n", i);
		3189	} else {
1963	serge	3190	DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1412	serge	3191	scratch, tmp);
		3192	r = -EINVAL;
		3193	}
		3194	radeon_scratch_free(rdev, scratch);
		3195	return r;
		3196	}
		3197
1963	serge	3198	#if 0
		3199
		3200	void r100_ring_ib_execute(struct radeon_device rdev, struct radeon_ib ib)
		3201	{
		3202	radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
		3203	radeon_ring_write(rdev, ib->gpu_addr);
		3204	radeon_ring_write(rdev, ib->length_dw);
		3205	}
		3206
		3207	int r100_ib_test(struct radeon_device *rdev)
		3208	{
		3209	struct radeon_ib *ib;
		3210	uint32_t scratch;
		3211	uint32_t tmp = 0;
		3212	unsigned i;
		3213	int r;
		3214
		3215	r = radeon_scratch_get(rdev, &scratch);
		3216	if (r) {
		3217	DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
		3218	return r;
		3219	}
		3220	WREG32(scratch, 0xCAFEDEAD);
		3221	r = radeon_ib_get(rdev, &ib);
		3222	if (r) {
		3223	return r;
		3224	}
		3225	ib->ptr[0] = PACKET0(scratch, 0);
		3226	ib->ptr[1] = 0xDEADBEEF;
		3227	ib->ptr[2] = PACKET2(0);
		3228	ib->ptr[3] = PACKET2(0);
		3229	ib->ptr[4] = PACKET2(0);
		3230	ib->ptr[5] = PACKET2(0);
		3231	ib->ptr[6] = PACKET2(0);
		3232	ib->ptr[7] = PACKET2(0);
		3233	ib->length_dw = 8;
		3234	r = radeon_ib_schedule(rdev, ib);
		3235	if (r) {
		3236	radeon_scratch_free(rdev, scratch);
		3237	radeon_ib_free(rdev, &ib);
		3238	return r;
		3239	}
		3240	r = radeon_fence_wait(ib->fence, false);
		3241	if (r) {
		3242	return r;
		3243	}
		3244	for (i = 0; i < rdev->usec_timeout; i++) {
		3245	tmp = RREG32(scratch);
		3246	if (tmp == 0xDEADBEEF) {
		3247	break;
		3248	}
		3249	DRM_UDELAY(1);
		3250	}
		3251	if (i < rdev->usec_timeout) {
		3252	DRM_INFO("ib test succeeded in %u usecs\n", i);
		3253	} else {
		3254	DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
		3255	scratch, tmp);
		3256	r = -EINVAL;
		3257	}
		3258	radeon_scratch_free(rdev, scratch);
		3259	radeon_ib_free(rdev, &ib);
		3260	return r;
		3261	}
		3262
		3263	void r100_ib_fini(struct radeon_device *rdev)
		3264	{
		3265	radeon_ib_pool_fini(rdev);
		3266	}
		3267
		3268	int r100_ib_init(struct radeon_device *rdev)
		3269	{
		3270	int r;
		3271
		3272	r = radeon_ib_pool_init(rdev);
		3273	if (r) {
		3274	dev_err(rdev->dev, "failed initializing IB pool (%d).\n", r);
		3275	r100_ib_fini(rdev);
		3276	return r;
		3277	}
		3278	r = r100_ib_test(rdev);
		3279	if (r) {
		3280	dev_err(rdev->dev, "failed testing IB (%d).\n", r);
		3281	r100_ib_fini(rdev);
		3282	return r;
		3283	}
		3284	return 0;
		3285	}
		3286	#endif
		3287
1179	serge	3288	void r100_mc_stop(struct radeon_device rdev, struct r100_mc_save save)
		3289	{
		3290	/* Shutdown CP we shouldn't need to do that but better be safe than
		3291	* sorry
		3292	*/
		3293	rdev->cp.ready = false;
		3294	WREG32(R_000740_CP_CSQ_CNTL, 0);
		3295
		3296	/* Save few CRTC registers */
1221	serge	3297	save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
1179	serge	3298	save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
		3299	save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
		3300	save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
		3301	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3302	save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
		3303	save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
		3304	}
		3305
		3306	/* Disable VGA aperture access */
1221	serge	3307	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
1179	serge	3308	/* Disable cursor, overlay, crtc */
		3309	WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET \| S_000260_CUR_LOCK(1));
		3310	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL \|
		3311	S_000054_CRTC_DISPLAY_DIS(1));
		3312	WREG32(R_000050_CRTC_GEN_CNTL,
		3313	(C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) \|
		3314	S_000050_CRTC_DISP_REQ_EN_B(1));
		3315	WREG32(R_000420_OV0_SCALE_CNTL,
		3316	C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
		3317	WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
		3318	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3319	WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET \|
		3320	S_000360_CUR2_LOCK(1));
		3321	WREG32(R_0003F8_CRTC2_GEN_CNTL,
		3322	(C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) \|
		3323	S_0003F8_CRTC2_DISPLAY_DIS(1) \|
		3324	S_0003F8_CRTC2_DISP_REQ_EN_B(1));
		3325	WREG32(R_000360_CUR2_OFFSET,
		3326	C_000360_CUR2_LOCK & save->CUR2_OFFSET);
		3327	}
		3328	}
		3329
		3330	void r100_mc_resume(struct radeon_device rdev, struct r100_mc_save save)
		3331	{
		3332	/* Update base address for crtc */
1430	serge	3333	WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
1179	serge	3334	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
1430	serge	3335	WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
1179	serge	3336	}
		3337	/* Restore CRTC registers */
1221	serge	3338	WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
1179	serge	3339	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
		3340	WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
		3341	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3342	WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
		3343	}
		3344	}
		3345
1221	serge	3346	void r100_vga_render_disable(struct radeon_device *rdev)
		3347	{
		3348	u32 tmp;
		3349
		3350	tmp = RREG8(R_0003C2_GENMO_WT);
		3351	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
		3352	}
		3353
		3354	static void r100_debugfs(struct radeon_device *rdev)
		3355	{
		3356	int r;
		3357
		3358	r = r100_debugfs_mc_info_init(rdev);
		3359	if (r)
		3360	dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		3361	}
		3362
		3363
1179	serge	3364	int drm_order(unsigned long size)
		3365	{
		3366	int order;
		3367	unsigned long tmp;
		3368
		3369	for (order = 0, tmp = size >> 1; tmp; tmp >>= 1, order++) ;
		3370
		3371	if (size & (size - 1))
		3372	++order;
		3373
		3374	return order;
		3375	}
		3376
1221	serge	3377	static void r100_mc_program(struct radeon_device *rdev)
		3378	{
		3379	struct r100_mc_save save;
		3380
		3381	/* Stops all mc clients */
		3382	r100_mc_stop(rdev, &save);
		3383	if (rdev->flags & RADEON_IS_AGP) {
		3384	WREG32(R_00014C_MC_AGP_LOCATION,
		3385	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		3386	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		3387	WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		3388	if (rdev->family > CHIP_RV200)
		3389	WREG32(R_00015C_AGP_BASE_2,
		3390	upper_32_bits(rdev->mc.agp_base) & 0xff);
		3391	} else {
		3392	WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		3393	WREG32(R_000170_AGP_BASE, 0);
		3394	if (rdev->family > CHIP_RV200)
		3395	WREG32(R_00015C_AGP_BASE_2, 0);
		3396	}
		3397	/* Wait for mc idle */
		3398	if (r100_mc_wait_for_idle(rdev))
		3399	dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
		3400	/* Program MC, should be a 32bits limited address space */
		3401	WREG32(R_000148_MC_FB_LOCATION,
		3402	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		3403	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		3404	r100_mc_resume(rdev, &save);
		3405	}
		3406
		3407	void r100_clock_startup(struct radeon_device *rdev)
		3408	{
		3409	u32 tmp;
		3410
		3411	if (radeon_dynclks != -1 && radeon_dynclks)
		3412	radeon_legacy_set_clock_gating(rdev, 1);
		3413	/* We need to force on some of the block */
		3414	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
		3415	tmp \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		3416	if ((rdev->family == CHIP_RV250) \|\| (rdev->family == CHIP_RV280))
		3417	tmp \|= S_00000D_FORCE_DISP1(1) \| S_00000D_FORCE_DISP2(1);
		3418	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
		3419	}
		3420
		3421	static int r100_startup(struct radeon_device *rdev)
		3422	{
		3423	int r;
		3424
1321	serge	3425	/* set common regs */
		3426	r100_set_common_regs(rdev);
		3427	/* program mc */
1221	serge	3428	r100_mc_program(rdev);
		3429	/* Resume clock */
		3430	r100_clock_startup(rdev);
		3431	/* Initialize GART (initialize after TTM so we can allocate
		3432	* memory through TTM but finalize after TTM) */
1321	serge	3433	r100_enable_bm(rdev);
1221	serge	3434	if (rdev->flags & RADEON_IS_PCI) {
		3435	r = r100_pci_gart_enable(rdev);
		3436	if (r)
		3437	return r;
		3438	}
		3439	/* Enable IRQ */
		3440	// r100_irq_set(rdev);
1404	serge	3441	rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1221	serge	3442	/* 1M ring buffer */
1412	serge	3443	r = r100_cp_init(rdev, 1024 * 1024);
		3444	if (r) {
1963	serge	3445	dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1412	serge	3446	return r;
		3447	}
1221	serge	3448	// r = r100_ib_init(rdev);
		3449	// if (r) {
		3450	// dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
		3451	// return r;
		3452	// }
		3453	return 0;
		3454	}
		3455
1963	serge	3456	/*
		3457	* Due to how kexec works, it can leave the hw fully initialised when it
		3458	* boots the new kernel. However doing our init sequence with the CP and
		3459	* WB stuff setup causes GPU hangs on the RN50 at least. So at startup
		3460	* do some quick sanity checks and restore sane values to avoid this
		3461	* problem.
		3462	*/
		3463	void r100_restore_sanity(struct radeon_device *rdev)
		3464	{
		3465	u32 tmp;
1221	serge	3466
1963	serge	3467	tmp = RREG32(RADEON_CP_CSQ_CNTL);
		3468	if (tmp) {
		3469	WREG32(RADEON_CP_CSQ_CNTL, 0);
		3470	}
		3471	tmp = RREG32(RADEON_CP_RB_CNTL);
		3472	if (tmp) {
		3473	WREG32(RADEON_CP_RB_CNTL, 0);
		3474	}
		3475	tmp = RREG32(RADEON_SCRATCH_UMSK);
		3476	if (tmp) {
		3477	WREG32(RADEON_SCRATCH_UMSK, 0);
		3478	}
		3479	}
1221	serge	3480
		3481	int r100_init(struct radeon_device *rdev)
		3482	{
		3483	int r;
		3484
		3485	/* Register debugfs file specific to this group of asics */
		3486	r100_debugfs(rdev);
		3487	/* Disable VGA */
		3488	r100_vga_render_disable(rdev);
		3489	/* Initialize scratch registers */
		3490	radeon_scratch_init(rdev);
		3491	/* Initialize surface registers */
		3492	radeon_surface_init(rdev);
1963	serge	3493	/* sanity check some register to avoid hangs like after kexec */
		3494	r100_restore_sanity(rdev);
1221	serge	3495	/* TODO: disable VGA need to use VGA request */
		3496	/* BIOS*/
		3497	if (!radeon_get_bios(rdev)) {
		3498	if (ASIC_IS_AVIVO(rdev))
		3499	return -EINVAL;
		3500	}
		3501	if (rdev->is_atom_bios) {
		3502	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		3503	return -EINVAL;
		3504	} else {
		3505	r = radeon_combios_init(rdev);
		3506	if (r)
		3507	return r;
		3508	}
		3509	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
1963	serge	3510	if (radeon_asic_reset(rdev)) {
1221	serge	3511	dev_warn(rdev->dev,
		3512	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		3513	RREG32(R_000E40_RBBM_STATUS),
		3514	RREG32(R_0007C0_CP_STAT));
		3515	}
		3516	/* check if cards are posted or not */
1321	serge	3517	if (radeon_boot_test_post_card(rdev) == false)
		3518	return -EINVAL;
1221	serge	3519	/* Set asic errata */
		3520	r100_errata(rdev);
		3521	/* Initialize clocks */
		3522	radeon_get_clock_info(rdev->ddev);
1430	serge	3523	/* initialize AGP */
		3524	if (rdev->flags & RADEON_IS_AGP) {
		3525	r = radeon_agp_init(rdev);
		3526	if (r) {
		3527	radeon_agp_disable(rdev);
		3528	}
		3529	}
		3530	/* initialize VRAM */
		3531	r100_mc_init(rdev);
1221	serge	3532	/* Fence driver */
		3533	// r = radeon_fence_driver_init(rdev);
		3534	// if (r)
		3535	// return r;
		3536	// r = radeon_irq_kms_init(rdev);
		3537	// if (r)
		3538	// return r;
		3539	/* Memory manager */
1321	serge	3540	r = radeon_bo_init(rdev);
1221	serge	3541	if (r)
		3542	return r;
		3543	if (rdev->flags & RADEON_IS_PCI) {
		3544	r = r100_pci_gart_init(rdev);
		3545	if (r)
		3546	return r;
		3547	}
		3548	r100_set_safe_registers(rdev);
		3549	rdev->accel_working = true;
		3550	r = r100_startup(rdev);
		3551	if (r) {
		3552	/* Somethings want wront with the accel init stop accel */
		3553	dev_err(rdev->dev, "Disabling GPU acceleration\n");
		3554	// r100_cp_fini(rdev);
		3555	// r100_wb_fini(rdev);
		3556	// r100_ib_fini(rdev);
		3557	if (rdev->flags & RADEON_IS_PCI)
		3558	r100_pci_gart_fini(rdev);
		3559	rdev->accel_working = false;
		3560	}
		3561	return 0;
		3562	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r100.c – Rev 1963