WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r100.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1179	serge	28	#include
1125	serge	29	#include "drmP.h"
		30	#include "drm.h"
1117	serge	31	#include "radeon_drm.h"
		32	#include "radeon_reg.h"
		33	#include "radeon.h"
1179	serge	34	#include "r100d.h"
1221	serge	35	#include "rs100d.h"
		36	#include "rv200d.h"
		37	#include "rv250d.h"
1117	serge	38
1221	serge	39	#include
		40
1179	serge	41	#include "r100_reg_safe.h"
		42	#include "rn50_reg_safe.h"
1221	serge	43
		44	/* Firmware Names */
		45	#define FIRMWARE_R100 "radeon/R100_cp.bin"
		46	#define FIRMWARE_R200 "radeon/R200_cp.bin"
		47	#define FIRMWARE_R300 "radeon/R300_cp.bin"
		48	#define FIRMWARE_R420 "radeon/R420_cp.bin"
		49	#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
		50	#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
		51	#define FIRMWARE_R520 "radeon/R520_cp.bin"
		52
		53	MODULE_FIRMWARE(FIRMWARE_R100);
		54	MODULE_FIRMWARE(FIRMWARE_R200);
		55	MODULE_FIRMWARE(FIRMWARE_R300);
		56	MODULE_FIRMWARE(FIRMWARE_R420);
		57	MODULE_FIRMWARE(FIRMWARE_RS690);
		58	MODULE_FIRMWARE(FIRMWARE_RS600);
		59	MODULE_FIRMWARE(FIRMWARE_R520);
		60
		61
1117	serge	62	/* This files gather functions specifics to:
		63	* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
		64	*/
		65
1321	serge	66	/* hpd for digital panel detect/disconnect */
		67	bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
		68	{
		69	bool connected = false;
		70
		71	switch (hpd) {
		72	case RADEON_HPD_1:
		73	if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
		74	connected = true;
		75	break;
		76	case RADEON_HPD_2:
		77	if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
		78	connected = true;
		79	break;
		80	default:
		81	break;
		82	}
		83	return connected;
		84	}
		85
		86	void r100_hpd_set_polarity(struct radeon_device *rdev,
		87	enum radeon_hpd_id hpd)
		88	{
		89	u32 tmp;
		90	bool connected = r100_hpd_sense(rdev, hpd);
		91
		92	switch (hpd) {
		93	case RADEON_HPD_1:
		94	tmp = RREG32(RADEON_FP_GEN_CNTL);
		95	if (connected)
		96	tmp &= ~RADEON_FP_DETECT_INT_POL;
		97	else
		98	tmp \|= RADEON_FP_DETECT_INT_POL;
		99	WREG32(RADEON_FP_GEN_CNTL, tmp);
		100	break;
		101	case RADEON_HPD_2:
		102	tmp = RREG32(RADEON_FP2_GEN_CNTL);
		103	if (connected)
		104	tmp &= ~RADEON_FP2_DETECT_INT_POL;
		105	else
		106	tmp \|= RADEON_FP2_DETECT_INT_POL;
		107	WREG32(RADEON_FP2_GEN_CNTL, tmp);
		108	break;
		109	default:
		110	break;
		111	}
		112	}
		113
		114	void r100_hpd_init(struct radeon_device *rdev)
		115	{
		116	struct drm_device *dev = rdev->ddev;
		117	struct drm_connector *connector;
		118
		119	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		120	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		121	switch (radeon_connector->hpd.hpd) {
		122	case RADEON_HPD_1:
1403	serge	123	// rdev->irq.hpd[0] = true;
1321	serge	124	break;
		125	case RADEON_HPD_2:
1403	serge	126	// rdev->irq.hpd[1] = true;
1321	serge	127	break;
		128	default:
		129	break;
		130	}
		131	}
1403	serge	132	// if (rdev->irq.installed)
		133	// r100_irq_set(rdev);
1321	serge	134	}
		135
		136	void r100_hpd_fini(struct radeon_device *rdev)
		137	{
		138	struct drm_device *dev = rdev->ddev;
		139	struct drm_connector *connector;
		140
		141	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		142	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		143	switch (radeon_connector->hpd.hpd) {
		144	case RADEON_HPD_1:
1403	serge	145	// rdev->irq.hpd[0] = false;
1321	serge	146	break;
		147	case RADEON_HPD_2:
1403	serge	148	// rdev->irq.hpd[1] = false;
1321	serge	149	break;
		150	default:
		151	break;
		152	}
		153	}
		154	}
		155
1117	serge	156	/*
		157	* PCI GART
		158	*/
		159	void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
		160	{
		161	/* TODO: can we do somethings here ? */
		162	/* It seems hw only cache one entry so we should discard this
		163	* entry otherwise if first GPU GART read hit this entry it
		164	* could end up in wrong address. */
		165	}
		166
1179	serge	167	int r100_pci_gart_init(struct radeon_device *rdev)
1117	serge	168	{
		169	int r;
		170
1179	serge	171	if (rdev->gart.table.ram.ptr) {
		172	WARN(1, "R100 PCI GART already initialized.\n");
		173	return 0;
		174	}
1117	serge	175	/* Initialize common gart structure */
		176	r = radeon_gart_init(rdev);
1179	serge	177	if (r)
1117	serge	178	return r;
1268	serge	179	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
1179	serge	180	rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
		181	rdev->asic->gart_set_page = &r100_pci_gart_set_page;
		182	return radeon_gart_table_ram_alloc(rdev);
		183	}
		184
1321	serge	185	/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
		186	void r100_enable_bm(struct radeon_device *rdev)
		187	{
		188	uint32_t tmp;
		189	/* Enable bus mastering */
		190	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
		191	WREG32(RADEON_BUS_CNTL, tmp);
		192	}
		193
1179	serge	194	int r100_pci_gart_enable(struct radeon_device *rdev)
		195	{
		196	uint32_t tmp;
		197
1117	serge	198	/* discard memory request outside of configured range */
		199	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		200	WREG32(RADEON_AIC_CNTL, tmp);
		201	/* set address range for PCI address translate */
		202	WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
		203	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
		204	WREG32(RADEON_AIC_HI_ADDR, tmp);
		205	/* set PCI GART page-table base address */
		206	WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
		207	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_PCIGART_TRANSLATE_EN;
		208	WREG32(RADEON_AIC_CNTL, tmp);
		209	r100_pci_gart_tlb_flush(rdev);
		210	rdev->gart.ready = true;
		211	return 0;
		212	}
		213
		214	void r100_pci_gart_disable(struct radeon_device *rdev)
		215	{
		216	uint32_t tmp;
		217
		218	/* discard memory request outside of configured range */
		219	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		220	WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
		221	WREG32(RADEON_AIC_LO_ADDR, 0);
		222	WREG32(RADEON_AIC_HI_ADDR, 0);
		223	}
		224
		225	int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
		226	{
		227	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
		228	return -EINVAL;
		229	}
1179	serge	230	rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
1117	serge	231	return 0;
		232	}
		233
1179	serge	234	void r100_pci_gart_fini(struct radeon_device *rdev)
1117	serge	235	{
		236	r100_pci_gart_disable(rdev);
1179	serge	237	radeon_gart_table_ram_free(rdev);
		238	radeon_gart_fini(rdev);
1117	serge	239	}
		240
		241
1221	serge	242	void r100_irq_disable(struct radeon_device *rdev)
1117	serge	243	{
1221	serge	244	u32 tmp;
1117	serge	245
1221	serge	246	WREG32(R_000040_GEN_INT_CNTL, 0);
		247	/* Wait and acknowledge irq */
		248	mdelay(1);
		249	tmp = RREG32(R_000044_GEN_INT_STATUS);
		250	WREG32(R_000044_GEN_INT_STATUS, tmp);
1117	serge	251	}
		252
1221	serge	253	static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
1117	serge	254	{
1221	serge	255	uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
1321	serge	256	uint32_t irq_mask = RADEON_SW_INT_TEST \|
		257	RADEON_CRTC_VBLANK_STAT \| RADEON_CRTC2_VBLANK_STAT \|
		258	RADEON_FP_DETECT_STAT \| RADEON_FP2_DETECT_STAT;
1117	serge	259
1221	serge	260	if (irqs) {
		261	WREG32(RADEON_GEN_INT_STATUS, irqs);
1129	serge	262	}
1221	serge	263	return irqs & irq_mask;
1117	serge	264	}
		265
		266
1403	serge	267	u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
		268	{
		269	if (crtc == 0)
		270	return RREG32(RADEON_CRTC_CRNT_FRAME);
		271	else
		272	return RREG32(RADEON_CRTC2_CRNT_FRAME);
		273	}
1117	serge	274
		275	void r100_fence_ring_emit(struct radeon_device *rdev,
		276	struct radeon_fence *fence)
		277	{
		278	/* Who ever call radeon_fence_emit should call ring_lock and ask
		279	* for enough space (today caller are ib schedule and buffer move) */
		280	/* Wait until IDLE & CLEAN */
		281	radeon_ring_write(rdev, PACKET0(0x1720, 0));
		282	radeon_ring_write(rdev, (1 << 16) \| (1 << 17));
1403	serge	283	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		284	radeon_ring_write(rdev, rdev->config.r100.hdp_cntl \|
		285	RADEON_HDP_READ_BUFFER_INVALIDATE);
		286	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		287	radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
1117	serge	288	/* Emit fence sequence & fire IRQ */
		289	radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
		290	radeon_ring_write(rdev, fence->seq);
		291	radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
		292	radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
		293	}
		294
1128	serge	295	#if 0
1117	serge	296	/*
		297	* Writeback
		298	*/
		299	int r100_wb_init(struct radeon_device *rdev)
		300	{
		301	int r;
		302
		303	if (rdev->wb.wb_obj == NULL) {
1321	serge	304	r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1117	serge	305	RADEON_GEM_DOMAIN_GTT,
1321	serge	306	&rdev->wb.wb_obj);
1117	serge	307	if (r) {
1321	serge	308	dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
1117	serge	309	return r;
		310	}
1321	serge	311	r = radeon_bo_reserve(rdev->wb.wb_obj, false);
		312	if (unlikely(r != 0))
		313	return r;
		314	r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1117	serge	315	&rdev->wb.gpu_addr);
		316	if (r) {
1321	serge	317	dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
		318	radeon_bo_unreserve(rdev->wb.wb_obj);
1117	serge	319	return r;
		320	}
1321	serge	321	r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
		322	radeon_bo_unreserve(rdev->wb.wb_obj);
1117	serge	323	if (r) {
1321	serge	324	dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
1117	serge	325	return r;
		326	}
		327	}
1179	serge	328	WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
		329	WREG32(R_00070C_CP_RB_RPTR_ADDR,
		330	S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
		331	WREG32(R_000770_SCRATCH_UMSK, 0xff);
1117	serge	332	return 0;
		333	}
		334
1179	serge	335	void r100_wb_disable(struct radeon_device *rdev)
		336	{
		337	WREG32(R_000770_SCRATCH_UMSK, 0);
		338	}
		339
1117	serge	340	void r100_wb_fini(struct radeon_device *rdev)
		341	{
1321	serge	342	int r;
		343
1179	serge	344	r100_wb_disable(rdev);
1117	serge	345	if (rdev->wb.wb_obj) {
1120	serge	346	// radeon_object_kunmap(rdev->wb.wb_obj);
		347	// radeon_object_unpin(rdev->wb.wb_obj);
		348	// radeon_object_unref(&rdev->wb.wb_obj);
1117	serge	349	rdev->wb.wb = NULL;
		350	rdev->wb.wb_obj = NULL;
		351	}
		352	}
		353
		354	int r100_copy_blit(struct radeon_device *rdev,
		355	uint64_t src_offset,
		356	uint64_t dst_offset,
		357	unsigned num_pages,
		358	struct radeon_fence *fence)
		359	{
		360	uint32_t cur_pages;
		361	uint32_t stride_bytes = PAGE_SIZE;
		362	uint32_t pitch;
		363	uint32_t stride_pixels;
		364	unsigned ndw;
		365	int num_loops;
		366	int r = 0;
		367
		368	/* radeon limited to 16k stride */
		369	stride_bytes &= 0x3fff;
		370	/* radeon pitch is /64 */
		371	pitch = stride_bytes / 64;
		372	stride_pixels = stride_bytes / 4;
		373	num_loops = DIV_ROUND_UP(num_pages, 8191);
		374
		375	/* Ask for enough room for blit + flush + fence */
		376	ndw = 64 + (10 * num_loops);
		377	r = radeon_ring_lock(rdev, ndw);
		378	if (r) {
		379	DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
		380	return -EINVAL;
		381	}
		382	while (num_pages > 0) {
		383	cur_pages = num_pages;
		384	if (cur_pages > 8191) {
		385	cur_pages = 8191;
		386	}
		387	num_pages -= cur_pages;
		388
		389	/* pages are in Y direction - height
		390	page width in X direction - width */
		391	radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
		392	radeon_ring_write(rdev,
		393	RADEON_GMC_SRC_PITCH_OFFSET_CNTL \|
		394	RADEON_GMC_DST_PITCH_OFFSET_CNTL \|
		395	RADEON_GMC_SRC_CLIPPING \|
		396	RADEON_GMC_DST_CLIPPING \|
		397	RADEON_GMC_BRUSH_NONE \|
		398	(RADEON_COLOR_FORMAT_ARGB8888 << 8) \|
		399	RADEON_GMC_SRC_DATATYPE_COLOR \|
		400	RADEON_ROP3_S \|
		401	RADEON_DP_SRC_SOURCE_MEMORY \|
		402	RADEON_GMC_CLR_CMP_CNTL_DIS \|
		403	RADEON_GMC_WR_MSK_DIS);
		404	radeon_ring_write(rdev, (pitch << 22) \| (src_offset >> 10));
		405	radeon_ring_write(rdev, (pitch << 22) \| (dst_offset >> 10));
		406	radeon_ring_write(rdev, (0x1fff) \| (0x1fff << 16));
		407	radeon_ring_write(rdev, 0);
		408	radeon_ring_write(rdev, (0x1fff) \| (0x1fff << 16));
		409	radeon_ring_write(rdev, num_pages);
		410	radeon_ring_write(rdev, num_pages);
		411	radeon_ring_write(rdev, cur_pages \| (stride_pixels << 16));
		412	}
		413	radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
		414	radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
		415	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		416	radeon_ring_write(rdev,
		417	RADEON_WAIT_2D_IDLECLEAN \|
		418	RADEON_WAIT_HOST_IDLECLEAN \|
		419	RADEON_WAIT_DMA_GUI_IDLE);
		420	if (fence) {
		421	r = radeon_fence_emit(rdev, fence);
		422	}
		423	radeon_ring_unlock_commit(rdev);
		424	return r;
		425	}
		426
1128	serge	427	#endif
1117	serge	428
1221	serge	429
1179	serge	430	static int r100_cp_wait_for_idle(struct radeon_device *rdev)
		431	{
		432	unsigned i;
		433	u32 tmp;
		434
		435	for (i = 0; i < rdev->usec_timeout; i++) {
		436	tmp = RREG32(R_000E40_RBBM_STATUS);
		437	if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
		438	return 0;
		439	}
		440	udelay(1);
		441	}
		442	return -1;
		443	}
		444
1117	serge	445	void r100_ring_start(struct radeon_device *rdev)
		446	{
		447	int r;
		448
		449	r = radeon_ring_lock(rdev, 2);
		450	if (r) {
		451	return;
		452	}
		453	radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
		454	radeon_ring_write(rdev,
		455	RADEON_ISYNC_ANY2D_IDLE3D \|
		456	RADEON_ISYNC_ANY3D_IDLE2D \|
		457	RADEON_ISYNC_WAIT_IDLEGUI \|
		458	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
		459	radeon_ring_unlock_commit(rdev);
		460	}
		461
1221	serge	462
		463	/* Load the microcode for the CP */
		464	static int r100_cp_init_microcode(struct radeon_device *rdev)
1117	serge	465	{
1221	serge	466	struct platform_device *pdev;
		467	const char *fw_name = NULL;
		468	int err;
1117	serge	469
1221	serge	470	DRM_DEBUG("\n");
1117	serge	471
1221	serge	472	// pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
		473	// err = IS_ERR(pdev);
		474	// if (err) {
		475	// printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
		476	// return -EINVAL;
		477	// }
1117	serge	478	if ((rdev->family == CHIP_R100) \|\| (rdev->family == CHIP_RV100) \|\|
		479	(rdev->family == CHIP_RV200) \|\| (rdev->family == CHIP_RS100) \|\|
		480	(rdev->family == CHIP_RS200)) {
		481	DRM_INFO("Loading R100 Microcode\n");
1221	serge	482	fw_name = FIRMWARE_R100;
1117	serge	483	} else if ((rdev->family == CHIP_R200) \|\|
		484	(rdev->family == CHIP_RV250) \|\|
		485	(rdev->family == CHIP_RV280) \|\|
		486	(rdev->family == CHIP_RS300)) {
		487	DRM_INFO("Loading R200 Microcode\n");
1221	serge	488	fw_name = FIRMWARE_R200;
1117	serge	489	} else if ((rdev->family == CHIP_R300) \|\|
		490	(rdev->family == CHIP_R350) \|\|
		491	(rdev->family == CHIP_RV350) \|\|
		492	(rdev->family == CHIP_RV380) \|\|
		493	(rdev->family == CHIP_RS400) \|\|
		494	(rdev->family == CHIP_RS480)) {
		495	DRM_INFO("Loading R300 Microcode\n");
1221	serge	496	fw_name = FIRMWARE_R300;
1117	serge	497	} else if ((rdev->family == CHIP_R420) \|\|
		498	(rdev->family == CHIP_R423) \|\|
		499	(rdev->family == CHIP_RV410)) {
		500	DRM_INFO("Loading R400 Microcode\n");
1221	serge	501	fw_name = FIRMWARE_R420;
1117	serge	502	} else if ((rdev->family == CHIP_RS690) \|\|
		503	(rdev->family == CHIP_RS740)) {
		504	DRM_INFO("Loading RS690/RS740 Microcode\n");
1221	serge	505	fw_name = FIRMWARE_RS690;
1117	serge	506	} else if (rdev->family == CHIP_RS600) {
		507	DRM_INFO("Loading RS600 Microcode\n");
1221	serge	508	fw_name = FIRMWARE_RS600;
1117	serge	509	} else if ((rdev->family == CHIP_RV515) \|\|
		510	(rdev->family == CHIP_R520) \|\|
		511	(rdev->family == CHIP_RV530) \|\|
		512	(rdev->family == CHIP_R580) \|\|
		513	(rdev->family == CHIP_RV560) \|\|
		514	(rdev->family == CHIP_RV570)) {
		515	DRM_INFO("Loading R500 Microcode\n");
1221	serge	516	fw_name = FIRMWARE_R520;
1117	serge	517	}
1221	serge	518
		519	// err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
		520	// platform_device_unregister(pdev);
		521	if (err) {
		522	printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
		523	fw_name);
		524	} else if (rdev->me_fw->size % 8) {
		525	printk(KERN_ERR
		526	"radeon_cp: Bogus length %zu in firmware \"%s\"\n",
		527	rdev->me_fw->size, fw_name);
		528	err = -EINVAL;
		529	release_firmware(rdev->me_fw);
		530	rdev->me_fw = NULL;
1117	serge	531	}
1221	serge	532	return err;
1117	serge	533	}
		534
1179	serge	535
1221	serge	536	static void r100_cp_load_microcode(struct radeon_device *rdev)
		537	{
		538	const __be32 *fw_data;
		539	int i, size;
		540
		541	if (r100_gui_wait_for_idle(rdev)) {
		542	printk(KERN_WARNING "Failed to wait GUI idle while "
		543	"programming pipes. Bad things might happen.\n");
		544	}
		545
		546	if (rdev->me_fw) {
		547	size = rdev->me_fw->size / 4;
		548	fw_data = (const __be32 *)&rdev->me_fw->data[0];
		549	WREG32(RADEON_CP_ME_RAM_ADDR, 0);
		550	for (i = 0; i < size; i += 2) {
		551	WREG32(RADEON_CP_ME_RAM_DATAH,
		552	be32_to_cpup(&fw_data[i]));
		553	WREG32(RADEON_CP_ME_RAM_DATAL,
		554	be32_to_cpup(&fw_data[i + 1]));
		555	}
		556	}
		557	}
		558
1117	serge	559	int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
		560	{
		561	unsigned rb_bufsz;
		562	unsigned rb_blksz;
		563	unsigned max_fetch;
		564	unsigned pre_write_timer;
		565	unsigned pre_write_limit;
		566	unsigned indirect2_start;
		567	unsigned indirect1_start;
		568	uint32_t tmp;
		569	int r;
		570
1129	serge	571	if (r100_debugfs_cp_init(rdev)) {
		572	DRM_ERROR("Failed to register debugfs file for CP !\n");
		573	}
1117	serge	574	/* Reset CP */
		575	tmp = RREG32(RADEON_CP_CSQ_STAT);
		576	if ((tmp & (1 << 31))) {
		577	DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
		578	WREG32(RADEON_CP_CSQ_MODE, 0);
		579	WREG32(RADEON_CP_CSQ_CNTL, 0);
		580	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
		581	tmp = RREG32(RADEON_RBBM_SOFT_RESET);
		582	mdelay(2);
		583	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		584	tmp = RREG32(RADEON_RBBM_SOFT_RESET);
		585	mdelay(2);
		586	tmp = RREG32(RADEON_CP_CSQ_STAT);
		587	if ((tmp & (1 << 31))) {
		588	DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
		589	}
		590	} else {
		591	DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
		592	}
1179	serge	593
		594	if (!rdev->me_fw) {
		595	r = r100_cp_init_microcode(rdev);
		596	if (r) {
		597	DRM_ERROR("Failed to load firmware!\n");
		598	return r;
		599	}
		600	}
		601
1117	serge	602	/* Align ring size */
		603	rb_bufsz = drm_order(ring_size / 8);
		604	ring_size = (1 << (rb_bufsz + 1)) * 4;
		605	r100_cp_load_microcode(rdev);
		606	r = radeon_ring_init(rdev, ring_size);
		607	if (r) {
		608	return r;
		609	}
		610	/* Each time the cp read 1024 bytes (16 dword/quadword) update
		611	* the rptr copy in system ram */
		612	rb_blksz = 9;
		613	/* cp will read 128bytes at a time (4 dwords) */
		614	max_fetch = 1;
		615	rdev->cp.align_mask = 16 - 1;
		616	/* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
		617	pre_write_timer = 64;
		618	/* Force CP_RB_WPTR write if written more than one time before the
		619	* delay expire
		620	*/
		621	pre_write_limit = 0;
		622	/* Setup the cp cache like this (cache size is 96 dwords) :
		623	* RING 0 to 15
		624	* INDIRECT1 16 to 79
		625	* INDIRECT2 80 to 95
		626	* So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		627	* indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
		628	* indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		629	* Idea being that most of the gpu cmd will be through indirect1 buffer
		630	* so it gets the bigger cache.
		631	*/
		632	indirect2_start = 80;
		633	indirect1_start = 16;
		634	/* cp setup */
		635	WREG32(0x718, pre_write_timer \| (pre_write_limit << 28));
1268	serge	636	tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) \|
1117	serge	637	REG_SET(RADEON_RB_BLKSZ, rb_blksz) \|
		638	REG_SET(RADEON_MAX_FETCH, max_fetch) \|
		639	RADEON_RB_NO_UPDATE);
1268	serge	640	#ifdef __BIG_ENDIAN
		641	tmp \|= RADEON_BUF_SWAP_32BIT;
		642	#endif
		643	WREG32(RADEON_CP_RB_CNTL, tmp);
		644
1117	serge	645	/* Set ring address */
		646	DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
		647	WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
		648	/* Force read & write ptr to 0 */
		649	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);
		650	WREG32(RADEON_CP_RB_RPTR_WR, 0);
		651	WREG32(RADEON_CP_RB_WPTR, 0);
		652	WREG32(RADEON_CP_RB_CNTL, tmp);
		653	udelay(10);
		654	rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
		655	rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
		656	/* Set cp mode to bus mastering & enable cp*/
		657	WREG32(RADEON_CP_CSQ_MODE,
		658	REG_SET(RADEON_INDIRECT2_START, indirect2_start) \|
		659	REG_SET(RADEON_INDIRECT1_START, indirect1_start));
		660	WREG32(0x718, 0);
		661	WREG32(0x744, 0x00004D4D);
		662	WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
		663	radeon_ring_start(rdev);
		664	r = radeon_ring_test(rdev);
		665	if (r) {
		666	DRM_ERROR("radeon: cp isn't working (%d).\n", r);
		667	return r;
		668	}
		669	rdev->cp.ready = true;
		670	return 0;
		671	}
		672
		673	void r100_cp_fini(struct radeon_device *rdev)
		674	{
1179	serge	675	if (r100_cp_wait_for_idle(rdev)) {
		676	DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
		677	}
1117	serge	678	/* Disable ring */
1179	serge	679	r100_cp_disable(rdev);
1117	serge	680	radeon_ring_fini(rdev);
		681	DRM_INFO("radeon: cp finalized\n");
		682	}
		683
		684	void r100_cp_disable(struct radeon_device *rdev)
		685	{
		686	/* Disable ring */
		687	rdev->cp.ready = false;
		688	WREG32(RADEON_CP_CSQ_MODE, 0);
		689	WREG32(RADEON_CP_CSQ_CNTL, 0);
		690	if (r100_gui_wait_for_idle(rdev)) {
		691	printk(KERN_WARNING "Failed to wait GUI idle while "
		692	"programming pipes. Bad things might happen.\n");
		693	}
		694	}
		695
		696	int r100_cp_reset(struct radeon_device *rdev)
		697	{
		698	uint32_t tmp;
		699	bool reinit_cp;
		700	int i;
		701
1179	serge	702	ENTER();
1117	serge	703
		704	reinit_cp = rdev->cp.ready;
		705	rdev->cp.ready = false;
		706	WREG32(RADEON_CP_CSQ_MODE, 0);
		707	WREG32(RADEON_CP_CSQ_CNTL, 0);
		708	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
		709	(void)RREG32(RADEON_RBBM_SOFT_RESET);
		710	udelay(200);
		711	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		712	/* Wait to prevent race in RBBM_STATUS */
		713	mdelay(1);
		714	for (i = 0; i < rdev->usec_timeout; i++) {
		715	tmp = RREG32(RADEON_RBBM_STATUS);
		716	if (!(tmp & (1 << 16))) {
		717	DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
		718	tmp);
		719	if (reinit_cp) {
		720	return r100_cp_init(rdev, rdev->cp.ring_size);
		721	}
		722	return 0;
		723	}
		724	DRM_UDELAY(1);
		725	}
		726	tmp = RREG32(RADEON_RBBM_STATUS);
		727	DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
		728	return -1;
		729	}
		730
1179	serge	731	void r100_cp_commit(struct radeon_device *rdev)
		732	{
		733	WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
		734	(void)RREG32(RADEON_CP_RB_WPTR);
		735	}
		736
		737
1117	serge	738	#if 0
		739	/*
		740	* CS functions
		741	*/
		742	int r100_cs_parse_packet0(struct radeon_cs_parser *p,
		743	struct radeon_cs_packet *pkt,
		744	const unsigned *auth, unsigned n,
		745	radeon_packet0_check_t check)
		746	{
		747	unsigned reg;
		748	unsigned i, j, m;
		749	unsigned idx;
		750	int r;
		751
		752	idx = pkt->idx + 1;
		753	reg = pkt->reg;
		754	/* Check that register fall into register range
		755	* determined by the number of entry (n) in the
		756	* safe register bitmap.
		757	*/
		758	if (pkt->one_reg_wr) {
		759	if ((reg >> 7) > n) {
		760	return -EINVAL;
		761	}
		762	} else {
		763	if (((reg + (pkt->count << 2)) >> 7) > n) {
		764	return -EINVAL;
		765	}
		766	}
		767	for (i = 0; i <= pkt->count; i++, idx++) {
		768	j = (reg >> 7);
		769	m = 1 << ((reg >> 2) & 31);
		770	if (auth[j] & m) {
		771	r = check(p, pkt, idx, reg);
		772	if (r) {
		773	return r;
		774	}
		775	}
		776	if (pkt->one_reg_wr) {
		777	if (!(auth[j] & m)) {
		778	break;
		779	}
		780	} else {
		781	reg += 4;
		782	}
		783	}
		784	return 0;
		785	}
		786
		787	void r100_cs_dump_packet(struct radeon_cs_parser *p,
		788	struct radeon_cs_packet *pkt)
		789	{
		790	volatile uint32_t *ib;
		791	unsigned i;
		792	unsigned idx;
		793
		794	ib = p->ib->ptr;
		795	idx = pkt->idx;
		796	for (i = 0; i <= (pkt->count + 1); i++, idx++) {
		797	DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
		798	}
		799	}
		800
		801	/**
		802	* r100_cs_packet_parse() - parse cp packet and point ib index to next packet
		803	* @parser: parser structure holding parsing context.
		804	* @pkt: where to store packet informations
		805	*
		806	* Assume that chunk_ib_index is properly set. Will return -EINVAL
		807	* if packet is bigger than remaining ib size. or if packets is unknown.
		808	**/
		809	int r100_cs_packet_parse(struct radeon_cs_parser *p,
		810	struct radeon_cs_packet *pkt,
		811	unsigned idx)
		812	{
		813	struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1179	serge	814	uint32_t header;
1117	serge	815
		816	if (idx >= ib_chunk->length_dw) {
		817	DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
		818	idx, ib_chunk->length_dw);
		819	return -EINVAL;
		820	}
1221	serge	821	header = radeon_get_ib_value(p, idx);
1117	serge	822	pkt->idx = idx;
		823	pkt->type = CP_PACKET_GET_TYPE(header);
		824	pkt->count = CP_PACKET_GET_COUNT(header);
		825	switch (pkt->type) {
		826	case PACKET_TYPE0:
		827	pkt->reg = CP_PACKET0_GET_REG(header);
		828	pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
		829	break;
		830	case PACKET_TYPE3:
		831	pkt->opcode = CP_PACKET3_GET_OPCODE(header);
		832	break;
		833	case PACKET_TYPE2:
		834	pkt->count = -1;
		835	break;
		836	default:
		837	DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
		838	return -EINVAL;
		839	}
		840	if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
		841	DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
		842	pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
		843	return -EINVAL;
		844	}
		845	return 0;
		846	}
		847
		848	/**
1179	serge	849	* r100_cs_packet_next_vline() - parse userspace VLINE packet
		850	* @parser: parser structure holding parsing context.
		851	*
		852	* Userspace sends a special sequence for VLINE waits.
		853	* PACKET0 - VLINE_START_END + value
		854	* PACKET0 - WAIT_UNTIL +_value
		855	* RELOC (P3) - crtc_id in reloc.
		856	*
		857	* This function parses this and relocates the VLINE START END
		858	* and WAIT UNTIL packets to the correct crtc.
		859	* It also detects a switched off crtc and nulls out the
		860	* wait in that case.
		861	*/
		862	int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
		863	{
		864	struct drm_mode_object *obj;
		865	struct drm_crtc *crtc;
		866	struct radeon_crtc *radeon_crtc;
		867	struct radeon_cs_packet p3reloc, waitreloc;
		868	int crtc_id;
		869	int r;
		870	uint32_t header, h_idx, reg;
1221	serge	871	volatile uint32_t *ib;
1179	serge	872
1221	serge	873	ib = p->ib->ptr;
1179	serge	874
		875	/* parse the wait until */
		876	r = r100_cs_packet_parse(p, &waitreloc, p->idx);
		877	if (r)
		878	return r;
		879
		880	/* check its a wait until and only 1 count */
		881	if (waitreloc.reg != RADEON_WAIT_UNTIL \|\|
		882	waitreloc.count != 0) {
		883	DRM_ERROR("vline wait had illegal wait until segment\n");
		884	r = -EINVAL;
		885	return r;
		886	}
		887
1221	serge	888	if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1179	serge	889	DRM_ERROR("vline wait had illegal wait until\n");
		890	r = -EINVAL;
		891	return r;
		892	}
		893
		894	/* jump over the NOP */
1221	serge	895	r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1179	serge	896	if (r)
		897	return r;
		898
		899	h_idx = p->idx - 2;
1221	serge	900	p->idx += waitreloc.count + 2;
		901	p->idx += p3reloc.count + 2;
1179	serge	902
1221	serge	903	header = radeon_get_ib_value(p, h_idx);
		904	crtc_id = radeon_get_ib_value(p, h_idx + 5);
		905	reg = CP_PACKET0_GET_REG(header);
1179	serge	906	mutex_lock(&p->rdev->ddev->mode_config.mutex);
		907	obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
		908	if (!obj) {
		909	DRM_ERROR("cannot find crtc %d\n", crtc_id);
		910	r = -EINVAL;
		911	goto out;
		912	}
		913	crtc = obj_to_crtc(obj);
		914	radeon_crtc = to_radeon_crtc(crtc);
		915	crtc_id = radeon_crtc->crtc_id;
		916
		917	if (!crtc->enabled) {
		918	/* if the CRTC isn't enabled - we need to nop out the wait until */
1221	serge	919	ib[h_idx + 2] = PACKET2(0);
		920	ib[h_idx + 3] = PACKET2(0);
1179	serge	921	} else if (crtc_id == 1) {
		922	switch (reg) {
		923	case AVIVO_D1MODE_VLINE_START_END:
1221	serge	924	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	925	header \|= AVIVO_D2MODE_VLINE_START_END >> 2;
		926	break;
		927	case RADEON_CRTC_GUI_TRIG_VLINE:
1221	serge	928	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	929	header \|= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
		930	break;
		931	default:
		932	DRM_ERROR("unknown crtc reloc\n");
		933	r = -EINVAL;
		934	goto out;
		935	}
1221	serge	936	ib[h_idx] = header;
		937	ib[h_idx + 3] \|= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1179	serge	938	}
		939	out:
		940	mutex_unlock(&p->rdev->ddev->mode_config.mutex);
		941	return r;
		942	}
		943
		944	/**
1117	serge	945	* r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
		946	* @parser: parser structure holding parsing context.
		947	* @data: pointer to relocation data
		948	* @offset_start: starting offset
		949	* @offset_mask: offset mask (to align start offset on)
		950	* @reloc: reloc informations
		951	*
		952	* Check next packet is relocation packet3, do bo validation and compute
		953	* GPU offset using the provided start.
		954	**/
		955	int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
		956	struct radeon_cs_reloc **cs_reloc)
		957	{
		958	struct radeon_cs_chunk *relocs_chunk;
		959	struct radeon_cs_packet p3reloc;
		960	unsigned idx;
		961	int r;
		962
		963	if (p->chunk_relocs_idx == -1) {
		964	DRM_ERROR("No relocation chunk !\n");
		965	return -EINVAL;
		966	}
		967	*cs_reloc = NULL;
		968	relocs_chunk = &p->chunks[p->chunk_relocs_idx];
		969	r = r100_cs_packet_parse(p, &p3reloc, p->idx);
		970	if (r) {
		971	return r;
		972	}
		973	p->idx += p3reloc.count + 2;
		974	if (p3reloc.type != PACKET_TYPE3 \|\| p3reloc.opcode != PACKET3_NOP) {
		975	DRM_ERROR("No packet3 for relocation for packet at %d.\n",
		976	p3reloc.idx);
		977	r100_cs_dump_packet(p, &p3reloc);
		978	return -EINVAL;
		979	}
1221	serge	980	idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1117	serge	981	if (idx >= relocs_chunk->length_dw) {
		982	DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
		983	idx, relocs_chunk->length_dw);
		984	r100_cs_dump_packet(p, &p3reloc);
		985	return -EINVAL;
		986	}
		987	/* FIXME: we assume reloc size is 4 dwords */
		988	*cs_reloc = p->relocs_ptr[(idx / 4)];
		989	return 0;
		990	}
		991
1179	serge	992	static int r100_get_vtx_size(uint32_t vtx_fmt)
		993	{
		994	int vtx_size;
		995	vtx_size = 2;
		996	/* ordered according to bits in spec */
		997	if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
		998	vtx_size++;
		999	if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
		1000	vtx_size += 3;
		1001	if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
		1002	vtx_size++;
		1003	if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
		1004	vtx_size++;
		1005	if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
		1006	vtx_size += 3;
		1007	if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
		1008	vtx_size++;
		1009	if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
		1010	vtx_size++;
		1011	if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
		1012	vtx_size += 2;
		1013	if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
		1014	vtx_size += 2;
		1015	if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
		1016	vtx_size++;
		1017	if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
		1018	vtx_size += 2;
		1019	if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
		1020	vtx_size++;
		1021	if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
		1022	vtx_size += 2;
		1023	if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
		1024	vtx_size++;
		1025	if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
		1026	vtx_size++;
		1027	/* blend weight */
		1028	if (vtx_fmt & (0x7 << 15))
		1029	vtx_size += (vtx_fmt >> 15) & 0x7;
		1030	if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
		1031	vtx_size += 3;
		1032	if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
		1033	vtx_size += 2;
		1034	if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
		1035	vtx_size++;
		1036	if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
		1037	vtx_size++;
		1038	if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
		1039	vtx_size++;
		1040	if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
		1041	vtx_size++;
		1042	return vtx_size;
		1043	}
		1044
1117	serge	1045	static int r100_packet0_check(struct radeon_cs_parser *p,
1179	serge	1046	struct radeon_cs_packet *pkt,
		1047	unsigned idx, unsigned reg)
1117	serge	1048	{
		1049	struct radeon_cs_reloc *reloc;
1179	serge	1050	struct r100_cs_track *track;
1117	serge	1051	volatile uint32_t *ib;
		1052	uint32_t tmp;
		1053	int r;
1179	serge	1054	int i, face;
		1055	u32 tile_flags = 0;
1221	serge	1056	u32 idx_value;
1117	serge	1057
		1058	ib = p->ib->ptr;
1179	serge	1059	track = (struct r100_cs_track *)p->track;
		1060
1221	serge	1061	idx_value = radeon_get_ib_value(p, idx);
		1062
1117	serge	1063	switch (reg) {
1179	serge	1064	case RADEON_CRTC_GUI_TRIG_VLINE:
		1065	r = r100_cs_packet_parse_vline(p);
		1066	if (r) {
		1067	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1068	idx, reg);
		1069	r100_cs_dump_packet(p, pkt);
		1070	return r;
		1071	}
		1072	break;
1117	serge	1073	/* FIXME: only allow PACKET3 blit? easier to check for out of
		1074	* range access */
		1075	case RADEON_DST_PITCH_OFFSET:
		1076	case RADEON_SRC_PITCH_OFFSET:
1179	serge	1077	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		1078	if (r)
		1079	return r;
		1080	break;
		1081	case RADEON_RB3D_DEPTHOFFSET:
1117	serge	1082	r = r100_cs_packet_next_reloc(p, &reloc);
		1083	if (r) {
		1084	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1085	idx, reg);
		1086	r100_cs_dump_packet(p, pkt);
		1087	return r;
		1088	}
1179	serge	1089	track->zb.robj = reloc->robj;
1221	serge	1090	track->zb.offset = idx_value;
		1091	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1117	serge	1092	break;
		1093	case RADEON_RB3D_COLOROFFSET:
1179	serge	1094	r = r100_cs_packet_next_reloc(p, &reloc);
		1095	if (r) {
		1096	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1097	idx, reg);
		1098	r100_cs_dump_packet(p, pkt);
		1099	return r;
		1100	}
		1101	track->cb[0].robj = reloc->robj;
1221	serge	1102	track->cb[0].offset = idx_value;
		1103	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1104	break;
1117	serge	1105	case RADEON_PP_TXOFFSET_0:
		1106	case RADEON_PP_TXOFFSET_1:
		1107	case RADEON_PP_TXOFFSET_2:
1179	serge	1108	i = (reg - RADEON_PP_TXOFFSET_0) / 24;
		1109	r = r100_cs_packet_next_reloc(p, &reloc);
		1110	if (r) {
		1111	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1112	idx, reg);
		1113	r100_cs_dump_packet(p, pkt);
		1114	return r;
		1115	}
1221	serge	1116	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1117	track->textures[i].robj = reloc->robj;
		1118	break;
		1119	case RADEON_PP_CUBIC_OFFSET_T0_0:
		1120	case RADEON_PP_CUBIC_OFFSET_T0_1:
		1121	case RADEON_PP_CUBIC_OFFSET_T0_2:
		1122	case RADEON_PP_CUBIC_OFFSET_T0_3:
		1123	case RADEON_PP_CUBIC_OFFSET_T0_4:
		1124	i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
		1125	r = r100_cs_packet_next_reloc(p, &reloc);
		1126	if (r) {
		1127	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1128	idx, reg);
		1129	r100_cs_dump_packet(p, pkt);
		1130	return r;
		1131	}
1221	serge	1132	track->textures[0].cube_info[i].offset = idx_value;
		1133	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1134	track->textures[0].cube_info[i].robj = reloc->robj;
		1135	break;
		1136	case RADEON_PP_CUBIC_OFFSET_T1_0:
		1137	case RADEON_PP_CUBIC_OFFSET_T1_1:
		1138	case RADEON_PP_CUBIC_OFFSET_T1_2:
		1139	case RADEON_PP_CUBIC_OFFSET_T1_3:
		1140	case RADEON_PP_CUBIC_OFFSET_T1_4:
		1141	i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
		1142	r = r100_cs_packet_next_reloc(p, &reloc);
		1143	if (r) {
		1144	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1145	idx, reg);
		1146	r100_cs_dump_packet(p, pkt);
		1147	return r;
		1148	}
1221	serge	1149	track->textures[1].cube_info[i].offset = idx_value;
		1150	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1151	track->textures[1].cube_info[i].robj = reloc->robj;
		1152	break;
		1153	case RADEON_PP_CUBIC_OFFSET_T2_0:
		1154	case RADEON_PP_CUBIC_OFFSET_T2_1:
		1155	case RADEON_PP_CUBIC_OFFSET_T2_2:
		1156	case RADEON_PP_CUBIC_OFFSET_T2_3:
		1157	case RADEON_PP_CUBIC_OFFSET_T2_4:
		1158	i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1117	serge	1159	r = r100_cs_packet_next_reloc(p, &reloc);
		1160	if (r) {
		1161	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1162	idx, reg);
		1163	r100_cs_dump_packet(p, pkt);
		1164	return r;
		1165	}
1221	serge	1166	track->textures[2].cube_info[i].offset = idx_value;
		1167	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1168	track->textures[2].cube_info[i].robj = reloc->robj;
		1169	break;
		1170	case RADEON_RE_WIDTH_HEIGHT:
1221	serge	1171	track->maxy = ((idx_value >> 16) & 0x7FF);
1117	serge	1172	break;
1179	serge	1173	case RADEON_RB3D_COLORPITCH:
		1174	r = r100_cs_packet_next_reloc(p, &reloc);
		1175	if (r) {
		1176	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1177	idx, reg);
		1178	r100_cs_dump_packet(p, pkt);
		1179	return r;
		1180	}
		1181
		1182	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		1183	tile_flags \|= RADEON_COLOR_TILE_ENABLE;
		1184	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		1185	tile_flags \|= RADEON_COLOR_MICROTILE_ENABLE;
		1186
1221	serge	1187	tmp = idx_value & ~(0x7 << 16);
1179	serge	1188	tmp \|= tile_flags;
		1189	ib[idx] = tmp;
		1190
1221	serge	1191	track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1179	serge	1192	break;
		1193	case RADEON_RB3D_DEPTHPITCH:
1221	serge	1194	track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1179	serge	1195	break;
		1196	case RADEON_RB3D_CNTL:
1221	serge	1197	switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1179	serge	1198	case 7:
		1199	case 8:
		1200	case 9:
		1201	case 11:
		1202	case 12:
		1203	track->cb[0].cpp = 1;
		1204	break;
		1205	case 3:
		1206	case 4:
		1207	case 15:
		1208	track->cb[0].cpp = 2;
		1209	break;
		1210	case 6:
		1211	track->cb[0].cpp = 4;
		1212	break;
1117	serge	1213	default:
1179	serge	1214	DRM_ERROR("Invalid color buffer format (%d) !\n",
1221	serge	1215	((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1179	serge	1216	return -EINVAL;
		1217	}
1221	serge	1218	track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1179	serge	1219	break;
		1220	case RADEON_RB3D_ZSTENCILCNTL:
1221	serge	1221	switch (idx_value & 0xf) {
1179	serge	1222	case 0:
		1223	track->zb.cpp = 2;
1117	serge	1224	break;
1179	serge	1225	case 2:
		1226	case 3:
		1227	case 4:
		1228	case 5:
		1229	case 9:
		1230	case 11:
		1231	track->zb.cpp = 4;
		1232	break;
		1233	default:
		1234	break;
1117	serge	1235	}
		1236	break;
1179	serge	1237	case RADEON_RB3D_ZPASS_ADDR:
		1238	r = r100_cs_packet_next_reloc(p, &reloc);
		1239	if (r) {
		1240	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1241	idx, reg);
		1242	r100_cs_dump_packet(p, pkt);
		1243	return r;
		1244	}
1221	serge	1245	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1246	break;
		1247	case RADEON_PP_CNTL:
		1248	{
1221	serge	1249	uint32_t temp = idx_value >> 4;
1179	serge	1250	for (i = 0; i < track->num_texture; i++)
		1251	track->textures[i].enabled = !!(temp & (1 << i));
1117	serge	1252	}
1179	serge	1253	break;
		1254	case RADEON_SE_VF_CNTL:
1221	serge	1255	track->vap_vf_cntl = idx_value;
1179	serge	1256	break;
		1257	case RADEON_SE_VTX_FMT:
1221	serge	1258	track->vtx_size = r100_get_vtx_size(idx_value);
1179	serge	1259	break;
		1260	case RADEON_PP_TEX_SIZE_0:
		1261	case RADEON_PP_TEX_SIZE_1:
		1262	case RADEON_PP_TEX_SIZE_2:
		1263	i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1221	serge	1264	track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
		1265	track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1179	serge	1266	break;
		1267	case RADEON_PP_TEX_PITCH_0:
		1268	case RADEON_PP_TEX_PITCH_1:
		1269	case RADEON_PP_TEX_PITCH_2:
		1270	i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1221	serge	1271	track->textures[i].pitch = idx_value + 32;
1179	serge	1272	break;
		1273	case RADEON_PP_TXFILTER_0:
		1274	case RADEON_PP_TXFILTER_1:
		1275	case RADEON_PP_TXFILTER_2:
		1276	i = (reg - RADEON_PP_TXFILTER_0) / 24;
1221	serge	1277	track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1179	serge	1278	>> RADEON_MAX_MIP_LEVEL_SHIFT);
1221	serge	1279	tmp = (idx_value >> 23) & 0x7;
1179	serge	1280	if (tmp == 2 \|\| tmp == 6)
		1281	track->textures[i].roundup_w = false;
1221	serge	1282	tmp = (idx_value >> 27) & 0x7;
1179	serge	1283	if (tmp == 2 \|\| tmp == 6)
		1284	track->textures[i].roundup_h = false;
		1285	break;
		1286	case RADEON_PP_TXFORMAT_0:
		1287	case RADEON_PP_TXFORMAT_1:
		1288	case RADEON_PP_TXFORMAT_2:
		1289	i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1221	serge	1290	if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1179	serge	1291	track->textures[i].use_pitch = 1;
		1292	} else {
		1293	track->textures[i].use_pitch = 0;
1221	serge	1294	track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
		1295	track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1179	serge	1296	}
1221	serge	1297	if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1179	serge	1298	track->textures[i].tex_coord_type = 2;
1221	serge	1299	switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1179	serge	1300	case RADEON_TXFORMAT_I8:
		1301	case RADEON_TXFORMAT_RGB332:
		1302	case RADEON_TXFORMAT_Y8:
		1303	track->textures[i].cpp = 1;
		1304	break;
		1305	case RADEON_TXFORMAT_AI88:
		1306	case RADEON_TXFORMAT_ARGB1555:
		1307	case RADEON_TXFORMAT_RGB565:
		1308	case RADEON_TXFORMAT_ARGB4444:
		1309	case RADEON_TXFORMAT_VYUY422:
		1310	case RADEON_TXFORMAT_YVYU422:
		1311	case RADEON_TXFORMAT_SHADOW16:
		1312	case RADEON_TXFORMAT_LDUDV655:
		1313	case RADEON_TXFORMAT_DUDV88:
		1314	track->textures[i].cpp = 2;
		1315	break;
		1316	case RADEON_TXFORMAT_ARGB8888:
		1317	case RADEON_TXFORMAT_RGBA8888:
		1318	case RADEON_TXFORMAT_SHADOW32:
		1319	case RADEON_TXFORMAT_LDUDUV8888:
		1320	track->textures[i].cpp = 4;
		1321	break;
1403	serge	1322	case RADEON_TXFORMAT_DXT1:
		1323	track->textures[i].cpp = 1;
		1324	track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
		1325	break;
		1326	case RADEON_TXFORMAT_DXT23:
		1327	case RADEON_TXFORMAT_DXT45:
		1328	track->textures[i].cpp = 1;
		1329	track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
		1330	break;
1179	serge	1331	}
1221	serge	1332	track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
		1333	track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1179	serge	1334	break;
		1335	case RADEON_PP_CUBIC_FACES_0:
		1336	case RADEON_PP_CUBIC_FACES_1:
		1337	case RADEON_PP_CUBIC_FACES_2:
1221	serge	1338	tmp = idx_value;
1179	serge	1339	i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
		1340	for (face = 0; face < 4; face++) {
		1341	track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
		1342	track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
		1343	}
		1344	break;
		1345	default:
		1346	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
		1347	reg, idx);
		1348	return -EINVAL;
1117	serge	1349	}
		1350	return 0;
		1351	}
		1352
		1353	int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
		1354	struct radeon_cs_packet *pkt,
1321	serge	1355	struct radeon_bo *robj)
1117	serge	1356	{
		1357	unsigned idx;
1221	serge	1358	u32 value;
1117	serge	1359	idx = pkt->idx + 1;
1221	serge	1360	value = radeon_get_ib_value(p, idx + 2);
1321	serge	1361	if ((value + 1) > radeon_bo_size(robj)) {
1117	serge	1362	DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
		1363	"(need %u have %lu) !\n",
1221	serge	1364	value + 1,
1321	serge	1365	radeon_bo_size(robj));
1117	serge	1366	return -EINVAL;
		1367	}
		1368	return 0;
		1369	}
		1370
		1371	static int r100_packet3_check(struct radeon_cs_parser *p,
		1372	struct radeon_cs_packet *pkt)
		1373	{
		1374	struct radeon_cs_reloc *reloc;
1179	serge	1375	struct r100_cs_track *track;
1117	serge	1376	unsigned idx;
		1377	volatile uint32_t *ib;
		1378	int r;
		1379
		1380	ib = p->ib->ptr;
		1381	idx = pkt->idx + 1;
1179	serge	1382	track = (struct r100_cs_track *)p->track;
1117	serge	1383	switch (pkt->opcode) {
		1384	case PACKET3_3D_LOAD_VBPNTR:
1221	serge	1385	r = r100_packet3_load_vbpntr(p, pkt, idx);
		1386	if (r)
1117	serge	1387	return r;
		1388	break;
		1389	case PACKET3_INDX_BUFFER:
		1390	r = r100_cs_packet_next_reloc(p, &reloc);
		1391	if (r) {
		1392	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1393	r100_cs_dump_packet(p, pkt);
		1394	return r;
		1395	}
1221	serge	1396	ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1117	serge	1397	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		1398	if (r) {
		1399	return r;
		1400	}
		1401	break;
		1402	case 0x23:
		1403	/* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
		1404	r = r100_cs_packet_next_reloc(p, &reloc);
		1405	if (r) {
		1406	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1407	r100_cs_dump_packet(p, pkt);
		1408	return r;
		1409	}
1221	serge	1410	ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1179	serge	1411	track->num_arrays = 1;
1221	serge	1412	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1179	serge	1413
		1414	track->arrays[0].robj = reloc->robj;
		1415	track->arrays[0].esize = track->vtx_size;
		1416
1221	serge	1417	track->max_indx = radeon_get_ib_value(p, idx+1);
1179	serge	1418
1221	serge	1419	track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1179	serge	1420	track->immd_dwords = pkt->count - 1;
		1421	r = r100_cs_track_check(p->rdev, track);
		1422	if (r)
		1423	return r;
1117	serge	1424	break;
		1425	case PACKET3_3D_DRAW_IMMD:
1221	serge	1426	if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1179	serge	1427	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1428	return -EINVAL;
		1429	}
1403	serge	1430	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1221	serge	1431	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1432	track->immd_dwords = pkt->count - 1;
		1433	r = r100_cs_track_check(p->rdev, track);
		1434	if (r)
		1435	return r;
		1436	break;
1117	serge	1437	/* triggers drawing using in-packet vertex data */
		1438	case PACKET3_3D_DRAW_IMMD_2:
1221	serge	1439	if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1179	serge	1440	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1441	return -EINVAL;
		1442	}
1221	serge	1443	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1444	track->immd_dwords = pkt->count;
		1445	r = r100_cs_track_check(p->rdev, track);
		1446	if (r)
		1447	return r;
		1448	break;
1117	serge	1449	/* triggers drawing using in-packet vertex data */
		1450	case PACKET3_3D_DRAW_VBUF_2:
1221	serge	1451	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1452	r = r100_cs_track_check(p->rdev, track);
		1453	if (r)
		1454	return r;
		1455	break;
1117	serge	1456	/* triggers drawing of vertex buffers setup elsewhere */
		1457	case PACKET3_3D_DRAW_INDX_2:
1221	serge	1458	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1459	r = r100_cs_track_check(p->rdev, track);
		1460	if (r)
		1461	return r;
		1462	break;
1117	serge	1463	/* triggers drawing using indices to vertex buffer */
		1464	case PACKET3_3D_DRAW_VBUF:
1221	serge	1465	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1466	r = r100_cs_track_check(p->rdev, track);
		1467	if (r)
		1468	return r;
		1469	break;
1117	serge	1470	/* triggers drawing of vertex buffers setup elsewhere */
		1471	case PACKET3_3D_DRAW_INDX:
1221	serge	1472	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1473	r = r100_cs_track_check(p->rdev, track);
		1474	if (r)
		1475	return r;
		1476	break;
1117	serge	1477	/* triggers drawing using indices to vertex buffer */
		1478	case PACKET3_NOP:
		1479	break;
		1480	default:
		1481	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		1482	return -EINVAL;
		1483	}
		1484	return 0;
		1485	}
		1486
		1487	int r100_cs_parse(struct radeon_cs_parser *p)
		1488	{
		1489	struct radeon_cs_packet pkt;
1179	serge	1490	struct r100_cs_track *track;
1117	serge	1491	int r;
		1492
1179	serge	1493	track = kzalloc(sizeof(*track), GFP_KERNEL);
		1494	r100_cs_track_clear(p->rdev, track);
		1495	p->track = track;
1117	serge	1496	do {
		1497	r = r100_cs_packet_parse(p, &pkt, p->idx);
		1498	if (r) {
		1499	return r;
		1500	}
		1501	p->idx += pkt.count + 2;
		1502	switch (pkt.type) {
		1503	case PACKET_TYPE0:
1179	serge	1504	if (p->rdev->family >= CHIP_R200)
		1505	r = r100_cs_parse_packet0(p, &pkt,
		1506	p->rdev->config.r100.reg_safe_bm,
		1507	p->rdev->config.r100.reg_safe_bm_size,
		1508	&r200_packet0_check);
		1509	else
		1510	r = r100_cs_parse_packet0(p, &pkt,
		1511	p->rdev->config.r100.reg_safe_bm,
		1512	p->rdev->config.r100.reg_safe_bm_size,
		1513	&r100_packet0_check);
1117	serge	1514	break;
		1515	case PACKET_TYPE2:
		1516	break;
		1517	case PACKET_TYPE3:
		1518	r = r100_packet3_check(p, &pkt);
		1519	break;
		1520	default:
		1521	DRM_ERROR("Unknown packet type %d !\n",
		1522	pkt.type);
		1523	return -EINVAL;
		1524	}
		1525	if (r) {
		1526	return r;
		1527	}
		1528	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
		1529	return 0;
		1530	}
		1531
1128	serge	1532	#endif
1117	serge	1533
		1534	/*
		1535	* Global GPU functions
		1536	*/
		1537	void r100_errata(struct radeon_device *rdev)
		1538	{
		1539	rdev->pll_errata = 0;
		1540
		1541	if (rdev->family == CHIP_RV200 \|\| rdev->family == CHIP_RS200) {
		1542	rdev->pll_errata \|= CHIP_ERRATA_PLL_DUMMYREADS;
		1543	}
		1544
		1545	if (rdev->family == CHIP_RV100 \|\|
		1546	rdev->family == CHIP_RS100 \|\|
		1547	rdev->family == CHIP_RS200) {
		1548	rdev->pll_errata \|= CHIP_ERRATA_PLL_DELAY;
		1549	}
		1550	}
		1551
		1552	/* Wait for vertical sync on primary CRTC */
		1553	void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
		1554	{
		1555	uint32_t crtc_gen_cntl, tmp;
		1556	int i;
		1557
		1558	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
		1559	if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) \|\|
		1560	!(crtc_gen_cntl & RADEON_CRTC_EN)) {
		1561	return;
		1562	}
		1563	/* Clear the CRTC_VBLANK_SAVE bit */
		1564	WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
		1565	for (i = 0; i < rdev->usec_timeout; i++) {
		1566	tmp = RREG32(RADEON_CRTC_STATUS);
		1567	if (tmp & RADEON_CRTC_VBLANK_SAVE) {
		1568	return;
		1569	}
		1570	DRM_UDELAY(1);
		1571	}
		1572	}
		1573
		1574	/* Wait for vertical sync on secondary CRTC */
		1575	void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
		1576	{
		1577	uint32_t crtc2_gen_cntl, tmp;
		1578	int i;
		1579
		1580	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1581	if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) \|\|
		1582	!(crtc2_gen_cntl & RADEON_CRTC2_EN))
		1583	return;
		1584
		1585	/* Clear the CRTC_VBLANK_SAVE bit */
		1586	WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
		1587	for (i = 0; i < rdev->usec_timeout; i++) {
		1588	tmp = RREG32(RADEON_CRTC2_STATUS);
		1589	if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
		1590	return;
		1591	}
		1592	DRM_UDELAY(1);
		1593	}
		1594	}
		1595
		1596	int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
		1597	{
		1598	unsigned i;
		1599	uint32_t tmp;
		1600
		1601	for (i = 0; i < rdev->usec_timeout; i++) {
		1602	tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
		1603	if (tmp >= n) {
		1604	return 0;
		1605	}
		1606	DRM_UDELAY(1);
		1607	}
		1608	return -1;
		1609	}
		1610
		1611	int r100_gui_wait_for_idle(struct radeon_device *rdev)
		1612	{
		1613	unsigned i;
		1614	uint32_t tmp;
		1615
		1616	if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
		1617	printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
		1618	" Bad things might happen.\n");
		1619	}
		1620	for (i = 0; i < rdev->usec_timeout; i++) {
		1621	tmp = RREG32(RADEON_RBBM_STATUS);
		1622	if (!(tmp & (1 << 31))) {
		1623	return 0;
		1624	}
		1625	DRM_UDELAY(1);
		1626	}
		1627	return -1;
		1628	}
		1629
		1630	int r100_mc_wait_for_idle(struct radeon_device *rdev)
		1631	{
		1632	unsigned i;
		1633	uint32_t tmp;
		1634
		1635	for (i = 0; i < rdev->usec_timeout; i++) {
		1636	/* read MC_STATUS */
		1637	tmp = RREG32(0x0150);
		1638	if (tmp & (1 << 2)) {
		1639	return 0;
		1640	}
		1641	DRM_UDELAY(1);
		1642	}
		1643	return -1;
		1644	}
		1645
		1646	void r100_gpu_init(struct radeon_device *rdev)
		1647	{
		1648	/* TODO: anythings to do here ? pipes ? */
		1649	r100_hdp_reset(rdev);
		1650	}
		1651
		1652	void r100_hdp_reset(struct radeon_device *rdev)
		1653	{
		1654	uint32_t tmp;
		1655
1179	serge	1656	ENTER();
1117	serge	1657
		1658	tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
		1659	tmp \|= (7 << 28);
		1660	WREG32(RADEON_HOST_PATH_CNTL, tmp \| RADEON_HDP_SOFT_RESET \| RADEON_HDP_READ_BUFFER_INVALIDATE);
		1661	(void)RREG32(RADEON_HOST_PATH_CNTL);
		1662	udelay(200);
		1663	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		1664	WREG32(RADEON_HOST_PATH_CNTL, tmp);
		1665	(void)RREG32(RADEON_HOST_PATH_CNTL);
		1666	}
		1667
		1668	int r100_rb2d_reset(struct radeon_device *rdev)
		1669	{
		1670	uint32_t tmp;
		1671	int i;
		1672
1179	serge	1673	ENTER();
1117	serge	1674
		1675	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
		1676	(void)RREG32(RADEON_RBBM_SOFT_RESET);
		1677	udelay(200);
		1678	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		1679	/* Wait to prevent race in RBBM_STATUS */
		1680	mdelay(1);
		1681	for (i = 0; i < rdev->usec_timeout; i++) {
		1682	tmp = RREG32(RADEON_RBBM_STATUS);
		1683	if (!(tmp & (1 << 26))) {
		1684	DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
		1685	tmp);
		1686	return 0;
		1687	}
		1688	DRM_UDELAY(1);
		1689	}
		1690	tmp = RREG32(RADEON_RBBM_STATUS);
		1691	DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
		1692	return -1;
		1693	}
		1694
		1695	int r100_gpu_reset(struct radeon_device *rdev)
		1696	{
		1697	uint32_t status;
		1698
		1699	/* reset order likely matter */
		1700	status = RREG32(RADEON_RBBM_STATUS);
		1701	/* reset HDP */
		1702	r100_hdp_reset(rdev);
		1703	/* reset rb2d */
		1704	if (status & ((1 << 17) \| (1 << 18) \| (1 << 27))) {
		1705	r100_rb2d_reset(rdev);
		1706	}
		1707	/* TODO: reset 3D engine */
		1708	/* reset CP */
		1709	status = RREG32(RADEON_RBBM_STATUS);
		1710	if (status & (1 << 16)) {
		1711	r100_cp_reset(rdev);
		1712	}
		1713	/* Check if GPU is idle */
		1714	status = RREG32(RADEON_RBBM_STATUS);
		1715	if (status & (1 << 31)) {
		1716	DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
		1717	return -1;
		1718	}
		1719	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
		1720	return 0;
		1721	}
		1722
1321	serge	1723	void r100_set_common_regs(struct radeon_device *rdev)
		1724	{
		1725	/* set these so they don't interfere with anything */
		1726	WREG32(RADEON_OV0_SCALE_CNTL, 0);
		1727	WREG32(RADEON_SUBPIC_CNTL, 0);
		1728	WREG32(RADEON_VIPH_CONTROL, 0);
		1729	WREG32(RADEON_I2C_CNTL_1, 0);
		1730	WREG32(RADEON_DVI_I2C_CNTL_1, 0);
		1731	WREG32(RADEON_CAP0_TRIG_CNTL, 0);
		1732	WREG32(RADEON_CAP1_TRIG_CNTL, 0);
		1733	}
1117	serge	1734
		1735	/*
		1736	* VRAM info
		1737	*/
		1738	static void r100_vram_get_type(struct radeon_device *rdev)
		1739	{
		1740	uint32_t tmp;
		1741
		1742	rdev->mc.vram_is_ddr = false;
		1743	if (rdev->flags & RADEON_IS_IGP)
		1744	rdev->mc.vram_is_ddr = true;
		1745	else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
		1746	rdev->mc.vram_is_ddr = true;
		1747	if ((rdev->family == CHIP_RV100) \|\|
		1748	(rdev->family == CHIP_RS100) \|\|
		1749	(rdev->family == CHIP_RS200)) {
		1750	tmp = RREG32(RADEON_MEM_CNTL);
		1751	if (tmp & RV100_HALF_MODE) {
		1752	rdev->mc.vram_width = 32;
		1753	} else {
		1754	rdev->mc.vram_width = 64;
		1755	}
		1756	if (rdev->flags & RADEON_SINGLE_CRTC) {
		1757	rdev->mc.vram_width /= 4;
		1758	rdev->mc.vram_is_ddr = true;
		1759	}
		1760	} else if (rdev->family <= CHIP_RV280) {
		1761	tmp = RREG32(RADEON_MEM_CNTL);
		1762	if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
		1763	rdev->mc.vram_width = 128;
		1764	} else {
		1765	rdev->mc.vram_width = 64;
		1766	}
		1767	} else {
		1768	/* newer IGPs */
		1769	rdev->mc.vram_width = 128;
		1770	}
		1771	}
		1772
1179	serge	1773	static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1117	serge	1774	{
1179	serge	1775	u32 aper_size;
		1776	u8 byte;
1117	serge	1777
1179	serge	1778	aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
		1779
		1780	/* Set HDP_APER_CNTL only on cards that are known not to be broken,
		1781	* that is has the 2nd generation multifunction PCI interface
		1782	*/
		1783	if (rdev->family == CHIP_RV280 \|\|
		1784	rdev->family >= CHIP_RV350) {
		1785	WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
		1786	~RADEON_HDP_APER_CNTL);
		1787	DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
		1788	return aper_size * 2;
		1789	}
		1790
		1791	/* Older cards have all sorts of funny issues to deal with. First
		1792	* check if it's a multifunction card by reading the PCI config
		1793	* header type... Limit those to one aperture size
		1794	*/
		1795	// pci_read_config_byte(rdev->pdev, 0xe, &byte);
		1796	// if (byte & 0x80) {
		1797	// DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
		1798	// DRM_INFO("Limiting VRAM to one aperture\n");
		1799	// return aper_size;
		1800	// }
		1801
		1802	/* Single function older card. We read HDP_APER_CNTL to see how the BIOS
		1803	* have set it up. We don't write this as it's broken on some ASICs but
		1804	* we expect the BIOS to have done the right thing (might be too optimistic...)
		1805	*/
		1806	if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
		1807	return aper_size * 2;
		1808	return aper_size;
		1809	}
		1810
		1811	void r100_vram_init_sizes(struct radeon_device *rdev)
		1812	{
		1813	u64 config_aper_size;
		1814	u32 accessible;
		1815
		1816	config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
		1817
1117	serge	1818	if (rdev->flags & RADEON_IS_IGP) {
		1819	uint32_t tom;
		1820	/* read NB_TOM to get the amount of ram stolen for the GPU */
		1821	tom = RREG32(RADEON_NB_TOM);
1179	serge	1822	rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
		1823	/* for IGPs we need to keep VRAM where it was put by the BIOS */
		1824	rdev->mc.vram_location = (tom & 0xffff) << 16;
		1825	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
		1826	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	1827	} else {
1179	serge	1828	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1117	serge	1829	/* Some production boards of m6 will report 0
		1830	* if it's 8 MB
		1831	*/
1179	serge	1832	if (rdev->mc.real_vram_size == 0) {
		1833	rdev->mc.real_vram_size = 8192 * 1024;
		1834	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1117	serge	1835	}
1179	serge	1836	/* let driver place VRAM */
		1837	rdev->mc.vram_location = 0xFFFFFFFFUL;
		1838	/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
		1839	* Novell bug 204882 + along with lots of ubuntu ones */
		1840	if (config_aper_size > rdev->mc.real_vram_size)
		1841	rdev->mc.mc_vram_size = config_aper_size;
		1842	else
		1843	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	1844	}
		1845
1179	serge	1846	/* work out accessible VRAM */
		1847	accessible = r100_get_accessible_vram(rdev);
		1848
1117	serge	1849	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
		1850	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1179	serge	1851
		1852	if (accessible > rdev->mc.aper_size)
		1853	accessible = rdev->mc.aper_size;
		1854
		1855	if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
		1856	rdev->mc.mc_vram_size = rdev->mc.aper_size;
		1857
		1858	if (rdev->mc.real_vram_size > rdev->mc.aper_size)
		1859	rdev->mc.real_vram_size = rdev->mc.aper_size;
1117	serge	1860	}
		1861
1179	serge	1862	void r100_vga_set_state(struct radeon_device *rdev, bool state)
		1863	{
		1864	uint32_t temp;
		1865
		1866	temp = RREG32(RADEON_CONFIG_CNTL);
		1867	if (state == false) {
		1868	temp &= ~(1<<8);
		1869	temp \|= (1<<9);
		1870	} else {
		1871	temp &= ~(1<<9);
		1872	}
		1873	WREG32(RADEON_CONFIG_CNTL, temp);
		1874	}
		1875
		1876	void r100_vram_info(struct radeon_device *rdev)
		1877	{
		1878	r100_vram_get_type(rdev);
		1879
		1880	r100_vram_init_sizes(rdev);
		1881	}
		1882
		1883
1117	serge	1884	/*
		1885	* Indirect registers accessor
		1886	*/
		1887	void r100_pll_errata_after_index(struct radeon_device *rdev)
		1888	{
		1889	if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
		1890	return;
		1891	}
		1892	(void)RREG32(RADEON_CLOCK_CNTL_DATA);
		1893	(void)RREG32(RADEON_CRTC_GEN_CNTL);
		1894	}
		1895
		1896	static void r100_pll_errata_after_data(struct radeon_device *rdev)
		1897	{
		1898	/* This workarounds is necessary on RV100, RS100 and RS200 chips
		1899	* or the chip could hang on a subsequent access
		1900	*/
		1901	if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
		1902	udelay(5000);
		1903	}
		1904
		1905	/* This function is required to workaround a hardware bug in some (all?)
		1906	* revisions of the R300. This workaround should be called after every
		1907	* CLOCK_CNTL_INDEX register access. If not, register reads afterward
		1908	* may not be correct.
		1909	*/
		1910	if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
		1911	uint32_t save, tmp;
		1912
		1913	save = RREG32(RADEON_CLOCK_CNTL_INDEX);
		1914	tmp = save & ~(0x3f \| RADEON_PLL_WR_EN);
		1915	WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
		1916	tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
		1917	WREG32(RADEON_CLOCK_CNTL_INDEX, save);
		1918	}
		1919	}
		1920
		1921	uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
		1922	{
		1923	uint32_t data;
		1924
		1925	WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
		1926	r100_pll_errata_after_index(rdev);
		1927	data = RREG32(RADEON_CLOCK_CNTL_DATA);
		1928	r100_pll_errata_after_data(rdev);
		1929	return data;
		1930	}
		1931
		1932	void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		1933	{
		1934	WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) \| RADEON_PLL_WR_EN));
		1935	r100_pll_errata_after_index(rdev);
		1936	WREG32(RADEON_CLOCK_CNTL_DATA, v);
		1937	r100_pll_errata_after_data(rdev);
		1938	}
		1939
1221	serge	1940	void r100_set_safe_registers(struct radeon_device *rdev)
1117	serge	1941	{
1179	serge	1942	if (ASIC_IS_RN50(rdev)) {
		1943	rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
		1944	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
		1945	} else if (rdev->family < CHIP_R200) {
		1946	rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
		1947	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
		1948	} else {
1221	serge	1949	r200_set_safe_registers(rdev);
1117	serge	1950	}
		1951	}
		1952
1129	serge	1953	/*
		1954	* Debugfs info
		1955	*/
		1956	#if defined(CONFIG_DEBUG_FS)
		1957	static int r100_debugfs_rbbm_info(struct seq_file m, void data)
		1958	{
		1959	struct drm_info_node node = (struct drm_info_node ) m->private;
		1960	struct drm_device *dev = node->minor->dev;
		1961	struct radeon_device *rdev = dev->dev_private;
		1962	uint32_t reg, value;
		1963	unsigned i;
		1964
		1965	seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
		1966	seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
		1967	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		1968	for (i = 0; i < 64; i++) {
		1969	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i \| 0x100);
		1970	reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
		1971	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
		1972	value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
		1973	seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
		1974	}
		1975	return 0;
		1976	}
		1977
		1978	static int r100_debugfs_cp_ring_info(struct seq_file m, void data)
		1979	{
		1980	struct drm_info_node node = (struct drm_info_node ) m->private;
		1981	struct drm_device *dev = node->minor->dev;
		1982	struct radeon_device *rdev = dev->dev_private;
		1983	uint32_t rdp, wdp;
		1984	unsigned count, i, j;
		1985
		1986	radeon_ring_free_size(rdev);
		1987	rdp = RREG32(RADEON_CP_RB_RPTR);
		1988	wdp = RREG32(RADEON_CP_RB_WPTR);
		1989	count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
		1990	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		1991	seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
		1992	seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
		1993	seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
		1994	seq_printf(m, "%u dwords in ring\n", count);
		1995	for (j = 0; j <= count; j++) {
		1996	i = (rdp + j) & rdev->cp.ptr_mask;
		1997	seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
		1998	}
		1999	return 0;
		2000	}
		2001
		2002
		2003	static int r100_debugfs_cp_csq_fifo(struct seq_file m, void data)
		2004	{
		2005	struct drm_info_node node = (struct drm_info_node ) m->private;
		2006	struct drm_device *dev = node->minor->dev;
		2007	struct radeon_device *rdev = dev->dev_private;
		2008	uint32_t csq_stat, csq2_stat, tmp;
		2009	unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
		2010	unsigned i;
		2011
		2012	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2013	seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
		2014	csq_stat = RREG32(RADEON_CP_CSQ_STAT);
		2015	csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
		2016	r_rptr = (csq_stat >> 0) & 0x3ff;
		2017	r_wptr = (csq_stat >> 10) & 0x3ff;
		2018	ib1_rptr = (csq_stat >> 20) & 0x3ff;
		2019	ib1_wptr = (csq2_stat >> 0) & 0x3ff;
		2020	ib2_rptr = (csq2_stat >> 10) & 0x3ff;
		2021	ib2_wptr = (csq2_stat >> 20) & 0x3ff;
		2022	seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
		2023	seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
		2024	seq_printf(m, "Ring rptr %u\n", r_rptr);
		2025	seq_printf(m, "Ring wptr %u\n", r_wptr);
		2026	seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
		2027	seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
		2028	seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
		2029	seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
		2030	/* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
		2031	* 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
		2032	seq_printf(m, "Ring fifo:\n");
		2033	for (i = 0; i < 256; i++) {
		2034	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2035	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2036	seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
		2037	}
		2038	seq_printf(m, "Indirect1 fifo:\n");
		2039	for (i = 256; i <= 512; i++) {
		2040	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2041	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2042	seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
		2043	}
		2044	seq_printf(m, "Indirect2 fifo:\n");
		2045	for (i = 640; i < ib1_wptr; i++) {
		2046	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2047	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2048	seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
		2049	}
		2050	return 0;
		2051	}
		2052
		2053	static int r100_debugfs_mc_info(struct seq_file m, void data)
		2054	{
		2055	struct drm_info_node node = (struct drm_info_node ) m->private;
		2056	struct drm_device *dev = node->minor->dev;
		2057	struct radeon_device *rdev = dev->dev_private;
		2058	uint32_t tmp;
		2059
		2060	tmp = RREG32(RADEON_CONFIG_MEMSIZE);
		2061	seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
		2062	tmp = RREG32(RADEON_MC_FB_LOCATION);
		2063	seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
		2064	tmp = RREG32(RADEON_BUS_CNTL);
		2065	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
		2066	tmp = RREG32(RADEON_MC_AGP_LOCATION);
		2067	seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
		2068	tmp = RREG32(RADEON_AGP_BASE);
		2069	seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
		2070	tmp = RREG32(RADEON_HOST_PATH_CNTL);
		2071	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
		2072	tmp = RREG32(0x01D0);
		2073	seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
		2074	tmp = RREG32(RADEON_AIC_LO_ADDR);
		2075	seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
		2076	tmp = RREG32(RADEON_AIC_HI_ADDR);
		2077	seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
		2078	tmp = RREG32(0x01E4);
		2079	seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
		2080	return 0;
		2081	}
		2082
		2083	static struct drm_info_list r100_debugfs_rbbm_list[] = {
		2084	{"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
		2085	};
		2086
		2087	static struct drm_info_list r100_debugfs_cp_list[] = {
		2088	{"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
		2089	{"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
		2090	};
		2091
		2092	static struct drm_info_list r100_debugfs_mc_info_list[] = {
		2093	{"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
		2094	};
		2095	#endif
		2096
		2097	int r100_debugfs_rbbm_init(struct radeon_device *rdev)
		2098	{
		2099	#if defined(CONFIG_DEBUG_FS)
		2100	return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
		2101	#else
		2102	return 0;
		2103	#endif
		2104	}
		2105
		2106	int r100_debugfs_cp_init(struct radeon_device *rdev)
		2107	{
		2108	#if defined(CONFIG_DEBUG_FS)
		2109	return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
		2110	#else
		2111	return 0;
		2112	#endif
		2113	}
		2114
		2115	int r100_debugfs_mc_info_init(struct radeon_device *rdev)
		2116	{
		2117	#if defined(CONFIG_DEBUG_FS)
		2118	return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
		2119	#else
		2120	return 0;
		2121	#endif
		2122	}
1179	serge	2123
		2124	int r100_set_surface_reg(struct radeon_device *rdev, int reg,
		2125	uint32_t tiling_flags, uint32_t pitch,
		2126	uint32_t offset, uint32_t obj_size)
		2127	{
		2128	int surf_index = reg * 16;
		2129	int flags = 0;
		2130
		2131	/* r100/r200 divide by 16 */
		2132	if (rdev->family < CHIP_R300)
		2133	flags = pitch / 16;
		2134	else
		2135	flags = pitch / 8;
		2136
		2137	if (rdev->family <= CHIP_RS200) {
		2138	if ((tiling_flags & (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		2139	== (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		2140	flags \|= RADEON_SURF_TILE_COLOR_BOTH;
		2141	if (tiling_flags & RADEON_TILING_MACRO)
		2142	flags \|= RADEON_SURF_TILE_COLOR_MACRO;
		2143	} else if (rdev->family <= CHIP_RV280) {
		2144	if (tiling_flags & (RADEON_TILING_MACRO))
		2145	flags \|= R200_SURF_TILE_COLOR_MACRO;
		2146	if (tiling_flags & RADEON_TILING_MICRO)
		2147	flags \|= R200_SURF_TILE_COLOR_MICRO;
		2148	} else {
		2149	if (tiling_flags & RADEON_TILING_MACRO)
		2150	flags \|= R300_SURF_TILE_MACRO;
		2151	if (tiling_flags & RADEON_TILING_MICRO)
		2152	flags \|= R300_SURF_TILE_MICRO;
		2153	}
		2154
		2155	if (tiling_flags & RADEON_TILING_SWAP_16BIT)
		2156	flags \|= RADEON_SURF_AP0_SWP_16BPP \| RADEON_SURF_AP1_SWP_16BPP;
		2157	if (tiling_flags & RADEON_TILING_SWAP_32BIT)
		2158	flags \|= RADEON_SURF_AP0_SWP_32BPP \| RADEON_SURF_AP1_SWP_32BPP;
		2159
		2160	DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
		2161	WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
		2162	WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
		2163	WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
		2164	return 0;
		2165	}
		2166
		2167	void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
		2168	{
		2169	int surf_index = reg * 16;
		2170	WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
		2171	}
		2172
		2173	void r100_bandwidth_update(struct radeon_device *rdev)
		2174	{
		2175	fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
		2176	fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
		2177	fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
		2178	uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
		2179	fixed20_12 memtcas_ff[8] = {
		2180	fixed_init(1),
		2181	fixed_init(2),
		2182	fixed_init(3),
		2183	fixed_init(0),
		2184	fixed_init_half(1),
		2185	fixed_init_half(2),
		2186	fixed_init(0),
		2187	};
		2188	fixed20_12 memtcas_rs480_ff[8] = {
		2189	fixed_init(0),
		2190	fixed_init(1),
		2191	fixed_init(2),
		2192	fixed_init(3),
		2193	fixed_init(0),
		2194	fixed_init_half(1),
		2195	fixed_init_half(2),
		2196	fixed_init_half(3),
		2197	};
		2198	fixed20_12 memtcas2_ff[8] = {
		2199	fixed_init(0),
		2200	fixed_init(1),
		2201	fixed_init(2),
		2202	fixed_init(3),
		2203	fixed_init(4),
		2204	fixed_init(5),
		2205	fixed_init(6),
		2206	fixed_init(7),
		2207	};
		2208	fixed20_12 memtrbs[8] = {
		2209	fixed_init(1),
		2210	fixed_init_half(1),
		2211	fixed_init(2),
		2212	fixed_init_half(2),
		2213	fixed_init(3),
		2214	fixed_init_half(3),
		2215	fixed_init(4),
		2216	fixed_init_half(4)
		2217	};
		2218	fixed20_12 memtrbs_r4xx[8] = {
		2219	fixed_init(4),
		2220	fixed_init(5),
		2221	fixed_init(6),
		2222	fixed_init(7),
		2223	fixed_init(8),
		2224	fixed_init(9),
		2225	fixed_init(10),
		2226	fixed_init(11)
		2227	};
		2228	fixed20_12 min_mem_eff;
		2229	fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
		2230	fixed20_12 cur_latency_mclk, cur_latency_sclk;
		2231	fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
		2232	disp_drain_rate2, read_return_rate;
		2233	fixed20_12 time_disp1_drop_priority;
		2234	int c;
		2235	int cur_size = 16; /* in octawords */
		2236	int critical_point = 0, critical_point2;
		2237	/* uint32_t read_return_rate, time_disp1_drop_priority; */
		2238	int stop_req, max_stop_req;
		2239	struct drm_display_mode *mode1 = NULL;
		2240	struct drm_display_mode *mode2 = NULL;
		2241	uint32_t pixel_bytes1 = 0;
		2242	uint32_t pixel_bytes2 = 0;
		2243
		2244	if (rdev->mode_info.crtcs[0]->base.enabled) {
		2245	mode1 = &rdev->mode_info.crtcs[0]->base.mode;
		2246	pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
		2247	}
1221	serge	2248	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
1179	serge	2249	if (rdev->mode_info.crtcs[1]->base.enabled) {
		2250	mode2 = &rdev->mode_info.crtcs[1]->base.mode;
		2251	pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
		2252	}
1221	serge	2253	}
1179	serge	2254
		2255	min_mem_eff.full = rfixed_const_8(0);
		2256	/* get modes */
		2257	if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
		2258	uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
		2259	mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
		2260	mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
		2261	/* check crtc enables */
		2262	if (mode2)
		2263	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
		2264	if (mode1)
		2265	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
		2266	WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
		2267	}
		2268
		2269	/*
		2270	* determine is there is enough bw for current mode
		2271	*/
		2272	mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
		2273	temp_ff.full = rfixed_const(100);
		2274	mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
		2275	sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
		2276	sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
		2277
		2278	temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
		2279	temp_ff.full = rfixed_const(temp);
		2280	mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
		2281
		2282	pix_clk.full = 0;
		2283	pix_clk2.full = 0;
		2284	peak_disp_bw.full = 0;
		2285	if (mode1) {
		2286	temp_ff.full = rfixed_const(1000);
		2287	pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
		2288	pix_clk.full = rfixed_div(pix_clk, temp_ff);
		2289	temp_ff.full = rfixed_const(pixel_bytes1);
		2290	peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
		2291	}
		2292	if (mode2) {
		2293	temp_ff.full = rfixed_const(1000);
		2294	pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
		2295	pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
		2296	temp_ff.full = rfixed_const(pixel_bytes2);
		2297	peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
		2298	}
		2299
		2300	mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
		2301	if (peak_disp_bw.full >= mem_bw.full) {
		2302	DRM_ERROR("You may not have enough display bandwidth for current mode\n"
		2303	"If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
		2304	}
		2305
		2306	/* Get values from the EXT_MEM_CNTL register...converting its contents. */
		2307	temp = RREG32(RADEON_MEM_TIMING_CNTL);
		2308	if ((rdev->family == CHIP_RV100) \|\| (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
		2309	mem_trcd = ((temp >> 2) & 0x3) + 1;
		2310	mem_trp = ((temp & 0x3)) + 1;
		2311	mem_tras = ((temp & 0x70) >> 4) + 1;
		2312	} else if (rdev->family == CHIP_R300 \|\|
		2313	rdev->family == CHIP_R350) { /* r300, r350 */
		2314	mem_trcd = (temp & 0x7) + 1;
		2315	mem_trp = ((temp >> 8) & 0x7) + 1;
		2316	mem_tras = ((temp >> 11) & 0xf) + 4;
		2317	} else if (rdev->family == CHIP_RV350 \|\|
		2318	rdev->family <= CHIP_RV380) {
		2319	/* rv3x0 */
		2320	mem_trcd = (temp & 0x7) + 3;
		2321	mem_trp = ((temp >> 8) & 0x7) + 3;
		2322	mem_tras = ((temp >> 11) & 0xf) + 6;
		2323	} else if (rdev->family == CHIP_R420 \|\|
		2324	rdev->family == CHIP_R423 \|\|
		2325	rdev->family == CHIP_RV410) {
		2326	/* r4xx */
		2327	mem_trcd = (temp & 0xf) + 3;
		2328	if (mem_trcd > 15)
		2329	mem_trcd = 15;
		2330	mem_trp = ((temp >> 8) & 0xf) + 3;
		2331	if (mem_trp > 15)
		2332	mem_trp = 15;
		2333	mem_tras = ((temp >> 12) & 0x1f) + 6;
		2334	if (mem_tras > 31)
		2335	mem_tras = 31;
		2336	} else { /* RV200, R200 */
		2337	mem_trcd = (temp & 0x7) + 1;
		2338	mem_trp = ((temp >> 8) & 0x7) + 1;
		2339	mem_tras = ((temp >> 12) & 0xf) + 4;
		2340	}
		2341	/* convert to FF */
		2342	trcd_ff.full = rfixed_const(mem_trcd);
		2343	trp_ff.full = rfixed_const(mem_trp);
		2344	tras_ff.full = rfixed_const(mem_tras);
		2345
		2346	/* Get values from the MEM_SDRAM_MODE_REG register...converting its */
		2347	temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		2348	data = (temp & (7 << 20)) >> 20;
		2349	if ((rdev->family == CHIP_RV100) \|\| rdev->flags & RADEON_IS_IGP) {
		2350	if (rdev->family == CHIP_RS480) /* don't think rs400 */
		2351	tcas_ff = memtcas_rs480_ff[data];
		2352	else
		2353	tcas_ff = memtcas_ff[data];
		2354	} else
		2355	tcas_ff = memtcas2_ff[data];
		2356
		2357	if (rdev->family == CHIP_RS400 \|\|
		2358	rdev->family == CHIP_RS480) {
		2359	/* extra cas latency stored in bits 23-25 0-4 clocks */
		2360	data = (temp >> 23) & 0x7;
		2361	if (data < 5)
		2362	tcas_ff.full += rfixed_const(data);
		2363	}
		2364
		2365	if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
		2366	/* on the R300, Tcas is included in Trbs.
		2367	*/
		2368	temp = RREG32(RADEON_MEM_CNTL);
		2369	data = (R300_MEM_NUM_CHANNELS_MASK & temp);
		2370	if (data == 1) {
		2371	if (R300_MEM_USE_CD_CH_ONLY & temp) {
		2372	temp = RREG32(R300_MC_IND_INDEX);
		2373	temp &= ~R300_MC_IND_ADDR_MASK;
		2374	temp \|= R300_MC_READ_CNTL_CD_mcind;
		2375	WREG32(R300_MC_IND_INDEX, temp);
		2376	temp = RREG32(R300_MC_IND_DATA);
		2377	data = (R300_MEM_RBS_POSITION_C_MASK & temp);
		2378	} else {
		2379	temp = RREG32(R300_MC_READ_CNTL_AB);
		2380	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		2381	}
		2382	} else {
		2383	temp = RREG32(R300_MC_READ_CNTL_AB);
		2384	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		2385	}
		2386	if (rdev->family == CHIP_RV410 \|\|
		2387	rdev->family == CHIP_R420 \|\|
		2388	rdev->family == CHIP_R423)
		2389	trbs_ff = memtrbs_r4xx[data];
		2390	else
		2391	trbs_ff = memtrbs[data];
		2392	tcas_ff.full += trbs_ff.full;
		2393	}
		2394
		2395	sclk_eff_ff.full = sclk_ff.full;
		2396
		2397	if (rdev->flags & RADEON_IS_AGP) {
		2398	fixed20_12 agpmode_ff;
		2399	agpmode_ff.full = rfixed_const(radeon_agpmode);
		2400	temp_ff.full = rfixed_const_666(16);
		2401	sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
		2402	}
		2403	/* TODO PCIE lanes may affect this - agpmode == 16?? */
		2404
		2405	if (ASIC_IS_R300(rdev)) {
		2406	sclk_delay_ff.full = rfixed_const(250);
		2407	} else {
		2408	if ((rdev->family == CHIP_RV100) \|\|
		2409	rdev->flags & RADEON_IS_IGP) {
		2410	if (rdev->mc.vram_is_ddr)
		2411	sclk_delay_ff.full = rfixed_const(41);
		2412	else
		2413	sclk_delay_ff.full = rfixed_const(33);
		2414	} else {
		2415	if (rdev->mc.vram_width == 128)
		2416	sclk_delay_ff.full = rfixed_const(57);
		2417	else
		2418	sclk_delay_ff.full = rfixed_const(41);
		2419	}
		2420	}
		2421
		2422	mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
		2423
		2424	if (rdev->mc.vram_is_ddr) {
		2425	if (rdev->mc.vram_width == 32) {
		2426	k1.full = rfixed_const(40);
		2427	c = 3;
		2428	} else {
		2429	k1.full = rfixed_const(20);
		2430	c = 1;
		2431	}
		2432	} else {
		2433	k1.full = rfixed_const(40);
		2434	c = 3;
		2435	}
		2436
		2437	temp_ff.full = rfixed_const(2);
		2438	mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
		2439	temp_ff.full = rfixed_const(c);
		2440	mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
		2441	temp_ff.full = rfixed_const(4);
		2442	mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
		2443	mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
		2444	mc_latency_mclk.full += k1.full;
		2445
		2446	mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
		2447	mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
		2448
		2449	/*
		2450	HW cursor time assuming worst case of full size colour cursor.
		2451	*/
		2452	temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
		2453	temp_ff.full += trcd_ff.full;
		2454	if (temp_ff.full < tras_ff.full)
		2455	temp_ff.full = tras_ff.full;
		2456	cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
		2457
		2458	temp_ff.full = rfixed_const(cur_size);
		2459	cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
		2460	/*
		2461	Find the total latency for the display data.
		2462	*/
1268	serge	2463	disp_latency_overhead.full = rfixed_const(8);
1179	serge	2464	disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
		2465	mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
		2466	mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
		2467
		2468	if (mc_latency_mclk.full > mc_latency_sclk.full)
		2469	disp_latency.full = mc_latency_mclk.full;
		2470	else
		2471	disp_latency.full = mc_latency_sclk.full;
		2472
		2473	/* setup Max GRPH_STOP_REQ default value */
		2474	if (ASIC_IS_RV100(rdev))
		2475	max_stop_req = 0x5c;
		2476	else
		2477	max_stop_req = 0x7c;
		2478
		2479	if (mode1) {
		2480	/* CRTC1
		2481	Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
		2482	GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
		2483	*/
		2484	stop_req = mode1->hdisplay * pixel_bytes1 / 16;
		2485
		2486	if (stop_req > max_stop_req)
		2487	stop_req = max_stop_req;
		2488
		2489	/*
		2490	Find the drain rate of the display buffer.
		2491	*/
		2492	temp_ff.full = rfixed_const((16/pixel_bytes1));
		2493	disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
		2494
		2495	/*
		2496	Find the critical point of the display buffer.
		2497	*/
		2498	crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
		2499	crit_point_ff.full += rfixed_const_half(0);
		2500
		2501	critical_point = rfixed_trunc(crit_point_ff);
		2502
		2503	if (rdev->disp_priority == 2) {
		2504	critical_point = 0;
		2505	}
		2506
		2507	/*
		2508	The critical point should never be above max_stop_req-4. Setting
		2509	GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
		2510	*/
		2511	if (max_stop_req - critical_point < 4)
		2512	critical_point = 0;
		2513
		2514	if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
		2515	/* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
		2516	critical_point = 0x10;
		2517	}
		2518
		2519	temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
		2520	temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
		2521	temp \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		2522	temp &= ~(RADEON_GRPH_START_REQ_MASK);
		2523	if ((rdev->family == CHIP_R350) &&
		2524	(stop_req > 0x15)) {
		2525	stop_req -= 0x10;
		2526	}
		2527	temp \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		2528	temp \|= RADEON_GRPH_BUFFER_SIZE;
		2529	temp &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		2530	RADEON_GRPH_CRITICAL_AT_SOF \|
		2531	RADEON_GRPH_STOP_CNTL);
		2532	/*
		2533	Write the result into the register.
		2534	*/
		2535	WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		2536	(critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		2537
		2538	#if 0
		2539	if ((rdev->family == CHIP_RS400) \|\|
		2540	(rdev->family == CHIP_RS480)) {
		2541	/* attempt to program RS400 disp regs correctly ??? */
		2542	temp = RREG32(RS400_DISP1_REG_CNTL);
		2543	temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK \|
		2544	RS400_DISP1_STOP_REQ_LEVEL_MASK);
		2545	WREG32(RS400_DISP1_REQ_CNTL1, (temp \|
		2546	(critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		2547	(critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		2548	temp = RREG32(RS400_DMIF_MEM_CNTL1);
		2549	temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK \|
		2550	RS400_DISP1_CRITICAL_POINT_STOP_MASK);
		2551	WREG32(RS400_DMIF_MEM_CNTL1, (temp \|
		2552	(critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) \|
		2553	(critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
		2554	}
		2555	#endif
		2556
		2557	DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
		2558	/* (unsigned int)info->SavedReg->grph_buffer_cntl, */
		2559	(unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
		2560	}
		2561
		2562	if (mode2) {
		2563	u32 grph2_cntl;
		2564	stop_req = mode2->hdisplay * pixel_bytes2 / 16;
		2565
		2566	if (stop_req > max_stop_req)
		2567	stop_req = max_stop_req;
		2568
		2569	/*
		2570	Find the drain rate of the display buffer.
		2571	*/
		2572	temp_ff.full = rfixed_const((16/pixel_bytes2));
		2573	disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
		2574
		2575	grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
		2576	grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
		2577	grph2_cntl \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		2578	grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
		2579	if ((rdev->family == CHIP_R350) &&
		2580	(stop_req > 0x15)) {
		2581	stop_req -= 0x10;
		2582	}
		2583	grph2_cntl \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		2584	grph2_cntl \|= RADEON_GRPH_BUFFER_SIZE;
		2585	grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		2586	RADEON_GRPH_CRITICAL_AT_SOF \|
		2587	RADEON_GRPH_STOP_CNTL);
		2588
		2589	if ((rdev->family == CHIP_RS100) \|\|
		2590	(rdev->family == CHIP_RS200))
		2591	critical_point2 = 0;
		2592	else {
		2593	temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
		2594	temp_ff.full = rfixed_const(temp);
		2595	temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
		2596	if (sclk_ff.full < temp_ff.full)
		2597	temp_ff.full = sclk_ff.full;
		2598
		2599	read_return_rate.full = temp_ff.full;
		2600
		2601	if (mode1) {
		2602	temp_ff.full = read_return_rate.full - disp_drain_rate.full;
		2603	time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
		2604	} else {
		2605	time_disp1_drop_priority.full = 0;
		2606	}
		2607	crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
		2608	crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
		2609	crit_point_ff.full += rfixed_const_half(0);
		2610
		2611	critical_point2 = rfixed_trunc(crit_point_ff);
		2612
		2613	if (rdev->disp_priority == 2) {
		2614	critical_point2 = 0;
		2615	}
		2616
		2617	if (max_stop_req - critical_point2 < 4)
		2618	critical_point2 = 0;
		2619
		2620	}
		2621
		2622	if (critical_point2 == 0 && rdev->family == CHIP_R300) {
		2623	/* some R300 cards have problem with this set to 0 */
		2624	critical_point2 = 0x10;
		2625	}
		2626
		2627	WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		2628	(critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		2629
		2630	if ((rdev->family == CHIP_RS400) \|\|
		2631	(rdev->family == CHIP_RS480)) {
		2632	#if 0
		2633	/* attempt to program RS400 disp2 regs correctly ??? */
		2634	temp = RREG32(RS400_DISP2_REQ_CNTL1);
		2635	temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK \|
		2636	RS400_DISP2_STOP_REQ_LEVEL_MASK);
		2637	WREG32(RS400_DISP2_REQ_CNTL1, (temp \|
		2638	(critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		2639	(critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		2640	temp = RREG32(RS400_DISP2_REQ_CNTL2);
		2641	temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK \|
		2642	RS400_DISP2_CRITICAL_POINT_STOP_MASK);
		2643	WREG32(RS400_DISP2_REQ_CNTL2, (temp \|
		2644	(critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) \|
		2645	(critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
		2646	#endif
		2647	WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
		2648	WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
		2649	WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
		2650	WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
		2651	}
		2652
		2653	DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
		2654	(unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
		2655	}
		2656	}
		2657
		2658
		2659
		2660
		2661	void r100_mc_stop(struct radeon_device rdev, struct r100_mc_save save)
		2662	{
		2663	/* Shutdown CP we shouldn't need to do that but better be safe than
		2664	* sorry
		2665	*/
		2666	rdev->cp.ready = false;
		2667	WREG32(R_000740_CP_CSQ_CNTL, 0);
		2668
		2669	/* Save few CRTC registers */
1221	serge	2670	save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
1179	serge	2671	save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
		2672	save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
		2673	save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
		2674	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		2675	save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
		2676	save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
		2677	}
		2678
		2679	/* Disable VGA aperture access */
1221	serge	2680	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
1179	serge	2681	/* Disable cursor, overlay, crtc */
		2682	WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET \| S_000260_CUR_LOCK(1));
		2683	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL \|
		2684	S_000054_CRTC_DISPLAY_DIS(1));
		2685	WREG32(R_000050_CRTC_GEN_CNTL,
		2686	(C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) \|
		2687	S_000050_CRTC_DISP_REQ_EN_B(1));
		2688	WREG32(R_000420_OV0_SCALE_CNTL,
		2689	C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
		2690	WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
		2691	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		2692	WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET \|
		2693	S_000360_CUR2_LOCK(1));
		2694	WREG32(R_0003F8_CRTC2_GEN_CNTL,
		2695	(C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) \|
		2696	S_0003F8_CRTC2_DISPLAY_DIS(1) \|
		2697	S_0003F8_CRTC2_DISP_REQ_EN_B(1));
		2698	WREG32(R_000360_CUR2_OFFSET,
		2699	C_000360_CUR2_LOCK & save->CUR2_OFFSET);
		2700	}
		2701	}
		2702
		2703	void r100_mc_resume(struct radeon_device rdev, struct r100_mc_save save)
		2704	{
		2705	/* Update base address for crtc */
		2706	WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
		2707	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		2708	WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
		2709	rdev->mc.vram_location);
		2710	}
		2711	/* Restore CRTC registers */
1221	serge	2712	WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
1179	serge	2713	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
		2714	WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
		2715	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		2716	WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
		2717	}
		2718	}
		2719
1221	serge	2720	void r100_vga_render_disable(struct radeon_device *rdev)
		2721	{
		2722	u32 tmp;
		2723
		2724	tmp = RREG8(R_0003C2_GENMO_WT);
		2725	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
		2726	}
		2727
		2728	static void r100_debugfs(struct radeon_device *rdev)
		2729	{
		2730	int r;
		2731
		2732	r = r100_debugfs_mc_info_init(rdev);
		2733	if (r)
		2734	dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		2735	}
		2736
		2737
1179	serge	2738	int drm_order(unsigned long size)
		2739	{
		2740	int order;
		2741	unsigned long tmp;
		2742
		2743	for (order = 0, tmp = size >> 1; tmp; tmp >>= 1, order++) ;
		2744
		2745	if (size & (size - 1))
		2746	++order;
		2747
		2748	return order;
		2749	}
		2750
1221	serge	2751	static void r100_mc_program(struct radeon_device *rdev)
		2752	{
		2753	struct r100_mc_save save;
		2754
		2755	/* Stops all mc clients */
		2756	r100_mc_stop(rdev, &save);
		2757	if (rdev->flags & RADEON_IS_AGP) {
		2758	WREG32(R_00014C_MC_AGP_LOCATION,
		2759	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		2760	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		2761	WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		2762	if (rdev->family > CHIP_RV200)
		2763	WREG32(R_00015C_AGP_BASE_2,
		2764	upper_32_bits(rdev->mc.agp_base) & 0xff);
		2765	} else {
		2766	WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		2767	WREG32(R_000170_AGP_BASE, 0);
		2768	if (rdev->family > CHIP_RV200)
		2769	WREG32(R_00015C_AGP_BASE_2, 0);
		2770	}
		2771	/* Wait for mc idle */
		2772	if (r100_mc_wait_for_idle(rdev))
		2773	dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
		2774	/* Program MC, should be a 32bits limited address space */
		2775	WREG32(R_000148_MC_FB_LOCATION,
		2776	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		2777	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		2778	r100_mc_resume(rdev, &save);
		2779	}
		2780
		2781	void r100_clock_startup(struct radeon_device *rdev)
		2782	{
		2783	u32 tmp;
		2784
		2785	if (radeon_dynclks != -1 && radeon_dynclks)
		2786	radeon_legacy_set_clock_gating(rdev, 1);
		2787	/* We need to force on some of the block */
		2788	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
		2789	tmp \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		2790	if ((rdev->family == CHIP_RV250) \|\| (rdev->family == CHIP_RV280))
		2791	tmp \|= S_00000D_FORCE_DISP1(1) \| S_00000D_FORCE_DISP2(1);
		2792	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
		2793	}
		2794
		2795	static int r100_startup(struct radeon_device *rdev)
		2796	{
		2797	int r;
		2798
1321	serge	2799	/* set common regs */
		2800	r100_set_common_regs(rdev);
		2801	/* program mc */
1221	serge	2802	r100_mc_program(rdev);
		2803	/* Resume clock */
		2804	r100_clock_startup(rdev);
		2805	/* Initialize GPU configuration (# pipes, ...) */
		2806	r100_gpu_init(rdev);
		2807	/* Initialize GART (initialize after TTM so we can allocate
		2808	* memory through TTM but finalize after TTM) */
1321	serge	2809	r100_enable_bm(rdev);
1221	serge	2810	if (rdev->flags & RADEON_IS_PCI) {
		2811	r = r100_pci_gart_enable(rdev);
		2812	if (r)
		2813	return r;
		2814	}
		2815	/* Enable IRQ */
		2816	// r100_irq_set(rdev);
		2817	/* 1M ring buffer */
		2818	// r = r100_cp_init(rdev, 1024 * 1024);
		2819	// if (r) {
		2820	// dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
		2821	// return r;
		2822	// }
		2823	// r = r100_wb_init(rdev);
		2824	// if (r)
		2825	// dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
		2826	// r = r100_ib_init(rdev);
		2827	// if (r) {
		2828	// dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
		2829	// return r;
		2830	// }
		2831	return 0;
		2832	}
		2833
		2834
		2835	int r100_mc_init(struct radeon_device *rdev)
		2836	{
		2837	int r;
		2838	u32 tmp;
		2839
		2840	/* Setup GPU memory space */
		2841	rdev->mc.vram_location = 0xFFFFFFFFUL;
		2842	rdev->mc.gtt_location = 0xFFFFFFFFUL;
		2843	if (rdev->flags & RADEON_IS_IGP) {
		2844	tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
		2845	rdev->mc.vram_location = tmp << 16;
		2846	}
		2847	if (rdev->flags & RADEON_IS_AGP) {
		2848	r = radeon_agp_init(rdev);
		2849	if (r) {
1403	serge	2850	radeon_agp_disable(rdev);
1221	serge	2851	} else {
		2852	rdev->mc.gtt_location = rdev->mc.agp_base;
		2853	}
		2854	}
		2855	r = radeon_mc_setup(rdev);
		2856	if (r)
		2857	return r;
		2858	return 0;
		2859	}
		2860
		2861	int r100_init(struct radeon_device *rdev)
		2862	{
		2863	int r;
		2864
		2865	/* Register debugfs file specific to this group of asics */
		2866	r100_debugfs(rdev);
		2867	/* Disable VGA */
		2868	r100_vga_render_disable(rdev);
		2869	/* Initialize scratch registers */
		2870	radeon_scratch_init(rdev);
		2871	/* Initialize surface registers */
		2872	radeon_surface_init(rdev);
		2873	/* TODO: disable VGA need to use VGA request */
		2874	/* BIOS*/
		2875	if (!radeon_get_bios(rdev)) {
		2876	if (ASIC_IS_AVIVO(rdev))
		2877	return -EINVAL;
		2878	}
		2879	if (rdev->is_atom_bios) {
		2880	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		2881	return -EINVAL;
		2882	} else {
		2883	r = radeon_combios_init(rdev);
		2884	if (r)
		2885	return r;
		2886	}
		2887	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
		2888	if (radeon_gpu_reset(rdev)) {
		2889	dev_warn(rdev->dev,
		2890	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		2891	RREG32(R_000E40_RBBM_STATUS),
		2892	RREG32(R_0007C0_CP_STAT));
		2893	}
		2894	/* check if cards are posted or not */
1321	serge	2895	if (radeon_boot_test_post_card(rdev) == false)
		2896	return -EINVAL;
1221	serge	2897	/* Set asic errata */
		2898	r100_errata(rdev);
		2899	/* Initialize clocks */
		2900	radeon_get_clock_info(rdev->ddev);
1403	serge	2901	/* Initialize power management */
		2902	radeon_pm_init(rdev);
1221	serge	2903	/* Get vram informations */
		2904	r100_vram_info(rdev);
		2905	/* Initialize memory controller (also test AGP) */
		2906	r = r100_mc_init(rdev);
1246	serge	2907	dbgprintf("mc vram location %x\n", rdev->mc.vram_location);
1221	serge	2908	if (r)
		2909	return r;
		2910	/* Fence driver */
		2911	// r = radeon_fence_driver_init(rdev);
		2912	// if (r)
		2913	// return r;
		2914	// r = radeon_irq_kms_init(rdev);
		2915	// if (r)
		2916	// return r;
		2917	/* Memory manager */
1321	serge	2918	r = radeon_bo_init(rdev);
1221	serge	2919	if (r)
		2920	return r;
		2921	if (rdev->flags & RADEON_IS_PCI) {
		2922	r = r100_pci_gart_init(rdev);
		2923	if (r)
		2924	return r;
		2925	}
		2926	r100_set_safe_registers(rdev);
		2927	rdev->accel_working = true;
		2928	r = r100_startup(rdev);
		2929	if (r) {
		2930	/* Somethings want wront with the accel init stop accel */
		2931	dev_err(rdev->dev, "Disabling GPU acceleration\n");
		2932	// r100_suspend(rdev);
		2933	// r100_cp_fini(rdev);
		2934	// r100_wb_fini(rdev);
		2935	// r100_ib_fini(rdev);
		2936	if (rdev->flags & RADEON_IS_PCI)
		2937	r100_pci_gart_fini(rdev);
		2938	// radeon_irq_kms_fini(rdev);
		2939	rdev->accel_working = false;
		2940	}
		2941	return 0;
		2942	}

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(root)/drivers/video/drm/radeon/r100.c – Rev 1403