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Rev | Author | Line No. | Line |
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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1179 | serge | 28 | #include |
1125 | serge | 29 | #include "drmP.h" |
30 | #include "drm.h" |
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1117 | serge | 31 | #include "radeon_drm.h" |
32 | #include "radeon_reg.h" |
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33 | #include "radeon.h" |
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1179 | serge | 34 | #include "r100d.h" |
1221 | serge | 35 | #include "rs100d.h" |
36 | #include "rv200d.h" |
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37 | #include "rv250d.h" |
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1117 | serge | 38 | |
1221 | serge | 39 | #include |
40 | |||
1179 | serge | 41 | #include "r100_reg_safe.h" |
42 | #include "rn50_reg_safe.h" |
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1221 | serge | 43 | |
44 | /* Firmware Names */ |
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45 | #define FIRMWARE_R100 "radeon/R100_cp.bin" |
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46 | #define FIRMWARE_R200 "radeon/R200_cp.bin" |
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47 | #define FIRMWARE_R300 "radeon/R300_cp.bin" |
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48 | #define FIRMWARE_R420 "radeon/R420_cp.bin" |
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49 | #define FIRMWARE_RS690 "radeon/RS690_cp.bin" |
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50 | #define FIRMWARE_RS600 "radeon/RS600_cp.bin" |
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51 | #define FIRMWARE_R520 "radeon/R520_cp.bin" |
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52 | |||
53 | MODULE_FIRMWARE(FIRMWARE_R100); |
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54 | MODULE_FIRMWARE(FIRMWARE_R200); |
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55 | MODULE_FIRMWARE(FIRMWARE_R300); |
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56 | MODULE_FIRMWARE(FIRMWARE_R420); |
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57 | MODULE_FIRMWARE(FIRMWARE_RS690); |
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58 | MODULE_FIRMWARE(FIRMWARE_RS600); |
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59 | MODULE_FIRMWARE(FIRMWARE_R520); |
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60 | |||
61 | |||
1117 | serge | 62 | /* This files gather functions specifics to: |
63 | * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
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64 | */ |
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65 | |||
1321 | serge | 66 | /* hpd for digital panel detect/disconnect */ |
67 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
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68 | { |
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69 | bool connected = false; |
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70 | |||
71 | switch (hpd) { |
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72 | case RADEON_HPD_1: |
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73 | if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) |
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74 | connected = true; |
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75 | break; |
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76 | case RADEON_HPD_2: |
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77 | if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) |
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78 | connected = true; |
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79 | break; |
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80 | default: |
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81 | break; |
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82 | } |
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83 | return connected; |
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84 | } |
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85 | |||
86 | void r100_hpd_set_polarity(struct radeon_device *rdev, |
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87 | enum radeon_hpd_id hpd) |
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88 | { |
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89 | u32 tmp; |
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90 | bool connected = r100_hpd_sense(rdev, hpd); |
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91 | |||
92 | switch (hpd) { |
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93 | case RADEON_HPD_1: |
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94 | tmp = RREG32(RADEON_FP_GEN_CNTL); |
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95 | if (connected) |
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96 | tmp &= ~RADEON_FP_DETECT_INT_POL; |
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97 | else |
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98 | tmp |= RADEON_FP_DETECT_INT_POL; |
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99 | WREG32(RADEON_FP_GEN_CNTL, tmp); |
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100 | break; |
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101 | case RADEON_HPD_2: |
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102 | tmp = RREG32(RADEON_FP2_GEN_CNTL); |
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103 | if (connected) |
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104 | tmp &= ~RADEON_FP2_DETECT_INT_POL; |
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105 | else |
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106 | tmp |= RADEON_FP2_DETECT_INT_POL; |
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107 | WREG32(RADEON_FP2_GEN_CNTL, tmp); |
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108 | break; |
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109 | default: |
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110 | break; |
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111 | } |
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112 | } |
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113 | |||
114 | void r100_hpd_init(struct radeon_device *rdev) |
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115 | { |
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116 | struct drm_device *dev = rdev->ddev; |
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117 | struct drm_connector *connector; |
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118 | |||
119 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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120 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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121 | switch (radeon_connector->hpd.hpd) { |
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122 | case RADEON_HPD_1: |
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123 | rdev->irq.hpd[0] = true; |
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124 | break; |
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125 | case RADEON_HPD_2: |
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126 | rdev->irq.hpd[1] = true; |
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127 | break; |
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128 | default: |
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129 | break; |
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130 | } |
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131 | } |
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132 | r100_irq_set(rdev); |
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133 | } |
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134 | |||
135 | void r100_hpd_fini(struct radeon_device *rdev) |
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136 | { |
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137 | struct drm_device *dev = rdev->ddev; |
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138 | struct drm_connector *connector; |
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139 | |||
140 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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141 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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142 | switch (radeon_connector->hpd.hpd) { |
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143 | case RADEON_HPD_1: |
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144 | rdev->irq.hpd[0] = false; |
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145 | break; |
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146 | case RADEON_HPD_2: |
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147 | rdev->irq.hpd[1] = false; |
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148 | break; |
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149 | default: |
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150 | break; |
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151 | } |
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152 | } |
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153 | } |
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154 | |||
1117 | serge | 155 | /* |
156 | * PCI GART |
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157 | */ |
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158 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev) |
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159 | { |
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160 | /* TODO: can we do somethings here ? */ |
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161 | /* It seems hw only cache one entry so we should discard this |
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162 | * entry otherwise if first GPU GART read hit this entry it |
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163 | * could end up in wrong address. */ |
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164 | } |
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165 | |||
1179 | serge | 166 | int r100_pci_gart_init(struct radeon_device *rdev) |
1117 | serge | 167 | { |
168 | int r; |
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169 | |||
1179 | serge | 170 | if (rdev->gart.table.ram.ptr) { |
171 | WARN(1, "R100 PCI GART already initialized.\n"); |
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172 | return 0; |
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173 | } |
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1117 | serge | 174 | /* Initialize common gart structure */ |
175 | r = radeon_gart_init(rdev); |
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1179 | serge | 176 | if (r) |
1117 | serge | 177 | return r; |
1268 | serge | 178 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
1179 | serge | 179 | rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; |
180 | rdev->asic->gart_set_page = &r100_pci_gart_set_page; |
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181 | return radeon_gart_table_ram_alloc(rdev); |
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182 | } |
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183 | |||
1321 | serge | 184 | /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ |
185 | void r100_enable_bm(struct radeon_device *rdev) |
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186 | { |
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187 | uint32_t tmp; |
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188 | /* Enable bus mastering */ |
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189 | tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
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190 | WREG32(RADEON_BUS_CNTL, tmp); |
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191 | } |
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192 | |||
1179 | serge | 193 | int r100_pci_gart_enable(struct radeon_device *rdev) |
194 | { |
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195 | uint32_t tmp; |
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196 | |||
1117 | serge | 197 | /* discard memory request outside of configured range */ |
198 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; |
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199 | WREG32(RADEON_AIC_CNTL, tmp); |
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200 | /* set address range for PCI address translate */ |
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201 | WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location); |
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202 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
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203 | WREG32(RADEON_AIC_HI_ADDR, tmp); |
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204 | /* set PCI GART page-table base address */ |
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205 | WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); |
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206 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; |
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207 | WREG32(RADEON_AIC_CNTL, tmp); |
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208 | r100_pci_gart_tlb_flush(rdev); |
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209 | rdev->gart.ready = true; |
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210 | return 0; |
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211 | } |
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212 | |||
213 | void r100_pci_gart_disable(struct radeon_device *rdev) |
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214 | { |
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215 | uint32_t tmp; |
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216 | |||
217 | /* discard memory request outside of configured range */ |
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218 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; |
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219 | WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); |
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220 | WREG32(RADEON_AIC_LO_ADDR, 0); |
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221 | WREG32(RADEON_AIC_HI_ADDR, 0); |
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222 | } |
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223 | |||
224 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
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225 | { |
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226 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
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227 | return -EINVAL; |
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228 | } |
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1179 | serge | 229 | rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr)); |
1117 | serge | 230 | return 0; |
231 | } |
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232 | |||
1179 | serge | 233 | void r100_pci_gart_fini(struct radeon_device *rdev) |
1117 | serge | 234 | { |
235 | r100_pci_gart_disable(rdev); |
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1179 | serge | 236 | radeon_gart_table_ram_free(rdev); |
237 | radeon_gart_fini(rdev); |
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1117 | serge | 238 | } |
239 | |||
240 | |||
1221 | serge | 241 | void r100_irq_disable(struct radeon_device *rdev) |
1117 | serge | 242 | { |
1221 | serge | 243 | u32 tmp; |
1117 | serge | 244 | |
1221 | serge | 245 | WREG32(R_000040_GEN_INT_CNTL, 0); |
246 | /* Wait and acknowledge irq */ |
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247 | mdelay(1); |
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248 | tmp = RREG32(R_000044_GEN_INT_STATUS); |
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249 | WREG32(R_000044_GEN_INT_STATUS, tmp); |
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1117 | serge | 250 | } |
251 | |||
1221 | serge | 252 | static inline uint32_t r100_irq_ack(struct radeon_device *rdev) |
1117 | serge | 253 | { |
1221 | serge | 254 | uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); |
1321 | serge | 255 | uint32_t irq_mask = RADEON_SW_INT_TEST | |
256 | RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | |
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257 | RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; |
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1117 | serge | 258 | |
1221 | serge | 259 | if (irqs) { |
260 | WREG32(RADEON_GEN_INT_STATUS, irqs); |
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1129 | serge | 261 | } |
1221 | serge | 262 | return irqs & irq_mask; |
1117 | serge | 263 | } |
264 | |||
265 | |||
266 | |||
267 | void r100_fence_ring_emit(struct radeon_device *rdev, |
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268 | struct radeon_fence *fence) |
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269 | { |
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270 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
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271 | * for enough space (today caller are ib schedule and buffer move) */ |
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272 | /* Wait until IDLE & CLEAN */ |
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273 | radeon_ring_write(rdev, PACKET0(0x1720, 0)); |
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274 | radeon_ring_write(rdev, (1 << 16) | (1 << 17)); |
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275 | /* Emit fence sequence & fire IRQ */ |
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276 | radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); |
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277 | radeon_ring_write(rdev, fence->seq); |
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278 | radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
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279 | radeon_ring_write(rdev, RADEON_SW_INT_FIRE); |
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280 | } |
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281 | |||
1128 | serge | 282 | #if 0 |
1117 | serge | 283 | /* |
284 | * Writeback |
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285 | */ |
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286 | int r100_wb_init(struct radeon_device *rdev) |
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287 | { |
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288 | int r; |
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289 | |||
290 | if (rdev->wb.wb_obj == NULL) { |
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1321 | serge | 291 | r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true, |
1117 | serge | 292 | RADEON_GEM_DOMAIN_GTT, |
1321 | serge | 293 | &rdev->wb.wb_obj); |
1117 | serge | 294 | if (r) { |
1321 | serge | 295 | dev_err(rdev->dev, "(%d) create WB buffer failed\n", r); |
1117 | serge | 296 | return r; |
297 | } |
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1321 | serge | 298 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
299 | if (unlikely(r != 0)) |
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300 | return r; |
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301 | r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, |
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1117 | serge | 302 | &rdev->wb.gpu_addr); |
303 | if (r) { |
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1321 | serge | 304 | dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r); |
305 | radeon_bo_unreserve(rdev->wb.wb_obj); |
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1117 | serge | 306 | return r; |
307 | } |
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1321 | serge | 308 | r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
309 | radeon_bo_unreserve(rdev->wb.wb_obj); |
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1117 | serge | 310 | if (r) { |
1321 | serge | 311 | dev_err(rdev->dev, "(%d) map WB buffer failed\n", r); |
1117 | serge | 312 | return r; |
313 | } |
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314 | } |
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1179 | serge | 315 | WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr); |
316 | WREG32(R_00070C_CP_RB_RPTR_ADDR, |
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317 | S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2)); |
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318 | WREG32(R_000770_SCRATCH_UMSK, 0xff); |
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1117 | serge | 319 | return 0; |
320 | } |
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321 | |||
1179 | serge | 322 | void r100_wb_disable(struct radeon_device *rdev) |
323 | { |
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324 | WREG32(R_000770_SCRATCH_UMSK, 0); |
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325 | } |
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326 | |||
1117 | serge | 327 | void r100_wb_fini(struct radeon_device *rdev) |
328 | { |
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1321 | serge | 329 | int r; |
330 | |||
1179 | serge | 331 | r100_wb_disable(rdev); |
1117 | serge | 332 | if (rdev->wb.wb_obj) { |
1120 | serge | 333 | // radeon_object_kunmap(rdev->wb.wb_obj); |
334 | // radeon_object_unpin(rdev->wb.wb_obj); |
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335 | // radeon_object_unref(&rdev->wb.wb_obj); |
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1117 | serge | 336 | rdev->wb.wb = NULL; |
337 | rdev->wb.wb_obj = NULL; |
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338 | } |
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339 | } |
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340 | |||
341 | int r100_copy_blit(struct radeon_device *rdev, |
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342 | uint64_t src_offset, |
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343 | uint64_t dst_offset, |
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344 | unsigned num_pages, |
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345 | struct radeon_fence *fence) |
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346 | { |
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347 | uint32_t cur_pages; |
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348 | uint32_t stride_bytes = PAGE_SIZE; |
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349 | uint32_t pitch; |
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350 | uint32_t stride_pixels; |
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351 | unsigned ndw; |
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352 | int num_loops; |
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353 | int r = 0; |
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354 | |||
355 | /* radeon limited to 16k stride */ |
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356 | stride_bytes &= 0x3fff; |
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357 | /* radeon pitch is /64 */ |
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358 | pitch = stride_bytes / 64; |
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359 | stride_pixels = stride_bytes / 4; |
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360 | num_loops = DIV_ROUND_UP(num_pages, 8191); |
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361 | |||
362 | /* Ask for enough room for blit + flush + fence */ |
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363 | ndw = 64 + (10 * num_loops); |
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364 | r = radeon_ring_lock(rdev, ndw); |
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365 | if (r) { |
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366 | DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); |
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367 | return -EINVAL; |
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368 | } |
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369 | while (num_pages > 0) { |
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370 | cur_pages = num_pages; |
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371 | if (cur_pages > 8191) { |
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372 | cur_pages = 8191; |
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373 | } |
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374 | num_pages -= cur_pages; |
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375 | |||
376 | /* pages are in Y direction - height |
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377 | page width in X direction - width */ |
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378 | radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8)); |
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379 | radeon_ring_write(rdev, |
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380 | RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
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381 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
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382 | RADEON_GMC_SRC_CLIPPING | |
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383 | RADEON_GMC_DST_CLIPPING | |
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384 | RADEON_GMC_BRUSH_NONE | |
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385 | (RADEON_COLOR_FORMAT_ARGB8888 << 8) | |
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386 | RADEON_GMC_SRC_DATATYPE_COLOR | |
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387 | RADEON_ROP3_S | |
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388 | RADEON_DP_SRC_SOURCE_MEMORY | |
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389 | RADEON_GMC_CLR_CMP_CNTL_DIS | |
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390 | RADEON_GMC_WR_MSK_DIS); |
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391 | radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10)); |
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392 | radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10)); |
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393 | radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); |
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394 | radeon_ring_write(rdev, 0); |
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395 | radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); |
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396 | radeon_ring_write(rdev, num_pages); |
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397 | radeon_ring_write(rdev, num_pages); |
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398 | radeon_ring_write(rdev, cur_pages | (stride_pixels << 16)); |
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399 | } |
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400 | radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); |
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401 | radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL); |
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402 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
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403 | radeon_ring_write(rdev, |
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404 | RADEON_WAIT_2D_IDLECLEAN | |
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405 | RADEON_WAIT_HOST_IDLECLEAN | |
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406 | RADEON_WAIT_DMA_GUI_IDLE); |
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407 | if (fence) { |
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408 | r = radeon_fence_emit(rdev, fence); |
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409 | } |
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410 | radeon_ring_unlock_commit(rdev); |
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411 | return r; |
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412 | } |
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413 | |||
1128 | serge | 414 | #endif |
1117 | serge | 415 | |
1221 | serge | 416 | |
1179 | serge | 417 | static int r100_cp_wait_for_idle(struct radeon_device *rdev) |
418 | { |
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419 | unsigned i; |
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420 | u32 tmp; |
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421 | |||
422 | for (i = 0; i < rdev->usec_timeout; i++) { |
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423 | tmp = RREG32(R_000E40_RBBM_STATUS); |
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424 | if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { |
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425 | return 0; |
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426 | } |
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427 | udelay(1); |
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428 | } |
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429 | return -1; |
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430 | } |
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431 | |||
1117 | serge | 432 | void r100_ring_start(struct radeon_device *rdev) |
433 | { |
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434 | int r; |
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435 | |||
436 | r = radeon_ring_lock(rdev, 2); |
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437 | if (r) { |
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438 | return; |
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439 | } |
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440 | radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); |
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441 | radeon_ring_write(rdev, |
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442 | RADEON_ISYNC_ANY2D_IDLE3D | |
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443 | RADEON_ISYNC_ANY3D_IDLE2D | |
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444 | RADEON_ISYNC_WAIT_IDLEGUI | |
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445 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
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446 | radeon_ring_unlock_commit(rdev); |
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447 | } |
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448 | |||
1221 | serge | 449 | |
450 | /* Load the microcode for the CP */ |
||
451 | static int r100_cp_init_microcode(struct radeon_device *rdev) |
||
1117 | serge | 452 | { |
1221 | serge | 453 | struct platform_device *pdev; |
454 | const char *fw_name = NULL; |
||
455 | int err; |
||
1117 | serge | 456 | |
1221 | serge | 457 | DRM_DEBUG("\n"); |
1117 | serge | 458 | |
1221 | serge | 459 | // pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
460 | // err = IS_ERR(pdev); |
||
461 | // if (err) { |
||
462 | // printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); |
||
463 | // return -EINVAL; |
||
464 | // } |
||
1117 | serge | 465 | if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || |
466 | (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || |
||
467 | (rdev->family == CHIP_RS200)) { |
||
468 | DRM_INFO("Loading R100 Microcode\n"); |
||
1221 | serge | 469 | fw_name = FIRMWARE_R100; |
1117 | serge | 470 | } else if ((rdev->family == CHIP_R200) || |
471 | (rdev->family == CHIP_RV250) || |
||
472 | (rdev->family == CHIP_RV280) || |
||
473 | (rdev->family == CHIP_RS300)) { |
||
474 | DRM_INFO("Loading R200 Microcode\n"); |
||
1221 | serge | 475 | fw_name = FIRMWARE_R200; |
1117 | serge | 476 | } else if ((rdev->family == CHIP_R300) || |
477 | (rdev->family == CHIP_R350) || |
||
478 | (rdev->family == CHIP_RV350) || |
||
479 | (rdev->family == CHIP_RV380) || |
||
480 | (rdev->family == CHIP_RS400) || |
||
481 | (rdev->family == CHIP_RS480)) { |
||
482 | DRM_INFO("Loading R300 Microcode\n"); |
||
1221 | serge | 483 | fw_name = FIRMWARE_R300; |
1117 | serge | 484 | } else if ((rdev->family == CHIP_R420) || |
485 | (rdev->family == CHIP_R423) || |
||
486 | (rdev->family == CHIP_RV410)) { |
||
487 | DRM_INFO("Loading R400 Microcode\n"); |
||
1221 | serge | 488 | fw_name = FIRMWARE_R420; |
1117 | serge | 489 | } else if ((rdev->family == CHIP_RS690) || |
490 | (rdev->family == CHIP_RS740)) { |
||
491 | DRM_INFO("Loading RS690/RS740 Microcode\n"); |
||
1221 | serge | 492 | fw_name = FIRMWARE_RS690; |
1117 | serge | 493 | } else if (rdev->family == CHIP_RS600) { |
494 | DRM_INFO("Loading RS600 Microcode\n"); |
||
1221 | serge | 495 | fw_name = FIRMWARE_RS600; |
1117 | serge | 496 | } else if ((rdev->family == CHIP_RV515) || |
497 | (rdev->family == CHIP_R520) || |
||
498 | (rdev->family == CHIP_RV530) || |
||
499 | (rdev->family == CHIP_R580) || |
||
500 | (rdev->family == CHIP_RV560) || |
||
501 | (rdev->family == CHIP_RV570)) { |
||
502 | DRM_INFO("Loading R500 Microcode\n"); |
||
1221 | serge | 503 | fw_name = FIRMWARE_R520; |
1117 | serge | 504 | } |
1221 | serge | 505 | |
506 | // err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); |
||
507 | // platform_device_unregister(pdev); |
||
508 | if (err) { |
||
509 | printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", |
||
510 | fw_name); |
||
511 | } else if (rdev->me_fw->size % 8) { |
||
512 | printk(KERN_ERR |
||
513 | "radeon_cp: Bogus length %zu in firmware \"%s\"\n", |
||
514 | rdev->me_fw->size, fw_name); |
||
515 | err = -EINVAL; |
||
516 | release_firmware(rdev->me_fw); |
||
517 | rdev->me_fw = NULL; |
||
1117 | serge | 518 | } |
1221 | serge | 519 | return err; |
1117 | serge | 520 | } |
521 | |||
1221 | serge | 522 | static inline __u32 __swab32(__u32 x) |
1179 | serge | 523 | { |
1221 | serge | 524 | asm("bswapl %0" : |
525 | "=&r" (x) |
||
526 | :"r" (x)); |
||
527 | return x; |
||
1179 | serge | 528 | } |
529 | |||
1221 | serge | 530 | static inline __u32 be32_to_cpup(const __be32 *p) |
531 | { |
||
532 | return __swab32(*(__u32 *)p); |
||
533 | } |
||
1179 | serge | 534 | |
1221 | serge | 535 | |
536 | static void r100_cp_load_microcode(struct radeon_device *rdev) |
||
537 | { |
||
538 | const __be32 *fw_data; |
||
539 | int i, size; |
||
540 | |||
541 | if (r100_gui_wait_for_idle(rdev)) { |
||
542 | printk(KERN_WARNING "Failed to wait GUI idle while " |
||
543 | "programming pipes. Bad things might happen.\n"); |
||
544 | } |
||
545 | |||
546 | if (rdev->me_fw) { |
||
547 | size = rdev->me_fw->size / 4; |
||
548 | fw_data = (const __be32 *)&rdev->me_fw->data[0]; |
||
549 | WREG32(RADEON_CP_ME_RAM_ADDR, 0); |
||
550 | for (i = 0; i < size; i += 2) { |
||
551 | WREG32(RADEON_CP_ME_RAM_DATAH, |
||
552 | be32_to_cpup(&fw_data[i])); |
||
553 | WREG32(RADEON_CP_ME_RAM_DATAL, |
||
554 | be32_to_cpup(&fw_data[i + 1])); |
||
555 | } |
||
556 | } |
||
557 | } |
||
558 | |||
1117 | serge | 559 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) |
560 | { |
||
561 | unsigned rb_bufsz; |
||
562 | unsigned rb_blksz; |
||
563 | unsigned max_fetch; |
||
564 | unsigned pre_write_timer; |
||
565 | unsigned pre_write_limit; |
||
566 | unsigned indirect2_start; |
||
567 | unsigned indirect1_start; |
||
568 | uint32_t tmp; |
||
569 | int r; |
||
570 | |||
1129 | serge | 571 | if (r100_debugfs_cp_init(rdev)) { |
572 | DRM_ERROR("Failed to register debugfs file for CP !\n"); |
||
573 | } |
||
1117 | serge | 574 | /* Reset CP */ |
575 | tmp = RREG32(RADEON_CP_CSQ_STAT); |
||
576 | if ((tmp & (1 << 31))) { |
||
577 | DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp); |
||
578 | WREG32(RADEON_CP_CSQ_MODE, 0); |
||
579 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
||
580 | WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP); |
||
581 | tmp = RREG32(RADEON_RBBM_SOFT_RESET); |
||
582 | mdelay(2); |
||
583 | WREG32(RADEON_RBBM_SOFT_RESET, 0); |
||
584 | tmp = RREG32(RADEON_RBBM_SOFT_RESET); |
||
585 | mdelay(2); |
||
586 | tmp = RREG32(RADEON_CP_CSQ_STAT); |
||
587 | if ((tmp & (1 << 31))) { |
||
588 | DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp); |
||
589 | } |
||
590 | } else { |
||
591 | DRM_INFO("radeon: cp idle (0x%08X)\n", tmp); |
||
592 | } |
||
1179 | serge | 593 | |
594 | if (!rdev->me_fw) { |
||
595 | r = r100_cp_init_microcode(rdev); |
||
596 | if (r) { |
||
597 | DRM_ERROR("Failed to load firmware!\n"); |
||
598 | return r; |
||
599 | } |
||
600 | } |
||
601 | |||
1117 | serge | 602 | /* Align ring size */ |
603 | rb_bufsz = drm_order(ring_size / 8); |
||
604 | ring_size = (1 << (rb_bufsz + 1)) * 4; |
||
605 | r100_cp_load_microcode(rdev); |
||
606 | r = radeon_ring_init(rdev, ring_size); |
||
607 | if (r) { |
||
608 | return r; |
||
609 | } |
||
610 | /* Each time the cp read 1024 bytes (16 dword/quadword) update |
||
611 | * the rptr copy in system ram */ |
||
612 | rb_blksz = 9; |
||
613 | /* cp will read 128bytes at a time (4 dwords) */ |
||
614 | max_fetch = 1; |
||
615 | rdev->cp.align_mask = 16 - 1; |
||
616 | /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ |
||
617 | pre_write_timer = 64; |
||
618 | /* Force CP_RB_WPTR write if written more than one time before the |
||
619 | * delay expire |
||
620 | */ |
||
621 | pre_write_limit = 0; |
||
622 | /* Setup the cp cache like this (cache size is 96 dwords) : |
||
623 | * RING 0 to 15 |
||
624 | * INDIRECT1 16 to 79 |
||
625 | * INDIRECT2 80 to 95 |
||
626 | * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) |
||
627 | * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) |
||
628 | * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) |
||
629 | * Idea being that most of the gpu cmd will be through indirect1 buffer |
||
630 | * so it gets the bigger cache. |
||
631 | */ |
||
632 | indirect2_start = 80; |
||
633 | indirect1_start = 16; |
||
634 | /* cp setup */ |
||
635 | WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); |
||
1268 | serge | 636 | tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | |
1117 | serge | 637 | REG_SET(RADEON_RB_BLKSZ, rb_blksz) | |
638 | REG_SET(RADEON_MAX_FETCH, max_fetch) | |
||
639 | RADEON_RB_NO_UPDATE); |
||
1268 | serge | 640 | #ifdef __BIG_ENDIAN |
641 | tmp |= RADEON_BUF_SWAP_32BIT; |
||
642 | #endif |
||
643 | WREG32(RADEON_CP_RB_CNTL, tmp); |
||
644 | |||
1117 | serge | 645 | /* Set ring address */ |
646 | DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr); |
||
647 | WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr); |
||
648 | /* Force read & write ptr to 0 */ |
||
649 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
||
650 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
||
651 | WREG32(RADEON_CP_RB_WPTR, 0); |
||
652 | WREG32(RADEON_CP_RB_CNTL, tmp); |
||
653 | udelay(10); |
||
654 | rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); |
||
655 | rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR); |
||
656 | /* Set cp mode to bus mastering & enable cp*/ |
||
657 | WREG32(RADEON_CP_CSQ_MODE, |
||
658 | REG_SET(RADEON_INDIRECT2_START, indirect2_start) | |
||
659 | REG_SET(RADEON_INDIRECT1_START, indirect1_start)); |
||
660 | WREG32(0x718, 0); |
||
661 | WREG32(0x744, 0x00004D4D); |
||
662 | WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); |
||
663 | radeon_ring_start(rdev); |
||
664 | r = radeon_ring_test(rdev); |
||
665 | if (r) { |
||
666 | DRM_ERROR("radeon: cp isn't working (%d).\n", r); |
||
667 | return r; |
||
668 | } |
||
669 | rdev->cp.ready = true; |
||
670 | return 0; |
||
671 | } |
||
672 | |||
673 | void r100_cp_fini(struct radeon_device *rdev) |
||
674 | { |
||
1179 | serge | 675 | if (r100_cp_wait_for_idle(rdev)) { |
676 | DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); |
||
677 | } |
||
1117 | serge | 678 | /* Disable ring */ |
1179 | serge | 679 | r100_cp_disable(rdev); |
1117 | serge | 680 | radeon_ring_fini(rdev); |
681 | DRM_INFO("radeon: cp finalized\n"); |
||
682 | } |
||
683 | |||
684 | void r100_cp_disable(struct radeon_device *rdev) |
||
685 | { |
||
686 | /* Disable ring */ |
||
687 | rdev->cp.ready = false; |
||
688 | WREG32(RADEON_CP_CSQ_MODE, 0); |
||
689 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
||
690 | if (r100_gui_wait_for_idle(rdev)) { |
||
691 | printk(KERN_WARNING "Failed to wait GUI idle while " |
||
692 | "programming pipes. Bad things might happen.\n"); |
||
693 | } |
||
694 | } |
||
695 | |||
696 | int r100_cp_reset(struct radeon_device *rdev) |
||
697 | { |
||
698 | uint32_t tmp; |
||
699 | bool reinit_cp; |
||
700 | int i; |
||
701 | |||
1179 | serge | 702 | ENTER(); |
1117 | serge | 703 | |
704 | reinit_cp = rdev->cp.ready; |
||
705 | rdev->cp.ready = false; |
||
706 | WREG32(RADEON_CP_CSQ_MODE, 0); |
||
707 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
||
708 | WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP); |
||
709 | (void)RREG32(RADEON_RBBM_SOFT_RESET); |
||
710 | udelay(200); |
||
711 | WREG32(RADEON_RBBM_SOFT_RESET, 0); |
||
712 | /* Wait to prevent race in RBBM_STATUS */ |
||
713 | mdelay(1); |
||
714 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
715 | tmp = RREG32(RADEON_RBBM_STATUS); |
||
716 | if (!(tmp & (1 << 16))) { |
||
717 | DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n", |
||
718 | tmp); |
||
719 | if (reinit_cp) { |
||
720 | return r100_cp_init(rdev, rdev->cp.ring_size); |
||
721 | } |
||
722 | return 0; |
||
723 | } |
||
724 | DRM_UDELAY(1); |
||
725 | } |
||
726 | tmp = RREG32(RADEON_RBBM_STATUS); |
||
727 | DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp); |
||
728 | return -1; |
||
729 | } |
||
730 | |||
1179 | serge | 731 | void r100_cp_commit(struct radeon_device *rdev) |
732 | { |
||
733 | WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); |
||
734 | (void)RREG32(RADEON_CP_RB_WPTR); |
||
735 | } |
||
736 | |||
737 | |||
1117 | serge | 738 | #if 0 |
739 | /* |
||
740 | * CS functions |
||
741 | */ |
||
742 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
||
743 | struct radeon_cs_packet *pkt, |
||
744 | const unsigned *auth, unsigned n, |
||
745 | radeon_packet0_check_t check) |
||
746 | { |
||
747 | unsigned reg; |
||
748 | unsigned i, j, m; |
||
749 | unsigned idx; |
||
750 | int r; |
||
751 | |||
752 | idx = pkt->idx + 1; |
||
753 | reg = pkt->reg; |
||
754 | /* Check that register fall into register range |
||
755 | * determined by the number of entry (n) in the |
||
756 | * safe register bitmap. |
||
757 | */ |
||
758 | if (pkt->one_reg_wr) { |
||
759 | if ((reg >> 7) > n) { |
||
760 | return -EINVAL; |
||
761 | } |
||
762 | } else { |
||
763 | if (((reg + (pkt->count << 2)) >> 7) > n) { |
||
764 | return -EINVAL; |
||
765 | } |
||
766 | } |
||
767 | for (i = 0; i <= pkt->count; i++, idx++) { |
||
768 | j = (reg >> 7); |
||
769 | m = 1 << ((reg >> 2) & 31); |
||
770 | if (auth[j] & m) { |
||
771 | r = check(p, pkt, idx, reg); |
||
772 | if (r) { |
||
773 | return r; |
||
774 | } |
||
775 | } |
||
776 | if (pkt->one_reg_wr) { |
||
777 | if (!(auth[j] & m)) { |
||
778 | break; |
||
779 | } |
||
780 | } else { |
||
781 | reg += 4; |
||
782 | } |
||
783 | } |
||
784 | return 0; |
||
785 | } |
||
786 | |||
787 | void r100_cs_dump_packet(struct radeon_cs_parser *p, |
||
788 | struct radeon_cs_packet *pkt) |
||
789 | { |
||
790 | volatile uint32_t *ib; |
||
791 | unsigned i; |
||
792 | unsigned idx; |
||
793 | |||
794 | ib = p->ib->ptr; |
||
795 | idx = pkt->idx; |
||
796 | for (i = 0; i <= (pkt->count + 1); i++, idx++) { |
||
797 | DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); |
||
798 | } |
||
799 | } |
||
800 | |||
801 | /** |
||
802 | * r100_cs_packet_parse() - parse cp packet and point ib index to next packet |
||
803 | * @parser: parser structure holding parsing context. |
||
804 | * @pkt: where to store packet informations |
||
805 | * |
||
806 | * Assume that chunk_ib_index is properly set. Will return -EINVAL |
||
807 | * if packet is bigger than remaining ib size. or if packets is unknown. |
||
808 | **/ |
||
809 | int r100_cs_packet_parse(struct radeon_cs_parser *p, |
||
810 | struct radeon_cs_packet *pkt, |
||
811 | unsigned idx) |
||
812 | { |
||
813 | struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; |
||
1179 | serge | 814 | uint32_t header; |
1117 | serge | 815 | |
816 | if (idx >= ib_chunk->length_dw) { |
||
817 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n", |
||
818 | idx, ib_chunk->length_dw); |
||
819 | return -EINVAL; |
||
820 | } |
||
1221 | serge | 821 | header = radeon_get_ib_value(p, idx); |
1117 | serge | 822 | pkt->idx = idx; |
823 | pkt->type = CP_PACKET_GET_TYPE(header); |
||
824 | pkt->count = CP_PACKET_GET_COUNT(header); |
||
825 | switch (pkt->type) { |
||
826 | case PACKET_TYPE0: |
||
827 | pkt->reg = CP_PACKET0_GET_REG(header); |
||
828 | pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header); |
||
829 | break; |
||
830 | case PACKET_TYPE3: |
||
831 | pkt->opcode = CP_PACKET3_GET_OPCODE(header); |
||
832 | break; |
||
833 | case PACKET_TYPE2: |
||
834 | pkt->count = -1; |
||
835 | break; |
||
836 | default: |
||
837 | DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); |
||
838 | return -EINVAL; |
||
839 | } |
||
840 | if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { |
||
841 | DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", |
||
842 | pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); |
||
843 | return -EINVAL; |
||
844 | } |
||
845 | return 0; |
||
846 | } |
||
847 | |||
848 | /** |
||
1179 | serge | 849 | * r100_cs_packet_next_vline() - parse userspace VLINE packet |
850 | * @parser: parser structure holding parsing context. |
||
851 | * |
||
852 | * Userspace sends a special sequence for VLINE waits. |
||
853 | * PACKET0 - VLINE_START_END + value |
||
854 | * PACKET0 - WAIT_UNTIL +_value |
||
855 | * RELOC (P3) - crtc_id in reloc. |
||
856 | * |
||
857 | * This function parses this and relocates the VLINE START END |
||
858 | * and WAIT UNTIL packets to the correct crtc. |
||
859 | * It also detects a switched off crtc and nulls out the |
||
860 | * wait in that case. |
||
861 | */ |
||
862 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) |
||
863 | { |
||
864 | struct drm_mode_object *obj; |
||
865 | struct drm_crtc *crtc; |
||
866 | struct radeon_crtc *radeon_crtc; |
||
867 | struct radeon_cs_packet p3reloc, waitreloc; |
||
868 | int crtc_id; |
||
869 | int r; |
||
870 | uint32_t header, h_idx, reg; |
||
1221 | serge | 871 | volatile uint32_t *ib; |
1179 | serge | 872 | |
1221 | serge | 873 | ib = p->ib->ptr; |
1179 | serge | 874 | |
875 | /* parse the wait until */ |
||
876 | r = r100_cs_packet_parse(p, &waitreloc, p->idx); |
||
877 | if (r) |
||
878 | return r; |
||
879 | |||
880 | /* check its a wait until and only 1 count */ |
||
881 | if (waitreloc.reg != RADEON_WAIT_UNTIL || |
||
882 | waitreloc.count != 0) { |
||
883 | DRM_ERROR("vline wait had illegal wait until segment\n"); |
||
884 | r = -EINVAL; |
||
885 | return r; |
||
886 | } |
||
887 | |||
1221 | serge | 888 | if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { |
1179 | serge | 889 | DRM_ERROR("vline wait had illegal wait until\n"); |
890 | r = -EINVAL; |
||
891 | return r; |
||
892 | } |
||
893 | |||
894 | /* jump over the NOP */ |
||
1221 | serge | 895 | r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); |
1179 | serge | 896 | if (r) |
897 | return r; |
||
898 | |||
899 | h_idx = p->idx - 2; |
||
1221 | serge | 900 | p->idx += waitreloc.count + 2; |
901 | p->idx += p3reloc.count + 2; |
||
1179 | serge | 902 | |
1221 | serge | 903 | header = radeon_get_ib_value(p, h_idx); |
904 | crtc_id = radeon_get_ib_value(p, h_idx + 5); |
||
905 | reg = CP_PACKET0_GET_REG(header); |
||
1179 | serge | 906 | mutex_lock(&p->rdev->ddev->mode_config.mutex); |
907 | obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); |
||
908 | if (!obj) { |
||
909 | DRM_ERROR("cannot find crtc %d\n", crtc_id); |
||
910 | r = -EINVAL; |
||
911 | goto out; |
||
912 | } |
||
913 | crtc = obj_to_crtc(obj); |
||
914 | radeon_crtc = to_radeon_crtc(crtc); |
||
915 | crtc_id = radeon_crtc->crtc_id; |
||
916 | |||
917 | if (!crtc->enabled) { |
||
918 | /* if the CRTC isn't enabled - we need to nop out the wait until */ |
||
1221 | serge | 919 | ib[h_idx + 2] = PACKET2(0); |
920 | ib[h_idx + 3] = PACKET2(0); |
||
1179 | serge | 921 | } else if (crtc_id == 1) { |
922 | switch (reg) { |
||
923 | case AVIVO_D1MODE_VLINE_START_END: |
||
1221 | serge | 924 | header &= ~R300_CP_PACKET0_REG_MASK; |
1179 | serge | 925 | header |= AVIVO_D2MODE_VLINE_START_END >> 2; |
926 | break; |
||
927 | case RADEON_CRTC_GUI_TRIG_VLINE: |
||
1221 | serge | 928 | header &= ~R300_CP_PACKET0_REG_MASK; |
1179 | serge | 929 | header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; |
930 | break; |
||
931 | default: |
||
932 | DRM_ERROR("unknown crtc reloc\n"); |
||
933 | r = -EINVAL; |
||
934 | goto out; |
||
935 | } |
||
1221 | serge | 936 | ib[h_idx] = header; |
937 | ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; |
||
1179 | serge | 938 | } |
939 | out: |
||
940 | mutex_unlock(&p->rdev->ddev->mode_config.mutex); |
||
941 | return r; |
||
942 | } |
||
943 | |||
944 | /** |
||
1117 | serge | 945 | * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 |
946 | * @parser: parser structure holding parsing context. |
||
947 | * @data: pointer to relocation data |
||
948 | * @offset_start: starting offset |
||
949 | * @offset_mask: offset mask (to align start offset on) |
||
950 | * @reloc: reloc informations |
||
951 | * |
||
952 | * Check next packet is relocation packet3, do bo validation and compute |
||
953 | * GPU offset using the provided start. |
||
954 | **/ |
||
955 | int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, |
||
956 | struct radeon_cs_reloc **cs_reloc) |
||
957 | { |
||
958 | struct radeon_cs_chunk *relocs_chunk; |
||
959 | struct radeon_cs_packet p3reloc; |
||
960 | unsigned idx; |
||
961 | int r; |
||
962 | |||
963 | if (p->chunk_relocs_idx == -1) { |
||
964 | DRM_ERROR("No relocation chunk !\n"); |
||
965 | return -EINVAL; |
||
966 | } |
||
967 | *cs_reloc = NULL; |
||
968 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; |
||
969 | r = r100_cs_packet_parse(p, &p3reloc, p->idx); |
||
970 | if (r) { |
||
971 | return r; |
||
972 | } |
||
973 | p->idx += p3reloc.count + 2; |
||
974 | if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { |
||
975 | DRM_ERROR("No packet3 for relocation for packet at %d.\n", |
||
976 | p3reloc.idx); |
||
977 | r100_cs_dump_packet(p, &p3reloc); |
||
978 | return -EINVAL; |
||
979 | } |
||
1221 | serge | 980 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); |
1117 | serge | 981 | if (idx >= relocs_chunk->length_dw) { |
982 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", |
||
983 | idx, relocs_chunk->length_dw); |
||
984 | r100_cs_dump_packet(p, &p3reloc); |
||
985 | return -EINVAL; |
||
986 | } |
||
987 | /* FIXME: we assume reloc size is 4 dwords */ |
||
988 | *cs_reloc = p->relocs_ptr[(idx / 4)]; |
||
989 | return 0; |
||
990 | } |
||
991 | |||
1179 | serge | 992 | static int r100_get_vtx_size(uint32_t vtx_fmt) |
993 | { |
||
994 | int vtx_size; |
||
995 | vtx_size = 2; |
||
996 | /* ordered according to bits in spec */ |
||
997 | if (vtx_fmt & RADEON_SE_VTX_FMT_W0) |
||
998 | vtx_size++; |
||
999 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) |
||
1000 | vtx_size += 3; |
||
1001 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) |
||
1002 | vtx_size++; |
||
1003 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) |
||
1004 | vtx_size++; |
||
1005 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) |
||
1006 | vtx_size += 3; |
||
1007 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) |
||
1008 | vtx_size++; |
||
1009 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) |
||
1010 | vtx_size++; |
||
1011 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) |
||
1012 | vtx_size += 2; |
||
1013 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) |
||
1014 | vtx_size += 2; |
||
1015 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) |
||
1016 | vtx_size++; |
||
1017 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) |
||
1018 | vtx_size += 2; |
||
1019 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) |
||
1020 | vtx_size++; |
||
1021 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) |
||
1022 | vtx_size += 2; |
||
1023 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) |
||
1024 | vtx_size++; |
||
1025 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) |
||
1026 | vtx_size++; |
||
1027 | /* blend weight */ |
||
1028 | if (vtx_fmt & (0x7 << 15)) |
||
1029 | vtx_size += (vtx_fmt >> 15) & 0x7; |
||
1030 | if (vtx_fmt & RADEON_SE_VTX_FMT_N0) |
||
1031 | vtx_size += 3; |
||
1032 | if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) |
||
1033 | vtx_size += 2; |
||
1034 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) |
||
1035 | vtx_size++; |
||
1036 | if (vtx_fmt & RADEON_SE_VTX_FMT_W1) |
||
1037 | vtx_size++; |
||
1038 | if (vtx_fmt & RADEON_SE_VTX_FMT_N1) |
||
1039 | vtx_size++; |
||
1040 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z) |
||
1041 | vtx_size++; |
||
1042 | return vtx_size; |
||
1043 | } |
||
1044 | |||
1117 | serge | 1045 | static int r100_packet0_check(struct radeon_cs_parser *p, |
1179 | serge | 1046 | struct radeon_cs_packet *pkt, |
1047 | unsigned idx, unsigned reg) |
||
1117 | serge | 1048 | { |
1049 | struct radeon_cs_reloc *reloc; |
||
1179 | serge | 1050 | struct r100_cs_track *track; |
1117 | serge | 1051 | volatile uint32_t *ib; |
1052 | uint32_t tmp; |
||
1053 | int r; |
||
1179 | serge | 1054 | int i, face; |
1055 | u32 tile_flags = 0; |
||
1221 | serge | 1056 | u32 idx_value; |
1117 | serge | 1057 | |
1058 | ib = p->ib->ptr; |
||
1179 | serge | 1059 | track = (struct r100_cs_track *)p->track; |
1060 | |||
1221 | serge | 1061 | idx_value = radeon_get_ib_value(p, idx); |
1062 | |||
1117 | serge | 1063 | switch (reg) { |
1179 | serge | 1064 | case RADEON_CRTC_GUI_TRIG_VLINE: |
1065 | r = r100_cs_packet_parse_vline(p); |
||
1066 | if (r) { |
||
1067 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1068 | idx, reg); |
||
1069 | r100_cs_dump_packet(p, pkt); |
||
1070 | return r; |
||
1071 | } |
||
1072 | break; |
||
1117 | serge | 1073 | /* FIXME: only allow PACKET3 blit? easier to check for out of |
1074 | * range access */ |
||
1075 | case RADEON_DST_PITCH_OFFSET: |
||
1076 | case RADEON_SRC_PITCH_OFFSET: |
||
1179 | serge | 1077 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
1078 | if (r) |
||
1079 | return r; |
||
1080 | break; |
||
1081 | case RADEON_RB3D_DEPTHOFFSET: |
||
1117 | serge | 1082 | r = r100_cs_packet_next_reloc(p, &reloc); |
1083 | if (r) { |
||
1084 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1085 | idx, reg); |
||
1086 | r100_cs_dump_packet(p, pkt); |
||
1087 | return r; |
||
1088 | } |
||
1179 | serge | 1089 | track->zb.robj = reloc->robj; |
1221 | serge | 1090 | track->zb.offset = idx_value; |
1091 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
||
1117 | serge | 1092 | break; |
1093 | case RADEON_RB3D_COLOROFFSET: |
||
1179 | serge | 1094 | r = r100_cs_packet_next_reloc(p, &reloc); |
1095 | if (r) { |
||
1096 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1097 | idx, reg); |
||
1098 | r100_cs_dump_packet(p, pkt); |
||
1099 | return r; |
||
1100 | } |
||
1101 | track->cb[0].robj = reloc->robj; |
||
1221 | serge | 1102 | track->cb[0].offset = idx_value; |
1103 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
||
1179 | serge | 1104 | break; |
1117 | serge | 1105 | case RADEON_PP_TXOFFSET_0: |
1106 | case RADEON_PP_TXOFFSET_1: |
||
1107 | case RADEON_PP_TXOFFSET_2: |
||
1179 | serge | 1108 | i = (reg - RADEON_PP_TXOFFSET_0) / 24; |
1109 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1110 | if (r) { |
||
1111 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1112 | idx, reg); |
||
1113 | r100_cs_dump_packet(p, pkt); |
||
1114 | return r; |
||
1115 | } |
||
1221 | serge | 1116 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1179 | serge | 1117 | track->textures[i].robj = reloc->robj; |
1118 | break; |
||
1119 | case RADEON_PP_CUBIC_OFFSET_T0_0: |
||
1120 | case RADEON_PP_CUBIC_OFFSET_T0_1: |
||
1121 | case RADEON_PP_CUBIC_OFFSET_T0_2: |
||
1122 | case RADEON_PP_CUBIC_OFFSET_T0_3: |
||
1123 | case RADEON_PP_CUBIC_OFFSET_T0_4: |
||
1124 | i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; |
||
1125 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1126 | if (r) { |
||
1127 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1128 | idx, reg); |
||
1129 | r100_cs_dump_packet(p, pkt); |
||
1130 | return r; |
||
1131 | } |
||
1221 | serge | 1132 | track->textures[0].cube_info[i].offset = idx_value; |
1133 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
||
1179 | serge | 1134 | track->textures[0].cube_info[i].robj = reloc->robj; |
1135 | break; |
||
1136 | case RADEON_PP_CUBIC_OFFSET_T1_0: |
||
1137 | case RADEON_PP_CUBIC_OFFSET_T1_1: |
||
1138 | case RADEON_PP_CUBIC_OFFSET_T1_2: |
||
1139 | case RADEON_PP_CUBIC_OFFSET_T1_3: |
||
1140 | case RADEON_PP_CUBIC_OFFSET_T1_4: |
||
1141 | i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; |
||
1142 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1143 | if (r) { |
||
1144 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1145 | idx, reg); |
||
1146 | r100_cs_dump_packet(p, pkt); |
||
1147 | return r; |
||
1148 | } |
||
1221 | serge | 1149 | track->textures[1].cube_info[i].offset = idx_value; |
1150 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
||
1179 | serge | 1151 | track->textures[1].cube_info[i].robj = reloc->robj; |
1152 | break; |
||
1153 | case RADEON_PP_CUBIC_OFFSET_T2_0: |
||
1154 | case RADEON_PP_CUBIC_OFFSET_T2_1: |
||
1155 | case RADEON_PP_CUBIC_OFFSET_T2_2: |
||
1156 | case RADEON_PP_CUBIC_OFFSET_T2_3: |
||
1157 | case RADEON_PP_CUBIC_OFFSET_T2_4: |
||
1158 | i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; |
||
1117 | serge | 1159 | r = r100_cs_packet_next_reloc(p, &reloc); |
1160 | if (r) { |
||
1161 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1162 | idx, reg); |
||
1163 | r100_cs_dump_packet(p, pkt); |
||
1164 | return r; |
||
1165 | } |
||
1221 | serge | 1166 | track->textures[2].cube_info[i].offset = idx_value; |
1167 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
||
1179 | serge | 1168 | track->textures[2].cube_info[i].robj = reloc->robj; |
1169 | break; |
||
1170 | case RADEON_RE_WIDTH_HEIGHT: |
||
1221 | serge | 1171 | track->maxy = ((idx_value >> 16) & 0x7FF); |
1117 | serge | 1172 | break; |
1179 | serge | 1173 | case RADEON_RB3D_COLORPITCH: |
1174 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1175 | if (r) { |
||
1176 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1177 | idx, reg); |
||
1178 | r100_cs_dump_packet(p, pkt); |
||
1179 | return r; |
||
1180 | } |
||
1181 | |||
1182 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
||
1183 | tile_flags |= RADEON_COLOR_TILE_ENABLE; |
||
1184 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
||
1185 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
||
1186 | |||
1221 | serge | 1187 | tmp = idx_value & ~(0x7 << 16); |
1179 | serge | 1188 | tmp |= tile_flags; |
1189 | ib[idx] = tmp; |
||
1190 | |||
1221 | serge | 1191 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
1179 | serge | 1192 | break; |
1193 | case RADEON_RB3D_DEPTHPITCH: |
||
1221 | serge | 1194 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
1179 | serge | 1195 | break; |
1196 | case RADEON_RB3D_CNTL: |
||
1221 | serge | 1197 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
1179 | serge | 1198 | case 7: |
1199 | case 8: |
||
1200 | case 9: |
||
1201 | case 11: |
||
1202 | case 12: |
||
1203 | track->cb[0].cpp = 1; |
||
1204 | break; |
||
1205 | case 3: |
||
1206 | case 4: |
||
1207 | case 15: |
||
1208 | track->cb[0].cpp = 2; |
||
1209 | break; |
||
1210 | case 6: |
||
1211 | track->cb[0].cpp = 4; |
||
1212 | break; |
||
1117 | serge | 1213 | default: |
1179 | serge | 1214 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
1221 | serge | 1215 | ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
1179 | serge | 1216 | return -EINVAL; |
1217 | } |
||
1221 | serge | 1218 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
1179 | serge | 1219 | break; |
1220 | case RADEON_RB3D_ZSTENCILCNTL: |
||
1221 | serge | 1221 | switch (idx_value & 0xf) { |
1179 | serge | 1222 | case 0: |
1223 | track->zb.cpp = 2; |
||
1117 | serge | 1224 | break; |
1179 | serge | 1225 | case 2: |
1226 | case 3: |
||
1227 | case 4: |
||
1228 | case 5: |
||
1229 | case 9: |
||
1230 | case 11: |
||
1231 | track->zb.cpp = 4; |
||
1232 | break; |
||
1233 | default: |
||
1234 | break; |
||
1117 | serge | 1235 | } |
1236 | break; |
||
1179 | serge | 1237 | case RADEON_RB3D_ZPASS_ADDR: |
1238 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1239 | if (r) { |
||
1240 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1241 | idx, reg); |
||
1242 | r100_cs_dump_packet(p, pkt); |
||
1243 | return r; |
||
1244 | } |
||
1221 | serge | 1245 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1179 | serge | 1246 | break; |
1247 | case RADEON_PP_CNTL: |
||
1248 | { |
||
1221 | serge | 1249 | uint32_t temp = idx_value >> 4; |
1179 | serge | 1250 | for (i = 0; i < track->num_texture; i++) |
1251 | track->textures[i].enabled = !!(temp & (1 << i)); |
||
1117 | serge | 1252 | } |
1179 | serge | 1253 | break; |
1254 | case RADEON_SE_VF_CNTL: |
||
1221 | serge | 1255 | track->vap_vf_cntl = idx_value; |
1179 | serge | 1256 | break; |
1257 | case RADEON_SE_VTX_FMT: |
||
1221 | serge | 1258 | track->vtx_size = r100_get_vtx_size(idx_value); |
1179 | serge | 1259 | break; |
1260 | case RADEON_PP_TEX_SIZE_0: |
||
1261 | case RADEON_PP_TEX_SIZE_1: |
||
1262 | case RADEON_PP_TEX_SIZE_2: |
||
1263 | i = (reg - RADEON_PP_TEX_SIZE_0) / 8; |
||
1221 | serge | 1264 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
1265 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
||
1179 | serge | 1266 | break; |
1267 | case RADEON_PP_TEX_PITCH_0: |
||
1268 | case RADEON_PP_TEX_PITCH_1: |
||
1269 | case RADEON_PP_TEX_PITCH_2: |
||
1270 | i = (reg - RADEON_PP_TEX_PITCH_0) / 8; |
||
1221 | serge | 1271 | track->textures[i].pitch = idx_value + 32; |
1179 | serge | 1272 | break; |
1273 | case RADEON_PP_TXFILTER_0: |
||
1274 | case RADEON_PP_TXFILTER_1: |
||
1275 | case RADEON_PP_TXFILTER_2: |
||
1276 | i = (reg - RADEON_PP_TXFILTER_0) / 24; |
||
1221 | serge | 1277 | track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) |
1179 | serge | 1278 | >> RADEON_MAX_MIP_LEVEL_SHIFT); |
1221 | serge | 1279 | tmp = (idx_value >> 23) & 0x7; |
1179 | serge | 1280 | if (tmp == 2 || tmp == 6) |
1281 | track->textures[i].roundup_w = false; |
||
1221 | serge | 1282 | tmp = (idx_value >> 27) & 0x7; |
1179 | serge | 1283 | if (tmp == 2 || tmp == 6) |
1284 | track->textures[i].roundup_h = false; |
||
1285 | break; |
||
1286 | case RADEON_PP_TXFORMAT_0: |
||
1287 | case RADEON_PP_TXFORMAT_1: |
||
1288 | case RADEON_PP_TXFORMAT_2: |
||
1289 | i = (reg - RADEON_PP_TXFORMAT_0) / 24; |
||
1221 | serge | 1290 | if (idx_value & RADEON_TXFORMAT_NON_POWER2) { |
1179 | serge | 1291 | track->textures[i].use_pitch = 1; |
1292 | } else { |
||
1293 | track->textures[i].use_pitch = 0; |
||
1221 | serge | 1294 | track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
1295 | track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
||
1179 | serge | 1296 | } |
1221 | serge | 1297 | if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) |
1179 | serge | 1298 | track->textures[i].tex_coord_type = 2; |
1221 | serge | 1299 | switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
1179 | serge | 1300 | case RADEON_TXFORMAT_I8: |
1301 | case RADEON_TXFORMAT_RGB332: |
||
1302 | case RADEON_TXFORMAT_Y8: |
||
1303 | track->textures[i].cpp = 1; |
||
1304 | break; |
||
1305 | case RADEON_TXFORMAT_AI88: |
||
1306 | case RADEON_TXFORMAT_ARGB1555: |
||
1307 | case RADEON_TXFORMAT_RGB565: |
||
1308 | case RADEON_TXFORMAT_ARGB4444: |
||
1309 | case RADEON_TXFORMAT_VYUY422: |
||
1310 | case RADEON_TXFORMAT_YVYU422: |
||
1311 | case RADEON_TXFORMAT_DXT1: |
||
1312 | case RADEON_TXFORMAT_SHADOW16: |
||
1313 | case RADEON_TXFORMAT_LDUDV655: |
||
1314 | case RADEON_TXFORMAT_DUDV88: |
||
1315 | track->textures[i].cpp = 2; |
||
1316 | break; |
||
1317 | case RADEON_TXFORMAT_ARGB8888: |
||
1318 | case RADEON_TXFORMAT_RGBA8888: |
||
1319 | case RADEON_TXFORMAT_DXT23: |
||
1320 | case RADEON_TXFORMAT_DXT45: |
||
1321 | case RADEON_TXFORMAT_SHADOW32: |
||
1322 | case RADEON_TXFORMAT_LDUDUV8888: |
||
1323 | track->textures[i].cpp = 4; |
||
1324 | break; |
||
1325 | } |
||
1221 | serge | 1326 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
1327 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
||
1179 | serge | 1328 | break; |
1329 | case RADEON_PP_CUBIC_FACES_0: |
||
1330 | case RADEON_PP_CUBIC_FACES_1: |
||
1331 | case RADEON_PP_CUBIC_FACES_2: |
||
1221 | serge | 1332 | tmp = idx_value; |
1179 | serge | 1333 | i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; |
1334 | for (face = 0; face < 4; face++) { |
||
1335 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
||
1336 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); |
||
1337 | } |
||
1338 | break; |
||
1339 | default: |
||
1340 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
||
1341 | reg, idx); |
||
1342 | return -EINVAL; |
||
1117 | serge | 1343 | } |
1344 | return 0; |
||
1345 | } |
||
1346 | |||
1347 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
||
1348 | struct radeon_cs_packet *pkt, |
||
1321 | serge | 1349 | struct radeon_bo *robj) |
1117 | serge | 1350 | { |
1351 | unsigned idx; |
||
1221 | serge | 1352 | u32 value; |
1117 | serge | 1353 | idx = pkt->idx + 1; |
1221 | serge | 1354 | value = radeon_get_ib_value(p, idx + 2); |
1321 | serge | 1355 | if ((value + 1) > radeon_bo_size(robj)) { |
1117 | serge | 1356 | DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " |
1357 | "(need %u have %lu) !\n", |
||
1221 | serge | 1358 | value + 1, |
1321 | serge | 1359 | radeon_bo_size(robj)); |
1117 | serge | 1360 | return -EINVAL; |
1361 | } |
||
1362 | return 0; |
||
1363 | } |
||
1364 | |||
1365 | static int r100_packet3_check(struct radeon_cs_parser *p, |
||
1366 | struct radeon_cs_packet *pkt) |
||
1367 | { |
||
1368 | struct radeon_cs_reloc *reloc; |
||
1179 | serge | 1369 | struct r100_cs_track *track; |
1117 | serge | 1370 | unsigned idx; |
1371 | volatile uint32_t *ib; |
||
1372 | int r; |
||
1373 | |||
1374 | ib = p->ib->ptr; |
||
1375 | idx = pkt->idx + 1; |
||
1179 | serge | 1376 | track = (struct r100_cs_track *)p->track; |
1117 | serge | 1377 | switch (pkt->opcode) { |
1378 | case PACKET3_3D_LOAD_VBPNTR: |
||
1221 | serge | 1379 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
1380 | if (r) |
||
1117 | serge | 1381 | return r; |
1382 | break; |
||
1383 | case PACKET3_INDX_BUFFER: |
||
1384 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1385 | if (r) { |
||
1386 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
||
1387 | r100_cs_dump_packet(p, pkt); |
||
1388 | return r; |
||
1389 | } |
||
1221 | serge | 1390 | ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); |
1117 | serge | 1391 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1392 | if (r) { |
||
1393 | return r; |
||
1394 | } |
||
1395 | break; |
||
1396 | case 0x23: |
||
1397 | /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ |
||
1398 | r = r100_cs_packet_next_reloc(p, &reloc); |
||
1399 | if (r) { |
||
1400 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
||
1401 | r100_cs_dump_packet(p, pkt); |
||
1402 | return r; |
||
1403 | } |
||
1221 | serge | 1404 | ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); |
1179 | serge | 1405 | track->num_arrays = 1; |
1221 | serge | 1406 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); |
1179 | serge | 1407 | |
1408 | track->arrays[0].robj = reloc->robj; |
||
1409 | track->arrays[0].esize = track->vtx_size; |
||
1410 | |||
1221 | serge | 1411 | track->max_indx = radeon_get_ib_value(p, idx+1); |
1179 | serge | 1412 | |
1221 | serge | 1413 | track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); |
1179 | serge | 1414 | track->immd_dwords = pkt->count - 1; |
1415 | r = r100_cs_track_check(p->rdev, track); |
||
1416 | if (r) |
||
1417 | return r; |
||
1117 | serge | 1418 | break; |
1419 | case PACKET3_3D_DRAW_IMMD: |
||
1221 | serge | 1420 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
1179 | serge | 1421 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1422 | return -EINVAL; |
||
1423 | } |
||
1221 | serge | 1424 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1179 | serge | 1425 | track->immd_dwords = pkt->count - 1; |
1426 | r = r100_cs_track_check(p->rdev, track); |
||
1427 | if (r) |
||
1428 | return r; |
||
1429 | break; |
||
1117 | serge | 1430 | /* triggers drawing using in-packet vertex data */ |
1431 | case PACKET3_3D_DRAW_IMMD_2: |
||
1221 | serge | 1432 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
1179 | serge | 1433 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1434 | return -EINVAL; |
||
1435 | } |
||
1221 | serge | 1436 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1179 | serge | 1437 | track->immd_dwords = pkt->count; |
1438 | r = r100_cs_track_check(p->rdev, track); |
||
1439 | if (r) |
||
1440 | return r; |
||
1441 | break; |
||
1117 | serge | 1442 | /* triggers drawing using in-packet vertex data */ |
1443 | case PACKET3_3D_DRAW_VBUF_2: |
||
1221 | serge | 1444 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1179 | serge | 1445 | r = r100_cs_track_check(p->rdev, track); |
1446 | if (r) |
||
1447 | return r; |
||
1448 | break; |
||
1117 | serge | 1449 | /* triggers drawing of vertex buffers setup elsewhere */ |
1450 | case PACKET3_3D_DRAW_INDX_2: |
||
1221 | serge | 1451 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1179 | serge | 1452 | r = r100_cs_track_check(p->rdev, track); |
1453 | if (r) |
||
1454 | return r; |
||
1455 | break; |
||
1117 | serge | 1456 | /* triggers drawing using indices to vertex buffer */ |
1457 | case PACKET3_3D_DRAW_VBUF: |
||
1221 | serge | 1458 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1179 | serge | 1459 | r = r100_cs_track_check(p->rdev, track); |
1460 | if (r) |
||
1461 | return r; |
||
1462 | break; |
||
1117 | serge | 1463 | /* triggers drawing of vertex buffers setup elsewhere */ |
1464 | case PACKET3_3D_DRAW_INDX: |
||
1221 | serge | 1465 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1179 | serge | 1466 | r = r100_cs_track_check(p->rdev, track); |
1467 | if (r) |
||
1468 | return r; |
||
1469 | break; |
||
1117 | serge | 1470 | /* triggers drawing using indices to vertex buffer */ |
1471 | case PACKET3_NOP: |
||
1472 | break; |
||
1473 | default: |
||
1474 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); |
||
1475 | return -EINVAL; |
||
1476 | } |
||
1477 | return 0; |
||
1478 | } |
||
1479 | |||
1480 | int r100_cs_parse(struct radeon_cs_parser *p) |
||
1481 | { |
||
1482 | struct radeon_cs_packet pkt; |
||
1179 | serge | 1483 | struct r100_cs_track *track; |
1117 | serge | 1484 | int r; |
1485 | |||
1179 | serge | 1486 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
1487 | r100_cs_track_clear(p->rdev, track); |
||
1488 | p->track = track; |
||
1117 | serge | 1489 | do { |
1490 | r = r100_cs_packet_parse(p, &pkt, p->idx); |
||
1491 | if (r) { |
||
1492 | return r; |
||
1493 | } |
||
1494 | p->idx += pkt.count + 2; |
||
1495 | switch (pkt.type) { |
||
1496 | case PACKET_TYPE0: |
||
1179 | serge | 1497 | if (p->rdev->family >= CHIP_R200) |
1498 | r = r100_cs_parse_packet0(p, &pkt, |
||
1499 | p->rdev->config.r100.reg_safe_bm, |
||
1500 | p->rdev->config.r100.reg_safe_bm_size, |
||
1501 | &r200_packet0_check); |
||
1502 | else |
||
1503 | r = r100_cs_parse_packet0(p, &pkt, |
||
1504 | p->rdev->config.r100.reg_safe_bm, |
||
1505 | p->rdev->config.r100.reg_safe_bm_size, |
||
1506 | &r100_packet0_check); |
||
1117 | serge | 1507 | break; |
1508 | case PACKET_TYPE2: |
||
1509 | break; |
||
1510 | case PACKET_TYPE3: |
||
1511 | r = r100_packet3_check(p, &pkt); |
||
1512 | break; |
||
1513 | default: |
||
1514 | DRM_ERROR("Unknown packet type %d !\n", |
||
1515 | pkt.type); |
||
1516 | return -EINVAL; |
||
1517 | } |
||
1518 | if (r) { |
||
1519 | return r; |
||
1520 | } |
||
1521 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
||
1522 | return 0; |
||
1523 | } |
||
1524 | |||
1128 | serge | 1525 | #endif |
1117 | serge | 1526 | |
1527 | /* |
||
1528 | * Global GPU functions |
||
1529 | */ |
||
1530 | void r100_errata(struct radeon_device *rdev) |
||
1531 | { |
||
1532 | rdev->pll_errata = 0; |
||
1533 | |||
1534 | if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { |
||
1535 | rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; |
||
1536 | } |
||
1537 | |||
1538 | if (rdev->family == CHIP_RV100 || |
||
1539 | rdev->family == CHIP_RS100 || |
||
1540 | rdev->family == CHIP_RS200) { |
||
1541 | rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; |
||
1542 | } |
||
1543 | } |
||
1544 | |||
1545 | /* Wait for vertical sync on primary CRTC */ |
||
1546 | void r100_gpu_wait_for_vsync(struct radeon_device *rdev) |
||
1547 | { |
||
1548 | uint32_t crtc_gen_cntl, tmp; |
||
1549 | int i; |
||
1550 | |||
1551 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); |
||
1552 | if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || |
||
1553 | !(crtc_gen_cntl & RADEON_CRTC_EN)) { |
||
1554 | return; |
||
1555 | } |
||
1556 | /* Clear the CRTC_VBLANK_SAVE bit */ |
||
1557 | WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); |
||
1558 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
1559 | tmp = RREG32(RADEON_CRTC_STATUS); |
||
1560 | if (tmp & RADEON_CRTC_VBLANK_SAVE) { |
||
1561 | return; |
||
1562 | } |
||
1563 | DRM_UDELAY(1); |
||
1564 | } |
||
1565 | } |
||
1566 | |||
1567 | /* Wait for vertical sync on secondary CRTC */ |
||
1568 | void r100_gpu_wait_for_vsync2(struct radeon_device *rdev) |
||
1569 | { |
||
1570 | uint32_t crtc2_gen_cntl, tmp; |
||
1571 | int i; |
||
1572 | |||
1573 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
||
1574 | if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || |
||
1575 | !(crtc2_gen_cntl & RADEON_CRTC2_EN)) |
||
1576 | return; |
||
1577 | |||
1578 | /* Clear the CRTC_VBLANK_SAVE bit */ |
||
1579 | WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); |
||
1580 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
1581 | tmp = RREG32(RADEON_CRTC2_STATUS); |
||
1582 | if (tmp & RADEON_CRTC2_VBLANK_SAVE) { |
||
1583 | return; |
||
1584 | } |
||
1585 | DRM_UDELAY(1); |
||
1586 | } |
||
1587 | } |
||
1588 | |||
1589 | int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) |
||
1590 | { |
||
1591 | unsigned i; |
||
1592 | uint32_t tmp; |
||
1593 | |||
1594 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
1595 | tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; |
||
1596 | if (tmp >= n) { |
||
1597 | return 0; |
||
1598 | } |
||
1599 | DRM_UDELAY(1); |
||
1600 | } |
||
1601 | return -1; |
||
1602 | } |
||
1603 | |||
1604 | int r100_gui_wait_for_idle(struct radeon_device *rdev) |
||
1605 | { |
||
1606 | unsigned i; |
||
1607 | uint32_t tmp; |
||
1608 | |||
1609 | if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { |
||
1610 | printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" |
||
1611 | " Bad things might happen.\n"); |
||
1612 | } |
||
1613 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
1614 | tmp = RREG32(RADEON_RBBM_STATUS); |
||
1615 | if (!(tmp & (1 << 31))) { |
||
1616 | return 0; |
||
1617 | } |
||
1618 | DRM_UDELAY(1); |
||
1619 | } |
||
1620 | return -1; |
||
1621 | } |
||
1622 | |||
1623 | int r100_mc_wait_for_idle(struct radeon_device *rdev) |
||
1624 | { |
||
1625 | unsigned i; |
||
1626 | uint32_t tmp; |
||
1627 | |||
1628 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
1629 | /* read MC_STATUS */ |
||
1630 | tmp = RREG32(0x0150); |
||
1631 | if (tmp & (1 << 2)) { |
||
1632 | return 0; |
||
1633 | } |
||
1634 | DRM_UDELAY(1); |
||
1635 | } |
||
1636 | return -1; |
||
1637 | } |
||
1638 | |||
1639 | void r100_gpu_init(struct radeon_device *rdev) |
||
1640 | { |
||
1641 | /* TODO: anythings to do here ? pipes ? */ |
||
1642 | r100_hdp_reset(rdev); |
||
1643 | } |
||
1644 | |||
1321 | serge | 1645 | void r100_hdp_flush(struct radeon_device *rdev) |
1646 | { |
||
1647 | u32 tmp; |
||
1648 | tmp = RREG32(RADEON_HOST_PATH_CNTL); |
||
1649 | tmp |= RADEON_HDP_READ_BUFFER_INVALIDATE; |
||
1650 | WREG32(RADEON_HOST_PATH_CNTL, tmp); |
||
1651 | } |
||
1652 | |||
1117 | serge | 1653 | void r100_hdp_reset(struct radeon_device *rdev) |
1654 | { |
||
1655 | uint32_t tmp; |
||
1656 | |||
1179 | serge | 1657 | ENTER(); |
1117 | serge | 1658 | |
1659 | tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL; |
||
1660 | tmp |= (7 << 28); |
||
1661 | WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE); |
||
1662 | (void)RREG32(RADEON_HOST_PATH_CNTL); |
||
1663 | udelay(200); |
||
1664 | WREG32(RADEON_RBBM_SOFT_RESET, 0); |
||
1665 | WREG32(RADEON_HOST_PATH_CNTL, tmp); |
||
1666 | (void)RREG32(RADEON_HOST_PATH_CNTL); |
||
1667 | } |
||
1668 | |||
1669 | int r100_rb2d_reset(struct radeon_device *rdev) |
||
1670 | { |
||
1671 | uint32_t tmp; |
||
1672 | int i; |
||
1673 | |||
1179 | serge | 1674 | ENTER(); |
1117 | serge | 1675 | |
1676 | WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2); |
||
1677 | (void)RREG32(RADEON_RBBM_SOFT_RESET); |
||
1678 | udelay(200); |
||
1679 | WREG32(RADEON_RBBM_SOFT_RESET, 0); |
||
1680 | /* Wait to prevent race in RBBM_STATUS */ |
||
1681 | mdelay(1); |
||
1682 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
1683 | tmp = RREG32(RADEON_RBBM_STATUS); |
||
1684 | if (!(tmp & (1 << 26))) { |
||
1685 | DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n", |
||
1686 | tmp); |
||
1687 | return 0; |
||
1688 | } |
||
1689 | DRM_UDELAY(1); |
||
1690 | } |
||
1691 | tmp = RREG32(RADEON_RBBM_STATUS); |
||
1692 | DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp); |
||
1693 | return -1; |
||
1694 | } |
||
1695 | |||
1696 | int r100_gpu_reset(struct radeon_device *rdev) |
||
1697 | { |
||
1698 | uint32_t status; |
||
1699 | |||
1700 | /* reset order likely matter */ |
||
1701 | status = RREG32(RADEON_RBBM_STATUS); |
||
1702 | /* reset HDP */ |
||
1703 | r100_hdp_reset(rdev); |
||
1704 | /* reset rb2d */ |
||
1705 | if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { |
||
1706 | r100_rb2d_reset(rdev); |
||
1707 | } |
||
1708 | /* TODO: reset 3D engine */ |
||
1709 | /* reset CP */ |
||
1710 | status = RREG32(RADEON_RBBM_STATUS); |
||
1711 | if (status & (1 << 16)) { |
||
1712 | r100_cp_reset(rdev); |
||
1713 | } |
||
1714 | /* Check if GPU is idle */ |
||
1715 | status = RREG32(RADEON_RBBM_STATUS); |
||
1716 | if (status & (1 << 31)) { |
||
1717 | DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); |
||
1718 | return -1; |
||
1719 | } |
||
1720 | DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
||
1721 | return 0; |
||
1722 | } |
||
1723 | |||
1321 | serge | 1724 | void r100_set_common_regs(struct radeon_device *rdev) |
1725 | { |
||
1726 | /* set these so they don't interfere with anything */ |
||
1727 | WREG32(RADEON_OV0_SCALE_CNTL, 0); |
||
1728 | WREG32(RADEON_SUBPIC_CNTL, 0); |
||
1729 | WREG32(RADEON_VIPH_CONTROL, 0); |
||
1730 | WREG32(RADEON_I2C_CNTL_1, 0); |
||
1731 | WREG32(RADEON_DVI_I2C_CNTL_1, 0); |
||
1732 | WREG32(RADEON_CAP0_TRIG_CNTL, 0); |
||
1733 | WREG32(RADEON_CAP1_TRIG_CNTL, 0); |
||
1734 | } |
||
1117 | serge | 1735 | |
1736 | /* |
||
1737 | * VRAM info |
||
1738 | */ |
||
1739 | static void r100_vram_get_type(struct radeon_device *rdev) |
||
1740 | { |
||
1741 | uint32_t tmp; |
||
1742 | |||
1743 | rdev->mc.vram_is_ddr = false; |
||
1744 | if (rdev->flags & RADEON_IS_IGP) |
||
1745 | rdev->mc.vram_is_ddr = true; |
||
1746 | else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) |
||
1747 | rdev->mc.vram_is_ddr = true; |
||
1748 | if ((rdev->family == CHIP_RV100) || |
||
1749 | (rdev->family == CHIP_RS100) || |
||
1750 | (rdev->family == CHIP_RS200)) { |
||
1751 | tmp = RREG32(RADEON_MEM_CNTL); |
||
1752 | if (tmp & RV100_HALF_MODE) { |
||
1753 | rdev->mc.vram_width = 32; |
||
1754 | } else { |
||
1755 | rdev->mc.vram_width = 64; |
||
1756 | } |
||
1757 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
||
1758 | rdev->mc.vram_width /= 4; |
||
1759 | rdev->mc.vram_is_ddr = true; |
||
1760 | } |
||
1761 | } else if (rdev->family <= CHIP_RV280) { |
||
1762 | tmp = RREG32(RADEON_MEM_CNTL); |
||
1763 | if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { |
||
1764 | rdev->mc.vram_width = 128; |
||
1765 | } else { |
||
1766 | rdev->mc.vram_width = 64; |
||
1767 | } |
||
1768 | } else { |
||
1769 | /* newer IGPs */ |
||
1770 | rdev->mc.vram_width = 128; |
||
1771 | } |
||
1772 | } |
||
1773 | |||
1179 | serge | 1774 | static u32 r100_get_accessible_vram(struct radeon_device *rdev) |
1117 | serge | 1775 | { |
1179 | serge | 1776 | u32 aper_size; |
1777 | u8 byte; |
||
1117 | serge | 1778 | |
1179 | serge | 1779 | aper_size = RREG32(RADEON_CONFIG_APER_SIZE); |
1780 | |||
1781 | /* Set HDP_APER_CNTL only on cards that are known not to be broken, |
||
1782 | * that is has the 2nd generation multifunction PCI interface |
||
1783 | */ |
||
1784 | if (rdev->family == CHIP_RV280 || |
||
1785 | rdev->family >= CHIP_RV350) { |
||
1786 | WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, |
||
1787 | ~RADEON_HDP_APER_CNTL); |
||
1788 | DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); |
||
1789 | return aper_size * 2; |
||
1790 | } |
||
1791 | |||
1792 | /* Older cards have all sorts of funny issues to deal with. First |
||
1793 | * check if it's a multifunction card by reading the PCI config |
||
1794 | * header type... Limit those to one aperture size |
||
1795 | */ |
||
1796 | // pci_read_config_byte(rdev->pdev, 0xe, &byte); |
||
1797 | // if (byte & 0x80) { |
||
1798 | // DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); |
||
1799 | // DRM_INFO("Limiting VRAM to one aperture\n"); |
||
1800 | // return aper_size; |
||
1801 | // } |
||
1802 | |||
1803 | /* Single function older card. We read HDP_APER_CNTL to see how the BIOS |
||
1804 | * have set it up. We don't write this as it's broken on some ASICs but |
||
1805 | * we expect the BIOS to have done the right thing (might be too optimistic...) |
||
1806 | */ |
||
1807 | if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) |
||
1808 | return aper_size * 2; |
||
1809 | return aper_size; |
||
1810 | } |
||
1811 | |||
1812 | void r100_vram_init_sizes(struct radeon_device *rdev) |
||
1813 | { |
||
1814 | u64 config_aper_size; |
||
1815 | u32 accessible; |
||
1816 | |||
1817 | config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); |
||
1818 | |||
1117 | serge | 1819 | if (rdev->flags & RADEON_IS_IGP) { |
1820 | uint32_t tom; |
||
1821 | /* read NB_TOM to get the amount of ram stolen for the GPU */ |
||
1822 | tom = RREG32(RADEON_NB_TOM); |
||
1179 | serge | 1823 | rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); |
1824 | /* for IGPs we need to keep VRAM where it was put by the BIOS */ |
||
1825 | rdev->mc.vram_location = (tom & 0xffff) << 16; |
||
1826 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
||
1827 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
||
1117 | serge | 1828 | } else { |
1179 | serge | 1829 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
1117 | serge | 1830 | /* Some production boards of m6 will report 0 |
1831 | * if it's 8 MB |
||
1832 | */ |
||
1179 | serge | 1833 | if (rdev->mc.real_vram_size == 0) { |
1834 | rdev->mc.real_vram_size = 8192 * 1024; |
||
1835 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
||
1117 | serge | 1836 | } |
1179 | serge | 1837 | /* let driver place VRAM */ |
1838 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
||
1839 | /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - |
||
1840 | * Novell bug 204882 + along with lots of ubuntu ones */ |
||
1841 | if (config_aper_size > rdev->mc.real_vram_size) |
||
1842 | rdev->mc.mc_vram_size = config_aper_size; |
||
1843 | else |
||
1844 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
||
1117 | serge | 1845 | } |
1846 | |||
1179 | serge | 1847 | /* work out accessible VRAM */ |
1848 | accessible = r100_get_accessible_vram(rdev); |
||
1849 | |||
1117 | serge | 1850 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
1851 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
||
1179 | serge | 1852 | |
1853 | if (accessible > rdev->mc.aper_size) |
||
1854 | accessible = rdev->mc.aper_size; |
||
1855 | |||
1856 | if (rdev->mc.mc_vram_size > rdev->mc.aper_size) |
||
1857 | rdev->mc.mc_vram_size = rdev->mc.aper_size; |
||
1858 | |||
1859 | if (rdev->mc.real_vram_size > rdev->mc.aper_size) |
||
1860 | rdev->mc.real_vram_size = rdev->mc.aper_size; |
||
1117 | serge | 1861 | } |
1862 | |||
1179 | serge | 1863 | void r100_vga_set_state(struct radeon_device *rdev, bool state) |
1864 | { |
||
1865 | uint32_t temp; |
||
1866 | |||
1867 | temp = RREG32(RADEON_CONFIG_CNTL); |
||
1868 | if (state == false) { |
||
1869 | temp &= ~(1<<8); |
||
1870 | temp |= (1<<9); |
||
1871 | } else { |
||
1872 | temp &= ~(1<<9); |
||
1873 | } |
||
1874 | WREG32(RADEON_CONFIG_CNTL, temp); |
||
1875 | } |
||
1876 | |||
1877 | void r100_vram_info(struct radeon_device *rdev) |
||
1878 | { |
||
1879 | r100_vram_get_type(rdev); |
||
1880 | |||
1881 | r100_vram_init_sizes(rdev); |
||
1882 | } |
||
1883 | |||
1884 | |||
1117 | serge | 1885 | /* |
1886 | * Indirect registers accessor |
||
1887 | */ |
||
1888 | void r100_pll_errata_after_index(struct radeon_device *rdev) |
||
1889 | { |
||
1890 | if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) { |
||
1891 | return; |
||
1892 | } |
||
1893 | (void)RREG32(RADEON_CLOCK_CNTL_DATA); |
||
1894 | (void)RREG32(RADEON_CRTC_GEN_CNTL); |
||
1895 | } |
||
1896 | |||
1897 | static void r100_pll_errata_after_data(struct radeon_device *rdev) |
||
1898 | { |
||
1899 | /* This workarounds is necessary on RV100, RS100 and RS200 chips |
||
1900 | * or the chip could hang on a subsequent access |
||
1901 | */ |
||
1902 | if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { |
||
1903 | udelay(5000); |
||
1904 | } |
||
1905 | |||
1906 | /* This function is required to workaround a hardware bug in some (all?) |
||
1907 | * revisions of the R300. This workaround should be called after every |
||
1908 | * CLOCK_CNTL_INDEX register access. If not, register reads afterward |
||
1909 | * may not be correct. |
||
1910 | */ |
||
1911 | if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { |
||
1912 | uint32_t save, tmp; |
||
1913 | |||
1914 | save = RREG32(RADEON_CLOCK_CNTL_INDEX); |
||
1915 | tmp = save & ~(0x3f | RADEON_PLL_WR_EN); |
||
1916 | WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); |
||
1917 | tmp = RREG32(RADEON_CLOCK_CNTL_DATA); |
||
1918 | WREG32(RADEON_CLOCK_CNTL_INDEX, save); |
||
1919 | } |
||
1920 | } |
||
1921 | |||
1922 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) |
||
1923 | { |
||
1924 | uint32_t data; |
||
1925 | |||
1926 | WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); |
||
1927 | r100_pll_errata_after_index(rdev); |
||
1928 | data = RREG32(RADEON_CLOCK_CNTL_DATA); |
||
1929 | r100_pll_errata_after_data(rdev); |
||
1930 | return data; |
||
1931 | } |
||
1932 | |||
1933 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
||
1934 | { |
||
1935 | WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); |
||
1936 | r100_pll_errata_after_index(rdev); |
||
1937 | WREG32(RADEON_CLOCK_CNTL_DATA, v); |
||
1938 | r100_pll_errata_after_data(rdev); |
||
1939 | } |
||
1940 | |||
1221 | serge | 1941 | void r100_set_safe_registers(struct radeon_device *rdev) |
1117 | serge | 1942 | { |
1179 | serge | 1943 | if (ASIC_IS_RN50(rdev)) { |
1944 | rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; |
||
1945 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); |
||
1946 | } else if (rdev->family < CHIP_R200) { |
||
1947 | rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; |
||
1948 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); |
||
1949 | } else { |
||
1221 | serge | 1950 | r200_set_safe_registers(rdev); |
1117 | serge | 1951 | } |
1952 | } |
||
1953 | |||
1129 | serge | 1954 | /* |
1955 | * Debugfs info |
||
1956 | */ |
||
1957 | #if defined(CONFIG_DEBUG_FS) |
||
1958 | static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) |
||
1959 | { |
||
1960 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
1961 | struct drm_device *dev = node->minor->dev; |
||
1962 | struct radeon_device *rdev = dev->dev_private; |
||
1963 | uint32_t reg, value; |
||
1964 | unsigned i; |
||
1965 | |||
1966 | seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); |
||
1967 | seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); |
||
1968 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
||
1969 | for (i = 0; i < 64; i++) { |
||
1970 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); |
||
1971 | reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; |
||
1972 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); |
||
1973 | value = RREG32(RADEON_RBBM_CMDFIFO_DATA); |
||
1974 | seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); |
||
1975 | } |
||
1976 | return 0; |
||
1977 | } |
||
1978 | |||
1979 | static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) |
||
1980 | { |
||
1981 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
1982 | struct drm_device *dev = node->minor->dev; |
||
1983 | struct radeon_device *rdev = dev->dev_private; |
||
1984 | uint32_t rdp, wdp; |
||
1985 | unsigned count, i, j; |
||
1986 | |||
1987 | radeon_ring_free_size(rdev); |
||
1988 | rdp = RREG32(RADEON_CP_RB_RPTR); |
||
1989 | wdp = RREG32(RADEON_CP_RB_WPTR); |
||
1990 | count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask; |
||
1991 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
||
1992 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); |
||
1993 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); |
||
1994 | seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); |
||
1995 | seq_printf(m, "%u dwords in ring\n", count); |
||
1996 | for (j = 0; j <= count; j++) { |
||
1997 | i = (rdp + j) & rdev->cp.ptr_mask; |
||
1998 | seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); |
||
1999 | } |
||
2000 | return 0; |
||
2001 | } |
||
2002 | |||
2003 | |||
2004 | static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) |
||
2005 | { |
||
2006 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
2007 | struct drm_device *dev = node->minor->dev; |
||
2008 | struct radeon_device *rdev = dev->dev_private; |
||
2009 | uint32_t csq_stat, csq2_stat, tmp; |
||
2010 | unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; |
||
2011 | unsigned i; |
||
2012 | |||
2013 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
||
2014 | seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); |
||
2015 | csq_stat = RREG32(RADEON_CP_CSQ_STAT); |
||
2016 | csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); |
||
2017 | r_rptr = (csq_stat >> 0) & 0x3ff; |
||
2018 | r_wptr = (csq_stat >> 10) & 0x3ff; |
||
2019 | ib1_rptr = (csq_stat >> 20) & 0x3ff; |
||
2020 | ib1_wptr = (csq2_stat >> 0) & 0x3ff; |
||
2021 | ib2_rptr = (csq2_stat >> 10) & 0x3ff; |
||
2022 | ib2_wptr = (csq2_stat >> 20) & 0x3ff; |
||
2023 | seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); |
||
2024 | seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); |
||
2025 | seq_printf(m, "Ring rptr %u\n", r_rptr); |
||
2026 | seq_printf(m, "Ring wptr %u\n", r_wptr); |
||
2027 | seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); |
||
2028 | seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); |
||
2029 | seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); |
||
2030 | seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); |
||
2031 | /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms |
||
2032 | * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ |
||
2033 | seq_printf(m, "Ring fifo:\n"); |
||
2034 | for (i = 0; i < 256; i++) { |
||
2035 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
||
2036 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
||
2037 | seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); |
||
2038 | } |
||
2039 | seq_printf(m, "Indirect1 fifo:\n"); |
||
2040 | for (i = 256; i <= 512; i++) { |
||
2041 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
||
2042 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
||
2043 | seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); |
||
2044 | } |
||
2045 | seq_printf(m, "Indirect2 fifo:\n"); |
||
2046 | for (i = 640; i < ib1_wptr; i++) { |
||
2047 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
||
2048 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
||
2049 | seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); |
||
2050 | } |
||
2051 | return 0; |
||
2052 | } |
||
2053 | |||
2054 | static int r100_debugfs_mc_info(struct seq_file *m, void *data) |
||
2055 | { |
||
2056 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
2057 | struct drm_device *dev = node->minor->dev; |
||
2058 | struct radeon_device *rdev = dev->dev_private; |
||
2059 | uint32_t tmp; |
||
2060 | |||
2061 | tmp = RREG32(RADEON_CONFIG_MEMSIZE); |
||
2062 | seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); |
||
2063 | tmp = RREG32(RADEON_MC_FB_LOCATION); |
||
2064 | seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); |
||
2065 | tmp = RREG32(RADEON_BUS_CNTL); |
||
2066 | seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); |
||
2067 | tmp = RREG32(RADEON_MC_AGP_LOCATION); |
||
2068 | seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); |
||
2069 | tmp = RREG32(RADEON_AGP_BASE); |
||
2070 | seq_printf(m, "AGP_BASE 0x%08x\n", tmp); |
||
2071 | tmp = RREG32(RADEON_HOST_PATH_CNTL); |
||
2072 | seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); |
||
2073 | tmp = RREG32(0x01D0); |
||
2074 | seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); |
||
2075 | tmp = RREG32(RADEON_AIC_LO_ADDR); |
||
2076 | seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); |
||
2077 | tmp = RREG32(RADEON_AIC_HI_ADDR); |
||
2078 | seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); |
||
2079 | tmp = RREG32(0x01E4); |
||
2080 | seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); |
||
2081 | return 0; |
||
2082 | } |
||
2083 | |||
2084 | static struct drm_info_list r100_debugfs_rbbm_list[] = { |
||
2085 | {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, |
||
2086 | }; |
||
2087 | |||
2088 | static struct drm_info_list r100_debugfs_cp_list[] = { |
||
2089 | {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, |
||
2090 | {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, |
||
2091 | }; |
||
2092 | |||
2093 | static struct drm_info_list r100_debugfs_mc_info_list[] = { |
||
2094 | {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, |
||
2095 | }; |
||
2096 | #endif |
||
2097 | |||
2098 | int r100_debugfs_rbbm_init(struct radeon_device *rdev) |
||
2099 | { |
||
2100 | #if defined(CONFIG_DEBUG_FS) |
||
2101 | return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); |
||
2102 | #else |
||
2103 | return 0; |
||
2104 | #endif |
||
2105 | } |
||
2106 | |||
2107 | int r100_debugfs_cp_init(struct radeon_device *rdev) |
||
2108 | { |
||
2109 | #if defined(CONFIG_DEBUG_FS) |
||
2110 | return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); |
||
2111 | #else |
||
2112 | return 0; |
||
2113 | #endif |
||
2114 | } |
||
2115 | |||
2116 | int r100_debugfs_mc_info_init(struct radeon_device *rdev) |
||
2117 | { |
||
2118 | #if defined(CONFIG_DEBUG_FS) |
||
2119 | return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); |
||
2120 | #else |
||
2121 | return 0; |
||
2122 | #endif |
||
2123 | } |
||
1179 | serge | 2124 | |
2125 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
||
2126 | uint32_t tiling_flags, uint32_t pitch, |
||
2127 | uint32_t offset, uint32_t obj_size) |
||
2128 | { |
||
2129 | int surf_index = reg * 16; |
||
2130 | int flags = 0; |
||
2131 | |||
2132 | /* r100/r200 divide by 16 */ |
||
2133 | if (rdev->family < CHIP_R300) |
||
2134 | flags = pitch / 16; |
||
2135 | else |
||
2136 | flags = pitch / 8; |
||
2137 | |||
2138 | if (rdev->family <= CHIP_RS200) { |
||
2139 | if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) |
||
2140 | == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) |
||
2141 | flags |= RADEON_SURF_TILE_COLOR_BOTH; |
||
2142 | if (tiling_flags & RADEON_TILING_MACRO) |
||
2143 | flags |= RADEON_SURF_TILE_COLOR_MACRO; |
||
2144 | } else if (rdev->family <= CHIP_RV280) { |
||
2145 | if (tiling_flags & (RADEON_TILING_MACRO)) |
||
2146 | flags |= R200_SURF_TILE_COLOR_MACRO; |
||
2147 | if (tiling_flags & RADEON_TILING_MICRO) |
||
2148 | flags |= R200_SURF_TILE_COLOR_MICRO; |
||
2149 | } else { |
||
2150 | if (tiling_flags & RADEON_TILING_MACRO) |
||
2151 | flags |= R300_SURF_TILE_MACRO; |
||
2152 | if (tiling_flags & RADEON_TILING_MICRO) |
||
2153 | flags |= R300_SURF_TILE_MICRO; |
||
2154 | } |
||
2155 | |||
2156 | if (tiling_flags & RADEON_TILING_SWAP_16BIT) |
||
2157 | flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; |
||
2158 | if (tiling_flags & RADEON_TILING_SWAP_32BIT) |
||
2159 | flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; |
||
2160 | |||
2161 | DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); |
||
2162 | WREG32(RADEON_SURFACE0_INFO + surf_index, flags); |
||
2163 | WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); |
||
2164 | WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); |
||
2165 | return 0; |
||
2166 | } |
||
2167 | |||
2168 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg) |
||
2169 | { |
||
2170 | int surf_index = reg * 16; |
||
2171 | WREG32(RADEON_SURFACE0_INFO + surf_index, 0); |
||
2172 | } |
||
2173 | |||
2174 | void r100_bandwidth_update(struct radeon_device *rdev) |
||
2175 | { |
||
2176 | fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; |
||
2177 | fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; |
||
2178 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; |
||
2179 | uint32_t temp, data, mem_trcd, mem_trp, mem_tras; |
||
2180 | fixed20_12 memtcas_ff[8] = { |
||
2181 | fixed_init(1), |
||
2182 | fixed_init(2), |
||
2183 | fixed_init(3), |
||
2184 | fixed_init(0), |
||
2185 | fixed_init_half(1), |
||
2186 | fixed_init_half(2), |
||
2187 | fixed_init(0), |
||
2188 | }; |
||
2189 | fixed20_12 memtcas_rs480_ff[8] = { |
||
2190 | fixed_init(0), |
||
2191 | fixed_init(1), |
||
2192 | fixed_init(2), |
||
2193 | fixed_init(3), |
||
2194 | fixed_init(0), |
||
2195 | fixed_init_half(1), |
||
2196 | fixed_init_half(2), |
||
2197 | fixed_init_half(3), |
||
2198 | }; |
||
2199 | fixed20_12 memtcas2_ff[8] = { |
||
2200 | fixed_init(0), |
||
2201 | fixed_init(1), |
||
2202 | fixed_init(2), |
||
2203 | fixed_init(3), |
||
2204 | fixed_init(4), |
||
2205 | fixed_init(5), |
||
2206 | fixed_init(6), |
||
2207 | fixed_init(7), |
||
2208 | }; |
||
2209 | fixed20_12 memtrbs[8] = { |
||
2210 | fixed_init(1), |
||
2211 | fixed_init_half(1), |
||
2212 | fixed_init(2), |
||
2213 | fixed_init_half(2), |
||
2214 | fixed_init(3), |
||
2215 | fixed_init_half(3), |
||
2216 | fixed_init(4), |
||
2217 | fixed_init_half(4) |
||
2218 | }; |
||
2219 | fixed20_12 memtrbs_r4xx[8] = { |
||
2220 | fixed_init(4), |
||
2221 | fixed_init(5), |
||
2222 | fixed_init(6), |
||
2223 | fixed_init(7), |
||
2224 | fixed_init(8), |
||
2225 | fixed_init(9), |
||
2226 | fixed_init(10), |
||
2227 | fixed_init(11) |
||
2228 | }; |
||
2229 | fixed20_12 min_mem_eff; |
||
2230 | fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; |
||
2231 | fixed20_12 cur_latency_mclk, cur_latency_sclk; |
||
2232 | fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, |
||
2233 | disp_drain_rate2, read_return_rate; |
||
2234 | fixed20_12 time_disp1_drop_priority; |
||
2235 | int c; |
||
2236 | int cur_size = 16; /* in octawords */ |
||
2237 | int critical_point = 0, critical_point2; |
||
2238 | /* uint32_t read_return_rate, time_disp1_drop_priority; */ |
||
2239 | int stop_req, max_stop_req; |
||
2240 | struct drm_display_mode *mode1 = NULL; |
||
2241 | struct drm_display_mode *mode2 = NULL; |
||
2242 | uint32_t pixel_bytes1 = 0; |
||
2243 | uint32_t pixel_bytes2 = 0; |
||
2244 | |||
2245 | if (rdev->mode_info.crtcs[0]->base.enabled) { |
||
2246 | mode1 = &rdev->mode_info.crtcs[0]->base.mode; |
||
2247 | pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; |
||
2248 | } |
||
1221 | serge | 2249 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
1179 | serge | 2250 | if (rdev->mode_info.crtcs[1]->base.enabled) { |
2251 | mode2 = &rdev->mode_info.crtcs[1]->base.mode; |
||
2252 | pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; |
||
2253 | } |
||
1221 | serge | 2254 | } |
1179 | serge | 2255 | |
2256 | min_mem_eff.full = rfixed_const_8(0); |
||
2257 | /* get modes */ |
||
2258 | if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { |
||
2259 | uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); |
||
2260 | mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); |
||
2261 | mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); |
||
2262 | /* check crtc enables */ |
||
2263 | if (mode2) |
||
2264 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); |
||
2265 | if (mode1) |
||
2266 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); |
||
2267 | WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); |
||
2268 | } |
||
2269 | |||
2270 | /* |
||
2271 | * determine is there is enough bw for current mode |
||
2272 | */ |
||
2273 | mclk_ff.full = rfixed_const(rdev->clock.default_mclk); |
||
2274 | temp_ff.full = rfixed_const(100); |
||
2275 | mclk_ff.full = rfixed_div(mclk_ff, temp_ff); |
||
2276 | sclk_ff.full = rfixed_const(rdev->clock.default_sclk); |
||
2277 | sclk_ff.full = rfixed_div(sclk_ff, temp_ff); |
||
2278 | |||
2279 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); |
||
2280 | temp_ff.full = rfixed_const(temp); |
||
2281 | mem_bw.full = rfixed_mul(mclk_ff, temp_ff); |
||
2282 | |||
2283 | pix_clk.full = 0; |
||
2284 | pix_clk2.full = 0; |
||
2285 | peak_disp_bw.full = 0; |
||
2286 | if (mode1) { |
||
2287 | temp_ff.full = rfixed_const(1000); |
||
2288 | pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */ |
||
2289 | pix_clk.full = rfixed_div(pix_clk, temp_ff); |
||
2290 | temp_ff.full = rfixed_const(pixel_bytes1); |
||
2291 | peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff); |
||
2292 | } |
||
2293 | if (mode2) { |
||
2294 | temp_ff.full = rfixed_const(1000); |
||
2295 | pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */ |
||
2296 | pix_clk2.full = rfixed_div(pix_clk2, temp_ff); |
||
2297 | temp_ff.full = rfixed_const(pixel_bytes2); |
||
2298 | peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff); |
||
2299 | } |
||
2300 | |||
2301 | mem_bw.full = rfixed_mul(mem_bw, min_mem_eff); |
||
2302 | if (peak_disp_bw.full >= mem_bw.full) { |
||
2303 | DRM_ERROR("You may not have enough display bandwidth for current mode\n" |
||
2304 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); |
||
2305 | } |
||
2306 | |||
2307 | /* Get values from the EXT_MEM_CNTL register...converting its contents. */ |
||
2308 | temp = RREG32(RADEON_MEM_TIMING_CNTL); |
||
2309 | if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ |
||
2310 | mem_trcd = ((temp >> 2) & 0x3) + 1; |
||
2311 | mem_trp = ((temp & 0x3)) + 1; |
||
2312 | mem_tras = ((temp & 0x70) >> 4) + 1; |
||
2313 | } else if (rdev->family == CHIP_R300 || |
||
2314 | rdev->family == CHIP_R350) { /* r300, r350 */ |
||
2315 | mem_trcd = (temp & 0x7) + 1; |
||
2316 | mem_trp = ((temp >> 8) & 0x7) + 1; |
||
2317 | mem_tras = ((temp >> 11) & 0xf) + 4; |
||
2318 | } else if (rdev->family == CHIP_RV350 || |
||
2319 | rdev->family <= CHIP_RV380) { |
||
2320 | /* rv3x0 */ |
||
2321 | mem_trcd = (temp & 0x7) + 3; |
||
2322 | mem_trp = ((temp >> 8) & 0x7) + 3; |
||
2323 | mem_tras = ((temp >> 11) & 0xf) + 6; |
||
2324 | } else if (rdev->family == CHIP_R420 || |
||
2325 | rdev->family == CHIP_R423 || |
||
2326 | rdev->family == CHIP_RV410) { |
||
2327 | /* r4xx */ |
||
2328 | mem_trcd = (temp & 0xf) + 3; |
||
2329 | if (mem_trcd > 15) |
||
2330 | mem_trcd = 15; |
||
2331 | mem_trp = ((temp >> 8) & 0xf) + 3; |
||
2332 | if (mem_trp > 15) |
||
2333 | mem_trp = 15; |
||
2334 | mem_tras = ((temp >> 12) & 0x1f) + 6; |
||
2335 | if (mem_tras > 31) |
||
2336 | mem_tras = 31; |
||
2337 | } else { /* RV200, R200 */ |
||
2338 | mem_trcd = (temp & 0x7) + 1; |
||
2339 | mem_trp = ((temp >> 8) & 0x7) + 1; |
||
2340 | mem_tras = ((temp >> 12) & 0xf) + 4; |
||
2341 | } |
||
2342 | /* convert to FF */ |
||
2343 | trcd_ff.full = rfixed_const(mem_trcd); |
||
2344 | trp_ff.full = rfixed_const(mem_trp); |
||
2345 | tras_ff.full = rfixed_const(mem_tras); |
||
2346 | |||
2347 | /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ |
||
2348 | temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); |
||
2349 | data = (temp & (7 << 20)) >> 20; |
||
2350 | if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { |
||
2351 | if (rdev->family == CHIP_RS480) /* don't think rs400 */ |
||
2352 | tcas_ff = memtcas_rs480_ff[data]; |
||
2353 | else |
||
2354 | tcas_ff = memtcas_ff[data]; |
||
2355 | } else |
||
2356 | tcas_ff = memtcas2_ff[data]; |
||
2357 | |||
2358 | if (rdev->family == CHIP_RS400 || |
||
2359 | rdev->family == CHIP_RS480) { |
||
2360 | /* extra cas latency stored in bits 23-25 0-4 clocks */ |
||
2361 | data = (temp >> 23) & 0x7; |
||
2362 | if (data < 5) |
||
2363 | tcas_ff.full += rfixed_const(data); |
||
2364 | } |
||
2365 | |||
2366 | if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { |
||
2367 | /* on the R300, Tcas is included in Trbs. |
||
2368 | */ |
||
2369 | temp = RREG32(RADEON_MEM_CNTL); |
||
2370 | data = (R300_MEM_NUM_CHANNELS_MASK & temp); |
||
2371 | if (data == 1) { |
||
2372 | if (R300_MEM_USE_CD_CH_ONLY & temp) { |
||
2373 | temp = RREG32(R300_MC_IND_INDEX); |
||
2374 | temp &= ~R300_MC_IND_ADDR_MASK; |
||
2375 | temp |= R300_MC_READ_CNTL_CD_mcind; |
||
2376 | WREG32(R300_MC_IND_INDEX, temp); |
||
2377 | temp = RREG32(R300_MC_IND_DATA); |
||
2378 | data = (R300_MEM_RBS_POSITION_C_MASK & temp); |
||
2379 | } else { |
||
2380 | temp = RREG32(R300_MC_READ_CNTL_AB); |
||
2381 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); |
||
2382 | } |
||
2383 | } else { |
||
2384 | temp = RREG32(R300_MC_READ_CNTL_AB); |
||
2385 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); |
||
2386 | } |
||
2387 | if (rdev->family == CHIP_RV410 || |
||
2388 | rdev->family == CHIP_R420 || |
||
2389 | rdev->family == CHIP_R423) |
||
2390 | trbs_ff = memtrbs_r4xx[data]; |
||
2391 | else |
||
2392 | trbs_ff = memtrbs[data]; |
||
2393 | tcas_ff.full += trbs_ff.full; |
||
2394 | } |
||
2395 | |||
2396 | sclk_eff_ff.full = sclk_ff.full; |
||
2397 | |||
2398 | if (rdev->flags & RADEON_IS_AGP) { |
||
2399 | fixed20_12 agpmode_ff; |
||
2400 | agpmode_ff.full = rfixed_const(radeon_agpmode); |
||
2401 | temp_ff.full = rfixed_const_666(16); |
||
2402 | sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff); |
||
2403 | } |
||
2404 | /* TODO PCIE lanes may affect this - agpmode == 16?? */ |
||
2405 | |||
2406 | if (ASIC_IS_R300(rdev)) { |
||
2407 | sclk_delay_ff.full = rfixed_const(250); |
||
2408 | } else { |
||
2409 | if ((rdev->family == CHIP_RV100) || |
||
2410 | rdev->flags & RADEON_IS_IGP) { |
||
2411 | if (rdev->mc.vram_is_ddr) |
||
2412 | sclk_delay_ff.full = rfixed_const(41); |
||
2413 | else |
||
2414 | sclk_delay_ff.full = rfixed_const(33); |
||
2415 | } else { |
||
2416 | if (rdev->mc.vram_width == 128) |
||
2417 | sclk_delay_ff.full = rfixed_const(57); |
||
2418 | else |
||
2419 | sclk_delay_ff.full = rfixed_const(41); |
||
2420 | } |
||
2421 | } |
||
2422 | |||
2423 | mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff); |
||
2424 | |||
2425 | if (rdev->mc.vram_is_ddr) { |
||
2426 | if (rdev->mc.vram_width == 32) { |
||
2427 | k1.full = rfixed_const(40); |
||
2428 | c = 3; |
||
2429 | } else { |
||
2430 | k1.full = rfixed_const(20); |
||
2431 | c = 1; |
||
2432 | } |
||
2433 | } else { |
||
2434 | k1.full = rfixed_const(40); |
||
2435 | c = 3; |
||
2436 | } |
||
2437 | |||
2438 | temp_ff.full = rfixed_const(2); |
||
2439 | mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff); |
||
2440 | temp_ff.full = rfixed_const(c); |
||
2441 | mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff); |
||
2442 | temp_ff.full = rfixed_const(4); |
||
2443 | mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff); |
||
2444 | mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff); |
||
2445 | mc_latency_mclk.full += k1.full; |
||
2446 | |||
2447 | mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff); |
||
2448 | mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff); |
||
2449 | |||
2450 | /* |
||
2451 | HW cursor time assuming worst case of full size colour cursor. |
||
2452 | */ |
||
2453 | temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); |
||
2454 | temp_ff.full += trcd_ff.full; |
||
2455 | if (temp_ff.full < tras_ff.full) |
||
2456 | temp_ff.full = tras_ff.full; |
||
2457 | cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff); |
||
2458 | |||
2459 | temp_ff.full = rfixed_const(cur_size); |
||
2460 | cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff); |
||
2461 | /* |
||
2462 | Find the total latency for the display data. |
||
2463 | */ |
||
1268 | serge | 2464 | disp_latency_overhead.full = rfixed_const(8); |
1179 | serge | 2465 | disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff); |
2466 | mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; |
||
2467 | mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; |
||
2468 | |||
2469 | if (mc_latency_mclk.full > mc_latency_sclk.full) |
||
2470 | disp_latency.full = mc_latency_mclk.full; |
||
2471 | else |
||
2472 | disp_latency.full = mc_latency_sclk.full; |
||
2473 | |||
2474 | /* setup Max GRPH_STOP_REQ default value */ |
||
2475 | if (ASIC_IS_RV100(rdev)) |
||
2476 | max_stop_req = 0x5c; |
||
2477 | else |
||
2478 | max_stop_req = 0x7c; |
||
2479 | |||
2480 | if (mode1) { |
||
2481 | /* CRTC1 |
||
2482 | Set GRPH_BUFFER_CNTL register using h/w defined optimal values. |
||
2483 | GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] |
||
2484 | */ |
||
2485 | stop_req = mode1->hdisplay * pixel_bytes1 / 16; |
||
2486 | |||
2487 | if (stop_req > max_stop_req) |
||
2488 | stop_req = max_stop_req; |
||
2489 | |||
2490 | /* |
||
2491 | Find the drain rate of the display buffer. |
||
2492 | */ |
||
2493 | temp_ff.full = rfixed_const((16/pixel_bytes1)); |
||
2494 | disp_drain_rate.full = rfixed_div(pix_clk, temp_ff); |
||
2495 | |||
2496 | /* |
||
2497 | Find the critical point of the display buffer. |
||
2498 | */ |
||
2499 | crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency); |
||
2500 | crit_point_ff.full += rfixed_const_half(0); |
||
2501 | |||
2502 | critical_point = rfixed_trunc(crit_point_ff); |
||
2503 | |||
2504 | if (rdev->disp_priority == 2) { |
||
2505 | critical_point = 0; |
||
2506 | } |
||
2507 | |||
2508 | /* |
||
2509 | The critical point should never be above max_stop_req-4. Setting |
||
2510 | GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. |
||
2511 | */ |
||
2512 | if (max_stop_req - critical_point < 4) |
||
2513 | critical_point = 0; |
||
2514 | |||
2515 | if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { |
||
2516 | /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ |
||
2517 | critical_point = 0x10; |
||
2518 | } |
||
2519 | |||
2520 | temp = RREG32(RADEON_GRPH_BUFFER_CNTL); |
||
2521 | temp &= ~(RADEON_GRPH_STOP_REQ_MASK); |
||
2522 | temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); |
||
2523 | temp &= ~(RADEON_GRPH_START_REQ_MASK); |
||
2524 | if ((rdev->family == CHIP_R350) && |
||
2525 | (stop_req > 0x15)) { |
||
2526 | stop_req -= 0x10; |
||
2527 | } |
||
2528 | temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
||
2529 | temp |= RADEON_GRPH_BUFFER_SIZE; |
||
2530 | temp &= ~(RADEON_GRPH_CRITICAL_CNTL | |
||
2531 | RADEON_GRPH_CRITICAL_AT_SOF | |
||
2532 | RADEON_GRPH_STOP_CNTL); |
||
2533 | /* |
||
2534 | Write the result into the register. |
||
2535 | */ |
||
2536 | WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | |
||
2537 | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); |
||
2538 | |||
2539 | #if 0 |
||
2540 | if ((rdev->family == CHIP_RS400) || |
||
2541 | (rdev->family == CHIP_RS480)) { |
||
2542 | /* attempt to program RS400 disp regs correctly ??? */ |
||
2543 | temp = RREG32(RS400_DISP1_REG_CNTL); |
||
2544 | temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | |
||
2545 | RS400_DISP1_STOP_REQ_LEVEL_MASK); |
||
2546 | WREG32(RS400_DISP1_REQ_CNTL1, (temp | |
||
2547 | (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | |
||
2548 | (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); |
||
2549 | temp = RREG32(RS400_DMIF_MEM_CNTL1); |
||
2550 | temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | |
||
2551 | RS400_DISP1_CRITICAL_POINT_STOP_MASK); |
||
2552 | WREG32(RS400_DMIF_MEM_CNTL1, (temp | |
||
2553 | (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | |
||
2554 | (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); |
||
2555 | } |
||
2556 | #endif |
||
2557 | |||
2558 | DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n", |
||
2559 | /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ |
||
2560 | (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); |
||
2561 | } |
||
2562 | |||
2563 | if (mode2) { |
||
2564 | u32 grph2_cntl; |
||
2565 | stop_req = mode2->hdisplay * pixel_bytes2 / 16; |
||
2566 | |||
2567 | if (stop_req > max_stop_req) |
||
2568 | stop_req = max_stop_req; |
||
2569 | |||
2570 | /* |
||
2571 | Find the drain rate of the display buffer. |
||
2572 | */ |
||
2573 | temp_ff.full = rfixed_const((16/pixel_bytes2)); |
||
2574 | disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff); |
||
2575 | |||
2576 | grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); |
||
2577 | grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); |
||
2578 | grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); |
||
2579 | grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); |
||
2580 | if ((rdev->family == CHIP_R350) && |
||
2581 | (stop_req > 0x15)) { |
||
2582 | stop_req -= 0x10; |
||
2583 | } |
||
2584 | grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
||
2585 | grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; |
||
2586 | grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | |
||
2587 | RADEON_GRPH_CRITICAL_AT_SOF | |
||
2588 | RADEON_GRPH_STOP_CNTL); |
||
2589 | |||
2590 | if ((rdev->family == CHIP_RS100) || |
||
2591 | (rdev->family == CHIP_RS200)) |
||
2592 | critical_point2 = 0; |
||
2593 | else { |
||
2594 | temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; |
||
2595 | temp_ff.full = rfixed_const(temp); |
||
2596 | temp_ff.full = rfixed_mul(mclk_ff, temp_ff); |
||
2597 | if (sclk_ff.full < temp_ff.full) |
||
2598 | temp_ff.full = sclk_ff.full; |
||
2599 | |||
2600 | read_return_rate.full = temp_ff.full; |
||
2601 | |||
2602 | if (mode1) { |
||
2603 | temp_ff.full = read_return_rate.full - disp_drain_rate.full; |
||
2604 | time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff); |
||
2605 | } else { |
||
2606 | time_disp1_drop_priority.full = 0; |
||
2607 | } |
||
2608 | crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; |
||
2609 | crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2); |
||
2610 | crit_point_ff.full += rfixed_const_half(0); |
||
2611 | |||
2612 | critical_point2 = rfixed_trunc(crit_point_ff); |
||
2613 | |||
2614 | if (rdev->disp_priority == 2) { |
||
2615 | critical_point2 = 0; |
||
2616 | } |
||
2617 | |||
2618 | if (max_stop_req - critical_point2 < 4) |
||
2619 | critical_point2 = 0; |
||
2620 | |||
2621 | } |
||
2622 | |||
2623 | if (critical_point2 == 0 && rdev->family == CHIP_R300) { |
||
2624 | /* some R300 cards have problem with this set to 0 */ |
||
2625 | critical_point2 = 0x10; |
||
2626 | } |
||
2627 | |||
2628 | WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | |
||
2629 | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); |
||
2630 | |||
2631 | if ((rdev->family == CHIP_RS400) || |
||
2632 | (rdev->family == CHIP_RS480)) { |
||
2633 | #if 0 |
||
2634 | /* attempt to program RS400 disp2 regs correctly ??? */ |
||
2635 | temp = RREG32(RS400_DISP2_REQ_CNTL1); |
||
2636 | temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | |
||
2637 | RS400_DISP2_STOP_REQ_LEVEL_MASK); |
||
2638 | WREG32(RS400_DISP2_REQ_CNTL1, (temp | |
||
2639 | (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | |
||
2640 | (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); |
||
2641 | temp = RREG32(RS400_DISP2_REQ_CNTL2); |
||
2642 | temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | |
||
2643 | RS400_DISP2_CRITICAL_POINT_STOP_MASK); |
||
2644 | WREG32(RS400_DISP2_REQ_CNTL2, (temp | |
||
2645 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | |
||
2646 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); |
||
2647 | #endif |
||
2648 | WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); |
||
2649 | WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); |
||
2650 | WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); |
||
2651 | WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); |
||
2652 | } |
||
2653 | |||
2654 | DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n", |
||
2655 | (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); |
||
2656 | } |
||
2657 | } |
||
2658 | |||
2659 | |||
2660 | |||
2661 | |||
2662 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) |
||
2663 | { |
||
2664 | /* Shutdown CP we shouldn't need to do that but better be safe than |
||
2665 | * sorry |
||
2666 | */ |
||
2667 | rdev->cp.ready = false; |
||
2668 | WREG32(R_000740_CP_CSQ_CNTL, 0); |
||
2669 | |||
2670 | /* Save few CRTC registers */ |
||
1221 | serge | 2671 | save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); |
1179 | serge | 2672 | save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); |
2673 | save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); |
||
2674 | save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); |
||
2675 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
||
2676 | save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); |
||
2677 | save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); |
||
2678 | } |
||
2679 | |||
2680 | /* Disable VGA aperture access */ |
||
1221 | serge | 2681 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); |
1179 | serge | 2682 | /* Disable cursor, overlay, crtc */ |
2683 | WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); |
||
2684 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | |
||
2685 | S_000054_CRTC_DISPLAY_DIS(1)); |
||
2686 | WREG32(R_000050_CRTC_GEN_CNTL, |
||
2687 | (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | |
||
2688 | S_000050_CRTC_DISP_REQ_EN_B(1)); |
||
2689 | WREG32(R_000420_OV0_SCALE_CNTL, |
||
2690 | C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); |
||
2691 | WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); |
||
2692 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
||
2693 | WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | |
||
2694 | S_000360_CUR2_LOCK(1)); |
||
2695 | WREG32(R_0003F8_CRTC2_GEN_CNTL, |
||
2696 | (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | |
||
2697 | S_0003F8_CRTC2_DISPLAY_DIS(1) | |
||
2698 | S_0003F8_CRTC2_DISP_REQ_EN_B(1)); |
||
2699 | WREG32(R_000360_CUR2_OFFSET, |
||
2700 | C_000360_CUR2_LOCK & save->CUR2_OFFSET); |
||
2701 | } |
||
2702 | } |
||
2703 | |||
2704 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) |
||
2705 | { |
||
2706 | /* Update base address for crtc */ |
||
2707 | WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location); |
||
2708 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
||
2709 | WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, |
||
2710 | rdev->mc.vram_location); |
||
2711 | } |
||
2712 | /* Restore CRTC registers */ |
||
1221 | serge | 2713 | WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); |
1179 | serge | 2714 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); |
2715 | WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); |
||
2716 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
||
2717 | WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); |
||
2718 | } |
||
2719 | } |
||
2720 | |||
1221 | serge | 2721 | void r100_vga_render_disable(struct radeon_device *rdev) |
2722 | { |
||
2723 | u32 tmp; |
||
2724 | |||
2725 | tmp = RREG8(R_0003C2_GENMO_WT); |
||
2726 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); |
||
2727 | } |
||
2728 | |||
2729 | static void r100_debugfs(struct radeon_device *rdev) |
||
2730 | { |
||
2731 | int r; |
||
2732 | |||
2733 | r = r100_debugfs_mc_info_init(rdev); |
||
2734 | if (r) |
||
2735 | dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); |
||
2736 | } |
||
2737 | |||
2738 | |||
1179 | serge | 2739 | int drm_order(unsigned long size) |
2740 | { |
||
2741 | int order; |
||
2742 | unsigned long tmp; |
||
2743 | |||
2744 | for (order = 0, tmp = size >> 1; tmp; tmp >>= 1, order++) ; |
||
2745 | |||
2746 | if (size & (size - 1)) |
||
2747 | ++order; |
||
2748 | |||
2749 | return order; |
||
2750 | } |
||
2751 | |||
1221 | serge | 2752 | static void r100_mc_program(struct radeon_device *rdev) |
2753 | { |
||
2754 | struct r100_mc_save save; |
||
2755 | |||
2756 | /* Stops all mc clients */ |
||
2757 | r100_mc_stop(rdev, &save); |
||
2758 | if (rdev->flags & RADEON_IS_AGP) { |
||
2759 | WREG32(R_00014C_MC_AGP_LOCATION, |
||
2760 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
||
2761 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
||
2762 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
||
2763 | if (rdev->family > CHIP_RV200) |
||
2764 | WREG32(R_00015C_AGP_BASE_2, |
||
2765 | upper_32_bits(rdev->mc.agp_base) & 0xff); |
||
2766 | } else { |
||
2767 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); |
||
2768 | WREG32(R_000170_AGP_BASE, 0); |
||
2769 | if (rdev->family > CHIP_RV200) |
||
2770 | WREG32(R_00015C_AGP_BASE_2, 0); |
||
2771 | } |
||
2772 | /* Wait for mc idle */ |
||
2773 | if (r100_mc_wait_for_idle(rdev)) |
||
2774 | dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); |
||
2775 | /* Program MC, should be a 32bits limited address space */ |
||
2776 | WREG32(R_000148_MC_FB_LOCATION, |
||
2777 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
||
2778 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
||
2779 | r100_mc_resume(rdev, &save); |
||
2780 | } |
||
2781 | |||
2782 | void r100_clock_startup(struct radeon_device *rdev) |
||
2783 | { |
||
2784 | u32 tmp; |
||
2785 | |||
2786 | if (radeon_dynclks != -1 && radeon_dynclks) |
||
2787 | radeon_legacy_set_clock_gating(rdev, 1); |
||
2788 | /* We need to force on some of the block */ |
||
2789 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); |
||
2790 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
||
2791 | if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) |
||
2792 | tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); |
||
2793 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); |
||
2794 | } |
||
2795 | |||
2796 | static int r100_startup(struct radeon_device *rdev) |
||
2797 | { |
||
2798 | int r; |
||
2799 | |||
1321 | serge | 2800 | /* set common regs */ |
2801 | r100_set_common_regs(rdev); |
||
2802 | /* program mc */ |
||
1221 | serge | 2803 | r100_mc_program(rdev); |
2804 | /* Resume clock */ |
||
2805 | r100_clock_startup(rdev); |
||
2806 | /* Initialize GPU configuration (# pipes, ...) */ |
||
2807 | r100_gpu_init(rdev); |
||
2808 | /* Initialize GART (initialize after TTM so we can allocate |
||
2809 | * memory through TTM but finalize after TTM) */ |
||
1321 | serge | 2810 | r100_enable_bm(rdev); |
1221 | serge | 2811 | if (rdev->flags & RADEON_IS_PCI) { |
2812 | r = r100_pci_gart_enable(rdev); |
||
2813 | if (r) |
||
2814 | return r; |
||
2815 | } |
||
2816 | /* Enable IRQ */ |
||
2817 | // r100_irq_set(rdev); |
||
2818 | /* 1M ring buffer */ |
||
2819 | // r = r100_cp_init(rdev, 1024 * 1024); |
||
2820 | // if (r) { |
||
2821 | // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
||
2822 | // return r; |
||
2823 | // } |
||
2824 | // r = r100_wb_init(rdev); |
||
2825 | // if (r) |
||
2826 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
||
2827 | // r = r100_ib_init(rdev); |
||
2828 | // if (r) { |
||
2829 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
||
2830 | // return r; |
||
2831 | // } |
||
2832 | return 0; |
||
2833 | } |
||
2834 | |||
2835 | |||
2836 | int r100_mc_init(struct radeon_device *rdev) |
||
2837 | { |
||
2838 | int r; |
||
2839 | u32 tmp; |
||
2840 | |||
2841 | /* Setup GPU memory space */ |
||
2842 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
||
2843 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
||
2844 | if (rdev->flags & RADEON_IS_IGP) { |
||
2845 | tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM)); |
||
2846 | rdev->mc.vram_location = tmp << 16; |
||
2847 | } |
||
2848 | if (rdev->flags & RADEON_IS_AGP) { |
||
2849 | r = radeon_agp_init(rdev); |
||
2850 | if (r) { |
||
2851 | printk(KERN_WARNING "[drm] Disabling AGP\n"); |
||
2852 | rdev->flags &= ~RADEON_IS_AGP; |
||
2853 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
||
2854 | } else { |
||
2855 | rdev->mc.gtt_location = rdev->mc.agp_base; |
||
2856 | } |
||
2857 | } |
||
2858 | r = radeon_mc_setup(rdev); |
||
2859 | if (r) |
||
2860 | return r; |
||
2861 | return 0; |
||
2862 | } |
||
2863 | |||
2864 | int r100_init(struct radeon_device *rdev) |
||
2865 | { |
||
2866 | int r; |
||
2867 | |||
2868 | /* Register debugfs file specific to this group of asics */ |
||
2869 | r100_debugfs(rdev); |
||
2870 | /* Disable VGA */ |
||
2871 | r100_vga_render_disable(rdev); |
||
2872 | /* Initialize scratch registers */ |
||
2873 | radeon_scratch_init(rdev); |
||
2874 | /* Initialize surface registers */ |
||
2875 | radeon_surface_init(rdev); |
||
2876 | /* TODO: disable VGA need to use VGA request */ |
||
2877 | /* BIOS*/ |
||
2878 | if (!radeon_get_bios(rdev)) { |
||
2879 | if (ASIC_IS_AVIVO(rdev)) |
||
2880 | return -EINVAL; |
||
2881 | } |
||
2882 | if (rdev->is_atom_bios) { |
||
2883 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); |
||
2884 | return -EINVAL; |
||
2885 | } else { |
||
2886 | r = radeon_combios_init(rdev); |
||
2887 | if (r) |
||
2888 | return r; |
||
2889 | } |
||
2890 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
2891 | if (radeon_gpu_reset(rdev)) { |
||
2892 | dev_warn(rdev->dev, |
||
2893 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
||
2894 | RREG32(R_000E40_RBBM_STATUS), |
||
2895 | RREG32(R_0007C0_CP_STAT)); |
||
2896 | } |
||
2897 | /* check if cards are posted or not */ |
||
1321 | serge | 2898 | if (radeon_boot_test_post_card(rdev) == false) |
2899 | return -EINVAL; |
||
1221 | serge | 2900 | /* Set asic errata */ |
2901 | r100_errata(rdev); |
||
2902 | /* Initialize clocks */ |
||
2903 | radeon_get_clock_info(rdev->ddev); |
||
2904 | /* Get vram informations */ |
||
2905 | r100_vram_info(rdev); |
||
2906 | /* Initialize memory controller (also test AGP) */ |
||
2907 | r = r100_mc_init(rdev); |
||
1246 | serge | 2908 | dbgprintf("mc vram location %x\n", rdev->mc.vram_location); |
1221 | serge | 2909 | if (r) |
2910 | return r; |
||
2911 | /* Fence driver */ |
||
2912 | // r = radeon_fence_driver_init(rdev); |
||
2913 | // if (r) |
||
2914 | // return r; |
||
2915 | // r = radeon_irq_kms_init(rdev); |
||
2916 | // if (r) |
||
2917 | // return r; |
||
2918 | /* Memory manager */ |
||
1321 | serge | 2919 | r = radeon_bo_init(rdev); |
1221 | serge | 2920 | if (r) |
2921 | return r; |
||
2922 | if (rdev->flags & RADEON_IS_PCI) { |
||
2923 | r = r100_pci_gart_init(rdev); |
||
2924 | if (r) |
||
2925 | return r; |
||
2926 | } |
||
2927 | r100_set_safe_registers(rdev); |
||
2928 | rdev->accel_working = true; |
||
2929 | r = r100_startup(rdev); |
||
2930 | if (r) { |
||
2931 | /* Somethings want wront with the accel init stop accel */ |
||
2932 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
||
2933 | // r100_suspend(rdev); |
||
2934 | // r100_cp_fini(rdev); |
||
2935 | // r100_wb_fini(rdev); |
||
2936 | // r100_ib_fini(rdev); |
||
2937 | if (rdev->flags & RADEON_IS_PCI) |
||
2938 | r100_pci_gart_fini(rdev); |
||
2939 | // radeon_irq_kms_fini(rdev); |
||
2940 | rdev->accel_working = false; |
||
2941 | } |
||
2942 | return 0; |
||
2943 | }><>><>><>><>><>><>>>><>><>><>><>><>><>><>><>><>>=>>>><>=>><>><>><>><>=>=>>><>>><>=>><>>=>>>9); |