WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r100.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1179	serge	28	#include
1125	serge	29	#include "drmP.h"
		30	#include "drm.h"
1117	serge	31	#include "radeon_drm.h"
		32	#include "radeon_reg.h"
		33	#include "radeon.h"
1179	serge	34	#include "r100d.h"
1221	serge	35	#include "rs100d.h"
		36	#include "rv200d.h"
		37	#include "rv250d.h"
1117	serge	38
1221	serge	39	#include
		40
1179	serge	41	#include "r100_reg_safe.h"
		42	#include "rn50_reg_safe.h"
1221	serge	43
		44	/* Firmware Names */
		45	#define FIRMWARE_R100 "radeon/R100_cp.bin"
		46	#define FIRMWARE_R200 "radeon/R200_cp.bin"
		47	#define FIRMWARE_R300 "radeon/R300_cp.bin"
		48	#define FIRMWARE_R420 "radeon/R420_cp.bin"
		49	#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
		50	#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
		51	#define FIRMWARE_R520 "radeon/R520_cp.bin"
		52
		53	MODULE_FIRMWARE(FIRMWARE_R100);
		54	MODULE_FIRMWARE(FIRMWARE_R200);
		55	MODULE_FIRMWARE(FIRMWARE_R300);
		56	MODULE_FIRMWARE(FIRMWARE_R420);
		57	MODULE_FIRMWARE(FIRMWARE_RS690);
		58	MODULE_FIRMWARE(FIRMWARE_RS600);
		59	MODULE_FIRMWARE(FIRMWARE_R520);
		60
		61
1117	serge	62	/* This files gather functions specifics to:
		63	* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
		64	*/
		65
		66	/*
		67	* PCI GART
		68	*/
		69	void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
		70	{
		71	/* TODO: can we do somethings here ? */
		72	/* It seems hw only cache one entry so we should discard this
		73	* entry otherwise if first GPU GART read hit this entry it
		74	* could end up in wrong address. */
		75	}
		76
1179	serge	77	int r100_pci_gart_init(struct radeon_device *rdev)
1117	serge	78	{
		79	int r;
		80
1179	serge	81	if (rdev->gart.table.ram.ptr) {
		82	WARN(1, "R100 PCI GART already initialized.\n");
		83	return 0;
		84	}
1117	serge	85	/* Initialize common gart structure */
		86	r = radeon_gart_init(rdev);
1179	serge	87	if (r)
1117	serge	88	return r;
		89	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
1179	serge	90	rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
		91	rdev->asic->gart_set_page = &r100_pci_gart_set_page;
		92	return radeon_gart_table_ram_alloc(rdev);
		93	}
		94
		95	int r100_pci_gart_enable(struct radeon_device *rdev)
		96	{
		97	uint32_t tmp;
		98
1117	serge	99	/* discard memory request outside of configured range */
		100	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		101	WREG32(RADEON_AIC_CNTL, tmp);
		102	/* set address range for PCI address translate */
		103	WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
		104	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
		105	WREG32(RADEON_AIC_HI_ADDR, tmp);
		106	/* Enable bus mastering */
		107	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
		108	WREG32(RADEON_BUS_CNTL, tmp);
		109	/* set PCI GART page-table base address */
		110	WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
		111	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_PCIGART_TRANSLATE_EN;
		112	WREG32(RADEON_AIC_CNTL, tmp);
		113	r100_pci_gart_tlb_flush(rdev);
		114	rdev->gart.ready = true;
		115	return 0;
		116	}
		117
		118	void r100_pci_gart_disable(struct radeon_device *rdev)
		119	{
		120	uint32_t tmp;
		121
		122	/* discard memory request outside of configured range */
		123	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		124	WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
		125	WREG32(RADEON_AIC_LO_ADDR, 0);
		126	WREG32(RADEON_AIC_HI_ADDR, 0);
		127	}
		128
		129	int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
		130	{
		131	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
		132	return -EINVAL;
		133	}
1179	serge	134	rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
1117	serge	135	return 0;
		136	}
		137
1179	serge	138	void r100_pci_gart_fini(struct radeon_device *rdev)
1117	serge	139	{
		140	r100_pci_gart_disable(rdev);
1179	serge	141	radeon_gart_table_ram_free(rdev);
		142	radeon_gart_fini(rdev);
1117	serge	143	}
		144
		145
1221	serge	146	void r100_irq_disable(struct radeon_device *rdev)
1117	serge	147	{
1221	serge	148	u32 tmp;
1117	serge	149
1221	serge	150	WREG32(R_000040_GEN_INT_CNTL, 0);
		151	/* Wait and acknowledge irq */
		152	mdelay(1);
		153	tmp = RREG32(R_000044_GEN_INT_STATUS);
		154	WREG32(R_000044_GEN_INT_STATUS, tmp);
1117	serge	155	}
		156
1221	serge	157	static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
1117	serge	158	{
1221	serge	159	uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
		160	uint32_t irq_mask = RADEON_SW_INT_TEST \| RADEON_CRTC_VBLANK_STAT \|
		161	RADEON_CRTC2_VBLANK_STAT;
1117	serge	162
1221	serge	163	if (irqs) {
		164	WREG32(RADEON_GEN_INT_STATUS, irqs);
1129	serge	165	}
1221	serge	166	return irqs & irq_mask;
1117	serge	167	}
		168
		169
		170
		171	void r100_fence_ring_emit(struct radeon_device *rdev,
		172	struct radeon_fence *fence)
		173	{
		174	/* Who ever call radeon_fence_emit should call ring_lock and ask
		175	* for enough space (today caller are ib schedule and buffer move) */
		176	/* Wait until IDLE & CLEAN */
		177	radeon_ring_write(rdev, PACKET0(0x1720, 0));
		178	radeon_ring_write(rdev, (1 << 16) \| (1 << 17));
		179	/* Emit fence sequence & fire IRQ */
		180	radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
		181	radeon_ring_write(rdev, fence->seq);
		182	radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
		183	radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
		184	}
		185
1128	serge	186	#if 0
1117	serge	187	/*
		188	* Writeback
		189	*/
		190	int r100_wb_init(struct radeon_device *rdev)
		191	{
		192	int r;
		193
		194	if (rdev->wb.wb_obj == NULL) {
		195	r = radeon_object_create(rdev, NULL, 4096,
		196	true,
		197	RADEON_GEM_DOMAIN_GTT,
		198	false, &rdev->wb.wb_obj);
		199	if (r) {
		200	DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
		201	return r;
		202	}
		203	r = radeon_object_pin(rdev->wb.wb_obj,
		204	RADEON_GEM_DOMAIN_GTT,
		205	&rdev->wb.gpu_addr);
		206	if (r) {
		207	DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
		208	return r;
		209	}
		210	r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
		211	if (r) {
		212	DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
		213	return r;
		214	}
		215	}
1179	serge	216	WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
		217	WREG32(R_00070C_CP_RB_RPTR_ADDR,
		218	S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
		219	WREG32(R_000770_SCRATCH_UMSK, 0xff);
1117	serge	220	return 0;
		221	}
		222
1179	serge	223	void r100_wb_disable(struct radeon_device *rdev)
		224	{
		225	WREG32(R_000770_SCRATCH_UMSK, 0);
		226	}
		227
1117	serge	228	void r100_wb_fini(struct radeon_device *rdev)
		229	{
1179	serge	230	r100_wb_disable(rdev);
1117	serge	231	if (rdev->wb.wb_obj) {
1120	serge	232	// radeon_object_kunmap(rdev->wb.wb_obj);
		233	// radeon_object_unpin(rdev->wb.wb_obj);
		234	// radeon_object_unref(&rdev->wb.wb_obj);
1117	serge	235	rdev->wb.wb = NULL;
		236	rdev->wb.wb_obj = NULL;
		237	}
		238	}
		239
		240	int r100_copy_blit(struct radeon_device *rdev,
		241	uint64_t src_offset,
		242	uint64_t dst_offset,
		243	unsigned num_pages,
		244	struct radeon_fence *fence)
		245	{
		246	uint32_t cur_pages;
		247	uint32_t stride_bytes = PAGE_SIZE;
		248	uint32_t pitch;
		249	uint32_t stride_pixels;
		250	unsigned ndw;
		251	int num_loops;
		252	int r = 0;
		253
		254	/* radeon limited to 16k stride */
		255	stride_bytes &= 0x3fff;
		256	/* radeon pitch is /64 */
		257	pitch = stride_bytes / 64;
		258	stride_pixels = stride_bytes / 4;
		259	num_loops = DIV_ROUND_UP(num_pages, 8191);
		260
		261	/* Ask for enough room for blit + flush + fence */
		262	ndw = 64 + (10 * num_loops);
		263	r = radeon_ring_lock(rdev, ndw);
		264	if (r) {
		265	DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
		266	return -EINVAL;
		267	}
		268	while (num_pages > 0) {
		269	cur_pages = num_pages;
		270	if (cur_pages > 8191) {
		271	cur_pages = 8191;
		272	}
		273	num_pages -= cur_pages;
		274
		275	/* pages are in Y direction - height
		276	page width in X direction - width */
		277	radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
		278	radeon_ring_write(rdev,
		279	RADEON_GMC_SRC_PITCH_OFFSET_CNTL \|
		280	RADEON_GMC_DST_PITCH_OFFSET_CNTL \|
		281	RADEON_GMC_SRC_CLIPPING \|
		282	RADEON_GMC_DST_CLIPPING \|
		283	RADEON_GMC_BRUSH_NONE \|
		284	(RADEON_COLOR_FORMAT_ARGB8888 << 8) \|
		285	RADEON_GMC_SRC_DATATYPE_COLOR \|
		286	RADEON_ROP3_S \|
		287	RADEON_DP_SRC_SOURCE_MEMORY \|
		288	RADEON_GMC_CLR_CMP_CNTL_DIS \|
		289	RADEON_GMC_WR_MSK_DIS);
		290	radeon_ring_write(rdev, (pitch << 22) \| (src_offset >> 10));
		291	radeon_ring_write(rdev, (pitch << 22) \| (dst_offset >> 10));
		292	radeon_ring_write(rdev, (0x1fff) \| (0x1fff << 16));
		293	radeon_ring_write(rdev, 0);
		294	radeon_ring_write(rdev, (0x1fff) \| (0x1fff << 16));
		295	radeon_ring_write(rdev, num_pages);
		296	radeon_ring_write(rdev, num_pages);
		297	radeon_ring_write(rdev, cur_pages \| (stride_pixels << 16));
		298	}
		299	radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
		300	radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
		301	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		302	radeon_ring_write(rdev,
		303	RADEON_WAIT_2D_IDLECLEAN \|
		304	RADEON_WAIT_HOST_IDLECLEAN \|
		305	RADEON_WAIT_DMA_GUI_IDLE);
		306	if (fence) {
		307	r = radeon_fence_emit(rdev, fence);
		308	}
		309	radeon_ring_unlock_commit(rdev);
		310	return r;
		311	}
		312
1128	serge	313	#endif
1117	serge	314
1221	serge	315
1179	serge	316	static int r100_cp_wait_for_idle(struct radeon_device *rdev)
		317	{
		318	unsigned i;
		319	u32 tmp;
		320
		321	for (i = 0; i < rdev->usec_timeout; i++) {
		322	tmp = RREG32(R_000E40_RBBM_STATUS);
		323	if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
		324	return 0;
		325	}
		326	udelay(1);
		327	}
		328	return -1;
		329	}
		330
1117	serge	331	void r100_ring_start(struct radeon_device *rdev)
		332	{
		333	int r;
		334
		335	r = radeon_ring_lock(rdev, 2);
		336	if (r) {
		337	return;
		338	}
		339	radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
		340	radeon_ring_write(rdev,
		341	RADEON_ISYNC_ANY2D_IDLE3D \|
		342	RADEON_ISYNC_ANY3D_IDLE2D \|
		343	RADEON_ISYNC_WAIT_IDLEGUI \|
		344	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
		345	radeon_ring_unlock_commit(rdev);
		346	}
		347
1221	serge	348
		349	/* Load the microcode for the CP */
		350	static int r100_cp_init_microcode(struct radeon_device *rdev)
1117	serge	351	{
1221	serge	352	struct platform_device *pdev;
		353	const char *fw_name = NULL;
		354	int err;
1117	serge	355
1221	serge	356	DRM_DEBUG("\n");
1117	serge	357
1221	serge	358	// pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
		359	// err = IS_ERR(pdev);
		360	// if (err) {
		361	// printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
		362	// return -EINVAL;
		363	// }
1117	serge	364	if ((rdev->family == CHIP_R100) \|\| (rdev->family == CHIP_RV100) \|\|
		365	(rdev->family == CHIP_RV200) \|\| (rdev->family == CHIP_RS100) \|\|
		366	(rdev->family == CHIP_RS200)) {
		367	DRM_INFO("Loading R100 Microcode\n");
1221	serge	368	fw_name = FIRMWARE_R100;
1117	serge	369	} else if ((rdev->family == CHIP_R200) \|\|
		370	(rdev->family == CHIP_RV250) \|\|
		371	(rdev->family == CHIP_RV280) \|\|
		372	(rdev->family == CHIP_RS300)) {
		373	DRM_INFO("Loading R200 Microcode\n");
1221	serge	374	fw_name = FIRMWARE_R200;
1117	serge	375	} else if ((rdev->family == CHIP_R300) \|\|
		376	(rdev->family == CHIP_R350) \|\|
		377	(rdev->family == CHIP_RV350) \|\|
		378	(rdev->family == CHIP_RV380) \|\|
		379	(rdev->family == CHIP_RS400) \|\|
		380	(rdev->family == CHIP_RS480)) {
		381	DRM_INFO("Loading R300 Microcode\n");
1221	serge	382	fw_name = FIRMWARE_R300;
1117	serge	383	} else if ((rdev->family == CHIP_R420) \|\|
		384	(rdev->family == CHIP_R423) \|\|
		385	(rdev->family == CHIP_RV410)) {
		386	DRM_INFO("Loading R400 Microcode\n");
1221	serge	387	fw_name = FIRMWARE_R420;
1117	serge	388	} else if ((rdev->family == CHIP_RS690) \|\|
		389	(rdev->family == CHIP_RS740)) {
		390	DRM_INFO("Loading RS690/RS740 Microcode\n");
1221	serge	391	fw_name = FIRMWARE_RS690;
1117	serge	392	} else if (rdev->family == CHIP_RS600) {
		393	DRM_INFO("Loading RS600 Microcode\n");
1221	serge	394	fw_name = FIRMWARE_RS600;
1117	serge	395	} else if ((rdev->family == CHIP_RV515) \|\|
		396	(rdev->family == CHIP_R520) \|\|
		397	(rdev->family == CHIP_RV530) \|\|
		398	(rdev->family == CHIP_R580) \|\|
		399	(rdev->family == CHIP_RV560) \|\|
		400	(rdev->family == CHIP_RV570)) {
		401	DRM_INFO("Loading R500 Microcode\n");
1221	serge	402	fw_name = FIRMWARE_R520;
1117	serge	403	}
1221	serge	404
		405	// err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
		406	// platform_device_unregister(pdev);
		407	if (err) {
		408	printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
		409	fw_name);
		410	} else if (rdev->me_fw->size % 8) {
		411	printk(KERN_ERR
		412	"radeon_cp: Bogus length %zu in firmware \"%s\"\n",
		413	rdev->me_fw->size, fw_name);
		414	err = -EINVAL;
		415	release_firmware(rdev->me_fw);
		416	rdev->me_fw = NULL;
1117	serge	417	}
1221	serge	418	return err;
1117	serge	419	}
		420
1221	serge	421	static inline __u32 __swab32(__u32 x)
1179	serge	422	{
1221	serge	423	asm("bswapl %0" :
		424	"=&r" (x)
		425	:"r" (x));
		426	return x;
1179	serge	427	}
		428
1221	serge	429	static inline __u32 be32_to_cpup(const __be32 *p)
		430	{
		431	return __swab32((__u32 )p);
		432	}
1179	serge	433
1221	serge	434
		435	static void r100_cp_load_microcode(struct radeon_device *rdev)
		436	{
		437	const __be32 *fw_data;
		438	int i, size;
		439
		440	if (r100_gui_wait_for_idle(rdev)) {
		441	printk(KERN_WARNING "Failed to wait GUI idle while "
		442	"programming pipes. Bad things might happen.\n");
		443	}
		444
		445	if (rdev->me_fw) {
		446	size = rdev->me_fw->size / 4;
		447	fw_data = (const __be32 *)&rdev->me_fw->data[0];
		448	WREG32(RADEON_CP_ME_RAM_ADDR, 0);
		449	for (i = 0; i < size; i += 2) {
		450	WREG32(RADEON_CP_ME_RAM_DATAH,
		451	be32_to_cpup(&fw_data[i]));
		452	WREG32(RADEON_CP_ME_RAM_DATAL,
		453	be32_to_cpup(&fw_data[i + 1]));
		454	}
		455	}
		456	}
		457
1117	serge	458	int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
		459	{
		460	unsigned rb_bufsz;
		461	unsigned rb_blksz;
		462	unsigned max_fetch;
		463	unsigned pre_write_timer;
		464	unsigned pre_write_limit;
		465	unsigned indirect2_start;
		466	unsigned indirect1_start;
		467	uint32_t tmp;
		468	int r;
		469
1129	serge	470	if (r100_debugfs_cp_init(rdev)) {
		471	DRM_ERROR("Failed to register debugfs file for CP !\n");
		472	}
1117	serge	473	/* Reset CP */
		474	tmp = RREG32(RADEON_CP_CSQ_STAT);
		475	if ((tmp & (1 << 31))) {
		476	DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
		477	WREG32(RADEON_CP_CSQ_MODE, 0);
		478	WREG32(RADEON_CP_CSQ_CNTL, 0);
		479	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
		480	tmp = RREG32(RADEON_RBBM_SOFT_RESET);
		481	mdelay(2);
		482	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		483	tmp = RREG32(RADEON_RBBM_SOFT_RESET);
		484	mdelay(2);
		485	tmp = RREG32(RADEON_CP_CSQ_STAT);
		486	if ((tmp & (1 << 31))) {
		487	DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
		488	}
		489	} else {
		490	DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
		491	}
1179	serge	492
		493	if (!rdev->me_fw) {
		494	r = r100_cp_init_microcode(rdev);
		495	if (r) {
		496	DRM_ERROR("Failed to load firmware!\n");
		497	return r;
		498	}
		499	}
		500
1117	serge	501	/* Align ring size */
		502	rb_bufsz = drm_order(ring_size / 8);
		503	ring_size = (1 << (rb_bufsz + 1)) * 4;
		504	r100_cp_load_microcode(rdev);
		505	r = radeon_ring_init(rdev, ring_size);
		506	if (r) {
		507	return r;
		508	}
		509	/* Each time the cp read 1024 bytes (16 dword/quadword) update
		510	* the rptr copy in system ram */
		511	rb_blksz = 9;
		512	/* cp will read 128bytes at a time (4 dwords) */
		513	max_fetch = 1;
		514	rdev->cp.align_mask = 16 - 1;
		515	/* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
		516	pre_write_timer = 64;
		517	/* Force CP_RB_WPTR write if written more than one time before the
		518	* delay expire
		519	*/
		520	pre_write_limit = 0;
		521	/* Setup the cp cache like this (cache size is 96 dwords) :
		522	* RING 0 to 15
		523	* INDIRECT1 16 to 79
		524	* INDIRECT2 80 to 95
		525	* So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		526	* indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
		527	* indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		528	* Idea being that most of the gpu cmd will be through indirect1 buffer
		529	* so it gets the bigger cache.
		530	*/
		531	indirect2_start = 80;
		532	indirect1_start = 16;
		533	/* cp setup */
		534	WREG32(0x718, pre_write_timer \| (pre_write_limit << 28));
		535	WREG32(RADEON_CP_RB_CNTL,
		536	#ifdef __BIG_ENDIAN
		537	RADEON_BUF_SWAP_32BIT \|
		538	#endif
		539	REG_SET(RADEON_RB_BUFSZ, rb_bufsz) \|
		540	REG_SET(RADEON_RB_BLKSZ, rb_blksz) \|
		541	REG_SET(RADEON_MAX_FETCH, max_fetch) \|
		542	RADEON_RB_NO_UPDATE);
		543	/* Set ring address */
		544	DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
		545	WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
		546	/* Force read & write ptr to 0 */
		547	tmp = RREG32(RADEON_CP_RB_CNTL);
		548	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);
		549	WREG32(RADEON_CP_RB_RPTR_WR, 0);
		550	WREG32(RADEON_CP_RB_WPTR, 0);
		551	WREG32(RADEON_CP_RB_CNTL, tmp);
		552	udelay(10);
		553	rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
		554	rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
		555	/* Set cp mode to bus mastering & enable cp*/
		556	WREG32(RADEON_CP_CSQ_MODE,
		557	REG_SET(RADEON_INDIRECT2_START, indirect2_start) \|
		558	REG_SET(RADEON_INDIRECT1_START, indirect1_start));
		559	WREG32(0x718, 0);
		560	WREG32(0x744, 0x00004D4D);
		561	WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
		562	radeon_ring_start(rdev);
		563	r = radeon_ring_test(rdev);
		564	if (r) {
		565	DRM_ERROR("radeon: cp isn't working (%d).\n", r);
		566	return r;
		567	}
		568	rdev->cp.ready = true;
		569	return 0;
		570	}
		571
		572	void r100_cp_fini(struct radeon_device *rdev)
		573	{
1179	serge	574	if (r100_cp_wait_for_idle(rdev)) {
		575	DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
		576	}
1117	serge	577	/* Disable ring */
1179	serge	578	r100_cp_disable(rdev);
1117	serge	579	radeon_ring_fini(rdev);
		580	DRM_INFO("radeon: cp finalized\n");
		581	}
		582
		583	void r100_cp_disable(struct radeon_device *rdev)
		584	{
		585	/* Disable ring */
		586	rdev->cp.ready = false;
		587	WREG32(RADEON_CP_CSQ_MODE, 0);
		588	WREG32(RADEON_CP_CSQ_CNTL, 0);
		589	if (r100_gui_wait_for_idle(rdev)) {
		590	printk(KERN_WARNING "Failed to wait GUI idle while "
		591	"programming pipes. Bad things might happen.\n");
		592	}
		593	}
		594
		595	int r100_cp_reset(struct radeon_device *rdev)
		596	{
		597	uint32_t tmp;
		598	bool reinit_cp;
		599	int i;
		600
1179	serge	601	ENTER();
1117	serge	602
		603	reinit_cp = rdev->cp.ready;
		604	rdev->cp.ready = false;
		605	WREG32(RADEON_CP_CSQ_MODE, 0);
		606	WREG32(RADEON_CP_CSQ_CNTL, 0);
		607	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
		608	(void)RREG32(RADEON_RBBM_SOFT_RESET);
		609	udelay(200);
		610	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		611	/* Wait to prevent race in RBBM_STATUS */
		612	mdelay(1);
		613	for (i = 0; i < rdev->usec_timeout; i++) {
		614	tmp = RREG32(RADEON_RBBM_STATUS);
		615	if (!(tmp & (1 << 16))) {
		616	DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
		617	tmp);
		618	if (reinit_cp) {
		619	return r100_cp_init(rdev, rdev->cp.ring_size);
		620	}
		621	return 0;
		622	}
		623	DRM_UDELAY(1);
		624	}
		625	tmp = RREG32(RADEON_RBBM_STATUS);
		626	DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
		627	return -1;
		628	}
		629
1179	serge	630	void r100_cp_commit(struct radeon_device *rdev)
		631	{
		632	WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
		633	(void)RREG32(RADEON_CP_RB_WPTR);
		634	}
		635
		636
1117	serge	637	#if 0
		638	/*
		639	* CS functions
		640	*/
		641	int r100_cs_parse_packet0(struct radeon_cs_parser *p,
		642	struct radeon_cs_packet *pkt,
		643	const unsigned *auth, unsigned n,
		644	radeon_packet0_check_t check)
		645	{
		646	unsigned reg;
		647	unsigned i, j, m;
		648	unsigned idx;
		649	int r;
		650
		651	idx = pkt->idx + 1;
		652	reg = pkt->reg;
		653	/* Check that register fall into register range
		654	* determined by the number of entry (n) in the
		655	* safe register bitmap.
		656	*/
		657	if (pkt->one_reg_wr) {
		658	if ((reg >> 7) > n) {
		659	return -EINVAL;
		660	}
		661	} else {
		662	if (((reg + (pkt->count << 2)) >> 7) > n) {
		663	return -EINVAL;
		664	}
		665	}
		666	for (i = 0; i <= pkt->count; i++, idx++) {
		667	j = (reg >> 7);
		668	m = 1 << ((reg >> 2) & 31);
		669	if (auth[j] & m) {
		670	r = check(p, pkt, idx, reg);
		671	if (r) {
		672	return r;
		673	}
		674	}
		675	if (pkt->one_reg_wr) {
		676	if (!(auth[j] & m)) {
		677	break;
		678	}
		679	} else {
		680	reg += 4;
		681	}
		682	}
		683	return 0;
		684	}
		685
		686	void r100_cs_dump_packet(struct radeon_cs_parser *p,
		687	struct radeon_cs_packet *pkt)
		688	{
		689	volatile uint32_t *ib;
		690	unsigned i;
		691	unsigned idx;
		692
		693	ib = p->ib->ptr;
		694	idx = pkt->idx;
		695	for (i = 0; i <= (pkt->count + 1); i++, idx++) {
		696	DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
		697	}
		698	}
		699
		700	/**
		701	* r100_cs_packet_parse() - parse cp packet and point ib index to next packet
		702	* @parser: parser structure holding parsing context.
		703	* @pkt: where to store packet informations
		704	*
		705	* Assume that chunk_ib_index is properly set. Will return -EINVAL
		706	* if packet is bigger than remaining ib size. or if packets is unknown.
		707	**/
		708	int r100_cs_packet_parse(struct radeon_cs_parser *p,
		709	struct radeon_cs_packet *pkt,
		710	unsigned idx)
		711	{
		712	struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1179	serge	713	uint32_t header;
1117	serge	714
		715	if (idx >= ib_chunk->length_dw) {
		716	DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
		717	idx, ib_chunk->length_dw);
		718	return -EINVAL;
		719	}
1221	serge	720	header = radeon_get_ib_value(p, idx);
1117	serge	721	pkt->idx = idx;
		722	pkt->type = CP_PACKET_GET_TYPE(header);
		723	pkt->count = CP_PACKET_GET_COUNT(header);
		724	switch (pkt->type) {
		725	case PACKET_TYPE0:
		726	pkt->reg = CP_PACKET0_GET_REG(header);
		727	pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
		728	break;
		729	case PACKET_TYPE3:
		730	pkt->opcode = CP_PACKET3_GET_OPCODE(header);
		731	break;
		732	case PACKET_TYPE2:
		733	pkt->count = -1;
		734	break;
		735	default:
		736	DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
		737	return -EINVAL;
		738	}
		739	if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
		740	DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
		741	pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
		742	return -EINVAL;
		743	}
		744	return 0;
		745	}
		746
		747	/**
1179	serge	748	* r100_cs_packet_next_vline() - parse userspace VLINE packet
		749	* @parser: parser structure holding parsing context.
		750	*
		751	* Userspace sends a special sequence for VLINE waits.
		752	* PACKET0 - VLINE_START_END + value
		753	* PACKET0 - WAIT_UNTIL +_value
		754	* RELOC (P3) - crtc_id in reloc.
		755	*
		756	* This function parses this and relocates the VLINE START END
		757	* and WAIT UNTIL packets to the correct crtc.
		758	* It also detects a switched off crtc and nulls out the
		759	* wait in that case.
		760	*/
		761	int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
		762	{
		763	struct drm_mode_object *obj;
		764	struct drm_crtc *crtc;
		765	struct radeon_crtc *radeon_crtc;
		766	struct radeon_cs_packet p3reloc, waitreloc;
		767	int crtc_id;
		768	int r;
		769	uint32_t header, h_idx, reg;
1221	serge	770	volatile uint32_t *ib;
1179	serge	771
1221	serge	772	ib = p->ib->ptr;
1179	serge	773
		774	/* parse the wait until */
		775	r = r100_cs_packet_parse(p, &waitreloc, p->idx);
		776	if (r)
		777	return r;
		778
		779	/* check its a wait until and only 1 count */
		780	if (waitreloc.reg != RADEON_WAIT_UNTIL \|\|
		781	waitreloc.count != 0) {
		782	DRM_ERROR("vline wait had illegal wait until segment\n");
		783	r = -EINVAL;
		784	return r;
		785	}
		786
1221	serge	787	if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1179	serge	788	DRM_ERROR("vline wait had illegal wait until\n");
		789	r = -EINVAL;
		790	return r;
		791	}
		792
		793	/* jump over the NOP */
1221	serge	794	r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1179	serge	795	if (r)
		796	return r;
		797
		798	h_idx = p->idx - 2;
1221	serge	799	p->idx += waitreloc.count + 2;
		800	p->idx += p3reloc.count + 2;
1179	serge	801
1221	serge	802	header = radeon_get_ib_value(p, h_idx);
		803	crtc_id = radeon_get_ib_value(p, h_idx + 5);
		804	reg = CP_PACKET0_GET_REG(header);
1179	serge	805	mutex_lock(&p->rdev->ddev->mode_config.mutex);
		806	obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
		807	if (!obj) {
		808	DRM_ERROR("cannot find crtc %d\n", crtc_id);
		809	r = -EINVAL;
		810	goto out;
		811	}
		812	crtc = obj_to_crtc(obj);
		813	radeon_crtc = to_radeon_crtc(crtc);
		814	crtc_id = radeon_crtc->crtc_id;
		815
		816	if (!crtc->enabled) {
		817	/* if the CRTC isn't enabled - we need to nop out the wait until */
1221	serge	818	ib[h_idx + 2] = PACKET2(0);
		819	ib[h_idx + 3] = PACKET2(0);
1179	serge	820	} else if (crtc_id == 1) {
		821	switch (reg) {
		822	case AVIVO_D1MODE_VLINE_START_END:
1221	serge	823	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	824	header \|= AVIVO_D2MODE_VLINE_START_END >> 2;
		825	break;
		826	case RADEON_CRTC_GUI_TRIG_VLINE:
1221	serge	827	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	828	header \|= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
		829	break;
		830	default:
		831	DRM_ERROR("unknown crtc reloc\n");
		832	r = -EINVAL;
		833	goto out;
		834	}
1221	serge	835	ib[h_idx] = header;
		836	ib[h_idx + 3] \|= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1179	serge	837	}
		838	out:
		839	mutex_unlock(&p->rdev->ddev->mode_config.mutex);
		840	return r;
		841	}
		842
		843	/**
1117	serge	844	* r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
		845	* @parser: parser structure holding parsing context.
		846	* @data: pointer to relocation data
		847	* @offset_start: starting offset
		848	* @offset_mask: offset mask (to align start offset on)
		849	* @reloc: reloc informations
		850	*
		851	* Check next packet is relocation packet3, do bo validation and compute
		852	* GPU offset using the provided start.
		853	**/
		854	int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
		855	struct radeon_cs_reloc **cs_reloc)
		856	{
		857	struct radeon_cs_chunk *relocs_chunk;
		858	struct radeon_cs_packet p3reloc;
		859	unsigned idx;
		860	int r;
		861
		862	if (p->chunk_relocs_idx == -1) {
		863	DRM_ERROR("No relocation chunk !\n");
		864	return -EINVAL;
		865	}
		866	*cs_reloc = NULL;
		867	relocs_chunk = &p->chunks[p->chunk_relocs_idx];
		868	r = r100_cs_packet_parse(p, &p3reloc, p->idx);
		869	if (r) {
		870	return r;
		871	}
		872	p->idx += p3reloc.count + 2;
		873	if (p3reloc.type != PACKET_TYPE3 \|\| p3reloc.opcode != PACKET3_NOP) {
		874	DRM_ERROR("No packet3 for relocation for packet at %d.\n",
		875	p3reloc.idx);
		876	r100_cs_dump_packet(p, &p3reloc);
		877	return -EINVAL;
		878	}
1221	serge	879	idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1117	serge	880	if (idx >= relocs_chunk->length_dw) {
		881	DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
		882	idx, relocs_chunk->length_dw);
		883	r100_cs_dump_packet(p, &p3reloc);
		884	return -EINVAL;
		885	}
		886	/* FIXME: we assume reloc size is 4 dwords */
		887	*cs_reloc = p->relocs_ptr[(idx / 4)];
		888	return 0;
		889	}
		890
1179	serge	891	static int r100_get_vtx_size(uint32_t vtx_fmt)
		892	{
		893	int vtx_size;
		894	vtx_size = 2;
		895	/* ordered according to bits in spec */
		896	if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
		897	vtx_size++;
		898	if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
		899	vtx_size += 3;
		900	if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
		901	vtx_size++;
		902	if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
		903	vtx_size++;
		904	if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
		905	vtx_size += 3;
		906	if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
		907	vtx_size++;
		908	if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
		909	vtx_size++;
		910	if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
		911	vtx_size += 2;
		912	if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
		913	vtx_size += 2;
		914	if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
		915	vtx_size++;
		916	if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
		917	vtx_size += 2;
		918	if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
		919	vtx_size++;
		920	if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
		921	vtx_size += 2;
		922	if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
		923	vtx_size++;
		924	if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
		925	vtx_size++;
		926	/* blend weight */
		927	if (vtx_fmt & (0x7 << 15))
		928	vtx_size += (vtx_fmt >> 15) & 0x7;
		929	if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
		930	vtx_size += 3;
		931	if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
		932	vtx_size += 2;
		933	if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
		934	vtx_size++;
		935	if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
		936	vtx_size++;
		937	if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
		938	vtx_size++;
		939	if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
		940	vtx_size++;
		941	return vtx_size;
		942	}
		943
1117	serge	944	static int r100_packet0_check(struct radeon_cs_parser *p,
1179	serge	945	struct radeon_cs_packet *pkt,
		946	unsigned idx, unsigned reg)
1117	serge	947	{
		948	struct radeon_cs_reloc *reloc;
1179	serge	949	struct r100_cs_track *track;
1117	serge	950	volatile uint32_t *ib;
		951	uint32_t tmp;
		952	int r;
1179	serge	953	int i, face;
		954	u32 tile_flags = 0;
1221	serge	955	u32 idx_value;
1117	serge	956
		957	ib = p->ib->ptr;
1179	serge	958	track = (struct r100_cs_track *)p->track;
		959
1221	serge	960	idx_value = radeon_get_ib_value(p, idx);
		961
1117	serge	962	switch (reg) {
1179	serge	963	case RADEON_CRTC_GUI_TRIG_VLINE:
		964	r = r100_cs_packet_parse_vline(p);
		965	if (r) {
		966	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		967	idx, reg);
		968	r100_cs_dump_packet(p, pkt);
		969	return r;
		970	}
		971	break;
1117	serge	972	/* FIXME: only allow PACKET3 blit? easier to check for out of
		973	* range access */
		974	case RADEON_DST_PITCH_OFFSET:
		975	case RADEON_SRC_PITCH_OFFSET:
1179	serge	976	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		977	if (r)
		978	return r;
		979	break;
		980	case RADEON_RB3D_DEPTHOFFSET:
1117	serge	981	r = r100_cs_packet_next_reloc(p, &reloc);
		982	if (r) {
		983	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		984	idx, reg);
		985	r100_cs_dump_packet(p, pkt);
		986	return r;
		987	}
1179	serge	988	track->zb.robj = reloc->robj;
1221	serge	989	track->zb.offset = idx_value;
		990	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1117	serge	991	break;
		992	case RADEON_RB3D_COLOROFFSET:
1179	serge	993	r = r100_cs_packet_next_reloc(p, &reloc);
		994	if (r) {
		995	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		996	idx, reg);
		997	r100_cs_dump_packet(p, pkt);
		998	return r;
		999	}
		1000	track->cb[0].robj = reloc->robj;
1221	serge	1001	track->cb[0].offset = idx_value;
		1002	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1003	break;
1117	serge	1004	case RADEON_PP_TXOFFSET_0:
		1005	case RADEON_PP_TXOFFSET_1:
		1006	case RADEON_PP_TXOFFSET_2:
1179	serge	1007	i = (reg - RADEON_PP_TXOFFSET_0) / 24;
		1008	r = r100_cs_packet_next_reloc(p, &reloc);
		1009	if (r) {
		1010	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1011	idx, reg);
		1012	r100_cs_dump_packet(p, pkt);
		1013	return r;
		1014	}
1221	serge	1015	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1016	track->textures[i].robj = reloc->robj;
		1017	break;
		1018	case RADEON_PP_CUBIC_OFFSET_T0_0:
		1019	case RADEON_PP_CUBIC_OFFSET_T0_1:
		1020	case RADEON_PP_CUBIC_OFFSET_T0_2:
		1021	case RADEON_PP_CUBIC_OFFSET_T0_3:
		1022	case RADEON_PP_CUBIC_OFFSET_T0_4:
		1023	i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
		1024	r = r100_cs_packet_next_reloc(p, &reloc);
		1025	if (r) {
		1026	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1027	idx, reg);
		1028	r100_cs_dump_packet(p, pkt);
		1029	return r;
		1030	}
1221	serge	1031	track->textures[0].cube_info[i].offset = idx_value;
		1032	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1033	track->textures[0].cube_info[i].robj = reloc->robj;
		1034	break;
		1035	case RADEON_PP_CUBIC_OFFSET_T1_0:
		1036	case RADEON_PP_CUBIC_OFFSET_T1_1:
		1037	case RADEON_PP_CUBIC_OFFSET_T1_2:
		1038	case RADEON_PP_CUBIC_OFFSET_T1_3:
		1039	case RADEON_PP_CUBIC_OFFSET_T1_4:
		1040	i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
		1041	r = r100_cs_packet_next_reloc(p, &reloc);
		1042	if (r) {
		1043	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1044	idx, reg);
		1045	r100_cs_dump_packet(p, pkt);
		1046	return r;
		1047	}
1221	serge	1048	track->textures[1].cube_info[i].offset = idx_value;
		1049	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1050	track->textures[1].cube_info[i].robj = reloc->robj;
		1051	break;
		1052	case RADEON_PP_CUBIC_OFFSET_T2_0:
		1053	case RADEON_PP_CUBIC_OFFSET_T2_1:
		1054	case RADEON_PP_CUBIC_OFFSET_T2_2:
		1055	case RADEON_PP_CUBIC_OFFSET_T2_3:
		1056	case RADEON_PP_CUBIC_OFFSET_T2_4:
		1057	i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1117	serge	1058	r = r100_cs_packet_next_reloc(p, &reloc);
		1059	if (r) {
		1060	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1061	idx, reg);
		1062	r100_cs_dump_packet(p, pkt);
		1063	return r;
		1064	}
1221	serge	1065	track->textures[2].cube_info[i].offset = idx_value;
		1066	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1067	track->textures[2].cube_info[i].robj = reloc->robj;
		1068	break;
		1069	case RADEON_RE_WIDTH_HEIGHT:
1221	serge	1070	track->maxy = ((idx_value >> 16) & 0x7FF);
1117	serge	1071	break;
1179	serge	1072	case RADEON_RB3D_COLORPITCH:
		1073	r = r100_cs_packet_next_reloc(p, &reloc);
		1074	if (r) {
		1075	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1076	idx, reg);
		1077	r100_cs_dump_packet(p, pkt);
		1078	return r;
		1079	}
		1080
		1081	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		1082	tile_flags \|= RADEON_COLOR_TILE_ENABLE;
		1083	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		1084	tile_flags \|= RADEON_COLOR_MICROTILE_ENABLE;
		1085
1221	serge	1086	tmp = idx_value & ~(0x7 << 16);
1179	serge	1087	tmp \|= tile_flags;
		1088	ib[idx] = tmp;
		1089
1221	serge	1090	track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1179	serge	1091	break;
		1092	case RADEON_RB3D_DEPTHPITCH:
1221	serge	1093	track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1179	serge	1094	break;
		1095	case RADEON_RB3D_CNTL:
1221	serge	1096	switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1179	serge	1097	case 7:
		1098	case 8:
		1099	case 9:
		1100	case 11:
		1101	case 12:
		1102	track->cb[0].cpp = 1;
		1103	break;
		1104	case 3:
		1105	case 4:
		1106	case 15:
		1107	track->cb[0].cpp = 2;
		1108	break;
		1109	case 6:
		1110	track->cb[0].cpp = 4;
		1111	break;
1117	serge	1112	default:
1179	serge	1113	DRM_ERROR("Invalid color buffer format (%d) !\n",
1221	serge	1114	((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1179	serge	1115	return -EINVAL;
		1116	}
1221	serge	1117	track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1179	serge	1118	break;
		1119	case RADEON_RB3D_ZSTENCILCNTL:
1221	serge	1120	switch (idx_value & 0xf) {
1179	serge	1121	case 0:
		1122	track->zb.cpp = 2;
1117	serge	1123	break;
1179	serge	1124	case 2:
		1125	case 3:
		1126	case 4:
		1127	case 5:
		1128	case 9:
		1129	case 11:
		1130	track->zb.cpp = 4;
		1131	break;
		1132	default:
		1133	break;
1117	serge	1134	}
		1135	break;
1179	serge	1136	case RADEON_RB3D_ZPASS_ADDR:
		1137	r = r100_cs_packet_next_reloc(p, &reloc);
		1138	if (r) {
		1139	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1140	idx, reg);
		1141	r100_cs_dump_packet(p, pkt);
		1142	return r;
		1143	}
1221	serge	1144	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1145	break;
		1146	case RADEON_PP_CNTL:
		1147	{
1221	serge	1148	uint32_t temp = idx_value >> 4;
1179	serge	1149	for (i = 0; i < track->num_texture; i++)
		1150	track->textures[i].enabled = !!(temp & (1 << i));
1117	serge	1151	}
1179	serge	1152	break;
		1153	case RADEON_SE_VF_CNTL:
1221	serge	1154	track->vap_vf_cntl = idx_value;
1179	serge	1155	break;
		1156	case RADEON_SE_VTX_FMT:
1221	serge	1157	track->vtx_size = r100_get_vtx_size(idx_value);
1179	serge	1158	break;
		1159	case RADEON_PP_TEX_SIZE_0:
		1160	case RADEON_PP_TEX_SIZE_1:
		1161	case RADEON_PP_TEX_SIZE_2:
		1162	i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1221	serge	1163	track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
		1164	track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1179	serge	1165	break;
		1166	case RADEON_PP_TEX_PITCH_0:
		1167	case RADEON_PP_TEX_PITCH_1:
		1168	case RADEON_PP_TEX_PITCH_2:
		1169	i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1221	serge	1170	track->textures[i].pitch = idx_value + 32;
1179	serge	1171	break;
		1172	case RADEON_PP_TXFILTER_0:
		1173	case RADEON_PP_TXFILTER_1:
		1174	case RADEON_PP_TXFILTER_2:
		1175	i = (reg - RADEON_PP_TXFILTER_0) / 24;
1221	serge	1176	track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1179	serge	1177	>> RADEON_MAX_MIP_LEVEL_SHIFT);
1221	serge	1178	tmp = (idx_value >> 23) & 0x7;
1179	serge	1179	if (tmp == 2 \|\| tmp == 6)
		1180	track->textures[i].roundup_w = false;
1221	serge	1181	tmp = (idx_value >> 27) & 0x7;
1179	serge	1182	if (tmp == 2 \|\| tmp == 6)
		1183	track->textures[i].roundup_h = false;
		1184	break;
		1185	case RADEON_PP_TXFORMAT_0:
		1186	case RADEON_PP_TXFORMAT_1:
		1187	case RADEON_PP_TXFORMAT_2:
		1188	i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1221	serge	1189	if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1179	serge	1190	track->textures[i].use_pitch = 1;
		1191	} else {
		1192	track->textures[i].use_pitch = 0;
1221	serge	1193	track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
		1194	track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1179	serge	1195	}
1221	serge	1196	if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1179	serge	1197	track->textures[i].tex_coord_type = 2;
1221	serge	1198	switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1179	serge	1199	case RADEON_TXFORMAT_I8:
		1200	case RADEON_TXFORMAT_RGB332:
		1201	case RADEON_TXFORMAT_Y8:
		1202	track->textures[i].cpp = 1;
		1203	break;
		1204	case RADEON_TXFORMAT_AI88:
		1205	case RADEON_TXFORMAT_ARGB1555:
		1206	case RADEON_TXFORMAT_RGB565:
		1207	case RADEON_TXFORMAT_ARGB4444:
		1208	case RADEON_TXFORMAT_VYUY422:
		1209	case RADEON_TXFORMAT_YVYU422:
		1210	case RADEON_TXFORMAT_DXT1:
		1211	case RADEON_TXFORMAT_SHADOW16:
		1212	case RADEON_TXFORMAT_LDUDV655:
		1213	case RADEON_TXFORMAT_DUDV88:
		1214	track->textures[i].cpp = 2;
		1215	break;
		1216	case RADEON_TXFORMAT_ARGB8888:
		1217	case RADEON_TXFORMAT_RGBA8888:
		1218	case RADEON_TXFORMAT_DXT23:
		1219	case RADEON_TXFORMAT_DXT45:
		1220	case RADEON_TXFORMAT_SHADOW32:
		1221	case RADEON_TXFORMAT_LDUDUV8888:
		1222	track->textures[i].cpp = 4;
		1223	break;
		1224	}
1221	serge	1225	track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
		1226	track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1179	serge	1227	break;
		1228	case RADEON_PP_CUBIC_FACES_0:
		1229	case RADEON_PP_CUBIC_FACES_1:
		1230	case RADEON_PP_CUBIC_FACES_2:
1221	serge	1231	tmp = idx_value;
1179	serge	1232	i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
		1233	for (face = 0; face < 4; face++) {
		1234	track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
		1235	track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
		1236	}
		1237	break;
		1238	default:
		1239	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
		1240	reg, idx);
		1241	return -EINVAL;
1117	serge	1242	}
		1243	return 0;
		1244	}
		1245
		1246	int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
		1247	struct radeon_cs_packet *pkt,
		1248	struct radeon_object *robj)
		1249	{
		1250	unsigned idx;
1221	serge	1251	u32 value;
1117	serge	1252	idx = pkt->idx + 1;
1221	serge	1253	value = radeon_get_ib_value(p, idx + 2);
		1254	if ((value + 1) > radeon_object_size(robj)) {
1117	serge	1255	DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
		1256	"(need %u have %lu) !\n",
1221	serge	1257	value + 1,
1117	serge	1258	radeon_object_size(robj));
		1259	return -EINVAL;
		1260	}
		1261	return 0;
		1262	}
		1263
		1264	static int r100_packet3_check(struct radeon_cs_parser *p,
		1265	struct radeon_cs_packet *pkt)
		1266	{
		1267	struct radeon_cs_reloc *reloc;
1179	serge	1268	struct r100_cs_track *track;
1117	serge	1269	unsigned idx;
		1270	volatile uint32_t *ib;
		1271	int r;
		1272
		1273	ib = p->ib->ptr;
		1274	idx = pkt->idx + 1;
1179	serge	1275	track = (struct r100_cs_track *)p->track;
1117	serge	1276	switch (pkt->opcode) {
		1277	case PACKET3_3D_LOAD_VBPNTR:
1221	serge	1278	r = r100_packet3_load_vbpntr(p, pkt, idx);
		1279	if (r)
1117	serge	1280	return r;
		1281	break;
		1282	case PACKET3_INDX_BUFFER:
		1283	r = r100_cs_packet_next_reloc(p, &reloc);
		1284	if (r) {
		1285	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1286	r100_cs_dump_packet(p, pkt);
		1287	return r;
		1288	}
1221	serge	1289	ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1117	serge	1290	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		1291	if (r) {
		1292	return r;
		1293	}
		1294	break;
		1295	case 0x23:
		1296	/* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
		1297	r = r100_cs_packet_next_reloc(p, &reloc);
		1298	if (r) {
		1299	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1300	r100_cs_dump_packet(p, pkt);
		1301	return r;
		1302	}
1221	serge	1303	ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1179	serge	1304	track->num_arrays = 1;
1221	serge	1305	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1179	serge	1306
		1307	track->arrays[0].robj = reloc->robj;
		1308	track->arrays[0].esize = track->vtx_size;
		1309
1221	serge	1310	track->max_indx = radeon_get_ib_value(p, idx+1);
1179	serge	1311
1221	serge	1312	track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1179	serge	1313	track->immd_dwords = pkt->count - 1;
		1314	r = r100_cs_track_check(p->rdev, track);
		1315	if (r)
		1316	return r;
1117	serge	1317	break;
		1318	case PACKET3_3D_DRAW_IMMD:
1221	serge	1319	if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1179	serge	1320	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1321	return -EINVAL;
		1322	}
1221	serge	1323	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1324	track->immd_dwords = pkt->count - 1;
		1325	r = r100_cs_track_check(p->rdev, track);
		1326	if (r)
		1327	return r;
		1328	break;
1117	serge	1329	/* triggers drawing using in-packet vertex data */
		1330	case PACKET3_3D_DRAW_IMMD_2:
1221	serge	1331	if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1179	serge	1332	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1333	return -EINVAL;
		1334	}
1221	serge	1335	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1336	track->immd_dwords = pkt->count;
		1337	r = r100_cs_track_check(p->rdev, track);
		1338	if (r)
		1339	return r;
		1340	break;
1117	serge	1341	/* triggers drawing using in-packet vertex data */
		1342	case PACKET3_3D_DRAW_VBUF_2:
1221	serge	1343	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1344	r = r100_cs_track_check(p->rdev, track);
		1345	if (r)
		1346	return r;
		1347	break;
1117	serge	1348	/* triggers drawing of vertex buffers setup elsewhere */
		1349	case PACKET3_3D_DRAW_INDX_2:
1221	serge	1350	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1351	r = r100_cs_track_check(p->rdev, track);
		1352	if (r)
		1353	return r;
		1354	break;
1117	serge	1355	/* triggers drawing using indices to vertex buffer */
		1356	case PACKET3_3D_DRAW_VBUF:
1221	serge	1357	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1358	r = r100_cs_track_check(p->rdev, track);
		1359	if (r)
		1360	return r;
		1361	break;
1117	serge	1362	/* triggers drawing of vertex buffers setup elsewhere */
		1363	case PACKET3_3D_DRAW_INDX:
1221	serge	1364	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1365	r = r100_cs_track_check(p->rdev, track);
		1366	if (r)
		1367	return r;
		1368	break;
1117	serge	1369	/* triggers drawing using indices to vertex buffer */
		1370	case PACKET3_NOP:
		1371	break;
		1372	default:
		1373	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		1374	return -EINVAL;
		1375	}
		1376	return 0;
		1377	}
		1378
		1379	int r100_cs_parse(struct radeon_cs_parser *p)
		1380	{
		1381	struct radeon_cs_packet pkt;
1179	serge	1382	struct r100_cs_track *track;
1117	serge	1383	int r;
		1384
1179	serge	1385	track = kzalloc(sizeof(*track), GFP_KERNEL);
		1386	r100_cs_track_clear(p->rdev, track);
		1387	p->track = track;
1117	serge	1388	do {
		1389	r = r100_cs_packet_parse(p, &pkt, p->idx);
		1390	if (r) {
		1391	return r;
		1392	}
		1393	p->idx += pkt.count + 2;
		1394	switch (pkt.type) {
		1395	case PACKET_TYPE0:
1179	serge	1396	if (p->rdev->family >= CHIP_R200)
		1397	r = r100_cs_parse_packet0(p, &pkt,
		1398	p->rdev->config.r100.reg_safe_bm,
		1399	p->rdev->config.r100.reg_safe_bm_size,
		1400	&r200_packet0_check);
		1401	else
		1402	r = r100_cs_parse_packet0(p, &pkt,
		1403	p->rdev->config.r100.reg_safe_bm,
		1404	p->rdev->config.r100.reg_safe_bm_size,
		1405	&r100_packet0_check);
1117	serge	1406	break;
		1407	case PACKET_TYPE2:
		1408	break;
		1409	case PACKET_TYPE3:
		1410	r = r100_packet3_check(p, &pkt);
		1411	break;
		1412	default:
		1413	DRM_ERROR("Unknown packet type %d !\n",
		1414	pkt.type);
		1415	return -EINVAL;
		1416	}
		1417	if (r) {
		1418	return r;
		1419	}
		1420	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
		1421	return 0;
		1422	}
		1423
1128	serge	1424	#endif
1117	serge	1425
		1426	/*
		1427	* Global GPU functions
		1428	*/
		1429	void r100_errata(struct radeon_device *rdev)
		1430	{
		1431	rdev->pll_errata = 0;
		1432
		1433	if (rdev->family == CHIP_RV200 \|\| rdev->family == CHIP_RS200) {
		1434	rdev->pll_errata \|= CHIP_ERRATA_PLL_DUMMYREADS;
		1435	}
		1436
		1437	if (rdev->family == CHIP_RV100 \|\|
		1438	rdev->family == CHIP_RS100 \|\|
		1439	rdev->family == CHIP_RS200) {
		1440	rdev->pll_errata \|= CHIP_ERRATA_PLL_DELAY;
		1441	}
		1442	}
		1443
		1444	/* Wait for vertical sync on primary CRTC */
		1445	void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
		1446	{
		1447	uint32_t crtc_gen_cntl, tmp;
		1448	int i;
		1449
		1450	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
		1451	if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) \|\|
		1452	!(crtc_gen_cntl & RADEON_CRTC_EN)) {
		1453	return;
		1454	}
		1455	/* Clear the CRTC_VBLANK_SAVE bit */
		1456	WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
		1457	for (i = 0; i < rdev->usec_timeout; i++) {
		1458	tmp = RREG32(RADEON_CRTC_STATUS);
		1459	if (tmp & RADEON_CRTC_VBLANK_SAVE) {
		1460	return;
		1461	}
		1462	DRM_UDELAY(1);
		1463	}
		1464	}
		1465
		1466	/* Wait for vertical sync on secondary CRTC */
		1467	void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
		1468	{
		1469	uint32_t crtc2_gen_cntl, tmp;
		1470	int i;
		1471
		1472	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1473	if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) \|\|
		1474	!(crtc2_gen_cntl & RADEON_CRTC2_EN))
		1475	return;
		1476
		1477	/* Clear the CRTC_VBLANK_SAVE bit */
		1478	WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
		1479	for (i = 0; i < rdev->usec_timeout; i++) {
		1480	tmp = RREG32(RADEON_CRTC2_STATUS);
		1481	if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
		1482	return;
		1483	}
		1484	DRM_UDELAY(1);
		1485	}
		1486	}
		1487
		1488	int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
		1489	{
		1490	unsigned i;
		1491	uint32_t tmp;
		1492
		1493	for (i = 0; i < rdev->usec_timeout; i++) {
		1494	tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
		1495	if (tmp >= n) {
		1496	return 0;
		1497	}
		1498	DRM_UDELAY(1);
		1499	}
		1500	return -1;
		1501	}
		1502
		1503	int r100_gui_wait_for_idle(struct radeon_device *rdev)
		1504	{
		1505	unsigned i;
		1506	uint32_t tmp;
		1507
		1508	if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
		1509	printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
		1510	" Bad things might happen.\n");
		1511	}
		1512	for (i = 0; i < rdev->usec_timeout; i++) {
		1513	tmp = RREG32(RADEON_RBBM_STATUS);
		1514	if (!(tmp & (1 << 31))) {
		1515	return 0;
		1516	}
		1517	DRM_UDELAY(1);
		1518	}
		1519	return -1;
		1520	}
		1521
		1522	int r100_mc_wait_for_idle(struct radeon_device *rdev)
		1523	{
		1524	unsigned i;
		1525	uint32_t tmp;
		1526
		1527	for (i = 0; i < rdev->usec_timeout; i++) {
		1528	/* read MC_STATUS */
		1529	tmp = RREG32(0x0150);
		1530	if (tmp & (1 << 2)) {
		1531	return 0;
		1532	}
		1533	DRM_UDELAY(1);
		1534	}
		1535	return -1;
		1536	}
		1537
		1538	void r100_gpu_init(struct radeon_device *rdev)
		1539	{
		1540	/* TODO: anythings to do here ? pipes ? */
		1541	r100_hdp_reset(rdev);
		1542	}
		1543
		1544	void r100_hdp_reset(struct radeon_device *rdev)
		1545	{
		1546	uint32_t tmp;
		1547
1179	serge	1548	ENTER();
1117	serge	1549
		1550	tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
		1551	tmp \|= (7 << 28);
		1552	WREG32(RADEON_HOST_PATH_CNTL, tmp \| RADEON_HDP_SOFT_RESET \| RADEON_HDP_READ_BUFFER_INVALIDATE);
		1553	(void)RREG32(RADEON_HOST_PATH_CNTL);
		1554	udelay(200);
		1555	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		1556	WREG32(RADEON_HOST_PATH_CNTL, tmp);
		1557	(void)RREG32(RADEON_HOST_PATH_CNTL);
		1558	}
		1559
		1560	int r100_rb2d_reset(struct radeon_device *rdev)
		1561	{
		1562	uint32_t tmp;
		1563	int i;
		1564
1179	serge	1565	ENTER();
1117	serge	1566
		1567	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
		1568	(void)RREG32(RADEON_RBBM_SOFT_RESET);
		1569	udelay(200);
		1570	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		1571	/* Wait to prevent race in RBBM_STATUS */
		1572	mdelay(1);
		1573	for (i = 0; i < rdev->usec_timeout; i++) {
		1574	tmp = RREG32(RADEON_RBBM_STATUS);
		1575	if (!(tmp & (1 << 26))) {
		1576	DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
		1577	tmp);
		1578	return 0;
		1579	}
		1580	DRM_UDELAY(1);
		1581	}
		1582	tmp = RREG32(RADEON_RBBM_STATUS);
		1583	DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
		1584	return -1;
		1585	}
		1586
		1587	int r100_gpu_reset(struct radeon_device *rdev)
		1588	{
		1589	uint32_t status;
		1590
		1591	/* reset order likely matter */
		1592	status = RREG32(RADEON_RBBM_STATUS);
		1593	/* reset HDP */
		1594	r100_hdp_reset(rdev);
		1595	/* reset rb2d */
		1596	if (status & ((1 << 17) \| (1 << 18) \| (1 << 27))) {
		1597	r100_rb2d_reset(rdev);
		1598	}
		1599	/* TODO: reset 3D engine */
		1600	/* reset CP */
		1601	status = RREG32(RADEON_RBBM_STATUS);
		1602	if (status & (1 << 16)) {
		1603	r100_cp_reset(rdev);
		1604	}
		1605	/* Check if GPU is idle */
		1606	status = RREG32(RADEON_RBBM_STATUS);
		1607	if (status & (1 << 31)) {
		1608	DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
		1609	return -1;
		1610	}
		1611	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
		1612	return 0;
		1613	}
		1614
		1615
		1616	/*
		1617	* VRAM info
		1618	*/
		1619	static void r100_vram_get_type(struct radeon_device *rdev)
		1620	{
		1621	uint32_t tmp;
		1622
		1623	rdev->mc.vram_is_ddr = false;
		1624	if (rdev->flags & RADEON_IS_IGP)
		1625	rdev->mc.vram_is_ddr = true;
		1626	else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
		1627	rdev->mc.vram_is_ddr = true;
		1628	if ((rdev->family == CHIP_RV100) \|\|
		1629	(rdev->family == CHIP_RS100) \|\|
		1630	(rdev->family == CHIP_RS200)) {
		1631	tmp = RREG32(RADEON_MEM_CNTL);
		1632	if (tmp & RV100_HALF_MODE) {
		1633	rdev->mc.vram_width = 32;
		1634	} else {
		1635	rdev->mc.vram_width = 64;
		1636	}
		1637	if (rdev->flags & RADEON_SINGLE_CRTC) {
		1638	rdev->mc.vram_width /= 4;
		1639	rdev->mc.vram_is_ddr = true;
		1640	}
		1641	} else if (rdev->family <= CHIP_RV280) {
		1642	tmp = RREG32(RADEON_MEM_CNTL);
		1643	if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
		1644	rdev->mc.vram_width = 128;
		1645	} else {
		1646	rdev->mc.vram_width = 64;
		1647	}
		1648	} else {
		1649	/* newer IGPs */
		1650	rdev->mc.vram_width = 128;
		1651	}
		1652	}
		1653
1179	serge	1654	static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1117	serge	1655	{
1179	serge	1656	u32 aper_size;
		1657	u8 byte;
1117	serge	1658
1179	serge	1659	aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
		1660
		1661	/* Set HDP_APER_CNTL only on cards that are known not to be broken,
		1662	* that is has the 2nd generation multifunction PCI interface
		1663	*/
		1664	if (rdev->family == CHIP_RV280 \|\|
		1665	rdev->family >= CHIP_RV350) {
		1666	WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
		1667	~RADEON_HDP_APER_CNTL);
		1668	DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
		1669	return aper_size * 2;
		1670	}
		1671
		1672	/* Older cards have all sorts of funny issues to deal with. First
		1673	* check if it's a multifunction card by reading the PCI config
		1674	* header type... Limit those to one aperture size
		1675	*/
		1676	// pci_read_config_byte(rdev->pdev, 0xe, &byte);
		1677	// if (byte & 0x80) {
		1678	// DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
		1679	// DRM_INFO("Limiting VRAM to one aperture\n");
		1680	// return aper_size;
		1681	// }
		1682
		1683	/* Single function older card. We read HDP_APER_CNTL to see how the BIOS
		1684	* have set it up. We don't write this as it's broken on some ASICs but
		1685	* we expect the BIOS to have done the right thing (might be too optimistic...)
		1686	*/
		1687	if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
		1688	return aper_size * 2;
		1689	return aper_size;
		1690	}
		1691
		1692	void r100_vram_init_sizes(struct radeon_device *rdev)
		1693	{
		1694	u64 config_aper_size;
		1695	u32 accessible;
		1696
		1697	config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
		1698
1117	serge	1699	if (rdev->flags & RADEON_IS_IGP) {
		1700	uint32_t tom;
		1701	/* read NB_TOM to get the amount of ram stolen for the GPU */
		1702	tom = RREG32(RADEON_NB_TOM);
1179	serge	1703	rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
		1704	/* for IGPs we need to keep VRAM where it was put by the BIOS */
		1705	rdev->mc.vram_location = (tom & 0xffff) << 16;
		1706	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
		1707	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	1708	} else {
1179	serge	1709	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1117	serge	1710	/* Some production boards of m6 will report 0
		1711	* if it's 8 MB
		1712	*/
1179	serge	1713	if (rdev->mc.real_vram_size == 0) {
		1714	rdev->mc.real_vram_size = 8192 * 1024;
		1715	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1117	serge	1716	}
1179	serge	1717	/* let driver place VRAM */
		1718	rdev->mc.vram_location = 0xFFFFFFFFUL;
		1719	/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
		1720	* Novell bug 204882 + along with lots of ubuntu ones */
		1721	if (config_aper_size > rdev->mc.real_vram_size)
		1722	rdev->mc.mc_vram_size = config_aper_size;
		1723	else
		1724	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	1725	}
		1726
1179	serge	1727	/* work out accessible VRAM */
		1728	accessible = r100_get_accessible_vram(rdev);
		1729
1117	serge	1730	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
		1731	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1179	serge	1732
		1733	if (accessible > rdev->mc.aper_size)
		1734	accessible = rdev->mc.aper_size;
		1735
		1736	if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
		1737	rdev->mc.mc_vram_size = rdev->mc.aper_size;
		1738
		1739	if (rdev->mc.real_vram_size > rdev->mc.aper_size)
		1740	rdev->mc.real_vram_size = rdev->mc.aper_size;
1117	serge	1741	}
		1742
1179	serge	1743	void r100_vga_set_state(struct radeon_device *rdev, bool state)
		1744	{
		1745	uint32_t temp;
		1746
		1747	temp = RREG32(RADEON_CONFIG_CNTL);
		1748	if (state == false) {
		1749	temp &= ~(1<<8);
		1750	temp \|= (1<<9);
		1751	} else {
		1752	temp &= ~(1<<9);
		1753	}
		1754	WREG32(RADEON_CONFIG_CNTL, temp);
		1755	}
		1756
		1757	void r100_vram_info(struct radeon_device *rdev)
		1758	{
		1759	r100_vram_get_type(rdev);
		1760
		1761	r100_vram_init_sizes(rdev);
		1762	}
		1763
		1764
1117	serge	1765	/*
		1766	* Indirect registers accessor
		1767	*/
		1768	void r100_pll_errata_after_index(struct radeon_device *rdev)
		1769	{
		1770	if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
		1771	return;
		1772	}
		1773	(void)RREG32(RADEON_CLOCK_CNTL_DATA);
		1774	(void)RREG32(RADEON_CRTC_GEN_CNTL);
		1775	}
		1776
		1777	static void r100_pll_errata_after_data(struct radeon_device *rdev)
		1778	{
		1779	/* This workarounds is necessary on RV100, RS100 and RS200 chips
		1780	* or the chip could hang on a subsequent access
		1781	*/
		1782	if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
		1783	udelay(5000);
		1784	}
		1785
		1786	/* This function is required to workaround a hardware bug in some (all?)
		1787	* revisions of the R300. This workaround should be called after every
		1788	* CLOCK_CNTL_INDEX register access. If not, register reads afterward
		1789	* may not be correct.
		1790	*/
		1791	if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
		1792	uint32_t save, tmp;
		1793
		1794	save = RREG32(RADEON_CLOCK_CNTL_INDEX);
		1795	tmp = save & ~(0x3f \| RADEON_PLL_WR_EN);
		1796	WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
		1797	tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
		1798	WREG32(RADEON_CLOCK_CNTL_INDEX, save);
		1799	}
		1800	}
		1801
		1802	uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
		1803	{
		1804	uint32_t data;
		1805
		1806	WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
		1807	r100_pll_errata_after_index(rdev);
		1808	data = RREG32(RADEON_CLOCK_CNTL_DATA);
		1809	r100_pll_errata_after_data(rdev);
		1810	return data;
		1811	}
		1812
		1813	void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		1814	{
		1815	WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) \| RADEON_PLL_WR_EN));
		1816	r100_pll_errata_after_index(rdev);
		1817	WREG32(RADEON_CLOCK_CNTL_DATA, v);
		1818	r100_pll_errata_after_data(rdev);
		1819	}
		1820
1221	serge	1821	void r100_set_safe_registers(struct radeon_device *rdev)
1117	serge	1822	{
1179	serge	1823	if (ASIC_IS_RN50(rdev)) {
		1824	rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
		1825	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
		1826	} else if (rdev->family < CHIP_R200) {
		1827	rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
		1828	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
		1829	} else {
1221	serge	1830	r200_set_safe_registers(rdev);
1117	serge	1831	}
		1832	}
		1833
1129	serge	1834	/*
		1835	* Debugfs info
		1836	*/
		1837	#if defined(CONFIG_DEBUG_FS)
		1838	static int r100_debugfs_rbbm_info(struct seq_file m, void data)
		1839	{
		1840	struct drm_info_node node = (struct drm_info_node ) m->private;
		1841	struct drm_device *dev = node->minor->dev;
		1842	struct radeon_device *rdev = dev->dev_private;
		1843	uint32_t reg, value;
		1844	unsigned i;
		1845
		1846	seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
		1847	seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
		1848	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		1849	for (i = 0; i < 64; i++) {
		1850	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i \| 0x100);
		1851	reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
		1852	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
		1853	value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
		1854	seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
		1855	}
		1856	return 0;
		1857	}
		1858
		1859	static int r100_debugfs_cp_ring_info(struct seq_file m, void data)
		1860	{
		1861	struct drm_info_node node = (struct drm_info_node ) m->private;
		1862	struct drm_device *dev = node->minor->dev;
		1863	struct radeon_device *rdev = dev->dev_private;
		1864	uint32_t rdp, wdp;
		1865	unsigned count, i, j;
		1866
		1867	radeon_ring_free_size(rdev);
		1868	rdp = RREG32(RADEON_CP_RB_RPTR);
		1869	wdp = RREG32(RADEON_CP_RB_WPTR);
		1870	count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
		1871	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		1872	seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
		1873	seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
		1874	seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
		1875	seq_printf(m, "%u dwords in ring\n", count);
		1876	for (j = 0; j <= count; j++) {
		1877	i = (rdp + j) & rdev->cp.ptr_mask;
		1878	seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
		1879	}
		1880	return 0;
		1881	}
		1882
		1883
		1884	static int r100_debugfs_cp_csq_fifo(struct seq_file m, void data)
		1885	{
		1886	struct drm_info_node node = (struct drm_info_node ) m->private;
		1887	struct drm_device *dev = node->minor->dev;
		1888	struct radeon_device *rdev = dev->dev_private;
		1889	uint32_t csq_stat, csq2_stat, tmp;
		1890	unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
		1891	unsigned i;
		1892
		1893	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		1894	seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
		1895	csq_stat = RREG32(RADEON_CP_CSQ_STAT);
		1896	csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
		1897	r_rptr = (csq_stat >> 0) & 0x3ff;
		1898	r_wptr = (csq_stat >> 10) & 0x3ff;
		1899	ib1_rptr = (csq_stat >> 20) & 0x3ff;
		1900	ib1_wptr = (csq2_stat >> 0) & 0x3ff;
		1901	ib2_rptr = (csq2_stat >> 10) & 0x3ff;
		1902	ib2_wptr = (csq2_stat >> 20) & 0x3ff;
		1903	seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
		1904	seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
		1905	seq_printf(m, "Ring rptr %u\n", r_rptr);
		1906	seq_printf(m, "Ring wptr %u\n", r_wptr);
		1907	seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
		1908	seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
		1909	seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
		1910	seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
		1911	/* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
		1912	* 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
		1913	seq_printf(m, "Ring fifo:\n");
		1914	for (i = 0; i < 256; i++) {
		1915	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		1916	tmp = RREG32(RADEON_CP_CSQ_DATA);
		1917	seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
		1918	}
		1919	seq_printf(m, "Indirect1 fifo:\n");
		1920	for (i = 256; i <= 512; i++) {
		1921	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		1922	tmp = RREG32(RADEON_CP_CSQ_DATA);
		1923	seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
		1924	}
		1925	seq_printf(m, "Indirect2 fifo:\n");
		1926	for (i = 640; i < ib1_wptr; i++) {
		1927	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		1928	tmp = RREG32(RADEON_CP_CSQ_DATA);
		1929	seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
		1930	}
		1931	return 0;
		1932	}
		1933
		1934	static int r100_debugfs_mc_info(struct seq_file m, void data)
		1935	{
		1936	struct drm_info_node node = (struct drm_info_node ) m->private;
		1937	struct drm_device *dev = node->minor->dev;
		1938	struct radeon_device *rdev = dev->dev_private;
		1939	uint32_t tmp;
		1940
		1941	tmp = RREG32(RADEON_CONFIG_MEMSIZE);
		1942	seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
		1943	tmp = RREG32(RADEON_MC_FB_LOCATION);
		1944	seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
		1945	tmp = RREG32(RADEON_BUS_CNTL);
		1946	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
		1947	tmp = RREG32(RADEON_MC_AGP_LOCATION);
		1948	seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
		1949	tmp = RREG32(RADEON_AGP_BASE);
		1950	seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
		1951	tmp = RREG32(RADEON_HOST_PATH_CNTL);
		1952	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
		1953	tmp = RREG32(0x01D0);
		1954	seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
		1955	tmp = RREG32(RADEON_AIC_LO_ADDR);
		1956	seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
		1957	tmp = RREG32(RADEON_AIC_HI_ADDR);
		1958	seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
		1959	tmp = RREG32(0x01E4);
		1960	seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
		1961	return 0;
		1962	}
		1963
		1964	static struct drm_info_list r100_debugfs_rbbm_list[] = {
		1965	{"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
		1966	};
		1967
		1968	static struct drm_info_list r100_debugfs_cp_list[] = {
		1969	{"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
		1970	{"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
		1971	};
		1972
		1973	static struct drm_info_list r100_debugfs_mc_info_list[] = {
		1974	{"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
		1975	};
		1976	#endif
		1977
		1978	int r100_debugfs_rbbm_init(struct radeon_device *rdev)
		1979	{
		1980	#if defined(CONFIG_DEBUG_FS)
		1981	return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
		1982	#else
		1983	return 0;
		1984	#endif
		1985	}
		1986
		1987	int r100_debugfs_cp_init(struct radeon_device *rdev)
		1988	{
		1989	#if defined(CONFIG_DEBUG_FS)
		1990	return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
		1991	#else
		1992	return 0;
		1993	#endif
		1994	}
		1995
		1996	int r100_debugfs_mc_info_init(struct radeon_device *rdev)
		1997	{
		1998	#if defined(CONFIG_DEBUG_FS)
		1999	return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
		2000	#else
		2001	return 0;
		2002	#endif
		2003	}
1179	serge	2004
		2005	int r100_set_surface_reg(struct radeon_device *rdev, int reg,
		2006	uint32_t tiling_flags, uint32_t pitch,
		2007	uint32_t offset, uint32_t obj_size)
		2008	{
		2009	int surf_index = reg * 16;
		2010	int flags = 0;
		2011
		2012	/* r100/r200 divide by 16 */
		2013	if (rdev->family < CHIP_R300)
		2014	flags = pitch / 16;
		2015	else
		2016	flags = pitch / 8;
		2017
		2018	if (rdev->family <= CHIP_RS200) {
		2019	if ((tiling_flags & (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		2020	== (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		2021	flags \|= RADEON_SURF_TILE_COLOR_BOTH;
		2022	if (tiling_flags & RADEON_TILING_MACRO)
		2023	flags \|= RADEON_SURF_TILE_COLOR_MACRO;
		2024	} else if (rdev->family <= CHIP_RV280) {
		2025	if (tiling_flags & (RADEON_TILING_MACRO))
		2026	flags \|= R200_SURF_TILE_COLOR_MACRO;
		2027	if (tiling_flags & RADEON_TILING_MICRO)
		2028	flags \|= R200_SURF_TILE_COLOR_MICRO;
		2029	} else {
		2030	if (tiling_flags & RADEON_TILING_MACRO)
		2031	flags \|= R300_SURF_TILE_MACRO;
		2032	if (tiling_flags & RADEON_TILING_MICRO)
		2033	flags \|= R300_SURF_TILE_MICRO;
		2034	}
		2035
		2036	if (tiling_flags & RADEON_TILING_SWAP_16BIT)
		2037	flags \|= RADEON_SURF_AP0_SWP_16BPP \| RADEON_SURF_AP1_SWP_16BPP;
		2038	if (tiling_flags & RADEON_TILING_SWAP_32BIT)
		2039	flags \|= RADEON_SURF_AP0_SWP_32BPP \| RADEON_SURF_AP1_SWP_32BPP;
		2040
		2041	DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
		2042	WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
		2043	WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
		2044	WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
		2045	return 0;
		2046	}
		2047
		2048	void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
		2049	{
		2050	int surf_index = reg * 16;
		2051	WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
		2052	}
		2053
		2054	void r100_bandwidth_update(struct radeon_device *rdev)
		2055	{
		2056	fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
		2057	fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
		2058	fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
		2059	uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
		2060	fixed20_12 memtcas_ff[8] = {
		2061	fixed_init(1),
		2062	fixed_init(2),
		2063	fixed_init(3),
		2064	fixed_init(0),
		2065	fixed_init_half(1),
		2066	fixed_init_half(2),
		2067	fixed_init(0),
		2068	};
		2069	fixed20_12 memtcas_rs480_ff[8] = {
		2070	fixed_init(0),
		2071	fixed_init(1),
		2072	fixed_init(2),
		2073	fixed_init(3),
		2074	fixed_init(0),
		2075	fixed_init_half(1),
		2076	fixed_init_half(2),
		2077	fixed_init_half(3),
		2078	};
		2079	fixed20_12 memtcas2_ff[8] = {
		2080	fixed_init(0),
		2081	fixed_init(1),
		2082	fixed_init(2),
		2083	fixed_init(3),
		2084	fixed_init(4),
		2085	fixed_init(5),
		2086	fixed_init(6),
		2087	fixed_init(7),
		2088	};
		2089	fixed20_12 memtrbs[8] = {
		2090	fixed_init(1),
		2091	fixed_init_half(1),
		2092	fixed_init(2),
		2093	fixed_init_half(2),
		2094	fixed_init(3),
		2095	fixed_init_half(3),
		2096	fixed_init(4),
		2097	fixed_init_half(4)
		2098	};
		2099	fixed20_12 memtrbs_r4xx[8] = {
		2100	fixed_init(4),
		2101	fixed_init(5),
		2102	fixed_init(6),
		2103	fixed_init(7),
		2104	fixed_init(8),
		2105	fixed_init(9),
		2106	fixed_init(10),
		2107	fixed_init(11)
		2108	};
		2109	fixed20_12 min_mem_eff;
		2110	fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
		2111	fixed20_12 cur_latency_mclk, cur_latency_sclk;
		2112	fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
		2113	disp_drain_rate2, read_return_rate;
		2114	fixed20_12 time_disp1_drop_priority;
		2115	int c;
		2116	int cur_size = 16; /* in octawords */
		2117	int critical_point = 0, critical_point2;
		2118	/* uint32_t read_return_rate, time_disp1_drop_priority; */
		2119	int stop_req, max_stop_req;
		2120	struct drm_display_mode *mode1 = NULL;
		2121	struct drm_display_mode *mode2 = NULL;
		2122	uint32_t pixel_bytes1 = 0;
		2123	uint32_t pixel_bytes2 = 0;
		2124
		2125	if (rdev->mode_info.crtcs[0]->base.enabled) {
		2126	mode1 = &rdev->mode_info.crtcs[0]->base.mode;
		2127	pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
		2128	}
1221	serge	2129	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
1179	serge	2130	if (rdev->mode_info.crtcs[1]->base.enabled) {
		2131	mode2 = &rdev->mode_info.crtcs[1]->base.mode;
		2132	pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
		2133	}
1221	serge	2134	}
1179	serge	2135
		2136	min_mem_eff.full = rfixed_const_8(0);
		2137	/* get modes */
		2138	if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
		2139	uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
		2140	mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
		2141	mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
		2142	/* check crtc enables */
		2143	if (mode2)
		2144	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
		2145	if (mode1)
		2146	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
		2147	WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
		2148	}
		2149
		2150	/*
		2151	* determine is there is enough bw for current mode
		2152	*/
		2153	mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
		2154	temp_ff.full = rfixed_const(100);
		2155	mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
		2156	sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
		2157	sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
		2158
		2159	temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
		2160	temp_ff.full = rfixed_const(temp);
		2161	mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
		2162
		2163	pix_clk.full = 0;
		2164	pix_clk2.full = 0;
		2165	peak_disp_bw.full = 0;
		2166	if (mode1) {
		2167	temp_ff.full = rfixed_const(1000);
		2168	pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
		2169	pix_clk.full = rfixed_div(pix_clk, temp_ff);
		2170	temp_ff.full = rfixed_const(pixel_bytes1);
		2171	peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
		2172	}
		2173	if (mode2) {
		2174	temp_ff.full = rfixed_const(1000);
		2175	pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
		2176	pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
		2177	temp_ff.full = rfixed_const(pixel_bytes2);
		2178	peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
		2179	}
		2180
		2181	mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
		2182	if (peak_disp_bw.full >= mem_bw.full) {
		2183	DRM_ERROR("You may not have enough display bandwidth for current mode\n"
		2184	"If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
		2185	}
		2186
		2187	/* Get values from the EXT_MEM_CNTL register...converting its contents. */
		2188	temp = RREG32(RADEON_MEM_TIMING_CNTL);
		2189	if ((rdev->family == CHIP_RV100) \|\| (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
		2190	mem_trcd = ((temp >> 2) & 0x3) + 1;
		2191	mem_trp = ((temp & 0x3)) + 1;
		2192	mem_tras = ((temp & 0x70) >> 4) + 1;
		2193	} else if (rdev->family == CHIP_R300 \|\|
		2194	rdev->family == CHIP_R350) { /* r300, r350 */
		2195	mem_trcd = (temp & 0x7) + 1;
		2196	mem_trp = ((temp >> 8) & 0x7) + 1;
		2197	mem_tras = ((temp >> 11) & 0xf) + 4;
		2198	} else if (rdev->family == CHIP_RV350 \|\|
		2199	rdev->family <= CHIP_RV380) {
		2200	/* rv3x0 */
		2201	mem_trcd = (temp & 0x7) + 3;
		2202	mem_trp = ((temp >> 8) & 0x7) + 3;
		2203	mem_tras = ((temp >> 11) & 0xf) + 6;
		2204	} else if (rdev->family == CHIP_R420 \|\|
		2205	rdev->family == CHIP_R423 \|\|
		2206	rdev->family == CHIP_RV410) {
		2207	/* r4xx */
		2208	mem_trcd = (temp & 0xf) + 3;
		2209	if (mem_trcd > 15)
		2210	mem_trcd = 15;
		2211	mem_trp = ((temp >> 8) & 0xf) + 3;
		2212	if (mem_trp > 15)
		2213	mem_trp = 15;
		2214	mem_tras = ((temp >> 12) & 0x1f) + 6;
		2215	if (mem_tras > 31)
		2216	mem_tras = 31;
		2217	} else { /* RV200, R200 */
		2218	mem_trcd = (temp & 0x7) + 1;
		2219	mem_trp = ((temp >> 8) & 0x7) + 1;
		2220	mem_tras = ((temp >> 12) & 0xf) + 4;
		2221	}
		2222	/* convert to FF */
		2223	trcd_ff.full = rfixed_const(mem_trcd);
		2224	trp_ff.full = rfixed_const(mem_trp);
		2225	tras_ff.full = rfixed_const(mem_tras);
		2226
		2227	/* Get values from the MEM_SDRAM_MODE_REG register...converting its */
		2228	temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		2229	data = (temp & (7 << 20)) >> 20;
		2230	if ((rdev->family == CHIP_RV100) \|\| rdev->flags & RADEON_IS_IGP) {
		2231	if (rdev->family == CHIP_RS480) /* don't think rs400 */
		2232	tcas_ff = memtcas_rs480_ff[data];
		2233	else
		2234	tcas_ff = memtcas_ff[data];
		2235	} else
		2236	tcas_ff = memtcas2_ff[data];
		2237
		2238	if (rdev->family == CHIP_RS400 \|\|
		2239	rdev->family == CHIP_RS480) {
		2240	/* extra cas latency stored in bits 23-25 0-4 clocks */
		2241	data = (temp >> 23) & 0x7;
		2242	if (data < 5)
		2243	tcas_ff.full += rfixed_const(data);
		2244	}
		2245
		2246	if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
		2247	/* on the R300, Tcas is included in Trbs.
		2248	*/
		2249	temp = RREG32(RADEON_MEM_CNTL);
		2250	data = (R300_MEM_NUM_CHANNELS_MASK & temp);
		2251	if (data == 1) {
		2252	if (R300_MEM_USE_CD_CH_ONLY & temp) {
		2253	temp = RREG32(R300_MC_IND_INDEX);
		2254	temp &= ~R300_MC_IND_ADDR_MASK;
		2255	temp \|= R300_MC_READ_CNTL_CD_mcind;
		2256	WREG32(R300_MC_IND_INDEX, temp);
		2257	temp = RREG32(R300_MC_IND_DATA);
		2258	data = (R300_MEM_RBS_POSITION_C_MASK & temp);
		2259	} else {
		2260	temp = RREG32(R300_MC_READ_CNTL_AB);
		2261	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		2262	}
		2263	} else {
		2264	temp = RREG32(R300_MC_READ_CNTL_AB);
		2265	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		2266	}
		2267	if (rdev->family == CHIP_RV410 \|\|
		2268	rdev->family == CHIP_R420 \|\|
		2269	rdev->family == CHIP_R423)
		2270	trbs_ff = memtrbs_r4xx[data];
		2271	else
		2272	trbs_ff = memtrbs[data];
		2273	tcas_ff.full += trbs_ff.full;
		2274	}
		2275
		2276	sclk_eff_ff.full = sclk_ff.full;
		2277
		2278	if (rdev->flags & RADEON_IS_AGP) {
		2279	fixed20_12 agpmode_ff;
		2280	agpmode_ff.full = rfixed_const(radeon_agpmode);
		2281	temp_ff.full = rfixed_const_666(16);
		2282	sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
		2283	}
		2284	/* TODO PCIE lanes may affect this - agpmode == 16?? */
		2285
		2286	if (ASIC_IS_R300(rdev)) {
		2287	sclk_delay_ff.full = rfixed_const(250);
		2288	} else {
		2289	if ((rdev->family == CHIP_RV100) \|\|
		2290	rdev->flags & RADEON_IS_IGP) {
		2291	if (rdev->mc.vram_is_ddr)
		2292	sclk_delay_ff.full = rfixed_const(41);
		2293	else
		2294	sclk_delay_ff.full = rfixed_const(33);
		2295	} else {
		2296	if (rdev->mc.vram_width == 128)
		2297	sclk_delay_ff.full = rfixed_const(57);
		2298	else
		2299	sclk_delay_ff.full = rfixed_const(41);
		2300	}
		2301	}
		2302
		2303	mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
		2304
		2305	if (rdev->mc.vram_is_ddr) {
		2306	if (rdev->mc.vram_width == 32) {
		2307	k1.full = rfixed_const(40);
		2308	c = 3;
		2309	} else {
		2310	k1.full = rfixed_const(20);
		2311	c = 1;
		2312	}
		2313	} else {
		2314	k1.full = rfixed_const(40);
		2315	c = 3;
		2316	}
		2317
		2318	temp_ff.full = rfixed_const(2);
		2319	mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
		2320	temp_ff.full = rfixed_const(c);
		2321	mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
		2322	temp_ff.full = rfixed_const(4);
		2323	mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
		2324	mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
		2325	mc_latency_mclk.full += k1.full;
		2326
		2327	mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
		2328	mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
		2329
		2330	/*
		2331	HW cursor time assuming worst case of full size colour cursor.
		2332	*/
		2333	temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
		2334	temp_ff.full += trcd_ff.full;
		2335	if (temp_ff.full < tras_ff.full)
		2336	temp_ff.full = tras_ff.full;
		2337	cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
		2338
		2339	temp_ff.full = rfixed_const(cur_size);
		2340	cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
		2341	/*
		2342	Find the total latency for the display data.
		2343	*/
		2344	disp_latency_overhead.full = rfixed_const(80);
		2345	disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
		2346	mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
		2347	mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
		2348
		2349	if (mc_latency_mclk.full > mc_latency_sclk.full)
		2350	disp_latency.full = mc_latency_mclk.full;
		2351	else
		2352	disp_latency.full = mc_latency_sclk.full;
		2353
		2354	/* setup Max GRPH_STOP_REQ default value */
		2355	if (ASIC_IS_RV100(rdev))
		2356	max_stop_req = 0x5c;
		2357	else
		2358	max_stop_req = 0x7c;
		2359
		2360	if (mode1) {
		2361	/* CRTC1
		2362	Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
		2363	GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
		2364	*/
		2365	stop_req = mode1->hdisplay * pixel_bytes1 / 16;
		2366
		2367	if (stop_req > max_stop_req)
		2368	stop_req = max_stop_req;
		2369
		2370	/*
		2371	Find the drain rate of the display buffer.
		2372	*/
		2373	temp_ff.full = rfixed_const((16/pixel_bytes1));
		2374	disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
		2375
		2376	/*
		2377	Find the critical point of the display buffer.
		2378	*/
		2379	crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
		2380	crit_point_ff.full += rfixed_const_half(0);
		2381
		2382	critical_point = rfixed_trunc(crit_point_ff);
		2383
		2384	if (rdev->disp_priority == 2) {
		2385	critical_point = 0;
		2386	}
		2387
		2388	/*
		2389	The critical point should never be above max_stop_req-4. Setting
		2390	GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
		2391	*/
		2392	if (max_stop_req - critical_point < 4)
		2393	critical_point = 0;
		2394
		2395	if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
		2396	/* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
		2397	critical_point = 0x10;
		2398	}
		2399
		2400	temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
		2401	temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
		2402	temp \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		2403	temp &= ~(RADEON_GRPH_START_REQ_MASK);
		2404	if ((rdev->family == CHIP_R350) &&
		2405	(stop_req > 0x15)) {
		2406	stop_req -= 0x10;
		2407	}
		2408	temp \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		2409	temp \|= RADEON_GRPH_BUFFER_SIZE;
		2410	temp &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		2411	RADEON_GRPH_CRITICAL_AT_SOF \|
		2412	RADEON_GRPH_STOP_CNTL);
		2413	/*
		2414	Write the result into the register.
		2415	*/
		2416	WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		2417	(critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		2418
		2419	#if 0
		2420	if ((rdev->family == CHIP_RS400) \|\|
		2421	(rdev->family == CHIP_RS480)) {
		2422	/* attempt to program RS400 disp regs correctly ??? */
		2423	temp = RREG32(RS400_DISP1_REG_CNTL);
		2424	temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK \|
		2425	RS400_DISP1_STOP_REQ_LEVEL_MASK);
		2426	WREG32(RS400_DISP1_REQ_CNTL1, (temp \|
		2427	(critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		2428	(critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		2429	temp = RREG32(RS400_DMIF_MEM_CNTL1);
		2430	temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK \|
		2431	RS400_DISP1_CRITICAL_POINT_STOP_MASK);
		2432	WREG32(RS400_DMIF_MEM_CNTL1, (temp \|
		2433	(critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) \|
		2434	(critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
		2435	}
		2436	#endif
		2437
		2438	DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
		2439	/* (unsigned int)info->SavedReg->grph_buffer_cntl, */
		2440	(unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
		2441	}
		2442
		2443	if (mode2) {
		2444	u32 grph2_cntl;
		2445	stop_req = mode2->hdisplay * pixel_bytes2 / 16;
		2446
		2447	if (stop_req > max_stop_req)
		2448	stop_req = max_stop_req;
		2449
		2450	/*
		2451	Find the drain rate of the display buffer.
		2452	*/
		2453	temp_ff.full = rfixed_const((16/pixel_bytes2));
		2454	disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
		2455
		2456	grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
		2457	grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
		2458	grph2_cntl \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		2459	grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
		2460	if ((rdev->family == CHIP_R350) &&
		2461	(stop_req > 0x15)) {
		2462	stop_req -= 0x10;
		2463	}
		2464	grph2_cntl \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		2465	grph2_cntl \|= RADEON_GRPH_BUFFER_SIZE;
		2466	grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		2467	RADEON_GRPH_CRITICAL_AT_SOF \|
		2468	RADEON_GRPH_STOP_CNTL);
		2469
		2470	if ((rdev->family == CHIP_RS100) \|\|
		2471	(rdev->family == CHIP_RS200))
		2472	critical_point2 = 0;
		2473	else {
		2474	temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
		2475	temp_ff.full = rfixed_const(temp);
		2476	temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
		2477	if (sclk_ff.full < temp_ff.full)
		2478	temp_ff.full = sclk_ff.full;
		2479
		2480	read_return_rate.full = temp_ff.full;
		2481
		2482	if (mode1) {
		2483	temp_ff.full = read_return_rate.full - disp_drain_rate.full;
		2484	time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
		2485	} else {
		2486	time_disp1_drop_priority.full = 0;
		2487	}
		2488	crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
		2489	crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
		2490	crit_point_ff.full += rfixed_const_half(0);
		2491
		2492	critical_point2 = rfixed_trunc(crit_point_ff);
		2493
		2494	if (rdev->disp_priority == 2) {
		2495	critical_point2 = 0;
		2496	}
		2497
		2498	if (max_stop_req - critical_point2 < 4)
		2499	critical_point2 = 0;
		2500
		2501	}
		2502
		2503	if (critical_point2 == 0 && rdev->family == CHIP_R300) {
		2504	/* some R300 cards have problem with this set to 0 */
		2505	critical_point2 = 0x10;
		2506	}
		2507
		2508	WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		2509	(critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		2510
		2511	if ((rdev->family == CHIP_RS400) \|\|
		2512	(rdev->family == CHIP_RS480)) {
		2513	#if 0
		2514	/* attempt to program RS400 disp2 regs correctly ??? */
		2515	temp = RREG32(RS400_DISP2_REQ_CNTL1);
		2516	temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK \|
		2517	RS400_DISP2_STOP_REQ_LEVEL_MASK);
		2518	WREG32(RS400_DISP2_REQ_CNTL1, (temp \|
		2519	(critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		2520	(critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		2521	temp = RREG32(RS400_DISP2_REQ_CNTL2);
		2522	temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK \|
		2523	RS400_DISP2_CRITICAL_POINT_STOP_MASK);
		2524	WREG32(RS400_DISP2_REQ_CNTL2, (temp \|
		2525	(critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) \|
		2526	(critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
		2527	#endif
		2528	WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
		2529	WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
		2530	WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
		2531	WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
		2532	}
		2533
		2534	DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
		2535	(unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
		2536	}
		2537	}
		2538
		2539
		2540
		2541
		2542	void r100_mc_stop(struct radeon_device rdev, struct r100_mc_save save)
		2543	{
		2544	/* Shutdown CP we shouldn't need to do that but better be safe than
		2545	* sorry
		2546	*/
		2547	rdev->cp.ready = false;
		2548	WREG32(R_000740_CP_CSQ_CNTL, 0);
		2549
		2550	/* Save few CRTC registers */
1221	serge	2551	save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
1179	serge	2552	save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
		2553	save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
		2554	save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
		2555	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		2556	save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
		2557	save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
		2558	}
		2559
		2560	/* Disable VGA aperture access */
1221	serge	2561	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
1179	serge	2562	/* Disable cursor, overlay, crtc */
		2563	WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET \| S_000260_CUR_LOCK(1));
		2564	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL \|
		2565	S_000054_CRTC_DISPLAY_DIS(1));
		2566	WREG32(R_000050_CRTC_GEN_CNTL,
		2567	(C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) \|
		2568	S_000050_CRTC_DISP_REQ_EN_B(1));
		2569	WREG32(R_000420_OV0_SCALE_CNTL,
		2570	C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
		2571	WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
		2572	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		2573	WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET \|
		2574	S_000360_CUR2_LOCK(1));
		2575	WREG32(R_0003F8_CRTC2_GEN_CNTL,
		2576	(C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) \|
		2577	S_0003F8_CRTC2_DISPLAY_DIS(1) \|
		2578	S_0003F8_CRTC2_DISP_REQ_EN_B(1));
		2579	WREG32(R_000360_CUR2_OFFSET,
		2580	C_000360_CUR2_LOCK & save->CUR2_OFFSET);
		2581	}
		2582	}
		2583
		2584	void r100_mc_resume(struct radeon_device rdev, struct r100_mc_save save)
		2585	{
		2586	/* Update base address for crtc */
		2587	WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
		2588	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		2589	WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
		2590	rdev->mc.vram_location);
		2591	}
		2592	/* Restore CRTC registers */
1221	serge	2593	WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
1179	serge	2594	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
		2595	WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
		2596	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		2597	WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
		2598	}
		2599	}
		2600
1221	serge	2601	void r100_vga_render_disable(struct radeon_device *rdev)
		2602	{
		2603	u32 tmp;
		2604
		2605	tmp = RREG8(R_0003C2_GENMO_WT);
		2606	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
		2607	}
		2608
		2609	static void r100_debugfs(struct radeon_device *rdev)
		2610	{
		2611	int r;
		2612
		2613	r = r100_debugfs_mc_info_init(rdev);
		2614	if (r)
		2615	dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		2616	}
		2617
		2618
1179	serge	2619	int drm_order(unsigned long size)
		2620	{
		2621	int order;
		2622	unsigned long tmp;
		2623
		2624	for (order = 0, tmp = size >> 1; tmp; tmp >>= 1, order++) ;
		2625
		2626	if (size & (size - 1))
		2627	++order;
		2628
		2629	return order;
		2630	}
		2631
1221	serge	2632	static void r100_mc_program(struct radeon_device *rdev)
		2633	{
		2634	struct r100_mc_save save;
		2635
		2636	/* Stops all mc clients */
		2637	r100_mc_stop(rdev, &save);
		2638	if (rdev->flags & RADEON_IS_AGP) {
		2639	WREG32(R_00014C_MC_AGP_LOCATION,
		2640	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		2641	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		2642	WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		2643	if (rdev->family > CHIP_RV200)
		2644	WREG32(R_00015C_AGP_BASE_2,
		2645	upper_32_bits(rdev->mc.agp_base) & 0xff);
		2646	} else {
		2647	WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		2648	WREG32(R_000170_AGP_BASE, 0);
		2649	if (rdev->family > CHIP_RV200)
		2650	WREG32(R_00015C_AGP_BASE_2, 0);
		2651	}
		2652	/* Wait for mc idle */
		2653	if (r100_mc_wait_for_idle(rdev))
		2654	dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
		2655	/* Program MC, should be a 32bits limited address space */
		2656	WREG32(R_000148_MC_FB_LOCATION,
		2657	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		2658	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		2659	r100_mc_resume(rdev, &save);
		2660	}
		2661
		2662	void r100_clock_startup(struct radeon_device *rdev)
		2663	{
		2664	u32 tmp;
		2665
		2666	if (radeon_dynclks != -1 && radeon_dynclks)
		2667	radeon_legacy_set_clock_gating(rdev, 1);
		2668	/* We need to force on some of the block */
		2669	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
		2670	tmp \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		2671	if ((rdev->family == CHIP_RV250) \|\| (rdev->family == CHIP_RV280))
		2672	tmp \|= S_00000D_FORCE_DISP1(1) \| S_00000D_FORCE_DISP2(1);
		2673	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
		2674	}
		2675
		2676	static int r100_startup(struct radeon_device *rdev)
		2677	{
		2678	int r;
		2679
		2680	r100_mc_program(rdev);
		2681	/* Resume clock */
		2682	r100_clock_startup(rdev);
		2683	/* Initialize GPU configuration (# pipes, ...) */
		2684	r100_gpu_init(rdev);
		2685	/* Initialize GART (initialize after TTM so we can allocate
		2686	* memory through TTM but finalize after TTM) */
		2687	if (rdev->flags & RADEON_IS_PCI) {
		2688	r = r100_pci_gart_enable(rdev);
		2689	if (r)
		2690	return r;
		2691	}
		2692	/* Enable IRQ */
		2693	// rdev->irq.sw_int = true;
		2694	// r100_irq_set(rdev);
		2695	/* 1M ring buffer */
		2696	// r = r100_cp_init(rdev, 1024 * 1024);
		2697	// if (r) {
		2698	// dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
		2699	// return r;
		2700	// }
		2701	// r = r100_wb_init(rdev);
		2702	// if (r)
		2703	// dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
		2704	// r = r100_ib_init(rdev);
		2705	// if (r) {
		2706	// dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
		2707	// return r;
		2708	// }
		2709	return 0;
		2710	}
		2711
		2712
		2713	int r100_mc_init(struct radeon_device *rdev)
		2714	{
		2715	int r;
		2716	u32 tmp;
		2717
		2718	/* Setup GPU memory space */
		2719	rdev->mc.vram_location = 0xFFFFFFFFUL;
		2720	rdev->mc.gtt_location = 0xFFFFFFFFUL;
		2721	if (rdev->flags & RADEON_IS_IGP) {
		2722	tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
		2723	rdev->mc.vram_location = tmp << 16;
		2724	}
		2725	if (rdev->flags & RADEON_IS_AGP) {
		2726	r = radeon_agp_init(rdev);
		2727	if (r) {
		2728	printk(KERN_WARNING "[drm] Disabling AGP\n");
		2729	rdev->flags &= ~RADEON_IS_AGP;
		2730	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		2731	} else {
		2732	rdev->mc.gtt_location = rdev->mc.agp_base;
		2733	}
		2734	}
		2735	r = radeon_mc_setup(rdev);
		2736	if (r)
		2737	return r;
		2738	return 0;
		2739	}
		2740
		2741	int r100_init(struct radeon_device *rdev)
		2742	{
		2743	int r;
		2744
		2745	/* Register debugfs file specific to this group of asics */
		2746	r100_debugfs(rdev);
		2747	/* Disable VGA */
		2748	r100_vga_render_disable(rdev);
		2749	/* Initialize scratch registers */
		2750	radeon_scratch_init(rdev);
		2751	/* Initialize surface registers */
		2752	radeon_surface_init(rdev);
		2753	/* TODO: disable VGA need to use VGA request */
		2754	/* BIOS*/
		2755	if (!radeon_get_bios(rdev)) {
		2756	if (ASIC_IS_AVIVO(rdev))
		2757	return -EINVAL;
		2758	}
		2759	if (rdev->is_atom_bios) {
		2760	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		2761	return -EINVAL;
		2762	} else {
		2763	r = radeon_combios_init(rdev);
		2764	if (r)
		2765	return r;
		2766	}
		2767	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
		2768	if (radeon_gpu_reset(rdev)) {
		2769	dev_warn(rdev->dev,
		2770	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		2771	RREG32(R_000E40_RBBM_STATUS),
		2772	RREG32(R_0007C0_CP_STAT));
		2773	}
		2774	/* check if cards are posted or not */
		2775	if (!radeon_card_posted(rdev) && rdev->bios) {
		2776	DRM_INFO("GPU not posted. posting now...\n");
		2777	radeon_combios_asic_init(rdev->ddev);
		2778	}
		2779	/* Set asic errata */
		2780	r100_errata(rdev);
		2781	/* Initialize clocks */
		2782	radeon_get_clock_info(rdev->ddev);
		2783	/* Get vram informations */
		2784	r100_vram_info(rdev);
		2785	/* Initialize memory controller (also test AGP) */
		2786	r = r100_mc_init(rdev);
1246	serge	2787	dbgprintf("mc vram location %x\n", rdev->mc.vram_location);
1221	serge	2788	if (r)
		2789	return r;
		2790	/* Fence driver */
		2791	// r = radeon_fence_driver_init(rdev);
		2792	// if (r)
		2793	// return r;
		2794	// r = radeon_irq_kms_init(rdev);
		2795	// if (r)
		2796	// return r;
		2797	/* Memory manager */
		2798	r = radeon_object_init(rdev);
		2799	if (r)
		2800	return r;
		2801	if (rdev->flags & RADEON_IS_PCI) {
		2802	r = r100_pci_gart_init(rdev);
		2803	if (r)
		2804	return r;
		2805	}
		2806	r100_set_safe_registers(rdev);
		2807	rdev->accel_working = true;
		2808	r = r100_startup(rdev);
		2809	if (r) {
		2810	/* Somethings want wront with the accel init stop accel */
		2811	dev_err(rdev->dev, "Disabling GPU acceleration\n");
		2812	// r100_suspend(rdev);
		2813	// r100_cp_fini(rdev);
		2814	// r100_wb_fini(rdev);
		2815	// r100_ib_fini(rdev);
		2816	if (rdev->flags & RADEON_IS_PCI)
		2817	r100_pci_gart_fini(rdev);
		2818	// radeon_irq_kms_fini(rdev);
		2819	rdev->accel_working = false;
		2820	}
		2821	return 0;
		2822	}

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(root)/drivers/video/drm/radeon/r100.c – Rev 1246