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/*

 * Copyright 2008 Advanced Micro Devices, Inc.

 * Copyright 2008 Red Hat Inc.

 * Copyright 2009 Jerome Glisse.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Dave Airlie

 *          Alex Deucher

 *          Jerome Glisse

 */

#include 

#include "drmP.h"

#include "drm.h"

#include "radeon_drm.h"

#include "radeon_microcode.h"

#include "radeon_reg.h"

#include "radeon.h"

#include "r100d.h"

#include "r100_reg_safe.h"

#include "rn50_reg_safe.h"

/* This files gather functions specifics to:

 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280

 *

 * Some of these functions might be used by newer ASICs.

 */

int r200_init(struct radeon_device *rdev);

void r100_hdp_reset(struct radeon_device *rdev);

void r100_gpu_init(struct radeon_device *rdev);

int r100_gui_wait_for_idle(struct radeon_device *rdev);

int r100_mc_wait_for_idle(struct radeon_device *rdev);

void r100_gpu_wait_for_vsync(struct radeon_device *rdev);

void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);

int r100_debugfs_mc_info_init(struct radeon_device *rdev);

/*

 * PCI GART

 */

void r100_pci_gart_tlb_flush(struct radeon_device *rdev)

{

	/* TODO: can we do somethings here ? */

	/* It seems hw only cache one entry so we should discard this

	 * entry otherwise if first GPU GART read hit this entry it

	 * could end up in wrong address. */

}

int r100_pci_gart_init(struct radeon_device *rdev)

{

	int r;

	if (rdev->gart.table.ram.ptr) {

		WARN(1, "R100 PCI GART already initialized.\n");

		return 0;

	}

	/* Initialize common gart structure */

	r = radeon_gart_init(rdev);

	if (r)

		return r;

		rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;

	rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;

	rdev->asic->gart_set_page = &r100_pci_gart_set_page;

	return radeon_gart_table_ram_alloc(rdev);

}

int r100_pci_gart_enable(struct radeon_device *rdev)

{

	uint32_t tmp;

	/* discard memory request outside of configured range */

	tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;

	WREG32(RADEON_AIC_CNTL, tmp);

	/* set address range for PCI address translate */

	WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);

	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;

	WREG32(RADEON_AIC_HI_ADDR, tmp);

	/* Enable bus mastering */

	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;

	WREG32(RADEON_BUS_CNTL, tmp);

	/* set PCI GART page-table base address */

	WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);

	tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;

	WREG32(RADEON_AIC_CNTL, tmp);

	r100_pci_gart_tlb_flush(rdev);

	rdev->gart.ready = true;

	return 0;

}

void r100_pci_gart_disable(struct radeon_device *rdev)

{

	uint32_t tmp;

	/* discard memory request outside of configured range */

	tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;

	WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);

	WREG32(RADEON_AIC_LO_ADDR, 0);

	WREG32(RADEON_AIC_HI_ADDR, 0);

}

int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)

{

	if (i < 0 || i > rdev->gart.num_gpu_pages) {

		return -EINVAL;

	}

	rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));

	return 0;

}

void r100_pci_gart_fini(struct radeon_device *rdev)

{

		r100_pci_gart_disable(rdev);

	radeon_gart_table_ram_free(rdev);

	radeon_gart_fini(rdev);

}

/*

 * MC

 */

void r100_mc_disable_clients(struct radeon_device *rdev)

{

	uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;

	/* FIXME: is this function correct for rs100,rs200,rs300 ? */

	if (r100_gui_wait_for_idle(rdev)) {

		printk(KERN_WARNING "Failed to wait GUI idle while "

		       "programming pipes. Bad things might happen.\n");

	}

	/* stop display and memory access */

	ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);

	WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);

	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);

	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);

	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);

	r100_gpu_wait_for_vsync(rdev);

	WREG32(RADEON_CRTC_GEN_CNTL,

	       (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |

	       RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);

	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {

		crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);

		r100_gpu_wait_for_vsync2(rdev);

		WREG32(RADEON_CRTC2_GEN_CNTL,

		       (crtc2_gen_cntl &

		        ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |

		       RADEON_CRTC2_DISP_REQ_EN_B);

	}

	udelay(500);

}

void r100_mc_setup(struct radeon_device *rdev)

{

	uint32_t tmp;

	int r;

	r = r100_debugfs_mc_info_init(rdev);

	if (r) {

		DRM_ERROR("Failed to register debugfs file for R100 MC !\n");

	}

	/* Write VRAM size in case we are limiting it */

	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);

	/* Novell bug 204882 for RN50/M6/M7 with 8/16/32MB VRAM,

	 * if the aperture is 64MB but we have 32MB VRAM

	 * we report only 32MB VRAM but we have to set MC_FB_LOCATION

	 * to 64MB, otherwise the gpu accidentially dies */

	tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;

	tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);

	tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);

	WREG32(RADEON_MC_FB_LOCATION, tmp);

	/* Enable bus mastering */

	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;

	WREG32(RADEON_BUS_CNTL, tmp);

	if (rdev->flags & RADEON_IS_AGP) {

        tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;

		tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16);

		tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16);

		WREG32(RADEON_MC_AGP_LOCATION, tmp);

		WREG32(RADEON_AGP_BASE, rdev->mc.agp_base);

	} else {

		WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF);

		WREG32(RADEON_AGP_BASE, 0);

	}

	tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;

	tmp |= (7 << 28);

	WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);

	(void)RREG32(RADEON_HOST_PATH_CNTL);

	WREG32(RADEON_HOST_PATH_CNTL, tmp);

	(void)RREG32(RADEON_HOST_PATH_CNTL);

}

int r100_mc_init(struct radeon_device *rdev)

{

	int r;

	if (r100_debugfs_rbbm_init(rdev)) {

		DRM_ERROR("Failed to register debugfs file for RBBM !\n");

	}

	r100_gpu_init(rdev);

	/* Disable gart which also disable out of gart access */

	r100_pci_gart_disable(rdev);

	/* Setup GPU memory space */

	rdev->mc.gtt_location = 0xFFFFFFFFUL;

	r = radeon_mc_setup(rdev);

	if (r) {

		return r;

	}

	r100_mc_disable_clients(rdev);

	if (r100_mc_wait_for_idle(rdev)) {

       printk(KERN_WARNING "Failed to wait MC idle while