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5078 | serge | 1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | */ |
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23 | #ifndef PP_SMC_H |
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24 | #define PP_SMC_H |
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25 | |||
26 | #pragma pack(push, 1) |
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27 | |||
28 | #define PPSMC_SWSTATE_FLAG_DC 0x01 |
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29 | #define PPSMC_SWSTATE_FLAG_UVD 0x02 |
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30 | #define PPSMC_SWSTATE_FLAG_VCE 0x04 |
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31 | #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08 |
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32 | |||
33 | #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 |
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34 | #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 |
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35 | #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff |
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36 | |||
37 | #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 |
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38 | #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 |
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39 | #define PPSMC_SYSTEMFLAG_GDDR5 0x04 |
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40 | #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 |
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41 | #define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 |
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42 | #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 |
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43 | #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO 0x40 |
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44 | |||
45 | #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 |
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46 | #define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 |
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47 | #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 |
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48 | #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 |
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49 | #define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x02 |
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50 | |||
51 | #define PPSMC_DISPLAY_WATERMARK_LOW 0 |
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52 | #define PPSMC_DISPLAY_WATERMARK_HIGH 1 |
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53 | |||
54 | #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 |
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55 | #define PPSMC_STATEFLAG_POWERBOOST 0x02 |
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56 | #define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 |
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57 | #define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 |
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58 | |||
5271 | serge | 59 | #define FDO_MODE_HARDWARE 0 |
60 | #define FDO_MODE_PIECE_WISE_LINEAR 1 |
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61 | |||
62 | enum FAN_CONTROL { |
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63 | FAN_CONTROL_FUZZY, |
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64 | FAN_CONTROL_TABLE |
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65 | }; |
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66 | |||
5078 | serge | 67 | #define PPSMC_Result_OK ((uint8_t)0x01) |
68 | #define PPSMC_Result_Failed ((uint8_t)0xFF) |
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69 | |||
70 | typedef uint8_t PPSMC_Result; |
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71 | |||
72 | #define PPSMC_MSG_Halt ((uint8_t)0x10) |
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73 | #define PPSMC_MSG_Resume ((uint8_t)0x11) |
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74 | #define PPSMC_MSG_ZeroLevelsDisabled ((uint8_t)0x13) |
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75 | #define PPSMC_MSG_OneLevelsDisabled ((uint8_t)0x14) |
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76 | #define PPSMC_MSG_TwoLevelsDisabled ((uint8_t)0x15) |
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77 | #define PPSMC_MSG_EnableThermalInterrupt ((uint8_t)0x16) |
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78 | #define PPSMC_MSG_RunningOnAC ((uint8_t)0x17) |
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79 | #define PPSMC_MSG_SwitchToSwState ((uint8_t)0x20) |
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80 | #define PPSMC_MSG_SwitchToInitialState ((uint8_t)0x40) |
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81 | #define PPSMC_MSG_NoForcedLevel ((uint8_t)0x41) |
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82 | #define PPSMC_MSG_ForceHigh ((uint8_t)0x42) |
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83 | #define PPSMC_MSG_ForceMediumOrHigh ((uint8_t)0x43) |
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84 | #define PPSMC_MSG_SwitchToMinimumPower ((uint8_t)0x51) |
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85 | #define PPSMC_MSG_ResumeFromMinimumPower ((uint8_t)0x52) |
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86 | #define PPSMC_MSG_EnableCac ((uint8_t)0x53) |
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87 | #define PPSMC_MSG_DisableCac ((uint8_t)0x54) |
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88 | #define PPSMC_TDPClampingActive ((uint8_t)0x59) |
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89 | #define PPSMC_TDPClampingInactive ((uint8_t)0x5A) |
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5271 | serge | 90 | #define PPSMC_StartFanControl ((uint8_t)0x5B) |
91 | #define PPSMC_StopFanControl ((uint8_t)0x5C) |
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5078 | serge | 92 | #define PPSMC_MSG_NoDisplay ((uint8_t)0x5D) |
93 | #define PPSMC_MSG_HasDisplay ((uint8_t)0x5E) |
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94 | #define PPSMC_MSG_UVDPowerOFF ((uint8_t)0x60) |
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95 | #define PPSMC_MSG_UVDPowerON ((uint8_t)0x61) |
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96 | #define PPSMC_MSG_EnableULV ((uint8_t)0x62) |
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97 | #define PPSMC_MSG_DisableULV ((uint8_t)0x63) |
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98 | #define PPSMC_MSG_EnterULV ((uint8_t)0x64) |
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99 | #define PPSMC_MSG_ExitULV ((uint8_t)0x65) |
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100 | #define PPSMC_CACLongTermAvgEnable ((uint8_t)0x6E) |
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101 | #define PPSMC_CACLongTermAvgDisable ((uint8_t)0x6F) |
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102 | #define PPSMC_MSG_CollectCAC_PowerCorreln ((uint8_t)0x7A) |
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103 | #define PPSMC_FlushDataCache ((uint8_t)0x80) |
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104 | #define PPSMC_MSG_SetEnabledLevels ((uint8_t)0x82) |
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105 | #define PPSMC_MSG_SetForcedLevels ((uint8_t)0x83) |
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106 | #define PPSMC_MSG_ResetToDefaults ((uint8_t)0x84) |
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107 | #define PPSMC_MSG_EnableDTE ((uint8_t)0x87) |
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108 | #define PPSMC_MSG_DisableDTE ((uint8_t)0x88) |
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109 | #define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint8_t)0x96) |
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110 | #define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint8_t)0x97) |
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111 | |||
112 | /* CI/KV/KB */ |
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113 | #define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D) |
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114 | #define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E) |
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115 | #define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F) |
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116 | #define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) |
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117 | #define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) |
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118 | #define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) |
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5271 | serge | 119 | #define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133) |
5078 | serge | 120 | #define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) |
121 | #define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) |
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122 | #define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) |
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123 | #define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137) |
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124 | #define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138) |
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125 | #define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139) |
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126 | #define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a) |
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127 | #define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) |
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128 | #define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) |
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129 | #define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) |
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130 | #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) |
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131 | #define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) |
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132 | #define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147) |
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133 | #define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148) |
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134 | #define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a) |
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135 | #define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e) |
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136 | #define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f) |
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137 | #define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150) |
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138 | #define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151) |
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139 | #define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154) |
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140 | #define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155) |
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141 | #define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156) |
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142 | #define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157) |
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143 | #define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158) |
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144 | #define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159) |
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145 | #define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a) |
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146 | #define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b) |
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147 | #define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f) |
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148 | #define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162) |
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149 | #define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167) |
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150 | #define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169) |
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151 | #define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a) |
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152 | #define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185) |
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153 | #define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186) |
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154 | #define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187) |
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155 | #define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188) |
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156 | #define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189) |
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157 | #define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A) |
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158 | #define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B) |
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159 | #define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C) |
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160 | #define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F) |
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161 | #define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190) |
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162 | #define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191) |
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5271 | serge | 163 | #define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A) |
5078 | serge | 164 | |
5271 | serge | 165 | #define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C) |
166 | #define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D) |
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167 | |||
5078 | serge | 168 | #define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200) |
169 | #define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201) |
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170 | |||
171 | /* TN */ |
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172 | #define PPSMC_MSG_DPM_Config ((uint32_t) 0x102) |
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173 | #define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104) |
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174 | #define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108) |
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5271 | serge | 175 | #define PPSMC_MSG_Thermal_Cntl_Enable ((uint32_t) 0x10a) |
5078 | serge | 176 | #define PPSMC_MSG_Voltage_Cntl_Enable ((uint32_t) 0x109) |
177 | #define PPSMC_MSG_VCEPowerOFF ((uint32_t) 0x10e) |
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178 | #define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f) |
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5271 | serge | 179 | #define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112) |
5078 | serge | 180 | #define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d) |
181 | #define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e) |
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182 | #define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120) |
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183 | #define PPSMC_MSG_DisableBAPM ((uint32_t) 0x121) |
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184 | #define PPSMC_MSG_UVD_DPM_Config ((uint32_t) 0x124) |
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185 | |||
186 | |||
187 | typedef uint16_t PPSMC_Msg; |
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188 | |||
189 | #pragma pack(pop) |
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190 | |||
191 | #endif |