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#include 

#include 

#include 

#include 

#include 

#define IORESOURCE_PCI_FIXED            (1<<4)  /* Do not move resource */

 * Translate the low bits of the PCI base

 * to the resource type

 */

static inline unsigned int pci_calc_resource_flags(unsigned int flags)

{

    if (flags & PCI_BASE_ADDRESS_SPACE_IO)

        return IORESOURCE_IO;

        return IORESOURCE_MEM | IORESOURCE_PREFETCH;

}

{

    u32 size = mask & maxbase;      /* Find the significant bits */

        return 0;

       from that the extent.  */

    size = (size & ~(size-1)) - 1;

       already been programmed with all 1s.  */

    if (base == maxbase && ((base | size) & mask) != mask)

        return 0;

}

{

    u64 size = mask & maxbase;      /* Find the significant bits */

        return 0;

       from that the extent.  */

    size = (size & ~(size-1)) - 1;

       already been programmed with all 1s.  */

    if (base == maxbase && ((base | size) & mask) != mask)

        return 0;

}

{

    if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==

        (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))

        return 1;

    return 0;

}

{

    u32  pos, reg, next;

    u32  l, sz;

    struct resource *res;

    {

        u64  l64;

        u64  sz64;

        u32  raw_sz;

        l = PciRead32(dev->busnr, dev->devfn, reg);

        PciWrite32(dev->busnr, dev->devfn, reg, ~0);

        sz = PciRead32(dev->busnr, dev->devfn, reg);

        PciWrite32(dev->busnr, dev->devfn, reg, l);

            continue;

            l = 0;

        if ((l & PCI_BASE_ADDRESS_SPACE) ==

                        PCI_BASE_ADDRESS_SPACE_MEMORY)

        {

            sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);

            /*

             * For 64bit prefetchable memory sz could be 0, if the

             * real size is bigger than 4G, so we need to check

             * szhi for that.

             */

            if (!is_64bit_memory(l) && !sz)

                    continue;

            res->start = l & PCI_BASE_ADDRESS_MEM_MASK;

            res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;

        }

        else {

            sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);

            if (!sz)

                continue;

            res->start = l & PCI_BASE_ADDRESS_IO_MASK;

            res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;

        }

        res->end = res->start + (unsigned long) sz;

        res->flags |= pci_calc_resource_flags(l);

        if (is_64bit_memory(l))

        {

            u32 szhi, lhi;

            PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);

            szhi = PciRead32(dev->busnr, dev->devfn, reg+4);

            PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);

            sz64 = ((u64)szhi << 32) | raw_sz;

            l64 = ((u64)lhi << 32) | l;

            sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);

            next++;

            if (!sz64) {

                res->start = 0;

                res->end = 0;

                res->flags = 0;

                continue;

            }

            res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;

            res->end = res->start + sz64;

#else

            if (sz64 > 0x100000000ULL) {

                printk(KERN_ERR "PCI: Unable to handle 64-bit "

                                "BAR for device %s\n", pci_name(dev));

                res->start = 0;

                res->flags = 0;

            }

            else if (lhi)

            {

                /* 64-bit wide address, treat as disabled */

                PciWrite32(dev->busnr, dev->devfn, reg,

                        l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);

                PciWrite32(dev->busnr, dev->devfn, reg+4, 0);

                res->start = 0;

                res->end = sz;

            }

#endif

        }

    }

    {

        dev->rom_base_reg = rom;

        res = &dev->resource[PCI_ROM_RESOURCE];

        PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);

        sz = PciRead32(dev->busnr, dev->devfn, rom);

        PciWrite32(dev->busnr, dev->devfn, rom, l);

            l = 0;

        {

            sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);

            {

                res->flags = (l & IORESOURCE_ROM_ENABLE) |

                                  IORESOURCE_MEM | IORESOURCE_PREFETCH |

                                  IORESOURCE_READONLY | IORESOURCE_CACHEABLE;

                res->start = l & PCI_ROM_ADDRESS_MASK;

                res->end = res->start + (unsigned long) sz;

            }

        }

    }

}

{

    u8 irq;

    dev->pin = irq;

    if (irq)

        irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);

    dev->irq = irq;

};

{

    u32  class;

    dev->revision = class & 0xff;

    class >>= 8;                                /* upper 3 bytes */

    dev->class = class;

//    dev->current_state = PCI_UNKNOWN;

 //   pci_fixup_device(pci_fixup_early, dev);

    class = dev->class >> 8;

    {

        case PCI_HEADER_TYPE_NORMAL:                /* standard header */

            if (class == PCI_CLASS_BRIDGE_PCI)

                goto bad;

            pci_read_irq(dev);

            pci_read_bases(dev, 6, PCI_ROM_ADDRESS);

            dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);

            dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);

             *      Do the ugly legacy mode stuff here rather than broken chip

             *      quirk code. Legacy mode ATA controllers have fixed

             *      addresses. These are not always echoed in BAR0-3, and

             *      BAR0-3 in a few cases contain junk!

             */

            if (class == PCI_CLASS_STORAGE_IDE)

            {

                u8 progif;

                if ((progif & 1) == 0)

                {

                    dev->resource[0].start = 0x1F0;

                    dev->resource[0].end = 0x1F7;

                    dev->resource[0].flags = LEGACY_IO_RESOURCE;

                    dev->resource[1].start = 0x3F6;

                    dev->resource[1].end = 0x3F6;

                    dev->resource[1].flags = LEGACY_IO_RESOURCE;

                }

                if ((progif & 4) == 0)

                {

                    dev->resource[2].start = 0x170;

                    dev->resource[2].end = 0x177;

                    dev->resource[2].flags = LEGACY_IO_RESOURCE;

                    dev->resource[3].start = 0x376;

                    dev->resource[3].end = 0x376;

                    dev->resource[3].flags = LEGACY_IO_RESOURCE;

                };

            }

            break;

                if (class != PCI_CLASS_BRIDGE_PCI)

                        goto bad;

                /* The PCI-to-PCI bridge spec requires that subtractive

                   decoding (i.e. transparent) bridge must have programming

                   interface code of 0x01. */

                pci_read_irq(dev);

                dev->transparent = ((dev->class & 0xff) == 1);

                pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);

                break;

                if (class != PCI_CLASS_BRIDGE_CARDBUS)

                        goto bad;

                pci_read_irq(dev);

                pci_read_bases(dev, 1, 0);

                dev->subsystem_vendor = PciRead16(dev->busnr,

                                                  dev->devfn,

                                                  PCI_CB_SUBSYSTEM_VENDOR_ID);

                                                  dev->devfn,

                                                  PCI_CB_SUBSYSTEM_ID);

                break;

                printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",

                        pci_name(dev), dev->hdr_type);

                return -1;

                printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",

                       pci_name(dev), class, dev->hdr_type);

                dev->class = PCI_CLASS_NOT_DEFINED;

    }

};

{

    pci_dev_t  *dev;

    u8    hdr;

    if (id == 0xffffffff || id == 0x00000000 ||

        id == 0x0000ffff || id == 0xffff0000)

        return NULL;

    {

        timeout *= 2;

        if (timeout > 60 * 100)

        {

            printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "

                   "responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn));

            return NULL;

        }

    };

        return NULL;

    if(unlikely(dev == NULL))

        return NULL;

    dev->pci_dev.devfn    = devfn;

    dev->pci_dev.hdr_type = hdr & 0x7f;

    dev->pci_dev.multifunction    = !!(hdr & 0x80);

    dev->pci_dev.vendor   = id & 0xffff;

    dev->pci_dev.device   = (id >> 16) & 0xffff;

{

    int  func, nr = 0;

    {

        pci_dev_t  *dev;

        if( dev )

        {

            list_add(&dev->link, &devices);

             * If this is a single function device,

             * don't scan past the first function.

             */

            if (!dev->pci_dev.multifunction)

            {

                if (func > 0) {

                    dev->pci_dev.multifunction = 1;

                }

                else {

                    break;

                }

             }

        }

        else {

            if (func == 0)

                break;

        }

    };

};

                   u8 pos, int cap, int *ttl)

{

    u8 id;

        pos = PciRead8(bus, devfn, pos);

        if (pos < 0x40)

            break;

        pos &= ~3;

        id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);

        if (id == 0xff)

            break;

        if (id == cap)

            return pos;

        pos += PCI_CAP_LIST_NEXT;

    }

    return 0;

}

                   u8 pos, int cap)

{

    int ttl = PCI_FIND_CAP_TTL;

}

                    unsigned int devfn, u8 hdr_type)

{

    u16 status;

    if (!(status & PCI_STATUS_CAP_LIST))

        return 0;

    case PCI_HEADER_TYPE_NORMAL:

    case PCI_HEADER_TYPE_BRIDGE:

        return PCI_CAPABILITY_LIST;

    case PCI_HEADER_TYPE_CARDBUS:

        return PCI_CB_CAPABILITY_LIST;

    default:

        return 0;

    }

}

{

    int pos;

    if (pos)

        pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);

}

{

    pci_dev_t  *dev;

    u32       last_bus;

    u32       bus = 0 , devfn = 0;

        return -1;

    {

        for (devfn = 0; devfn < 0x100; devfn += 8)

            pci_scan_slot(bus, devfn);

    for(dev = (pci_dev_t*)devices.next;

        &dev->link != &devices;

        dev = (pci_dev_t*)dev->link.next)

    {

        dbgprintf("PCI device %x:%x bus:%x devfn:%x\n",

                dev->pci_dev.vendor,

                dev->pci_dev.device,

                dev->pci_dev.busnr,

                dev->pci_dev.devfn);

    return 0;

}

{

    pci_dev_t *dev;

    const struct pci_device_id *ent;

        &dev->link != &devices;

        dev = (pci_dev_t*)dev->link.next)

    {

        if( dev->pci_dev.vendor != idlist->vendor )

            continue;

        {

            if(unlikely(ent->device == dev->pci_dev.device))

            {

                pdev->pci_dev = dev->pci_dev;

                return  ent;

            }

        };

    }

};

pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from)

{

    pci_dev_t *dev;

    {

        for(; &dev->link != &devices;

            dev = (pci_dev_t*)dev->link.next)

        {

            if( &dev->pci_dev == from)

            {

                dev = (pci_dev_t*)dev->link.next;

                break;

            };

        }

    };

        dev = (pci_dev_t*)dev->link.next)

    {

        if( dev->pci_dev.vendor != vendor )

                continue;

        {

            return &dev->pci_dev;

        }

    }

    return NULL;

};

{

    pci_dev_t *dev;

        &dev->link != &devices;

        dev = (pci_dev_t*)dev->link.next)

    {

        if ( dev->pci_dev.busnr == bus && dev->pci_dev.devfn == devfn)

            return &dev->pci_dev;

    }

    return NULL;

}

{

    pci_dev_t *dev;

    {

        for(; &dev->link != &devices;

            dev = (pci_dev_t*)dev->link.next)

        {

            if( &dev->pci_dev == from)

            {

                dev = (pci_dev_t*)dev->link.next;

                break;

            };

        }

    };

        dev = (pci_dev_t*)dev->link.next)

    {

        if( dev->pci_dev.class == class)

        {

            return &dev->pci_dev;

        }

    }

}

#define PIO_MASK        0x0ffffUL

#define PIO_RESERVED    0x40000UL

    unsigned long port = (unsigned long __force)addr;  \

    if (port >= PIO_RESERVED) {                        \

        is_mmio;                                       \

    } else if (port > PIO_OFFSET) {                    \

        port &= PIO_MASK;                              \

        is_pio;                                        \

    };                                                 \

} while (0)

void __iomem *ioport_map(unsigned long port, unsigned int nr)

{

    if (port > PIO_MASK)

        return NULL;

    return (void __iomem *) (unsigned long) (port + PIO_OFFSET);

}

{

    resource_size_t start = pci_resource_start(dev, bar);

    resource_size_t len = pci_resource_len(dev, bar);

    unsigned long flags = pci_resource_flags(dev, bar);

        return NULL;

    if (maxlen && len > maxlen)

        len = maxlen;

    if (flags & IORESOURCE_IO)

        return ioport_map(start, len);

    if (flags & IORESOURCE_MEM) {

        return ioremap(start, len);

    }

    /* What? */

    return NULL;

}

{

    IO_COND(addr, /* nothing */, iounmap(addr));

}

pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,

                         struct resource *res)

{

    region->start = res->start;

    region->end = res->end;

}

{

    struct resource *res = pdev->resource + PCI_ROM_RESOURCE;

    struct pci_bus_region region;

    u32 rom_addr;

            return -1;

    pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);

    rom_addr &= ~PCI_ROM_ADDRESS_MASK;

    rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE;

    pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);

    return 0;

}

{

    u32 rom_addr;

    pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);

    rom_addr &= ~PCI_ROM_ADDRESS_ENABLE;

    pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);

}

 * pci_get_rom_size - obtain the actual size of the ROM image

 * @pdev: target PCI device

 * @rom: kernel virtual pointer to image of ROM

 * @size: size of PCI window

 *  return: size of actual ROM image

 *

 * Determine the actual length of the ROM image.

 * The PCI window size could be much larger than the

 * actual image size.

 */

size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size)

{

        void __iomem *image;

        int last_image;

        do {

                void __iomem *pds;

                /* Standard PCI ROMs start out with these bytes 55 AA */

                if (readb(image) != 0x55) {

                        dev_err(&pdev->dev, "Invalid ROM contents\n");

                        break;

            }

                if (readb(image + 1) != 0xAA)

                        break;

                /* get the PCI data structure and check its signature */

                pds = image + readw(image + 24);

                if (readb(pds) != 'P')

                        break;

                if (readb(pds + 1) != 'C')

                        break;

                if (readb(pds + 2) != 'I')

                        break;

                if (readb(pds + 3) != 'R')

                        break;

                last_image = readb(pds + 21) & 0x80;

                /* this length is reliable */

                image += readw(pds + 16) * 512;

        } while (!last_image);

        /* there are known ROMs that get the size wrong */

        return min((size_t)(image - rom), size);

}

 * pci_map_rom - map a PCI ROM to kernel space

 * @pdev: pointer to pci device struct

 * @size: pointer to receive size of pci window over ROM

 *

 * Return: kernel virtual pointer to image of ROM

 *

 * Map a PCI ROM into kernel space. If ROM is boot video ROM,

 * the shadow BIOS copy will be returned instead of the

 * actual ROM.

 */

void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)

{

    struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];

    loff_t start;

    void __iomem *rom;

     * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy

     * memory map if the VGA enable bit of the Bridge Control register is

     * set for embedded VGA.

     */

    if (res->flags & IORESOURCE_ROM_SHADOW) {

        /* primary video rom always starts here */

        start = (loff_t)0xC0000;

        *size = 0x20000; /* cover C000:0 through E000:0 */

    } else {

                if (res->flags &

                        (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) {

            *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);

             return (void __iomem *)(unsigned long)

             pci_resource_start(pdev, PCI_ROM_RESOURCE);

        } else {

    				start = (loff_t)0xC0000;

    				*size = 0x20000; /* cover C000:0 through E000:0 */

    }

    if (!rom) {

            /* restore enable if ioremap fails */

            if (!(res->flags & (IORESOURCE_ROM_ENABLE |

                                IORESOURCE_ROM_SHADOW |

                                IORESOURCE_ROM_COPY)))

                    pci_disable_rom(pdev);

            return NULL;

    }

     * Try to find the true size of the ROM since sometimes the PCI window

     * size is much larger than the actual size of the ROM.

     * True size is important if the ROM is going to be copied.

     */

    *size = pci_get_rom_size(pdev, rom, *size);

    return rom;

}

{

    struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];

            return;

    if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW)))

            pci_disable_rom(pdev);

}

{

    u16 old_cmd, cmd;

    if (enable)

        cmd = old_cmd | PCI_COMMAND_MASTER;

    else

        cmd = old_cmd & ~PCI_COMMAND_MASTER;

    if (cmd != old_cmd) {

            dbgprintf("%s bus mastering\n",

                    enable ? "enabling" : "disabling");

        pci_write_config_word(dev, PCI_COMMAND, cmd);

        }

    dev->is_busmaster = enable;

}

 * @dev: the PCI device to enable

 *

 * Enables bus-mastering on the device and calls pcibios_set_master()

 * to do the needed arch specific settings.

 */

void pci_set_master(struct pci_dev *dev)

{

        __pci_set_master(dev, true);

//        pcibios_set_master(dev);

}

 * pci_clear_master - disables bus-mastering for device dev

 * @dev: the PCI device to disable

 */

void pci_clear_master(struct pci_dev *dev)

{

        __pci_set_master(dev, false);

}

{

    return dev->pcie_flags_reg & PCI_EXP_FLAGS_VERS;

}

{

    return true;

}

{

    int type = pci_pcie_type(dev);

           type == PCI_EXP_TYPE_ROOT_PORT ||

           type == PCI_EXP_TYPE_ENDPOINT ||

           type == PCI_EXP_TYPE_LEG_END;

}

{

    int type = pci_pcie_type(dev);

           type == PCI_EXP_TYPE_ROOT_PORT ||

           (type == PCI_EXP_TYPE_DOWNSTREAM &&

        dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT);

}

{

    int type = pci_pcie_type(dev);

           type == PCI_EXP_TYPE_ROOT_PORT ||

           type == PCI_EXP_TYPE_RC_EC;

}

{

    if (!pci_is_pcie(dev))

        return false;

    case PCI_EXP_FLAGS_TYPE:

        return true;

    case PCI_EXP_DEVCAP:

    case PCI_EXP_DEVCTL:

    case PCI_EXP_DEVSTA:

        return pcie_cap_has_devctl(dev);

    case PCI_EXP_LNKCAP:

    case PCI_EXP_LNKCTL:

    case PCI_EXP_LNKSTA:

        return pcie_cap_has_lnkctl(dev);

    case PCI_EXP_SLTCAP:

    case PCI_EXP_SLTCTL:

    case PCI_EXP_SLTSTA:

        return pcie_cap_has_sltctl(dev);

    case PCI_EXP_RTCTL:

    case PCI_EXP_RTCAP:

    case PCI_EXP_RTSTA:

        return pcie_cap_has_rtctl(dev);

    case PCI_EXP_DEVCAP2:

    case PCI_EXP_DEVCTL2:

    case PCI_EXP_LNKCAP2:

    case PCI_EXP_LNKCTL2:

    case PCI_EXP_LNKSTA2:

        return pcie_cap_version(dev) > 1;

    default:

        return false;

    }

}

 * Note that these accessor functions are only for the "PCI Express

 * Capability" (see PCIe spec r3.0, sec 7.8).  They do not apply to the

 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)

 */

int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)

{

    int ret;

    if (pos & 1)

        return -EINVAL;

        ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);

        /*

         * Reset *val to 0 if pci_read_config_word() fails, it may

         * have been written as 0xFFFF if hardware error happens

         * during pci_read_config_word().

         */

        if (ret)

            *val = 0;

        return ret;

    }

     * For Functions that do not implement the Slot Capabilities,

     * Slot Status, and Slot Control registers, these spaces must

     * be hardwired to 0b, with the exception of the Presence Detect

     * State bit in the Slot Status register of Downstream Ports,

     * which must be hardwired to 1b.  (PCIe Base Spec 3.0, sec 7.8)

     */

    if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&

         pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {

        *val = PCI_EXP_SLTSTA_PDS;

    }

}

EXPORT_SYMBOL(pcie_capability_read_word);

{

    int ret;

    if (pos & 3)

        return -EINVAL;

        ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);

        /*

         * Reset *val to 0 if pci_read_config_dword() fails, it may

         * have been written as 0xFFFFFFFF if hardware error happens

         * during pci_read_config_dword().

         */

        if (ret)

            *val = 0;

        return ret;

    }

         pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {

        *val = PCI_EXP_SLTSTA_PDS;

    }

}

EXPORT_SYMBOL(pcie_capability_read_dword);

{

    if (pos & 1)

        return -EINVAL;

        return 0;

}

EXPORT_SYMBOL(pcie_capability_write_word);

{

    if (pos & 3)

        return -EINVAL;

        return 0;

}

EXPORT_SYMBOL(pcie_capability_write_dword);

                                       u16 clear, u16 set)

{

        int ret;

        u16 val;

        if (!ret) {

                val &= ~clear;

                val |= set;

                ret = pcie_capability_write_word(dev, pos, val);

        }

}

{

        u16 ctl;

}

EXPORT_SYMBOL(pcie_get_readrq);

 * pcie_set_readrq - set PCI Express maximum memory read request

 * @dev: PCI device to query

 * @rq: maximum memory read count in bytes

 *    valid values are 128, 256, 512, 1024, 2048, 4096

 *

 * If possible sets maximum memory read request in bytes

 */

int pcie_set_readrq(struct pci_dev *dev, int rq)

{

        u16 v;

                return -EINVAL;

                                                  PCI_EXP_DEVCTL_READRQ, v);

}