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Rev | Author | Line No. | Line |
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1117 | serge | 1 | |
1403 | serge | 2 | #include |
3764 | Serge | 3 | #include |
2997 | Serge | 4 | #include |
1630 | serge | 5 | #include |
1963 | serge | 6 | #include |
2160 | serge | 7 | #include |
1117 | serge | 8 | #include |
9 | |||
10 | |||
5078 | serge | 11 | bool is_power_of_2(unsigned long n) |
12 | { |
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13 | return (n != 0 && ((n & (n - 1)) == 0)); |
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14 | } |
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15 | |||
16 | |||
2997 | Serge | 17 | |
18 | |||
1120 | serge | 19 | |
1117 | serge | 20 | |
21 | #define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
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22 | |||
23 | |||
24 | |||
25 | |||
26 | * Translate the low bits of the PCI base |
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27 | * to the resource type |
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28 | */ |
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29 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) |
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30 | { |
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31 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) |
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32 | return IORESOURCE_IO; |
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33 | |||
34 | |||
35 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; |
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36 | |||
37 | |||
38 | } |
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39 | |||
40 | |||
41 | |||
42 | { |
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43 | u32_t size = mask & maxbase; /* Find the significant bits */ |
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44 | |||
45 | |||
46 | return 0; |
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47 | |||
48 | |||
49 | from that the extent. */ |
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50 | size = (size & ~(size-1)) - 1; |
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51 | |||
52 | |||
53 | already been programmed with all 1s. */ |
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54 | if (base == maxbase && ((base | size) & mask) != mask) |
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55 | return 0; |
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56 | |||
57 | |||
58 | } |
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59 | |||
60 | |||
61 | { |
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62 | u64_t size = mask & maxbase; /* Find the significant bits */ |
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63 | |||
64 | |||
65 | return 0; |
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66 | |||
67 | |||
68 | from that the extent. */ |
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69 | size = (size & ~(size-1)) - 1; |
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70 | |||
71 | |||
72 | already been programmed with all 1s. */ |
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73 | if (base == maxbase && ((base | size) & mask) != mask) |
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74 | return 0; |
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75 | |||
76 | |||
77 | } |
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78 | |||
79 | |||
80 | { |
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81 | if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == |
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82 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) |
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83 | return 1; |
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84 | return 0; |
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85 | } |
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86 | |||
87 | |||
88 | { |
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89 | u32_t pos, reg, next; |
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90 | u32_t l, sz; |
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91 | struct resource *res; |
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92 | |||
93 | |||
94 | { |
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95 | u64_t l64; |
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96 | u64_t sz64; |
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97 | u32_t raw_sz; |
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98 | |||
99 | |||
100 | |||
101 | |||
102 | |||
103 | |||
104 | l = PciRead32(dev->busnr, dev->devfn, reg); |
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2160 | serge | 105 | PciWrite32(dev->busnr, dev->devfn, reg, ~0); |
106 | sz = PciRead32(dev->busnr, dev->devfn, reg); |
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107 | PciWrite32(dev->busnr, dev->devfn, reg, l); |
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108 | |||
1117 | serge | 109 | |
110 | continue; |
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111 | |||
112 | |||
113 | l = 0; |
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114 | |||
115 | |||
116 | if ((l & PCI_BASE_ADDRESS_SPACE) == |
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117 | PCI_BASE_ADDRESS_SPACE_MEMORY) |
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118 | { |
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119 | sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
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120 | /* |
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121 | * For 64bit prefetchable memory sz could be 0, if the |
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122 | * real size is bigger than 4G, so we need to check |
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123 | * szhi for that. |
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124 | */ |
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125 | if (!is_64bit_memory(l) && !sz) |
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126 | continue; |
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127 | res->start = l & PCI_BASE_ADDRESS_MEM_MASK; |
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128 | res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; |
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129 | } |
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130 | else { |
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131 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); |
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132 | if (!sz) |
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133 | continue; |
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134 | res->start = l & PCI_BASE_ADDRESS_IO_MASK; |
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135 | res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; |
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136 | } |
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137 | res->end = res->start + (unsigned long) sz; |
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138 | res->flags |= pci_calc_resource_flags(l); |
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139 | if (is_64bit_memory(l)) |
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140 | { |
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141 | u32_t szhi, lhi; |
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142 | |||
143 | |||
2160 | serge | 144 | PciWrite32(dev->busnr, dev->devfn, reg+4, ~0); |
145 | szhi = PciRead32(dev->busnr, dev->devfn, reg+4); |
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146 | PciWrite32(dev->busnr, dev->devfn, reg+4, lhi); |
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147 | sz64 = ((u64_t)szhi << 32) | raw_sz; |
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1117 | serge | 148 | l64 = ((u64_t)lhi << 32) | l; |
149 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); |
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150 | next++; |
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151 | |||
152 | |||
153 | if (!sz64) { |
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154 | res->start = 0; |
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155 | res->end = 0; |
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156 | res->flags = 0; |
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157 | continue; |
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158 | } |
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159 | res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK; |
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160 | res->end = res->start + sz64; |
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161 | #else |
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162 | if (sz64 > 0x100000000ULL) { |
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163 | printk(KERN_ERR "PCI: Unable to handle 64-bit " |
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164 | "BAR for device %s\n", pci_name(dev)); |
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165 | res->start = 0; |
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166 | res->flags = 0; |
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167 | } |
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168 | else if (lhi) |
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169 | { |
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170 | /* 64-bit wide address, treat as disabled */ |
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171 | PciWrite32(dev->busnr, dev->devfn, reg, |
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2160 | serge | 172 | l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
1117 | serge | 173 | PciWrite32(dev->busnr, dev->devfn, reg+4, 0); |
2160 | serge | 174 | res->start = 0; |
1117 | serge | 175 | res->end = sz; |
176 | } |
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177 | #endif |
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178 | } |
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179 | } |
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180 | |||
181 | |||
182 | { |
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183 | dev->rom_base_reg = rom; |
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184 | res = &dev->resource[PCI_ROM_RESOURCE]; |
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185 | |||
186 | |||
2160 | serge | 187 | PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE); |
188 | sz = PciRead32(dev->busnr, dev->devfn, rom); |
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189 | PciWrite32(dev->busnr, dev->devfn, rom, l); |
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190 | |||
1117 | serge | 191 | |
192 | l = 0; |
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193 | |||
194 | |||
195 | { |
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196 | sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK); |
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197 | |||
198 | |||
199 | { |
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200 | res->flags = (l & IORESOURCE_ROM_ENABLE) | |
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201 | IORESOURCE_MEM | IORESOURCE_PREFETCH | |
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202 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE; |
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203 | res->start = l & PCI_ROM_ADDRESS_MASK; |
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204 | res->end = res->start + (unsigned long) sz; |
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205 | } |
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206 | } |
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207 | } |
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208 | } |
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209 | |||
210 | |||
211 | { |
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212 | u8_t irq; |
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213 | |||
214 | |||
2160 | serge | 215 | dev->pin = irq; |
1117 | serge | 216 | if (irq) |
217 | irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE); |
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2160 | serge | 218 | dev->irq = irq; |
1117 | serge | 219 | }; |
220 | |||
221 | |||
222 | |||
2160 | serge | 223 | { |
1117 | serge | 224 | u32_t class; |
225 | |||
226 | |||
2160 | serge | 227 | dev->revision = class & 0xff; |
1117 | serge | 228 | class >>= 8; /* upper 3 bytes */ |
229 | dev->class = class; |
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230 | |||
231 | |||
232 | // dev->current_state = PCI_UNKNOWN; |
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233 | |||
234 | |||
235 | // pci_fixup_device(pci_fixup_early, dev); |
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236 | class = dev->class >> 8; |
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237 | |||
238 | |||
239 | { |
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240 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
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241 | if (class == PCI_CLASS_BRIDGE_PCI) |
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242 | goto bad; |
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243 | pci_read_irq(dev); |
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244 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
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245 | dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID); |
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2160 | serge | 246 | dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID); |
247 | |||
1117 | serge | 248 | |
249 | * Do the ugly legacy mode stuff here rather than broken chip |
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250 | * quirk code. Legacy mode ATA controllers have fixed |
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251 | * addresses. These are not always echoed in BAR0-3, and |
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252 | * BAR0-3 in a few cases contain junk! |
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253 | */ |
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254 | if (class == PCI_CLASS_STORAGE_IDE) |
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255 | { |
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256 | u8_t progif; |
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257 | |||
258 | |||
2160 | serge | 259 | if ((progif & 1) == 0) |
1117 | serge | 260 | { |
261 | dev->resource[0].start = 0x1F0; |
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262 | dev->resource[0].end = 0x1F7; |
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263 | dev->resource[0].flags = LEGACY_IO_RESOURCE; |
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264 | dev->resource[1].start = 0x3F6; |
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265 | dev->resource[1].end = 0x3F6; |
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266 | dev->resource[1].flags = LEGACY_IO_RESOURCE; |
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267 | } |
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268 | if ((progif & 4) == 0) |
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269 | { |
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270 | dev->resource[2].start = 0x170; |
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271 | dev->resource[2].end = 0x177; |
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272 | dev->resource[2].flags = LEGACY_IO_RESOURCE; |
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273 | dev->resource[3].start = 0x376; |
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274 | dev->resource[3].end = 0x376; |
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275 | dev->resource[3].flags = LEGACY_IO_RESOURCE; |
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276 | }; |
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277 | } |
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278 | break; |
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279 | |||
280 | |||
281 | if (class != PCI_CLASS_BRIDGE_PCI) |
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282 | goto bad; |
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283 | /* The PCI-to-PCI bridge spec requires that subtractive |
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284 | decoding (i.e. transparent) bridge must have programming |
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285 | interface code of 0x01. */ |
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286 | pci_read_irq(dev); |
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287 | dev->transparent = ((dev->class & 0xff) == 1); |
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288 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); |
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289 | break; |
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290 | |||
291 | |||
292 | if (class != PCI_CLASS_BRIDGE_CARDBUS) |
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293 | goto bad; |
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294 | pci_read_irq(dev); |
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295 | pci_read_bases(dev, 1, 0); |
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296 | dev->subsystem_vendor = PciRead16(dev->busnr, |
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2160 | serge | 297 | dev->devfn, |
1117 | serge | 298 | PCI_CB_SUBSYSTEM_VENDOR_ID); |
299 | |||
300 | |||
2160 | serge | 301 | dev->devfn, |
1117 | serge | 302 | PCI_CB_SUBSYSTEM_ID); |
303 | break; |
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304 | |||
305 | |||
306 | printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n", |
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307 | pci_name(dev), dev->hdr_type); |
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308 | return -1; |
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309 | |||
310 | |||
311 | printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n", |
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312 | pci_name(dev), class, dev->hdr_type); |
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313 | dev->class = PCI_CLASS_NOT_DEFINED; |
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314 | } |
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315 | |||
316 | |||
317 | |||
318 | |||
319 | }; |
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320 | |||
321 | |||
2160 | serge | 322 | { |
1117 | serge | 323 | pci_dev_t *dev; |
1403 | serge | 324 | |
1117 | serge | 325 | |
326 | u8_t hdr; |
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327 | |||
328 | |||
329 | |||
330 | |||
2160 | serge | 331 | |
1117 | serge | 332 | |
333 | if (id == 0xffffffff || id == 0x00000000 || |
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334 | id == 0x0000ffff || id == 0xffff0000) |
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335 | return NULL; |
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336 | |||
337 | |||
338 | { |
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339 | |||
340 | |||
341 | timeout *= 2; |
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342 | |||
343 | |||
2160 | serge | 344 | |
1117 | serge | 345 | |
346 | if (timeout > 60 * 100) |
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347 | { |
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348 | printk(KERN_WARNING "Device %04x:%02x:%02x.%d not " |
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349 | "responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn)); |
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2160 | serge | 350 | return NULL; |
1117 | serge | 351 | } |
352 | }; |
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353 | |||
354 | |||
2997 | Serge | 355 | return NULL; |
356 | |||
357 | |||
2160 | serge | 358 | |
1117 | serge | 359 | |
1404 | serge | 360 | if(unlikely(dev == NULL)) |
2997 | Serge | 361 | return NULL; |
362 | |||
1117 | serge | 363 | |
1120 | serge | 364 | |
1117 | serge | 365 | |
366 | |||
2160 | serge | 367 | dev->pci_dev.devfn = devfn; |
1117 | serge | 368 | dev->pci_dev.hdr_type = hdr & 0x7f; |
369 | dev->pci_dev.multifunction = !!(hdr & 0x80); |
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370 | dev->pci_dev.vendor = id & 0xffff; |
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371 | dev->pci_dev.device = (id >> 16) & 0xffff; |
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372 | |||
373 | |||
374 | |||
375 | |||
376 | |||
377 | |||
378 | |||
379 | |||
2997 | Serge | 380 | |
381 | |||
382 | |||
1117 | serge | 383 | { |
384 | int func, nr = 0; |
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385 | |||
386 | |||
387 | { |
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388 | pci_dev_t *dev; |
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1403 | serge | 389 | |
1117 | serge | 390 | |
391 | if( dev ) |
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392 | { |
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393 | list_add(&dev->link, &devices); |
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1120 | serge | 394 | |
1117 | serge | 395 | |
396 | |||
397 | |||
398 | * If this is a single function device, |
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399 | * don't scan past the first function. |
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400 | */ |
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401 | if (!dev->pci_dev.multifunction) |
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402 | { |
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403 | if (func > 0) { |
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404 | dev->pci_dev.multifunction = 1; |
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405 | } |
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406 | else { |
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407 | break; |
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408 | } |
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409 | } |
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410 | } |
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411 | else { |
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412 | if (func == 0) |
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413 | break; |
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414 | } |
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415 | }; |
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416 | |||
417 | |||
418 | }; |
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419 | |||
420 | |||
1239 | serge | 421 | |
422 | |||
423 | u8 pos, int cap, int *ttl) |
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424 | { |
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425 | u8 id; |
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426 | |||
427 | |||
428 | pos = PciRead8(bus, devfn, pos); |
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429 | if (pos < 0x40) |
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430 | break; |
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431 | pos &= ~3; |
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432 | id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID); |
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433 | if (id == 0xff) |
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434 | break; |
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435 | if (id == cap) |
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436 | return pos; |
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437 | pos += PCI_CAP_LIST_NEXT; |
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438 | } |
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439 | return 0; |
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440 | } |
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441 | |||
442 | |||
443 | u8 pos, int cap) |
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444 | { |
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445 | int ttl = PCI_FIND_CAP_TTL; |
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446 | |||
447 | |||
448 | } |
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449 | |||
450 | |||
451 | unsigned int devfn, u8 hdr_type) |
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452 | { |
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453 | u16 status; |
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454 | |||
455 | |||
456 | if (!(status & PCI_STATUS_CAP_LIST)) |
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457 | return 0; |
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458 | |||
459 | |||
460 | case PCI_HEADER_TYPE_NORMAL: |
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461 | case PCI_HEADER_TYPE_BRIDGE: |
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462 | return PCI_CAPABILITY_LIST; |
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463 | case PCI_HEADER_TYPE_CARDBUS: |
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464 | return PCI_CB_CAPABILITY_LIST; |
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465 | default: |
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466 | return 0; |
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467 | } |
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468 | |||
469 | |||
470 | } |
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471 | |||
472 | |||
473 | |||
474 | { |
||
475 | int pos; |
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476 | |||
477 | |||
2160 | serge | 478 | if (pos) |
1239 | serge | 479 | pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap); |
2160 | serge | 480 | |
1239 | serge | 481 | |
482 | } |
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483 | |||
484 | |||
485 | |||
2997 | Serge | 486 | |
487 | |||
488 | { |
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1963 | serge | 489 | pci_dev_t *dev; |
2997 | Serge | 490 | u32_t last_bus; |
491 | u32_t bus = 0 , devfn = 0; |
||
492 | |||
1117 | serge | 493 | |
1963 | serge | 494 | |
2997 | Serge | 495 | |
1963 | serge | 496 | |
497 | |||
2997 | Serge | 498 | return -1; |
499 | |||
1963 | serge | 500 | |
2997 | Serge | 501 | { |
502 | for (devfn = 0; devfn < 0x100; devfn += 8) |
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503 | pci_scan_slot(bus, devfn); |
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504 | |||
1963 | serge | 505 | |
506 | |||
2997 | Serge | 507 | for(dev = (pci_dev_t*)devices.next; |
508 | &dev->link != &devices; |
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509 | dev = (pci_dev_t*)dev->link.next) |
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510 | { |
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511 | dbgprintf("PCI device %x:%x bus:%x devfn:%x\n", |
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512 | dev->pci_dev.vendor, |
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513 | dev->pci_dev.device, |
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514 | dev->pci_dev.busnr, |
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515 | dev->pci_dev.devfn); |
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516 | |||
1963 | serge | 517 | |
2997 | Serge | 518 | return 0; |
519 | } |
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520 | |||
1963 | serge | 521 | |
2997 | Serge | 522 | { |
523 | pci_dev_t *dev; |
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524 | const struct pci_device_id *ent; |
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525 | |||
1963 | serge | 526 | |
2997 | Serge | 527 | &dev->link != &devices; |
528 | dev = (pci_dev_t*)dev->link.next) |
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529 | { |
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530 | if( dev->pci_dev.vendor != idlist->vendor ) |
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531 | continue; |
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532 | |||
533 | |||
534 | { |
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535 | if(unlikely(ent->device == dev->pci_dev.device)) |
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536 | { |
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537 | pdev->pci_dev = dev->pci_dev; |
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538 | return ent; |
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539 | } |
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540 | }; |
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541 | } |
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542 | |||
543 | |||
544 | }; |
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545 | |||
546 | |||
547 | pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from) |
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548 | { |
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549 | pci_dev_t *dev; |
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550 | |||
551 | |||
552 | |||
553 | |||
554 | { |
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555 | for(; &dev->link != &devices; |
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556 | dev = (pci_dev_t*)dev->link.next) |
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557 | { |
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558 | if( &dev->pci_dev == from) |
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559 | { |
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560 | dev = (pci_dev_t*)dev->link.next; |
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561 | break; |
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1963 | serge | 562 | }; |
2997 | Serge | 563 | } |
1963 | serge | 564 | }; |
2997 | Serge | 565 | |
1963 | serge | 566 | |
2997 | Serge | 567 | dev = (pci_dev_t*)dev->link.next) |
568 | { |
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569 | if( dev->pci_dev.vendor != vendor ) |
||
570 | continue; |
||
571 | |||
1963 | serge | 572 | |
2997 | Serge | 573 | { |
574 | return &dev->pci_dev; |
||
575 | } |
||
576 | } |
||
577 | return NULL; |
||
578 | }; |
||
579 | |||
1963 | serge | 580 | |
581 | |||
2997 | Serge | 582 | { |
583 | pci_dev_t *dev; |
||
584 | |||
1963 | serge | 585 | |
2997 | Serge | 586 | &dev->link != &devices; |
587 | dev = (pci_dev_t*)dev->link.next) |
||
588 | { |
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589 | if ( dev->pci_dev.busnr == bus && dev->pci_dev.devfn == devfn) |
||
590 | return &dev->pci_dev; |
||
591 | } |
||
592 | return NULL; |
||
593 | } |
||
1963 | serge | 594 | |
595 | |||
2997 | Serge | 596 | { |
1117 | serge | 597 | pci_dev_t *dev; |
2997 | Serge | 598 | |
1117 | serge | 599 | |
2997 | Serge | 600 | |
601 | |||
602 | { |
||
1117 | serge | 603 | for(; &dev->link != &devices; |
2997 | Serge | 604 | dev = (pci_dev_t*)dev->link.next) |
605 | { |
||
606 | if( &dev->pci_dev == from) |
||
607 | { |
||
608 | dev = (pci_dev_t*)dev->link.next; |
||
609 | break; |
||
610 | }; |
||
611 | } |
||
612 | }; |
||
613 | |||
1117 | serge | 614 | |
2997 | Serge | 615 | dev = (pci_dev_t*)dev->link.next) |
616 | { |
||
617 | if( dev->pci_dev.class == class) |
||
618 | { |
||
619 | return &dev->pci_dev; |
||
620 | } |
||
1117 | serge | 621 | } |
622 | |||
2997 | Serge | 623 | |
624 | } |
||
1117 | serge | 625 | |
626 | |||
627 | |||
2997 | Serge | 628 | #define PIO_MASK 0x0ffffUL |
629 | #define PIO_RESERVED 0x40000UL |
||
630 | |||
631 | |||
632 | unsigned long port = (unsigned long __force)addr; \ |
||
633 | if (port >= PIO_RESERVED) { \ |
||
634 | is_mmio; \ |
||
635 | } else if (port > PIO_OFFSET) { \ |
||
636 | port &= PIO_MASK; \ |
||
637 | is_pio; \ |
||
638 | }; \ |
||
639 | } while (0) |
||
640 | |||
641 | |||
642 | void __iomem *ioport_map(unsigned long port, unsigned int nr) |
||
643 | { |
||
1117 | serge | 644 | if (port > PIO_MASK) |
3764 | Serge | 645 | return NULL; |
646 | return (void __iomem *) (unsigned long) (port + PIO_OFFSET); |
||
647 | } |
||
2997 | Serge | 648 | |
1117 | serge | 649 | |
2997 | Serge | 650 | { |
651 | resource_size_t start = pci_resource_start(dev, bar); |
||
652 | resource_size_t len = pci_resource_len(dev, bar); |
||
653 | unsigned long flags = pci_resource_flags(dev, bar); |
||
654 | |||
1117 | serge | 655 | |
2997 | Serge | 656 | return NULL; |
657 | if (maxlen && len > maxlen) |
||
658 | len = maxlen; |
||
659 | if (flags & IORESOURCE_IO) |
||
660 | return ioport_map(start, len); |
||
661 | if (flags & IORESOURCE_MEM) { |
||
662 | return ioremap(start, len); |
||
663 | } |
||
664 | /* What? */ |
||
665 | return NULL; |
||
666 | } |
||
1117 | serge | 667 | |
668 | |||
2997 | Serge | 669 | { |
670 | IO_COND(addr, /* nothing */, iounmap(addr)); |
||
671 | } |
||
672 | |||
1117 | serge | 673 | |
2997 | Serge | 674 | |
675 | resource_size_t start; |
||
676 | resource_size_t end; |
||
677 | }; |
||
678 | |||
679 | |||
680 | pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
||
681 | struct resource *res) |
||
682 | { |
||
1117 | serge | 683 | region->start = res->start; |
2997 | Serge | 684 | region->end = res->end; |
685 | } |
||
686 | |||
1117 | serge | 687 | |
688 | |||
2997 | Serge | 689 | { |
690 | struct resource *res = pdev->resource + PCI_ROM_RESOURCE; |
||
691 | struct pci_bus_region region; |
||
692 | u32 rom_addr; |
||
693 | |||
1117 | serge | 694 | |
2997 | Serge | 695 | return -1; |
696 | |||
697 | |||
698 | pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr); |
||
699 | rom_addr &= ~PCI_ROM_ADDRESS_MASK; |
||
700 | rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE; |
||
701 | pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr); |
||
702 | return 0; |
||
703 | } |
||
1117 | serge | 704 | |
705 | |||
2997 | Serge | 706 | { |
707 | u32 rom_addr; |
||
708 | pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr); |
||
709 | rom_addr &= ~PCI_ROM_ADDRESS_ENABLE; |
||
710 | pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr); |
||
711 | } |
||
712 | |||
1117 | serge | 713 | |
714 | * pci_get_rom_size - obtain the actual size of the ROM image |
||
2997 | Serge | 715 | * @pdev: target PCI device |
716 | * @rom: kernel virtual pointer to image of ROM |
||
717 | * @size: size of PCI window |
||
718 | * return: size of actual ROM image |
||
719 | * |
||
1117 | serge | 720 | * Determine the actual length of the ROM image. |
2997 | Serge | 721 | * The PCI window size could be much larger than the |
722 | * actual image size. |
||
723 | */ |
||
1117 | serge | 724 | size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size) |
2997 | Serge | 725 | { |
1117 | serge | 726 | void __iomem *image; |
2997 | Serge | 727 | int last_image; |
728 | |||
1117 | serge | 729 | |
2997 | Serge | 730 | do { |
731 | void __iomem *pds; |
||
732 | /* Standard PCI ROMs start out with these bytes 55 AA */ |
||
733 | if (readb(image) != 0x55) { |
||
734 | dev_err(&pdev->dev, "Invalid ROM contents\n"); |
||
735 | break; |
||
736 | } |
||
1117 | serge | 737 | if (readb(image + 1) != 0xAA) |
2997 | Serge | 738 | break; |
739 | /* get the PCI data structure and check its signature */ |
||
740 | pds = image + readw(image + 24); |
||
741 | if (readb(pds) != 'P') |
||
742 | break; |
||
743 | if (readb(pds + 1) != 'C') |
||
744 | break; |
||
745 | if (readb(pds + 2) != 'I') |
||
746 | break; |
||
747 | if (readb(pds + 3) != 'R') |
||
748 | break; |
||
749 | last_image = readb(pds + 21) & 0x80; |
||
750 | /* this length is reliable */ |
||
751 | image += readw(pds + 16) * 512; |
||
752 | } while (!last_image); |
||
753 | |||
1963 | serge | 754 | |
2997 | Serge | 755 | /* there are known ROMs that get the size wrong */ |
756 | return min((size_t)(image - rom), size); |
||
757 | } |
||
758 | |||
1117 | serge | 759 | |
760 | |||
761 | * pci_map_rom - map a PCI ROM to kernel space |
||
762 | * @pdev: pointer to pci device struct |
||
763 | * @size: pointer to receive size of pci window over ROM |
||
764 | * |
||
765 | * Return: kernel virtual pointer to image of ROM |
||
2997 | Serge | 766 | * |
767 | * Map a PCI ROM into kernel space. If ROM is boot video ROM, |
||
1117 | serge | 768 | * the shadow BIOS copy will be returned instead of the |
769 | * actual ROM. |
||
770 | */ |
||
771 | void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size) |
||
2997 | Serge | 772 | { |
1117 | serge | 773 | struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; |
774 | loff_t start; |
||
2997 | Serge | 775 | void __iomem *rom; |
776 | |||
1117 | serge | 777 | |
2997 | Serge | 778 | |
779 | |||
780 | // res->start, res->end, res->flags); |
||
781 | /* |
||
1963 | serge | 782 | * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy |
783 | * memory map if the VGA enable bit of the Bridge Control register is |
||
784 | * set for embedded VGA. |
||
785 | */ |
||
786 | |||
2997 | Serge | 787 | |
788 | *size = 0x20000; /* cover C000:0 through E000:0 */ |
||
789 | |||
790 | |||
791 | |||
792 | |||
1963 | serge | 793 | /* primary video rom always starts here */ |
794 | start = (loff_t)0xC0000; |
||
2997 | Serge | 795 | *size = 0x20000; /* cover C000:0 through E000:0 */ |
1963 | serge | 796 | } else { |
797 | if (res->flags & |
||
3764 | Serge | 798 | (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) { |
799 | *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
||
1963 | serge | 800 | return (void __iomem *)(unsigned long) |
2997 | Serge | 801 | pci_resource_start(pdev, PCI_ROM_RESOURCE); |
802 | } else { |
||
1963 | serge | 803 | /* assign the ROM an address if it doesn't have one */ |
804 | // if (res->parent == NULL && |
||
2997 | Serge | 805 | // pci_assign_resource(pdev,PCI_ROM_RESOURCE)) |
806 | return NULL; |
||
1963 | serge | 807 | // start = pci_resource_start(pdev, PCI_ROM_RESOURCE); |
2997 | Serge | 808 | // *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
809 | // if (*size == 0) |
||
810 | // return NULL; |
||
811 | |||
1963 | serge | 812 | |
813 | // if (pci_enable_rom(pdev)) |
||
2997 | Serge | 814 | // return NULL; |
815 | } |
||
1963 | serge | 816 | } |
817 | #endif |
||
2997 | Serge | 818 | |
1963 | serge | 819 | |
820 | if (!rom) { |
||
821 | /* restore enable if ioremap fails */ |
||
822 | if (!(res->flags & (IORESOURCE_ROM_ENABLE | |
||
823 | IORESOURCE_ROM_SHADOW | |
||
824 | IORESOURCE_ROM_COPY))) |
||
825 | pci_disable_rom(pdev); |
||
826 | return NULL; |
||
827 | } |
||
828 | |||
829 | |||
830 | * Try to find the true size of the ROM since sometimes the PCI window |
||
831 | * size is much larger than the actual size of the ROM. |
||
832 | * True size is important if the ROM is going to be copied. |
||
833 | */ |
||
834 | *size = pci_get_rom_size(pdev, rom, *size); |
||
2997 | Serge | 835 | // LEAVE(); |
836 | return rom; |
||
837 | } |
||
838 | |||
1963 | serge | 839 | |
2997 | Serge | 840 | { |
841 | struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; |
||
842 | |||
1117 | serge | 843 | |
2997 | Serge | 844 | return; |
845 | |||
1117 | serge | 846 | |
2997 | Serge | 847 | |
848 | |||
849 | if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW))) |
||
850 | pci_disable_rom(pdev); |
||
851 | } |
||
852 | |||
853 | |||
854 | { |
||
855 | u16 old_cmd, cmd; |
||
856 | |||
857 | |||
858 | if (enable) |
||
859 | cmd = old_cmd | PCI_COMMAND_MASTER; |
||
860 | else |
||
1117 | serge | 861 | cmd = old_cmd & ~PCI_COMMAND_MASTER; |
2997 | Serge | 862 | if (cmd != old_cmd) { |
863 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
||
864 | } |
||
865 | dev->is_busmaster = enable; |
||
866 | } |
||
867 | |||
1117 | serge | 868 | |
2997 | Serge | 869 | |
870 | * @dev: the PCI device to enable |
||
871 | * |
||
872 | * Enables bus-mastering on the device and calls pcibios_set_master() |
||
873 | * to do the needed arch specific settings. |
||
874 | */ |
||
875 | void pci_set_master(struct pci_dev *dev) |
||
876 | { |
||
877 | __pci_set_master(dev, true); |
||
878 | // pcibios_set_master(dev); |
||
879 | } |
||
1117 | serge | 880 | |
881 | |||
2997 | Serge | 882 | * pci_clear_master - disables bus-mastering for device dev |
883 | * @dev: the PCI device to disable |
||
884 | */ |
||
885 | void pci_clear_master(struct pci_dev *dev) |
||
886 | { |
||
887 | __pci_set_master(dev, false); |
||
888 | } |
||
889 | |||
1119 | serge | 890 | |
2997 | Serge | 891 | |
892 | { |
||
1119 | serge | 893 | return dev->pcie_flags_reg & PCI_EXP_FLAGS_VERS; |
2997 | Serge | 894 | } |
895 | |||
1119 | serge | 896 | |
2997 | Serge | 897 | { |
898 | return true; |
||
899 | } |
||
900 | |||
1119 | serge | 901 | |
2997 | Serge | 902 | { |
903 | int type = pci_pcie_type(dev); |
||
904 | |||
905 | |||
906 | type == PCI_EXP_TYPE_ROOT_PORT || |
||
907 | type == PCI_EXP_TYPE_ENDPOINT || |
||
908 | type == PCI_EXP_TYPE_LEG_END; |
||
909 | } |
||
910 | |||
911 | |||
912 | { |
||
913 | int type = pci_pcie_type(dev); |
||
914 | |||
915 | |||
916 | type == PCI_EXP_TYPE_ROOT_PORT || |
||
917 | (type == PCI_EXP_TYPE_DOWNSTREAM && |
||
918 | dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT); |
||
919 | } |
||
920 | |||
921 | |||
922 | { |
||
923 | int type = pci_pcie_type(dev); |
||
924 | |||
925 | |||
926 | type == PCI_EXP_TYPE_ROOT_PORT || |
||
927 | type == PCI_EXP_TYPE_RC_EC; |
||
928 | } |
||
929 | |||
930 | |||
931 | { |
||
932 | if (!pci_is_pcie(dev)) |
||
933 | return false; |
||
934 | |||
935 | |||
936 | case PCI_EXP_FLAGS_TYPE: |
||
937 | return true; |
||
938 | case PCI_EXP_DEVCAP: |
||
939 | case PCI_EXP_DEVCTL: |
||
940 | case PCI_EXP_DEVSTA: |
||
941 | return pcie_cap_has_devctl(dev); |
||
942 | case PCI_EXP_LNKCAP: |
||
943 | case PCI_EXP_LNKCTL: |
||
944 | case PCI_EXP_LNKSTA: |
||
945 | return pcie_cap_has_lnkctl(dev); |
||
946 | case PCI_EXP_SLTCAP: |
||
947 | case PCI_EXP_SLTCTL: |
||
948 | case PCI_EXP_SLTSTA: |
||
949 | return pcie_cap_has_sltctl(dev); |
||
950 | case PCI_EXP_RTCTL: |
||
951 | case PCI_EXP_RTCAP: |
||
952 | case PCI_EXP_RTSTA: |
||
953 | return pcie_cap_has_rtctl(dev); |
||
954 | case PCI_EXP_DEVCAP2: |
||
955 | case PCI_EXP_DEVCTL2: |
||
956 | case PCI_EXP_LNKCAP2: |
||
957 | case PCI_EXP_LNKCTL2: |
||
958 | case PCI_EXP_LNKSTA2: |
||
959 | return pcie_cap_version(dev) > 1; |
||
960 | default: |
||
961 | return false; |
||
962 | } |
||
963 | } |
||
964 | |||
965 | |||
966 | * Note that these accessor functions are only for the "PCI Express |
||
967 | * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the |
||
968 | * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.) |
||
969 | */ |
||
970 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val) |
||
971 | { |
||
972 | int ret; |
||
973 | |||
974 | |||
975 | if (pos & 1) |
||
976 | return -EINVAL; |
||
977 | |||
978 | |||
979 | ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); |
||
980 | /* |
||
981 | * Reset *val to 0 if pci_read_config_word() fails, it may |
||
982 | * have been written as 0xFFFF if hardware error happens |
||
983 | * during pci_read_config_word(). |
||
984 | */ |
||
985 | if (ret) |
||
986 | *val = 0; |
||
987 | return ret; |
||
988 | } |
||
989 | |||
990 | |||
991 | * For Functions that do not implement the Slot Capabilities, |
||
992 | * Slot Status, and Slot Control registers, these spaces must |
||
993 | * be hardwired to 0b, with the exception of the Presence Detect |
||
994 | * State bit in the Slot Status register of Downstream Ports, |
||
995 | * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8) |
||
996 | */ |
||
997 | if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA && |
||
998 | pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) { |
||
999 | *val = PCI_EXP_SLTSTA_PDS; |
||
1000 | } |
||
1001 | |||
1002 | |||
1003 | } |
||
1004 | EXPORT_SYMBOL(pcie_capability_read_word); |
||
1005 | |||
1006 | |||
1007 | { |
||
1008 | int ret; |
||
1009 | |||
1010 | |||
1011 | if (pos & 3) |
||
1012 | return -EINVAL; |
||
1013 | |||
1014 | |||
1015 | ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); |
||
1016 | /* |
||
1017 | * Reset *val to 0 if pci_read_config_dword() fails, it may |
||
1018 | * have been written as 0xFFFFFFFF if hardware error happens |
||
1019 | * during pci_read_config_dword(). |
||
1020 | */ |
||
1021 | if (ret) |
||
1022 | *val = 0; |
||
1023 | return ret; |
||
1024 | } |
||
1025 | |||
1026 | |||
1027 | pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) { |
||
1028 | *val = PCI_EXP_SLTSTA_PDS; |
||
1029 | } |
||
1030 | |||
1031 | |||
1032 | } |
||
1033 | EXPORT_SYMBOL(pcie_capability_read_dword); |
||
1034 | |||
1035 | |||
1036 | { |
||
1037 | if (pos & 1) |
||
1038 | return -EINVAL; |
||
1039 | |||
1040 | |||
1041 | return 0; |
||
1119 | serge | 1042 | |
2997 | Serge | 1043 | |
1044 | } |
||
1119 | serge | 1045 | EXPORT_SYMBOL(pcie_capability_write_word); |
2997 | Serge | 1046 | |
1119 | serge | 1047 | |
2997 | Serge | 1048 | { |
1049 | if (pos & 3) |
||
1050 | return -EINVAL; |
||
1051 | |||
1963 | serge | 1052 | |
2997 | Serge | 1053 | return 0; |
1054 | |||
1055 | |||
1056 | } |
||
1057 | EXPORT_SYMBOL(pcie_capability_write_dword); |
||
1058 | |||
1059 | |||
5078 | serge | 1060 | u16 clear, u16 set) |
1061 | { |
||
1062 | int ret; |
||
1063 | u16 val; |
||
1064 | |||
1065 | |||
1066 | if (!ret) { |
||
1067 | val &= ~clear; |
||
1068 | val |= set; |
||
1069 | ret = pcie_capability_write_word(dev, pos, val); |
||
1070 | } |
||
1071 | |||
1072 | |||
1073 | } |
||
1074 | |||
1075 | |||
1076 | |||
1077 | |||
1078 | { |
||
1079 | u16 ctl; |
||
1080 | |||
1081 | |||
1082 | |||
1083 | |||
1084 | } |
||
1085 | EXPORT_SYMBOL(pcie_get_readrq); |
||
1086 | |||
1087 | |||
1088 | * pcie_set_readrq - set PCI Express maximum memory read request |
||
1089 | * @dev: PCI device to query |
||
1090 | * @rq: maximum memory read count in bytes |
||
1091 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
||
1092 | * |
||
1093 | * If possible sets maximum memory read request in bytes |
||
1094 | */ |
||
1095 | int pcie_set_readrq(struct pci_dev *dev, int rq) |
||
1096 | { |
||
1097 | u16 v; |
||
1098 | |||
1099 | |||
1100 | return -EINVAL; |
||
1101 | |||
1102 | |||
1103 | |||
1104 | |||
1105 | PCI_EXP_DEVCTL_READRQ, v); |
||
1106 | }><>>><>>=>>>><>><>><>>4)><4)> |
||
1107 |