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Rev | Author | Line No. | Line |
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1117 | serge | 1 | |
1630 | serge | 2 | #include |
1403 | serge | 3 | #include |
1630 | serge | 4 | #include |
5 | #include |
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1117 | serge | 6 | #include |
7 | |||
8 | |||
1120 | serge | 9 | |
1117 | serge | 10 | |
1403 | serge | 11 | |
1117 | serge | 12 | |
13 | |||
14 | #define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
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15 | |||
16 | |||
17 | |||
18 | |||
19 | * Translate the low bits of the PCI base |
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20 | * to the resource type |
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21 | */ |
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22 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) |
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23 | { |
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24 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) |
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25 | return IORESOURCE_IO; |
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26 | |||
27 | |||
28 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; |
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29 | |||
30 | |||
31 | } |
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32 | |||
33 | |||
34 | |||
35 | { |
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36 | u32_t size = mask & maxbase; /* Find the significant bits */ |
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37 | |||
38 | |||
39 | return 0; |
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40 | |||
41 | |||
42 | from that the extent. */ |
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43 | size = (size & ~(size-1)) - 1; |
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44 | |||
45 | |||
46 | already been programmed with all 1s. */ |
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47 | if (base == maxbase && ((base | size) & mask) != mask) |
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48 | return 0; |
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49 | |||
50 | |||
51 | } |
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52 | |||
53 | |||
54 | { |
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55 | u64_t size = mask & maxbase; /* Find the significant bits */ |
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56 | |||
57 | |||
58 | return 0; |
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59 | |||
60 | |||
61 | from that the extent. */ |
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62 | size = (size & ~(size-1)) - 1; |
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63 | |||
64 | |||
65 | already been programmed with all 1s. */ |
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66 | if (base == maxbase && ((base | size) & mask) != mask) |
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67 | return 0; |
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68 | |||
69 | |||
70 | } |
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71 | |||
72 | |||
73 | { |
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74 | if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == |
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75 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) |
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76 | return 1; |
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77 | return 0; |
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78 | } |
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79 | |||
80 | |||
81 | { |
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82 | u32_t pos, reg, next; |
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83 | u32_t l, sz; |
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84 | struct resource *res; |
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85 | |||
86 | |||
87 | { |
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88 | u64_t l64; |
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89 | u64_t sz64; |
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90 | u32_t raw_sz; |
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91 | |||
92 | |||
93 | |||
94 | |||
95 | |||
96 | |||
97 | l = PciRead32(dev->busnr, dev->devfn, reg); |
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1630 | serge | 98 | PciWrite32(dev->busnr, dev->devfn, reg, ~0); |
99 | sz = PciRead32(dev->busnr, dev->devfn, reg); |
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100 | PciWrite32(dev->busnr, dev->devfn, reg, l); |
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101 | |||
1117 | serge | 102 | |
103 | continue; |
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104 | |||
105 | |||
106 | l = 0; |
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107 | |||
108 | |||
109 | if ((l & PCI_BASE_ADDRESS_SPACE) == |
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110 | PCI_BASE_ADDRESS_SPACE_MEMORY) |
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111 | { |
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112 | sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
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113 | /* |
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114 | * For 64bit prefetchable memory sz could be 0, if the |
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115 | * real size is bigger than 4G, so we need to check |
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116 | * szhi for that. |
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117 | */ |
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118 | if (!is_64bit_memory(l) && !sz) |
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119 | continue; |
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120 | res->start = l & PCI_BASE_ADDRESS_MEM_MASK; |
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121 | res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; |
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122 | } |
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123 | else { |
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124 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); |
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125 | if (!sz) |
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126 | continue; |
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127 | res->start = l & PCI_BASE_ADDRESS_IO_MASK; |
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128 | res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; |
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129 | } |
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130 | res->end = res->start + (unsigned long) sz; |
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131 | res->flags |= pci_calc_resource_flags(l); |
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132 | if (is_64bit_memory(l)) |
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133 | { |
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134 | u32_t szhi, lhi; |
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135 | |||
136 | |||
1630 | serge | 137 | PciWrite32(dev->busnr, dev->devfn, reg+4, ~0); |
138 | szhi = PciRead32(dev->busnr, dev->devfn, reg+4); |
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139 | PciWrite32(dev->busnr, dev->devfn, reg+4, lhi); |
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140 | sz64 = ((u64_t)szhi << 32) | raw_sz; |
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1117 | serge | 141 | l64 = ((u64_t)lhi << 32) | l; |
142 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); |
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143 | next++; |
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144 | |||
145 | |||
146 | if (!sz64) { |
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147 | res->start = 0; |
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148 | res->end = 0; |
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149 | res->flags = 0; |
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150 | continue; |
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151 | } |
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152 | res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK; |
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153 | res->end = res->start + sz64; |
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154 | #else |
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155 | if (sz64 > 0x100000000ULL) { |
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156 | printk(KERN_ERR "PCI: Unable to handle 64-bit " |
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157 | "BAR for device %s\n", pci_name(dev)); |
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158 | res->start = 0; |
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159 | res->flags = 0; |
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160 | } |
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161 | else if (lhi) |
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162 | { |
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163 | /* 64-bit wide address, treat as disabled */ |
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164 | PciWrite32(dev->busnr, dev->devfn, reg, |
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1630 | serge | 165 | l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
1117 | serge | 166 | PciWrite32(dev->busnr, dev->devfn, reg+4, 0); |
1630 | serge | 167 | res->start = 0; |
1117 | serge | 168 | res->end = sz; |
169 | } |
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170 | #endif |
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171 | } |
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172 | } |
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173 | |||
174 | |||
175 | { |
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176 | dev->rom_base_reg = rom; |
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177 | res = &dev->resource[PCI_ROM_RESOURCE]; |
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178 | |||
179 | |||
1630 | serge | 180 | PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE); |
181 | sz = PciRead32(dev->busnr, dev->devfn, rom); |
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182 | PciWrite32(dev->busnr, dev->devfn, rom, l); |
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183 | |||
1117 | serge | 184 | |
185 | l = 0; |
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186 | |||
187 | |||
188 | { |
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189 | sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK); |
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190 | |||
191 | |||
192 | { |
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193 | res->flags = (l & IORESOURCE_ROM_ENABLE) | |
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194 | IORESOURCE_MEM | IORESOURCE_PREFETCH | |
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195 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE; |
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196 | res->start = l & PCI_ROM_ADDRESS_MASK; |
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197 | res->end = res->start + (unsigned long) sz; |
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198 | } |
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199 | } |
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200 | } |
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201 | } |
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202 | |||
203 | |||
204 | { |
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205 | u8_t irq; |
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206 | |||
207 | |||
1630 | serge | 208 | dev->pin = irq; |
1117 | serge | 209 | if (irq) |
210 | PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE); |
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1630 | serge | 211 | dev->irq = irq; |
1117 | serge | 212 | }; |
213 | |||
214 | |||
215 | |||
216 | { |
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217 | u32_t class; |
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218 | |||
219 | |||
1630 | serge | 220 | dev->revision = class & 0xff; |
1117 | serge | 221 | class >>= 8; /* upper 3 bytes */ |
222 | dev->class = class; |
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223 | |||
224 | |||
225 | // dev->current_state = PCI_UNKNOWN; |
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226 | |||
227 | |||
228 | // pci_fixup_device(pci_fixup_early, dev); |
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229 | class = dev->class >> 8; |
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230 | |||
231 | |||
232 | { |
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233 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
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234 | if (class == PCI_CLASS_BRIDGE_PCI) |
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235 | goto bad; |
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236 | pci_read_irq(dev); |
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237 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
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238 | dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID); |
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1630 | serge | 239 | dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID); |
240 | |||
1117 | serge | 241 | |
242 | * Do the ugly legacy mode stuff here rather than broken chip |
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243 | * quirk code. Legacy mode ATA controllers have fixed |
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244 | * addresses. These are not always echoed in BAR0-3, and |
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245 | * BAR0-3 in a few cases contain junk! |
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246 | */ |
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247 | if (class == PCI_CLASS_STORAGE_IDE) |
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248 | { |
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249 | u8_t progif; |
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250 | |||
251 | |||
1630 | serge | 252 | if ((progif & 1) == 0) |
1117 | serge | 253 | { |
254 | dev->resource[0].start = 0x1F0; |
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255 | dev->resource[0].end = 0x1F7; |
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256 | dev->resource[0].flags = LEGACY_IO_RESOURCE; |
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257 | dev->resource[1].start = 0x3F6; |
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258 | dev->resource[1].end = 0x3F6; |
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259 | dev->resource[1].flags = LEGACY_IO_RESOURCE; |
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260 | } |
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261 | if ((progif & 4) == 0) |
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262 | { |
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263 | dev->resource[2].start = 0x170; |
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264 | dev->resource[2].end = 0x177; |
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265 | dev->resource[2].flags = LEGACY_IO_RESOURCE; |
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266 | dev->resource[3].start = 0x376; |
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267 | dev->resource[3].end = 0x376; |
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268 | dev->resource[3].flags = LEGACY_IO_RESOURCE; |
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269 | }; |
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270 | } |
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271 | break; |
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272 | |||
273 | |||
274 | if (class != PCI_CLASS_BRIDGE_PCI) |
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275 | goto bad; |
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276 | /* The PCI-to-PCI bridge spec requires that subtractive |
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277 | decoding (i.e. transparent) bridge must have programming |
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278 | interface code of 0x01. */ |
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279 | pci_read_irq(dev); |
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280 | dev->transparent = ((dev->class & 0xff) == 1); |
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281 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); |
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282 | break; |
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283 | |||
284 | |||
285 | if (class != PCI_CLASS_BRIDGE_CARDBUS) |
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286 | goto bad; |
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287 | pci_read_irq(dev); |
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288 | pci_read_bases(dev, 1, 0); |
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289 | dev->subsystem_vendor = PciRead16(dev->busnr, |
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1630 | serge | 290 | dev->devfn, |
1117 | serge | 291 | PCI_CB_SUBSYSTEM_VENDOR_ID); |
292 | |||
293 | |||
1630 | serge | 294 | dev->devfn, |
1117 | serge | 295 | PCI_CB_SUBSYSTEM_ID); |
296 | break; |
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297 | |||
298 | |||
299 | printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n", |
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300 | pci_name(dev), dev->hdr_type); |
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301 | return -1; |
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302 | |||
303 | |||
304 | printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n", |
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305 | pci_name(dev), class, dev->hdr_type); |
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306 | dev->class = PCI_CLASS_NOT_DEFINED; |
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307 | } |
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308 | |||
309 | |||
310 | |||
311 | |||
312 | }; |
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313 | |||
314 | |||
1403 | serge | 315 | { |
1117 | serge | 316 | pci_dev_t *dev; |
1403 | serge | 317 | |
1117 | serge | 318 | |
319 | u8_t hdr; |
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320 | |||
321 | |||
322 | |||
323 | |||
324 | |||
325 | |||
326 | if (id == 0xffffffff || id == 0x00000000 || |
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327 | id == 0x0000ffff || id == 0xffff0000) |
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328 | return NULL; |
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329 | |||
330 | |||
331 | { |
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332 | |||
333 | |||
334 | timeout *= 2; |
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335 | |||
336 | |||
337 | |||
338 | |||
339 | if (timeout > 60 * 100) |
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340 | { |
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341 | printk(KERN_WARNING "Device %04x:%02x:%02x.%d not " |
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342 | "responding\n", bus,PCI_SLOT(devfn),PCI_FUNC(devfn)); |
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343 | return NULL; |
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344 | } |
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345 | }; |
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346 | |||
347 | |||
348 | |||
349 | |||
1404 | serge | 350 | |
1117 | serge | 351 | |
1120 | serge | 352 | |
1117 | serge | 353 | |
354 | return NULL; |
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355 | |||
356 | |||
1630 | serge | 357 | dev->pci_dev.devfn = devfn; |
1117 | serge | 358 | dev->pci_dev.hdr_type = hdr & 0x7f; |
359 | dev->pci_dev.multifunction = !!(hdr & 0x80); |
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360 | dev->pci_dev.vendor = id & 0xffff; |
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361 | dev->pci_dev.device = (id >> 16) & 0xffff; |
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362 | |||
363 | |||
364 | |||
365 | |||
366 | |||
367 | |||
368 | |||
369 | |||
370 | { |
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371 | int func, nr = 0; |
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372 | |||
373 | |||
374 | { |
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375 | pci_dev_t *dev; |
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1403 | serge | 376 | |
1117 | serge | 377 | |
378 | if( dev ) |
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379 | { |
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380 | list_add(&dev->link, &devices); |
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1120 | serge | 381 | |
1117 | serge | 382 | |
383 | |||
384 | |||
385 | * If this is a single function device, |
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386 | * don't scan past the first function. |
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387 | */ |
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388 | if (!dev->pci_dev.multifunction) |
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389 | { |
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390 | if (func > 0) { |
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391 | dev->pci_dev.multifunction = 1; |
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392 | } |
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393 | else { |
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394 | break; |
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395 | } |
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396 | } |
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397 | } |
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398 | else { |
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399 | if (func == 0) |
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400 | break; |
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401 | } |
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402 | }; |
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403 | |||
404 | |||
405 | }; |
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406 | |||
407 | |||
408 | |||
409 | { |
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410 | u32_t devfn; |
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411 | pci_dev_t *dev; |
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1404 | serge | 412 | |
1117 | serge | 413 | |
414 | |||
415 | pci_scan_slot(bus, devfn); |
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416 | |||
417 | |||
418 | |||
419 | |||
420 | { |
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421 | pci_dev_t *dev; |
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1403 | serge | 422 | u32_t last_bus; |
423 | u32_t bus = 0 , devfn = 0; |
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424 | |||
1117 | serge | 425 | |
1120 | serge | 426 | |
1117 | serge | 427 | |
428 | |||
429 | |||
430 | |||
431 | return -1; |
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432 | |||
433 | |||
434 | pci_scan_bus(bus); |
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435 | |||
436 | |||
437 | // &dev->link != &devices; |
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438 | // dev = (dev_t*)dev->link.next) |
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439 | // { |
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440 | // dbgprintf("PCI device %x:%x bus:%x devfn:%x\n", |
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441 | // dev->pci_dev.vendor, |
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442 | // dev->pci_dev.device, |
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443 | // dev->pci_dev.bus, |
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444 | // dev->pci_dev.devfn); |
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445 | // |
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446 | // } |
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447 | return 0; |
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448 | } |
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449 | |||
450 | |||
1239 | serge | 451 | |
452 | |||
453 | u8 pos, int cap, int *ttl) |
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454 | { |
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455 | u8 id; |
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456 | |||
457 | |||
458 | pos = PciRead8(bus, devfn, pos); |
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459 | if (pos < 0x40) |
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460 | break; |
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461 | pos &= ~3; |
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462 | id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID); |
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463 | if (id == 0xff) |
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464 | break; |
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465 | if (id == cap) |
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466 | return pos; |
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467 | pos += PCI_CAP_LIST_NEXT; |
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468 | } |
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469 | return 0; |
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470 | } |
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471 | |||
472 | |||
473 | u8 pos, int cap) |
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474 | { |
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475 | int ttl = PCI_FIND_CAP_TTL; |
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476 | |||
477 | |||
478 | } |
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479 | |||
480 | |||
481 | unsigned int devfn, u8 hdr_type) |
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482 | { |
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483 | u16 status; |
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484 | |||
485 | |||
486 | if (!(status & PCI_STATUS_CAP_LIST)) |
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487 | return 0; |
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488 | |||
489 | |||
490 | case PCI_HEADER_TYPE_NORMAL: |
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491 | case PCI_HEADER_TYPE_BRIDGE: |
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492 | return PCI_CAPABILITY_LIST; |
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493 | case PCI_HEADER_TYPE_CARDBUS: |
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494 | return PCI_CB_CAPABILITY_LIST; |
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495 | default: |
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496 | return 0; |
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497 | } |
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498 | |||
499 | |||
500 | } |
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501 | |||
502 | |||
503 | |||
504 | { |
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505 | int pos; |
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506 | |||
507 | |||
1630 | serge | 508 | if (pos) |
1239 | serge | 509 | pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap); |
1630 | serge | 510 | |
1239 | serge | 511 | |
512 | } |
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513 | |||
514 | |||
515 | |||
1117 | serge | 516 | |
517 | { |
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518 | u16_t cmd, old_cmd; |
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519 | int idx; |
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520 | struct resource *r; |
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521 | |||
522 | |||
1630 | serge | 523 | old_cmd = cmd; |
1117 | serge | 524 | for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) |
525 | { |
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526 | /* Only set up the requested stuff */ |
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527 | if (!(mask & (1 << idx))) |
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528 | continue; |
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529 | |||
530 | |||
531 | if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) |
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532 | continue; |
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533 | if ((idx == PCI_ROM_RESOURCE) && |
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534 | (!(r->flags & IORESOURCE_ROM_ENABLE))) |
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535 | continue; |
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536 | if (!r->start && r->end) { |
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537 | printk(KERN_ERR "PCI: Device %s not available " |
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538 | "because of resource %d collisions\n", |
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539 | pci_name(dev), idx); |
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540 | return -EINVAL; |
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541 | } |
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542 | if (r->flags & IORESOURCE_IO) |
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543 | cmd |= PCI_COMMAND_IO; |
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544 | if (r->flags & IORESOURCE_MEM) |
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545 | cmd |= PCI_COMMAND_MEMORY; |
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546 | } |
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547 | if (cmd != old_cmd) { |
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548 | printk("PCI: Enabling device %s (%04x -> %04x)\n", |
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549 | pci_name(dev), old_cmd, cmd); |
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550 | PciWrite16(dev->busnr, dev->devfn, PCI_COMMAND, cmd); |
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1630 | serge | 551 | } |
1117 | serge | 552 | return 0; |
553 | } |
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554 | |||
555 | |||
556 | |||
557 | { |
||
558 | int err; |
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559 | |||
560 | |||
561 | return err; |
||
562 | |||
563 | |||
564 | // return pcibios_enable_irq(dev); |
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565 | return 0; |
||
566 | } |
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567 | |||
568 | |||
569 | |||
570 | { |
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571 | int err; |
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572 | |||
573 | |||
574 | // if (err < 0 && err != -EIO) |
||
575 | // return err; |
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576 | err = pcibios_enable_device(dev, bars); |
||
577 | // if (err < 0) |
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578 | // return err; |
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579 | // pci_fixup_device(pci_fixup_enable, dev); |
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580 | |||
581 | |||
582 | } |
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583 | |||
584 | |||
585 | |||
586 | resource_size_t flags) |
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587 | { |
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588 | int err; |
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589 | int i, bars = 0; |
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590 | |||
591 | |||
592 | // return 0; /* already enabled */ |
||
593 | |||
594 | |||
595 | if (dev->resource[i].flags & flags) |
||
596 | bars |= (1 << i); |
||
597 | |||
598 | |||
599 | // if (err < 0) |
||
600 | // atomic_dec(&dev->enable_cnt); |
||
601 | return err; |
||
602 | } |
||
603 | |||
604 | |||
605 | |||
606 | * pci_enable_device - Initialize device before it's used by a driver. |
||
607 | * @dev: PCI device to be initialized |
||
608 | * |
||
609 | * Initialize device before it's used by a driver. Ask low-level code |
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610 | * to enable I/O and memory. Wake up the device if it was suspended. |
||
611 | * Beware, this function can fail. |
||
612 | * |
||
613 | * Note we don't actually enable the device many times if we call |
||
614 | * this function repeatedly (we just increment the count). |
||
615 | */ |
||
616 | int pci_enable_device(struct pci_dev *dev) |
||
617 | { |
||
618 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
||
619 | } |
||
620 | |||
621 | |||
622 | |||
623 | |||
1403 | serge | 624 | { |
1117 | serge | 625 | pci_dev_t *dev; |
1403 | serge | 626 | struct pci_device_id *ent; |
1117 | serge | 627 | |
628 | |||
1403 | serge | 629 | &dev->link != &devices; |
1117 | serge | 630 | dev = (pci_dev_t*)dev->link.next) |
1403 | serge | 631 | { |
1117 | serge | 632 | if( dev->pci_dev.vendor != idlist->vendor ) |
633 | continue; |
||
634 | |||
635 | |||
636 | { |
||
637 | if(unlikely(ent->device == dev->pci_dev.device)) |
||
638 | { |
||
639 | pdev->pci_dev = dev->pci_dev; |
||
640 | return ent; |
||
641 | } |
||
642 | }; |
||
643 | } |
||
644 | return NULL; |
||
645 | }; |
||
646 | |||
647 | |||
648 | |||
649 | |||
650 | * pci_map_rom - map a PCI ROM to kernel space |
||
651 | * @pdev: pointer to pci device struct |
||
652 | * @size: pointer to receive size of pci window over ROM |
||
653 | * @return: kernel virtual pointer to image of ROM |
||
654 | * |
||
655 | * Map a PCI ROM into kernel space. If ROM is boot video ROM, |
||
656 | * the shadow BIOS copy will be returned instead of the |
||
657 | * actual ROM. |
||
658 | */ |
||
659 | |||
660 | |||
661 | #define OS_BASE 0x80000000 |
||
662 | |||
663 | |||
664 | { |
||
665 | struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; |
||
666 | u32_t start; |
||
667 | void *rom; |
||
668 | |||
669 | |||
670 | #endif |
||
671 | |||
672 | |||
673 | rom = NULL; |
||
674 | |||
675 | |||
676 | memcpy(tmp,(char*)(OS_BASE+legacyBIOSLocation), 32); |
||
677 | *size = tmp[2] * 512; |
||
678 | if (*size > 0x10000 ) |
||
679 | { |
||
680 | *size = 0; |
||
681 | dbgprintf("Invalid BIOS length field\n"); |
||
682 | } |
||
683 | else |
||
684 | rom = (void*)( OS_BASE+legacyBIOSLocation); |
||
685 | |||
686 | |||
687 | } |
||
688 | |||
689 | |||
1119 | serge | 690 | |
691 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) |
||
692 | { |
||
693 | // if (!pci_dma_supported(dev, mask)) |
||
694 | // return -EIO; |
||
695 | |||
696 | |||
697 | |||
698 | |||
699 | }>><>>>>>><>>>=>>>><>><>><>>4)><4)> |
||
700 |