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Rev | Author | Line No. | Line |
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1117 | serge | 1 | |
2 | #include |
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3 | #include |
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4 | |||
5 | |||
6 | |||
7 | |||
8 | |||
9 | |||
10 | |||
11 | #define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
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12 | |||
13 | |||
14 | |||
15 | |||
16 | * Translate the low bits of the PCI base |
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17 | * to the resource type |
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18 | */ |
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19 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) |
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20 | { |
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21 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) |
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22 | return IORESOURCE_IO; |
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23 | |||
24 | |||
25 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; |
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26 | |||
27 | |||
28 | } |
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29 | |||
30 | |||
31 | |||
32 | { |
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33 | u32_t size = mask & maxbase; /* Find the significant bits */ |
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34 | |||
35 | |||
36 | return 0; |
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37 | |||
38 | |||
39 | from that the extent. */ |
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40 | size = (size & ~(size-1)) - 1; |
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41 | |||
42 | |||
43 | already been programmed with all 1s. */ |
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44 | if (base == maxbase && ((base | size) & mask) != mask) |
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45 | return 0; |
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46 | |||
47 | |||
48 | } |
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49 | |||
50 | |||
51 | { |
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52 | u64_t size = mask & maxbase; /* Find the significant bits */ |
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53 | |||
54 | |||
55 | return 0; |
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56 | |||
57 | |||
58 | from that the extent. */ |
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59 | size = (size & ~(size-1)) - 1; |
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60 | |||
61 | |||
62 | already been programmed with all 1s. */ |
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63 | if (base == maxbase && ((base | size) & mask) != mask) |
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64 | return 0; |
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65 | |||
66 | |||
67 | } |
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68 | |||
69 | |||
70 | { |
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71 | if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == |
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72 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) |
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73 | return 1; |
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74 | return 0; |
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75 | } |
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76 | |||
77 | |||
78 | { |
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79 | u32_t pos, reg, next; |
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80 | u32_t l, sz; |
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81 | struct resource *res; |
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82 | |||
83 | |||
84 | { |
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85 | u64_t l64; |
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86 | u64_t sz64; |
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87 | u32_t raw_sz; |
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88 | |||
89 | |||
90 | |||
91 | |||
92 | |||
93 | |||
94 | l = PciRead32(dev->bus, dev->devfn, reg); |
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95 | PciWrite32(dev->bus, dev->devfn, reg, ~0); |
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96 | sz = PciRead32(dev->bus, dev->devfn, reg); |
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97 | PciWrite32(dev->bus, dev->devfn, reg, l); |
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98 | |||
99 | |||
100 | continue; |
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101 | |||
102 | |||
103 | l = 0; |
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104 | |||
105 | |||
106 | if ((l & PCI_BASE_ADDRESS_SPACE) == |
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107 | PCI_BASE_ADDRESS_SPACE_MEMORY) |
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108 | { |
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109 | sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
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110 | /* |
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111 | * For 64bit prefetchable memory sz could be 0, if the |
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112 | * real size is bigger than 4G, so we need to check |
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113 | * szhi for that. |
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114 | */ |
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115 | if (!is_64bit_memory(l) && !sz) |
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116 | continue; |
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117 | res->start = l & PCI_BASE_ADDRESS_MEM_MASK; |
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118 | res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; |
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119 | } |
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120 | else { |
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121 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); |
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122 | if (!sz) |
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123 | continue; |
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124 | res->start = l & PCI_BASE_ADDRESS_IO_MASK; |
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125 | res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; |
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126 | } |
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127 | res->end = res->start + (unsigned long) sz; |
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128 | res->flags |= pci_calc_resource_flags(l); |
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129 | if (is_64bit_memory(l)) |
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130 | { |
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131 | u32_t szhi, lhi; |
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132 | |||
133 | |||
134 | PciWrite32(dev->bus, dev->devfn, reg+4, ~0); |
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135 | szhi = PciRead32(dev->bus, dev->devfn, reg+4); |
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136 | PciWrite32(dev->bus, dev->devfn, reg+4, lhi); |
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137 | sz64 = ((u64_t)szhi << 32) | raw_sz; |
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138 | l64 = ((u64_t)lhi << 32) | l; |
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139 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); |
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140 | next++; |
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141 | |||
142 | |||
143 | if (!sz64) { |
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144 | res->start = 0; |
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145 | res->end = 0; |
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146 | res->flags = 0; |
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147 | continue; |
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148 | } |
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149 | res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK; |
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150 | res->end = res->start + sz64; |
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151 | #else |
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152 | if (sz64 > 0x100000000ULL) { |
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153 | printk(KERN_ERR "PCI: Unable to handle 64-bit " |
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154 | "BAR for device %s\n", pci_name(dev)); |
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155 | res->start = 0; |
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156 | res->flags = 0; |
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157 | } |
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158 | else if (lhi) |
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159 | { |
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160 | /* 64-bit wide address, treat as disabled */ |
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161 | PciWrite32(dev->bus, dev->devfn, reg, |
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162 | l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
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163 | PciWrite32(dev->bus, dev->devfn, reg+4, 0); |
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164 | res->start = 0; |
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165 | res->end = sz; |
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166 | } |
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167 | #endif |
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168 | } |
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169 | } |
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170 | |||
171 | |||
172 | { |
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173 | dev->rom_base_reg = rom; |
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174 | res = &dev->resource[PCI_ROM_RESOURCE]; |
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175 | |||
176 | |||
177 | PciWrite32(dev->bus, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE); |
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178 | sz = PciRead32(dev->bus, dev->devfn, rom); |
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179 | PciWrite32(dev->bus, dev->devfn, rom, l); |
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180 | |||
181 | |||
182 | l = 0; |
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183 | |||
184 | |||
185 | { |
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186 | sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK); |
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187 | |||
188 | |||
189 | { |
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190 | res->flags = (l & IORESOURCE_ROM_ENABLE) | |
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191 | IORESOURCE_MEM | IORESOURCE_PREFETCH | |
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192 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE; |
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193 | res->start = l & PCI_ROM_ADDRESS_MASK; |
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194 | res->end = res->start + (unsigned long) sz; |
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195 | } |
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196 | } |
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197 | } |
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198 | } |
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199 | |||
200 | |||
201 | { |
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202 | u8_t irq; |
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203 | |||
204 | |||
205 | dev->pin = irq; |
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206 | if (irq) |
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207 | PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_LINE); |
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208 | dev->irq = irq; |
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209 | }; |
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210 | |||
211 | |||
212 | |||
213 | { |
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214 | u32_t class; |
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215 | |||
216 | |||
217 | dev->revision = class & 0xff; |
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218 | class >>= 8; /* upper 3 bytes */ |
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219 | dev->class = class; |
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220 | |||
221 | |||
222 | // dev->current_state = PCI_UNKNOWN; |
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223 | |||
224 | |||
225 | // pci_fixup_device(pci_fixup_early, dev); |
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226 | class = dev->class >> 8; |
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227 | |||
228 | |||
229 | { |
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230 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
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231 | if (class == PCI_CLASS_BRIDGE_PCI) |
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232 | goto bad; |
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233 | pci_read_irq(dev); |
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234 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
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235 | dev->subsystem_vendor = PciRead16(dev->bus, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID); |
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236 | dev->subsystem_device = PciRead16(dev->bus, dev->devfn, PCI_SUBSYSTEM_ID); |
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237 | |||
238 | |||
239 | * Do the ugly legacy mode stuff here rather than broken chip |
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240 | * quirk code. Legacy mode ATA controllers have fixed |
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241 | * addresses. These are not always echoed in BAR0-3, and |
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242 | * BAR0-3 in a few cases contain junk! |
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243 | */ |
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244 | if (class == PCI_CLASS_STORAGE_IDE) |
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245 | { |
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246 | u8_t progif; |
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247 | |||
248 | |||
249 | if ((progif & 1) == 0) |
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250 | { |
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251 | dev->resource[0].start = 0x1F0; |
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252 | dev->resource[0].end = 0x1F7; |
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253 | dev->resource[0].flags = LEGACY_IO_RESOURCE; |
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254 | dev->resource[1].start = 0x3F6; |
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255 | dev->resource[1].end = 0x3F6; |
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256 | dev->resource[1].flags = LEGACY_IO_RESOURCE; |
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257 | } |
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258 | if ((progif & 4) == 0) |
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259 | { |
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260 | dev->resource[2].start = 0x170; |
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261 | dev->resource[2].end = 0x177; |
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262 | dev->resource[2].flags = LEGACY_IO_RESOURCE; |
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263 | dev->resource[3].start = 0x376; |
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264 | dev->resource[3].end = 0x376; |
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265 | dev->resource[3].flags = LEGACY_IO_RESOURCE; |
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266 | }; |
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267 | } |
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268 | break; |
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269 | |||
270 | |||
271 | if (class != PCI_CLASS_BRIDGE_PCI) |
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272 | goto bad; |
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273 | /* The PCI-to-PCI bridge spec requires that subtractive |
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274 | decoding (i.e. transparent) bridge must have programming |
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275 | interface code of 0x01. */ |
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276 | pci_read_irq(dev); |
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277 | dev->transparent = ((dev->class & 0xff) == 1); |
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278 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); |
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279 | break; |
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280 | |||
281 | |||
282 | if (class != PCI_CLASS_BRIDGE_CARDBUS) |
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283 | goto bad; |
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284 | pci_read_irq(dev); |
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285 | pci_read_bases(dev, 1, 0); |
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286 | dev->subsystem_vendor = PciRead16(dev->bus, |
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287 | dev->devfn, |
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288 | PCI_CB_SUBSYSTEM_VENDOR_ID); |
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289 | |||
290 | |||
291 | dev->devfn, |
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292 | PCI_CB_SUBSYSTEM_ID); |
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293 | break; |
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294 | |||
295 | |||
296 | printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n", |
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297 | pci_name(dev), dev->hdr_type); |
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298 | return -1; |
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299 | |||
300 | |||
301 | printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n", |
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302 | pci_name(dev), class, dev->hdr_type); |
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303 | dev->class = PCI_CLASS_NOT_DEFINED; |
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304 | } |
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305 | |||
306 | |||
307 | |||
308 | |||
309 | }; |
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310 | |||
311 | |||
312 | { |
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313 | dev_t *dev; |
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314 | |||
315 | |||
316 | u8_t hdr; |
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317 | |||
318 | |||
319 | |||
320 | |||
321 | |||
322 | |||
323 | if (id == 0xffffffff || id == 0x00000000 || |
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324 | id == 0x0000ffff || id == 0xffff0000) |
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325 | return NULL; |
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326 | |||
327 | |||
328 | { |
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329 | |||
330 | |||
331 | timeout *= 2; |
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332 | |||
333 | |||
334 | |||
335 | |||
336 | if (timeout > 60 * 100) |
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337 | { |
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338 | printk(KERN_WARNING "Device %04x:%02x:%02x.%d not " |
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339 | "responding\n", bus,PCI_SLOT(devfn),PCI_FUNC(devfn)); |
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340 | return NULL; |
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341 | } |
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342 | }; |
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343 | |||
344 | |||
345 | |||
346 | |||
347 | |||
348 | |||
349 | |||
350 | |||
351 | return NULL; |
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352 | |||
353 | |||
354 | dev->pci_dev.devfn = devfn; |
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355 | dev->pci_dev.hdr_type = hdr & 0x7f; |
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356 | dev->pci_dev.multifunction = !!(hdr & 0x80); |
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357 | dev->pci_dev.vendor = id & 0xffff; |
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358 | dev->pci_dev.device = (id >> 16) & 0xffff; |
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359 | |||
360 | |||
361 | |||
362 | |||
363 | |||
364 | |||
365 | |||
366 | |||
367 | { |
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368 | int func, nr = 0; |
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369 | |||
370 | |||
371 | { |
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372 | dev_t *dev; |
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373 | |||
374 | |||
375 | if( dev ) |
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376 | { |
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377 | list_append(&dev->link, &devices); |
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378 | |||
379 | |||
380 | |||
381 | |||
382 | * If this is a single function device, |
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383 | * don't scan past the first function. |
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384 | */ |
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385 | if (!dev->pci_dev.multifunction) |
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386 | { |
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387 | if (func > 0) { |
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388 | dev->pci_dev.multifunction = 1; |
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389 | } |
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390 | else { |
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391 | break; |
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392 | } |
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393 | } |
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394 | } |
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395 | else { |
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396 | if (func == 0) |
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397 | break; |
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398 | } |
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399 | }; |
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400 | |||
401 | |||
402 | }; |
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403 | |||
404 | |||
405 | |||
406 | { |
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407 | u32_t devfn; |
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408 | dev_t *dev; |
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409 | |||
410 | |||
411 | |||
412 | pci_scan_slot(bus, devfn); |
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413 | |||
414 | |||
415 | |||
416 | |||
417 | { |
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418 | dev_t *dev; |
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419 | u32_t last_bus; |
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420 | u32_t bus = 0 , devfn = 0; |
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421 | |||
422 | |||
423 | |||
424 | |||
425 | |||
426 | |||
427 | |||
428 | return -1; |
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429 | |||
430 | |||
431 | pci_scan_bus(bus); |
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432 | |||
433 | |||
434 | // &dev->link != &devices; |
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435 | // dev = (dev_t*)dev->link.next) |
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436 | // { |
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437 | // dbgprintf("PCI device %x:%x bus:%x devfn:%x\n", |
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438 | // dev->pci_dev.vendor, |
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439 | // dev->pci_dev.device, |
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440 | // dev->pci_dev.bus, |
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441 | // dev->pci_dev.devfn); |
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442 | // |
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443 | // } |
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444 | return 0; |
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445 | } |
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446 | |||
447 | |||
448 | /** |
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449 | * pci_set_power_state - Set the power state of a PCI device |
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450 | * @dev: PCI device to be suspended |
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451 | * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering |
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452 | * |
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453 | * Transition a device to a new power state, using the Power Management |
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454 | * Capabilities in the device's config space. |
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455 | * |
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456 | * RETURN VALUE: |
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457 | * -EINVAL if trying to enter a lower state than we're already in. |
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458 | * 0 if we're already in the requested state. |
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459 | * -EIO if device does not support PCI PM. |
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460 | * 0 if we can successfully change the power state. |
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461 | */ |
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462 | int |
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463 | pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
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464 | { |
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465 | int pm, need_restore = 0; |
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466 | u16 pmcsr, pmc; |
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467 | |||
468 | |||
469 | if (state > PCI_D3hot) |
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470 | state = PCI_D3hot; |
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471 | |||
472 | |||
473 | * If the device or the parent bridge can't support PCI PM, ignore |
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474 | * the request if we're doing anything besides putting it into D0 |
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475 | * (which would only happen on boot). |
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476 | */ |
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477 | if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) |
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478 | return 0; |
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479 | |||
480 | |||
481 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); |
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482 | |||
483 | |||
484 | if (!pm) |
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485 | return -EIO; |
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486 | |||
487 | |||
488 | * Can enter D0 from any state, but if we can only go deeper |
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489 | * to sleep if we're already in a low power state |
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490 | */ |
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491 | if (state != PCI_D0 && dev->current_state > state) { |
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492 | printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n", |
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493 | __FUNCTION__, pci_name(dev), state, dev->current_state); |
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494 | return -EINVAL; |
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495 | } else if (dev->current_state == state) |
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496 | return 0; /* we're already there */ |
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497 | |||
498 | |||
499 | |||
500 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
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501 | printk(KERN_DEBUG |
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502 | "PCI: %s has unsupported PM cap regs version (%u)\n", |
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503 | pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); |
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504 | return -EIO; |
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505 | } |
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506 | |||
507 | |||
508 | if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) |
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509 | return -EIO; |
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510 | else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) |
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511 | return -EIO; |
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512 | |||
513 | |||
514 | |||
515 | |||
516 | * This doesn't affect PME_Status, disables PME_En, and |
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517 | * sets PowerState to 0. |
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518 | */ |
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519 | switch (dev->current_state) { |
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520 | case PCI_D0: |
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521 | case PCI_D1: |
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522 | case PCI_D2: |
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523 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; |
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524 | pmcsr |= state; |
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525 | break; |
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526 | case PCI_UNKNOWN: /* Boot-up */ |
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527 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot |
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528 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
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529 | need_restore = 1; |
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530 | /* Fall-through: force to D0 */ |
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531 | default: |
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532 | pmcsr = 0; |
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533 | break; |
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534 | } |
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535 | |||
536 | |||
537 | pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); |
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538 | |||
539 | |||
540 | /* see PCI PM 1.1 5.6.1 table 18 */ |
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541 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) |
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542 | msleep(pci_pm_d3_delay); |
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543 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
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544 | udelay(200); |
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545 | |||
546 | |||
547 | * Give firmware a chance to be called, such as ACPI _PRx, _PSx |
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548 | * Firmware method after native method ? |
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549 | */ |
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550 | if (platform_pci_set_power_state) |
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551 | platform_pci_set_power_state(dev, state); |
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552 | |||
553 | |||
554 | |||
555 | |||
556 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
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557 | * from D3hot to D0 _may_ perform an internal reset, thereby |
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558 | * going to "D0 Uninitialized" rather than "D0 Initialized". |
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559 | * For example, at least some versions of the 3c905B and the |
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560 | * 3c556B exhibit this behaviour. |
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561 | * |
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562 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave |
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563 | * devices in a D3hot state at boot. Consequently, we need to |
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564 | * restore at least the BARs so that the device will be |
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565 | * accessible to its driver. |
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566 | */ |
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567 | if (need_restore) |
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568 | pci_restore_bars(dev); |
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569 | |||
570 | |||
571 | } |
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572 | #endif |
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573 | |||
574 | |||
575 | { |
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576 | u16_t cmd, old_cmd; |
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577 | int idx; |
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578 | struct resource *r; |
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579 | |||
580 | |||
581 | old_cmd = cmd; |
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582 | for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) |
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583 | { |
||
584 | /* Only set up the requested stuff */ |
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585 | if (!(mask & (1 << idx))) |
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586 | continue; |
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587 | |||
588 | |||
589 | if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) |
||
590 | continue; |
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591 | if ((idx == PCI_ROM_RESOURCE) && |
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592 | (!(r->flags & IORESOURCE_ROM_ENABLE))) |
||
593 | continue; |
||
594 | if (!r->start && r->end) { |
||
595 | printk(KERN_ERR "PCI: Device %s not available " |
||
596 | "because of resource %d collisions\n", |
||
597 | pci_name(dev), idx); |
||
598 | return -EINVAL; |
||
599 | } |
||
600 | if (r->flags & IORESOURCE_IO) |
||
601 | cmd |= PCI_COMMAND_IO; |
||
602 | if (r->flags & IORESOURCE_MEM) |
||
603 | cmd |= PCI_COMMAND_MEMORY; |
||
604 | } |
||
605 | if (cmd != old_cmd) { |
||
606 | printk("PCI: Enabling device %s (%04x -> %04x)\n", |
||
607 | pci_name(dev), old_cmd, cmd); |
||
608 | PciWrite16(dev->bus, dev->devfn, PCI_COMMAND, cmd); |
||
609 | } |
||
610 | return 0; |
||
611 | } |
||
612 | |||
613 | |||
614 | |||
615 | { |
||
616 | int err; |
||
617 | |||
618 | |||
619 | return err; |
||
620 | |||
621 | |||
622 | // return pcibios_enable_irq(dev); |
||
623 | return 0; |
||
624 | } |
||
625 | |||
626 | |||
627 | |||
628 | { |
||
629 | int err; |
||
630 | |||
631 | |||
632 | // if (err < 0 && err != -EIO) |
||
633 | // return err; |
||
634 | err = pcibios_enable_device(dev, bars); |
||
635 | // if (err < 0) |
||
636 | // return err; |
||
637 | // pci_fixup_device(pci_fixup_enable, dev); |
||
638 | |||
639 | |||
640 | } |
||
641 | |||
642 | |||
643 | |||
644 | resource_size_t flags) |
||
645 | { |
||
646 | int err; |
||
647 | int i, bars = 0; |
||
648 | |||
649 | |||
650 | // return 0; /* already enabled */ |
||
651 | |||
652 | |||
653 | if (dev->resource[i].flags & flags) |
||
654 | bars |= (1 << i); |
||
655 | |||
656 | |||
657 | // if (err < 0) |
||
658 | // atomic_dec(&dev->enable_cnt); |
||
659 | return err; |
||
660 | } |
||
661 | |||
662 | |||
663 | |||
664 | * pci_enable_device - Initialize device before it's used by a driver. |
||
665 | * @dev: PCI device to be initialized |
||
666 | * |
||
667 | * Initialize device before it's used by a driver. Ask low-level code |
||
668 | * to enable I/O and memory. Wake up the device if it was suspended. |
||
669 | * Beware, this function can fail. |
||
670 | * |
||
671 | * Note we don't actually enable the device many times if we call |
||
672 | * this function repeatedly (we just increment the count). |
||
673 | */ |
||
674 | int pci_enable_device(struct pci_dev *dev) |
||
675 | { |
||
676 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
||
677 | } |
||
678 | |||
679 | |||
680 | |||
681 | |||
682 | { |
||
683 | dev_t *dev; |
||
684 | struct pci_device_id *ent; |
||
685 | |||
686 | |||
687 | &dev->link != &devices; |
||
688 | dev = (dev_t*)dev->link.next) |
||
689 | { |
||
690 | if( dev->pci_dev.vendor != idlist->vendor ) |
||
691 | continue; |
||
692 | |||
693 | |||
694 | { |
||
695 | if(unlikely(ent->device == dev->pci_dev.device)) |
||
696 | { |
||
697 | pdev->pci_dev = dev->pci_dev; |
||
698 | return ent; |
||
699 | } |
||
700 | }; |
||
701 | } |
||
702 | |||
703 | |||
704 | }; |
||
705 | |||
706 | |||
707 | |||
708 | |||
709 | * pci_map_rom - map a PCI ROM to kernel space |
||
710 | * @pdev: pointer to pci device struct |
||
711 | * @size: pointer to receive size of pci window over ROM |
||
712 | * @return: kernel virtual pointer to image of ROM |
||
713 | * |
||
714 | * Map a PCI ROM into kernel space. If ROM is boot video ROM, |
||
715 | * the shadow BIOS copy will be returned instead of the |
||
716 | * actual ROM. |
||
717 | */ |
||
718 | |||
719 | |||
720 | #define OS_BASE 0x80000000 |
||
721 | |||
722 | |||
723 | { |
||
724 | struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; |
||
725 | u32_t start; |
||
726 | void *rom; |
||
727 | |||
728 | |||
729 | /* |
||
730 | * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy |
||
731 | * memory map if the VGA enable bit of the Bridge Control register is |
||
732 | * set for embedded VGA. |
||
733 | */ |
||
734 | if (res->flags & IORESOURCE_ROM_SHADOW) { |
||
735 | /* primary video rom always starts here */ |
||
736 | start = (u32_t)0xC0000; |
||
737 | *size = 0x20000; /* cover C000:0 through E000:0 */ |
||
738 | } else { |
||
739 | if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) { |
||
740 | *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
||
741 | return (void *)(unsigned long) |
||
742 | pci_resource_start(pdev, PCI_ROM_RESOURCE); |
||
743 | } else { |
||
744 | /* assign the ROM an address if it doesn't have one */ |
||
745 | //if (res->parent == NULL && |
||
746 | // pci_assign_resource(pdev,PCI_ROM_RESOURCE)) |
||
747 | // return NULL; |
||
748 | start = pci_resource_start(pdev, PCI_ROM_RESOURCE); |
||
749 | *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
||
750 | if (*size == 0) |
||
751 | return NULL; |
||
752 | |||
753 | |||
754 | if (pci_enable_rom(pdev)) |
||
755 | return NULL; |
||
756 | } |
||
757 | } |
||
758 | |||
759 | |||
760 | if (!rom) { |
||
761 | /* restore enable if ioremap fails */ |
||
762 | if (!(res->flags & (IORESOURCE_ROM_ENABLE | |
||
763 | IORESOURCE_ROM_SHADOW | |
||
764 | IORESOURCE_ROM_COPY))) |
||
765 | pci_disable_rom(pdev); |
||
766 | return NULL; |
||
767 | } |
||
768 | |||
769 | |||
770 | * Try to find the true size of the ROM since sometimes the PCI window |
||
771 | * size is much larger than the actual size of the ROM. |
||
772 | * True size is important if the ROM is going to be copied. |
||
773 | */ |
||
774 | *size = pci_get_rom_size(rom, *size); |
||
775 | |||
776 | |||
777 | |||
778 | |||
779 | rom = NULL; |
||
780 | |||
781 | |||
782 | memcpy(tmp,(char*)(OS_BASE+legacyBIOSLocation), 32); |
||
783 | *size = tmp[2] * 512; |
||
784 | if (*size > 0x10000 ) |
||
785 | { |
||
786 | *size = 0; |
||
787 | dbgprintf("Invalid BIOS length field\n"); |
||
788 | } |
||
789 | else |
||
790 | rom = (void*)( OS_BASE+legacyBIOSLocation); |
||
791 | |||
792 | |||
793 | }>><>>>>>><>>=>>>><>><>><>>4)><4)> |
||
794 |