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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5078 | serge | 1 | /* |
| 2 | * Copyright 2012 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | #ifndef __NISLANDS_SMC_H__ |
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| 24 | #define __NISLANDS_SMC_H__ |
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| 25 | |||
| 26 | #pragma pack(push, 1) |
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| 27 | |||
| 28 | #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 |
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| 29 | |||
| 30 | struct PP_NIslands_Dpm2PerfLevel |
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| 31 | { |
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| 32 | uint8_t MaxPS; |
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| 33 | uint8_t TgtAct; |
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| 34 | uint8_t MaxPS_StepInc; |
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| 35 | uint8_t MaxPS_StepDec; |
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| 36 | uint8_t PSST; |
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| 37 | uint8_t NearTDPDec; |
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| 38 | uint8_t AboveSafeInc; |
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| 39 | uint8_t BelowSafeInc; |
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| 40 | uint8_t PSDeltaLimit; |
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| 41 | uint8_t PSDeltaWin; |
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| 42 | uint8_t Reserved[6]; |
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| 43 | }; |
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| 44 | |||
| 45 | typedef struct PP_NIslands_Dpm2PerfLevel PP_NIslands_Dpm2PerfLevel; |
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| 46 | |||
| 47 | struct PP_NIslands_DPM2Parameters |
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| 48 | { |
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| 49 | uint32_t TDPLimit; |
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| 50 | uint32_t NearTDPLimit; |
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| 51 | uint32_t SafePowerLimit; |
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| 52 | uint32_t PowerBoostLimit; |
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| 53 | }; |
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| 54 | typedef struct PP_NIslands_DPM2Parameters PP_NIslands_DPM2Parameters; |
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| 55 | |||
| 56 | struct NISLANDS_SMC_SCLK_VALUE |
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| 57 | { |
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| 58 | uint32_t vCG_SPLL_FUNC_CNTL; |
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| 59 | uint32_t vCG_SPLL_FUNC_CNTL_2; |
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| 60 | uint32_t vCG_SPLL_FUNC_CNTL_3; |
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| 61 | uint32_t vCG_SPLL_FUNC_CNTL_4; |
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| 62 | uint32_t vCG_SPLL_SPREAD_SPECTRUM; |
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| 63 | uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; |
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| 64 | uint32_t sclk_value; |
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| 65 | }; |
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| 66 | |||
| 67 | typedef struct NISLANDS_SMC_SCLK_VALUE NISLANDS_SMC_SCLK_VALUE; |
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| 68 | |||
| 69 | struct NISLANDS_SMC_MCLK_VALUE |
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| 70 | { |
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| 71 | uint32_t vMPLL_FUNC_CNTL; |
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| 72 | uint32_t vMPLL_FUNC_CNTL_1; |
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| 73 | uint32_t vMPLL_FUNC_CNTL_2; |
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| 74 | uint32_t vMPLL_AD_FUNC_CNTL; |
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| 75 | uint32_t vMPLL_AD_FUNC_CNTL_2; |
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| 76 | uint32_t vMPLL_DQ_FUNC_CNTL; |
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| 77 | uint32_t vMPLL_DQ_FUNC_CNTL_2; |
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| 78 | uint32_t vMCLK_PWRMGT_CNTL; |
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| 79 | uint32_t vDLL_CNTL; |
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| 80 | uint32_t vMPLL_SS; |
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| 81 | uint32_t vMPLL_SS2; |
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| 82 | uint32_t mclk_value; |
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| 83 | }; |
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| 84 | |||
| 85 | typedef struct NISLANDS_SMC_MCLK_VALUE NISLANDS_SMC_MCLK_VALUE; |
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| 86 | |||
| 87 | struct NISLANDS_SMC_VOLTAGE_VALUE |
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| 88 | { |
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| 89 | uint16_t value; |
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| 90 | uint8_t index; |
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| 91 | uint8_t padding; |
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| 92 | }; |
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| 93 | |||
| 94 | typedef struct NISLANDS_SMC_VOLTAGE_VALUE NISLANDS_SMC_VOLTAGE_VALUE; |
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| 95 | |||
| 96 | struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL |
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| 97 | { |
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| 98 | uint8_t arbValue; |
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| 99 | uint8_t ACIndex; |
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| 100 | uint8_t displayWatermark; |
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| 101 | uint8_t gen2PCIE; |
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| 102 | uint8_t reserved1; |
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| 103 | uint8_t reserved2; |
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| 104 | uint8_t strobeMode; |
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| 105 | uint8_t mcFlags; |
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| 106 | uint32_t aT; |
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| 107 | uint32_t bSP; |
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| 108 | NISLANDS_SMC_SCLK_VALUE sclk; |
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| 109 | NISLANDS_SMC_MCLK_VALUE mclk; |
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| 110 | NISLANDS_SMC_VOLTAGE_VALUE vddc; |
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| 111 | NISLANDS_SMC_VOLTAGE_VALUE mvdd; |
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| 112 | NISLANDS_SMC_VOLTAGE_VALUE vddci; |
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| 113 | NISLANDS_SMC_VOLTAGE_VALUE std_vddc; |
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| 114 | uint32_t powergate_en; |
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| 115 | uint8_t hUp; |
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| 116 | uint8_t hDown; |
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| 117 | uint8_t stateFlags; |
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| 118 | uint8_t arbRefreshState; |
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| 119 | uint32_t SQPowerThrottle; |
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| 120 | uint32_t SQPowerThrottle_2; |
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| 121 | uint32_t reserved[2]; |
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| 122 | PP_NIslands_Dpm2PerfLevel dpm2; |
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| 123 | }; |
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| 124 | |||
| 125 | #define NISLANDS_SMC_STROBE_RATIO 0x0F |
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| 126 | #define NISLANDS_SMC_STROBE_ENABLE 0x10 |
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| 127 | |||
| 128 | #define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01 |
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| 129 | #define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02 |
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| 130 | #define NISLANDS_SMC_MC_RTT_ENABLE 0x04 |
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| 131 | #define NISLANDS_SMC_MC_STUTTER_EN 0x08 |
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| 132 | |||
| 133 | typedef struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL NISLANDS_SMC_HW_PERFORMANCE_LEVEL; |
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| 134 | |||
| 135 | struct NISLANDS_SMC_SWSTATE |
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| 136 | { |
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| 137 | uint8_t flags; |
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| 138 | uint8_t levelCount; |
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| 139 | uint8_t padding2; |
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| 140 | uint8_t padding3; |
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| 141 | NISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1]; |
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| 142 | }; |
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| 143 | |||
| 144 | typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE; |
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| 145 | |||
| 146 | #define NISLANDS_SMC_VOLTAGEMASK_VDDC 0 |
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| 147 | #define NISLANDS_SMC_VOLTAGEMASK_MVDD 1 |
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| 148 | #define NISLANDS_SMC_VOLTAGEMASK_VDDCI 2 |
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| 149 | #define NISLANDS_SMC_VOLTAGEMASK_MAX 4 |
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| 150 | |||
| 151 | struct NISLANDS_SMC_VOLTAGEMASKTABLE |
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| 152 | { |
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| 153 | uint8_t highMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; |
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| 154 | uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; |
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| 155 | }; |
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| 156 | |||
| 157 | typedef struct NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGEMASKTABLE; |
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| 158 | |||
| 159 | #define NISLANDS_MAX_NO_VREG_STEPS 32 |
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| 160 | |||
| 161 | struct NISLANDS_SMC_STATETABLE |
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| 162 | { |
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| 163 | uint8_t thermalProtectType; |
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| 164 | uint8_t systemFlags; |
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| 165 | uint8_t maxVDDCIndexInPPTable; |
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| 166 | uint8_t extraFlags; |
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| 167 | uint8_t highSMIO[NISLANDS_MAX_NO_VREG_STEPS]; |
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| 168 | uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS]; |
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| 169 | NISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable; |
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| 170 | PP_NIslands_DPM2Parameters dpm2Params; |
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| 171 | NISLANDS_SMC_SWSTATE initialState; |
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| 172 | NISLANDS_SMC_SWSTATE ACPIState; |
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| 173 | NISLANDS_SMC_SWSTATE ULVState; |
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| 174 | NISLANDS_SMC_SWSTATE driverState; |
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| 175 | NISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1]; |
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| 176 | }; |
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| 177 | |||
| 178 | typedef struct NISLANDS_SMC_STATETABLE NISLANDS_SMC_STATETABLE; |
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| 179 | |||
| 180 | #define NI_SMC_SOFT_REGISTERS_START 0x108 |
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| 181 | |||
| 182 | #define NI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0 |
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| 183 | #define NI_SMC_SOFT_REGISTER_delay_bbias 0xC |
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| 184 | #define NI_SMC_SOFT_REGISTER_delay_vreg 0x10 |
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| 185 | #define NI_SMC_SOFT_REGISTER_delay_acpi 0x2C |
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| 186 | #define NI_SMC_SOFT_REGISTER_seq_index 0x64 |
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| 187 | #define NI_SMC_SOFT_REGISTER_mvdd_chg_time 0x68 |
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| 188 | #define NI_SMC_SOFT_REGISTER_mclk_switch_lim 0x78 |
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| 189 | #define NI_SMC_SOFT_REGISTER_watermark_threshold 0x80 |
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| 190 | #define NI_SMC_SOFT_REGISTER_mc_block_delay 0x84 |
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| 191 | #define NI_SMC_SOFT_REGISTER_uvd_enabled 0x98 |
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| 192 | |||
| 193 | #define SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES 16 |
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| 194 | #define SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 |
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| 195 | #define SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 |
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| 196 | #define SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES 4 |
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| 197 | |||
| 198 | struct SMC_NISLANDS_MC_TPP_CAC_TABLE |
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| 199 | { |
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| 200 | uint32_t tpp[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES]; |
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| 201 | uint32_t cacValue[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES]; |
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| 202 | }; |
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| 203 | |||
| 204 | typedef struct SMC_NISLANDS_MC_TPP_CAC_TABLE SMC_NISLANDS_MC_TPP_CAC_TABLE; |
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| 205 | |||
| 206 | |||
| 207 | struct PP_NIslands_CACTABLES |
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| 208 | { |
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| 209 | uint32_t cac_bif_lut[SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES]; |
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| 210 | uint32_t cac_lkge_lut[SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES]; |
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| 211 | |||
| 212 | uint32_t pwr_const; |
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| 213 | |||
| 214 | uint32_t dc_cacValue; |
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| 215 | uint32_t bif_cacValue; |
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| 216 | uint32_t lkge_pwr; |
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| 217 | |||
| 218 | uint8_t cac_width; |
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| 219 | uint8_t window_size_p2; |
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| 220 | |||
| 221 | uint8_t num_drop_lsb; |
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| 222 | uint8_t padding_0; |
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| 223 | |||
| 224 | uint32_t last_power; |
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| 225 | |||
| 226 | uint8_t AllowOvrflw; |
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| 227 | uint8_t MCWrWeight; |
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| 228 | uint8_t MCRdWeight; |
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| 229 | uint8_t padding_1[9]; |
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| 230 | |||
| 231 | uint8_t enableWinAvg; |
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| 232 | uint8_t numWin_TDP; |
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| 233 | uint8_t l2numWin_TDP; |
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| 234 | uint8_t WinIndex; |
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| 235 | |||
| 236 | uint32_t dynPwr_TDP[4]; |
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| 237 | uint32_t lkgePwr_TDP[4]; |
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| 238 | uint32_t power_TDP[4]; |
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| 239 | uint32_t avg_dynPwr_TDP; |
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| 240 | uint32_t avg_lkgePwr_TDP; |
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| 241 | uint32_t avg_power_TDP; |
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| 242 | uint32_t lts_power_TDP; |
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| 243 | uint8_t lts_truncate_n; |
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| 244 | uint8_t padding_2[7]; |
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| 245 | }; |
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| 246 | |||
| 247 | typedef struct PP_NIslands_CACTABLES PP_NIslands_CACTABLES; |
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| 248 | |||
| 249 | #define SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 32 |
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| 250 | #define SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20 |
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| 251 | |||
| 252 | struct SMC_NIslands_MCRegisterAddress |
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| 253 | { |
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| 254 | uint16_t s0; |
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| 255 | uint16_t s1; |
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| 256 | }; |
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| 257 | |||
| 258 | typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress; |
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| 259 | |||
| 260 | |||
| 261 | struct SMC_NIslands_MCRegisterSet |
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| 262 | { |
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| 263 | uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; |
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| 264 | }; |
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| 265 | |||
| 266 | typedef struct SMC_NIslands_MCRegisterSet SMC_NIslands_MCRegisterSet; |
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| 267 | |||
| 268 | struct SMC_NIslands_MCRegisters |
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| 269 | { |
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| 270 | uint8_t last; |
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| 271 | uint8_t reserved[3]; |
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| 272 | SMC_NIslands_MCRegisterAddress address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; |
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| 273 | SMC_NIslands_MCRegisterSet data[SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT]; |
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| 274 | }; |
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| 275 | |||
| 276 | typedef struct SMC_NIslands_MCRegisters SMC_NIslands_MCRegisters; |
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| 277 | |||
| 278 | struct SMC_NIslands_MCArbDramTimingRegisterSet |
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| 279 | { |
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| 280 | uint32_t mc_arb_dram_timing; |
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| 281 | uint32_t mc_arb_dram_timing2; |
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| 282 | uint8_t mc_arb_rfsh_rate; |
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| 283 | uint8_t padding[3]; |
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| 284 | }; |
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| 285 | |||
| 286 | typedef struct SMC_NIslands_MCArbDramTimingRegisterSet SMC_NIslands_MCArbDramTimingRegisterSet; |
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| 287 | |||
| 288 | struct SMC_NIslands_MCArbDramTimingRegisters |
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| 289 | { |
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| 290 | uint8_t arb_current; |
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| 291 | uint8_t reserved[3]; |
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| 292 | SMC_NIslands_MCArbDramTimingRegisterSet data[20]; |
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| 293 | }; |
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| 294 | |||
| 295 | typedef struct SMC_NIslands_MCArbDramTimingRegisters SMC_NIslands_MCArbDramTimingRegisters; |
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| 296 | |||
| 297 | struct SMC_NISLANDS_SPLL_DIV_TABLE |
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| 298 | { |
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| 299 | uint32_t freq[256]; |
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| 300 | uint32_t ss[256]; |
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| 301 | }; |
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| 302 | |||
| 303 | #define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff |
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| 304 | #define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0 |
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| 305 | #define SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000 |
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| 306 | #define SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT 25 |
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| 307 | #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff |
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| 308 | #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0 |
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| 309 | #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000 |
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| 310 | #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT 20 |
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| 311 | |||
| 312 | typedef struct SMC_NISLANDS_SPLL_DIV_TABLE SMC_NISLANDS_SPLL_DIV_TABLE; |
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| 313 | |||
| 314 | #define NISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x100 |
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| 315 | |||
| 316 | #define NISLANDS_SMC_FIRMWARE_HEADER_version 0x0 |
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| 317 | #define NISLANDS_SMC_FIRMWARE_HEADER_flags 0x4 |
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| 318 | #define NISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0x8 |
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| 319 | #define NISLANDS_SMC_FIRMWARE_HEADER_stateTable 0xC |
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| 320 | #define NISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x10 |
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| 321 | #define NISLANDS_SMC_FIRMWARE_HEADER_cacTable 0x14 |
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| 322 | #define NISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x20 |
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| 323 | #define NISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x2C |
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| 324 | #define NISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x30 |
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| 325 | |||
| 326 | #pragma pack(pop) |
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| 327 | |||
| 328 | #endif |
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| 329 |