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1990 serge 1
/*
2
 * Copyright 2010 Advanced Micro Devices, Inc.
3
 *
4
 * Permission is hereby granted, free of charge, to any person obtaining a
5
 * copy of this software and associated documentation files (the "Software"),
6
 * to deal in the Software without restriction, including without limitation
7
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
 * and/or sell copies of the Software, and to permit persons to whom the
9
 * Software is furnished to do so, subject to the following conditions:
10
 *
11
 * The above copyright notice and this permission notice shall be included in
12
 * all copies or substantial portions of the Software.
13
 *
14
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
 * OTHER DEALINGS IN THE SOFTWARE.
21
 *
22
 * Authors: Alex Deucher
23
 */
24
#include 
25
//#include 
26
#include 
2997 Serge 27
#include 
28
#include 
1990 serge 29
#include "radeon.h"
30
#include "radeon_asic.h"
2997 Serge 31
#include 
1990 serge 32
#include "nid.h"
33
#include "atom.h"
34
#include "ni_reg.h"
2004 serge 35
#include "cayman_blit_shaders.h"
1990 serge 36
 
37
extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
38
extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
39
extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
40
extern void evergreen_mc_program(struct radeon_device *rdev);
41
extern void evergreen_irq_suspend(struct radeon_device *rdev);
42
extern int evergreen_mc_init(struct radeon_device *rdev);
2997 Serge 43
extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
44
extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
45
extern void si_rlc_fini(struct radeon_device *rdev);
46
extern int si_rlc_init(struct radeon_device *rdev);
1990 serge 47
 
48
#define EVERGREEN_PFP_UCODE_SIZE 1120
49
#define EVERGREEN_PM4_UCODE_SIZE 1376
50
#define EVERGREEN_RLC_UCODE_SIZE 768
51
#define BTC_MC_UCODE_SIZE 6024
52
 
53
#define CAYMAN_PFP_UCODE_SIZE 2176
54
#define CAYMAN_PM4_UCODE_SIZE 2176
55
#define CAYMAN_RLC_UCODE_SIZE 1024
56
#define CAYMAN_MC_UCODE_SIZE 6037
57
 
2997 Serge 58
#define ARUBA_RLC_UCODE_SIZE 1536
59
 
1990 serge 60
/* Firmware Names */
61
MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
62
MODULE_FIRMWARE("radeon/BARTS_me.bin");
63
MODULE_FIRMWARE("radeon/BARTS_mc.bin");
64
MODULE_FIRMWARE("radeon/BTC_rlc.bin");
65
MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
66
MODULE_FIRMWARE("radeon/TURKS_me.bin");
67
MODULE_FIRMWARE("radeon/TURKS_mc.bin");
68
MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
69
MODULE_FIRMWARE("radeon/CAICOS_me.bin");
70
MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
71
MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
72
MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
73
MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
74
MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
2997 Serge 75
MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
76
MODULE_FIRMWARE("radeon/ARUBA_me.bin");
77
MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
1990 serge 78
 
79
#define BTC_IO_MC_REGS_SIZE 29
80
 
81
static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
82
	{0x00000077, 0xff010100},
83
	{0x00000078, 0x00000000},
84
	{0x00000079, 0x00001434},
85
	{0x0000007a, 0xcc08ec08},
86
	{0x0000007b, 0x00040000},
87
	{0x0000007c, 0x000080c0},
88
	{0x0000007d, 0x09000000},
89
	{0x0000007e, 0x00210404},
90
	{0x00000081, 0x08a8e800},
91
	{0x00000082, 0x00030444},
92
	{0x00000083, 0x00000000},
93
	{0x00000085, 0x00000001},
94
	{0x00000086, 0x00000002},
95
	{0x00000087, 0x48490000},
96
	{0x00000088, 0x20244647},
97
	{0x00000089, 0x00000005},
98
	{0x0000008b, 0x66030000},
99
	{0x0000008c, 0x00006603},
100
	{0x0000008d, 0x00000100},
101
	{0x0000008f, 0x00001c0a},
102
	{0x00000090, 0xff000001},
103
	{0x00000094, 0x00101101},
104
	{0x00000095, 0x00000fff},
105
	{0x00000096, 0x00116fff},
106
	{0x00000097, 0x60010000},
107
	{0x00000098, 0x10010000},
108
	{0x00000099, 0x00006000},
109
	{0x0000009a, 0x00001000},
110
	{0x0000009f, 0x00946a00}
111
};
112
 
113
static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
114
	{0x00000077, 0xff010100},
115
	{0x00000078, 0x00000000},
116
	{0x00000079, 0x00001434},
117
	{0x0000007a, 0xcc08ec08},
118
	{0x0000007b, 0x00040000},
119
	{0x0000007c, 0x000080c0},
120
	{0x0000007d, 0x09000000},
121
	{0x0000007e, 0x00210404},
122
	{0x00000081, 0x08a8e800},
123
	{0x00000082, 0x00030444},
124
	{0x00000083, 0x00000000},
125
	{0x00000085, 0x00000001},
126
	{0x00000086, 0x00000002},
127
	{0x00000087, 0x48490000},
128
	{0x00000088, 0x20244647},
129
	{0x00000089, 0x00000005},
130
	{0x0000008b, 0x66030000},
131
	{0x0000008c, 0x00006603},
132
	{0x0000008d, 0x00000100},
133
	{0x0000008f, 0x00001c0a},
134
	{0x00000090, 0xff000001},
135
	{0x00000094, 0x00101101},
136
	{0x00000095, 0x00000fff},
137
	{0x00000096, 0x00116fff},
138
	{0x00000097, 0x60010000},
139
	{0x00000098, 0x10010000},
140
	{0x00000099, 0x00006000},
141
	{0x0000009a, 0x00001000},
142
	{0x0000009f, 0x00936a00}
143
};
144
 
145
static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
146
	{0x00000077, 0xff010100},
147
	{0x00000078, 0x00000000},
148
	{0x00000079, 0x00001434},
149
	{0x0000007a, 0xcc08ec08},
150
	{0x0000007b, 0x00040000},
151
	{0x0000007c, 0x000080c0},
152
	{0x0000007d, 0x09000000},
153
	{0x0000007e, 0x00210404},
154
	{0x00000081, 0x08a8e800},
155
	{0x00000082, 0x00030444},
156
	{0x00000083, 0x00000000},
157
	{0x00000085, 0x00000001},
158
	{0x00000086, 0x00000002},
159
	{0x00000087, 0x48490000},
160
	{0x00000088, 0x20244647},
161
	{0x00000089, 0x00000005},
162
	{0x0000008b, 0x66030000},
163
	{0x0000008c, 0x00006603},
164
	{0x0000008d, 0x00000100},
165
	{0x0000008f, 0x00001c0a},
166
	{0x00000090, 0xff000001},
167
	{0x00000094, 0x00101101},
168
	{0x00000095, 0x00000fff},
169
	{0x00000096, 0x00116fff},
170
	{0x00000097, 0x60010000},
171
	{0x00000098, 0x10010000},
172
	{0x00000099, 0x00006000},
173
	{0x0000009a, 0x00001000},
174
	{0x0000009f, 0x00916a00}
175
};
176
 
177
static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
178
	{0x00000077, 0xff010100},
179
	{0x00000078, 0x00000000},
180
	{0x00000079, 0x00001434},
181
	{0x0000007a, 0xcc08ec08},
182
	{0x0000007b, 0x00040000},
183
	{0x0000007c, 0x000080c0},
184
	{0x0000007d, 0x09000000},
185
	{0x0000007e, 0x00210404},
186
	{0x00000081, 0x08a8e800},
187
	{0x00000082, 0x00030444},
188
	{0x00000083, 0x00000000},
189
	{0x00000085, 0x00000001},
190
	{0x00000086, 0x00000002},
191
	{0x00000087, 0x48490000},
192
	{0x00000088, 0x20244647},
193
	{0x00000089, 0x00000005},
194
	{0x0000008b, 0x66030000},
195
	{0x0000008c, 0x00006603},
196
	{0x0000008d, 0x00000100},
197
	{0x0000008f, 0x00001c0a},
198
	{0x00000090, 0xff000001},
199
	{0x00000094, 0x00101101},
200
	{0x00000095, 0x00000fff},
201
	{0x00000096, 0x00116fff},
202
	{0x00000097, 0x60010000},
203
	{0x00000098, 0x10010000},
204
	{0x00000099, 0x00006000},
205
	{0x0000009a, 0x00001000},
206
	{0x0000009f, 0x00976b00}
207
};
208
 
209
int ni_mc_load_microcode(struct radeon_device *rdev)
210
{
211
	const __be32 *fw_data;
212
	u32 mem_type, running, blackout = 0;
213
	u32 *io_mc_regs;
214
	int i, ucode_size, regs_size;
215
 
216
	if (!rdev->mc_fw)
217
		return -EINVAL;
218
 
219
	switch (rdev->family) {
220
	case CHIP_BARTS:
221
		io_mc_regs = (u32 *)&barts_io_mc_regs;
222
		ucode_size = BTC_MC_UCODE_SIZE;
223
		regs_size = BTC_IO_MC_REGS_SIZE;
224
		break;
225
	case CHIP_TURKS:
226
		io_mc_regs = (u32 *)&turks_io_mc_regs;
227
		ucode_size = BTC_MC_UCODE_SIZE;
228
		regs_size = BTC_IO_MC_REGS_SIZE;
229
		break;
230
	case CHIP_CAICOS:
231
	default:
232
		io_mc_regs = (u32 *)&caicos_io_mc_regs;
233
		ucode_size = BTC_MC_UCODE_SIZE;
234
		regs_size = BTC_IO_MC_REGS_SIZE;
235
		break;
236
	case CHIP_CAYMAN:
237
		io_mc_regs = (u32 *)&cayman_io_mc_regs;
238
		ucode_size = CAYMAN_MC_UCODE_SIZE;
239
		regs_size = BTC_IO_MC_REGS_SIZE;
240
		break;
241
	}
242
 
243
	mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
244
	running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
245
 
246
	if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
247
		if (running) {
248
			blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
249
			WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
250
		}
251
 
252
		/* reset the engine and set to writable */
253
		WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
254
		WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
255
 
256
		/* load mc io regs */
257
		for (i = 0; i < regs_size; i++) {
258
			WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
259
			WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
260
		}
261
		/* load the MC ucode */
262
		fw_data = (const __be32 *)rdev->mc_fw->data;
263
		for (i = 0; i < ucode_size; i++)
264
			WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
265
 
266
		/* put the engine back into the active state */
267
		WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
268
		WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
269
		WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
270
 
271
		/* wait for training to complete */
2997 Serge 272
		for (i = 0; i < rdev->usec_timeout; i++) {
273
			if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
274
				break;
275
			udelay(1);
276
		}
1990 serge 277
 
278
		if (running)
279
			WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
280
	}
281
 
282
	return 0;
283
}
284
 
285
int ni_init_microcode(struct radeon_device *rdev)
286
{
287
	struct platform_device *pdev;
288
	const char *chip_name;
289
	const char *rlc_chip_name;
290
	size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
291
	char fw_name[30];
292
	int err;
293
 
294
	DRM_DEBUG("\n");
295
 
296
	pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
297
	err = IS_ERR(pdev);
298
	if (err) {
299
		printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
300
		return -EINVAL;
301
	}
302
 
303
	switch (rdev->family) {
304
	case CHIP_BARTS:
305
		chip_name = "BARTS";
306
		rlc_chip_name = "BTC";
307
		pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
308
		me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
309
		rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
310
		mc_req_size = BTC_MC_UCODE_SIZE * 4;
311
		break;
312
	case CHIP_TURKS:
313
		chip_name = "TURKS";
314
		rlc_chip_name = "BTC";
315
		pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
316
		me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
317
		rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
318
		mc_req_size = BTC_MC_UCODE_SIZE * 4;
319
		break;
320
	case CHIP_CAICOS:
321
		chip_name = "CAICOS";
322
		rlc_chip_name = "BTC";
323
		pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
324
		me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
325
		rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
326
		mc_req_size = BTC_MC_UCODE_SIZE * 4;
327
		break;
328
	case CHIP_CAYMAN:
329
		chip_name = "CAYMAN";
330
		rlc_chip_name = "CAYMAN";
331
		pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
332
		me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
333
		rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
334
		mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
335
		break;
2997 Serge 336
	case CHIP_ARUBA:
337
		chip_name = "ARUBA";
338
		rlc_chip_name = "ARUBA";
339
		/* pfp/me same size as CAYMAN */
340
		pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
341
		me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
342
		rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
343
		mc_req_size = 0;
344
		break;
1990 serge 345
	default: BUG();
346
	}
347
 
348
	DRM_INFO("Loading %s Microcode\n", chip_name);
349
 
350
	snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
351
	err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
352
	if (err)
353
		goto out;
354
	if (rdev->pfp_fw->size != pfp_req_size) {
355
		printk(KERN_ERR
356
		       "ni_cp: Bogus length %zu in firmware \"%s\"\n",
357
		       rdev->pfp_fw->size, fw_name);
358
		err = -EINVAL;
359
		goto out;
360
	}
361
 
362
	snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
363
	err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
364
	if (err)
365
		goto out;
366
	if (rdev->me_fw->size != me_req_size) {
367
		printk(KERN_ERR
368
		       "ni_cp: Bogus length %zu in firmware \"%s\"\n",
369
		       rdev->me_fw->size, fw_name);
370
		err = -EINVAL;
371
	}
372
 
373
	snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
374
	err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
375
	if (err)
376
		goto out;
377
	if (rdev->rlc_fw->size != rlc_req_size) {
378
		printk(KERN_ERR
379
		       "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
380
		       rdev->rlc_fw->size, fw_name);
381
		err = -EINVAL;
382
	}
383
 
2997 Serge 384
	/* no MC ucode on TN */
385
	if (!(rdev->flags & RADEON_IS_IGP)) {
1990 serge 386
	snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
387
	err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
388
	if (err)
389
		goto out;
390
	if (rdev->mc_fw->size != mc_req_size) {
391
		printk(KERN_ERR
392
		       "ni_mc: Bogus length %zu in firmware \"%s\"\n",
393
		       rdev->mc_fw->size, fw_name);
394
		err = -EINVAL;
395
	}
2997 Serge 396
	}
1990 serge 397
out:
398
	platform_device_unregister(pdev);
399
 
400
	if (err) {
401
		if (err != -EINVAL)
402
			printk(KERN_ERR
403
			       "ni_cp: Failed to load firmware \"%s\"\n",
404
			       fw_name);
405
		release_firmware(rdev->pfp_fw);
406
		rdev->pfp_fw = NULL;
407
		release_firmware(rdev->me_fw);
408
		rdev->me_fw = NULL;
409
		release_firmware(rdev->rlc_fw);
410
		rdev->rlc_fw = NULL;
411
		release_firmware(rdev->mc_fw);
412
		rdev->mc_fw = NULL;
413
	}
414
	return err;
415
}
416
 
417
/*
418
 * Core functions
419
 */
420
static void cayman_gpu_init(struct radeon_device *rdev)
421
{
422
	u32 gb_addr_config = 0;
423
	u32 mc_shared_chmap, mc_arb_ramcfg;
424
	u32 cgts_tcc_disable;
425
	u32 sx_debug_1;
426
	u32 smx_dc_ctl0;
427
	u32 cgts_sm_ctrl_reg;
428
	u32 hdp_host_path_cntl;
429
	u32 tmp;
2997 Serge 430
	u32 disabled_rb_mask;
1990 serge 431
	int i, j;
432
 
433
	switch (rdev->family) {
434
	case CHIP_CAYMAN:
435
		rdev->config.cayman.max_shader_engines = 2;
436
		rdev->config.cayman.max_pipes_per_simd = 4;
437
		rdev->config.cayman.max_tile_pipes = 8;
438
		rdev->config.cayman.max_simds_per_se = 12;
439
		rdev->config.cayman.max_backends_per_se = 4;
440
		rdev->config.cayman.max_texture_channel_caches = 8;
441
		rdev->config.cayman.max_gprs = 256;
442
		rdev->config.cayman.max_threads = 256;
443
		rdev->config.cayman.max_gs_threads = 32;
444
		rdev->config.cayman.max_stack_entries = 512;
445
		rdev->config.cayman.sx_num_of_sets = 8;
446
		rdev->config.cayman.sx_max_export_size = 256;
447
		rdev->config.cayman.sx_max_export_pos_size = 64;
448
		rdev->config.cayman.sx_max_export_smx_size = 192;
449
		rdev->config.cayman.max_hw_contexts = 8;
450
		rdev->config.cayman.sq_num_cf_insts = 2;
451
 
452
		rdev->config.cayman.sc_prim_fifo_size = 0x100;
453
		rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
454
		rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
2997 Serge 455
		gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
1990 serge 456
		break;
2997 Serge 457
	case CHIP_ARUBA:
458
	default:
459
		rdev->config.cayman.max_shader_engines = 1;
460
		rdev->config.cayman.max_pipes_per_simd = 4;
461
		rdev->config.cayman.max_tile_pipes = 2;
462
		if ((rdev->pdev->device == 0x9900) ||
463
		    (rdev->pdev->device == 0x9901) ||
464
		    (rdev->pdev->device == 0x9905) ||
465
		    (rdev->pdev->device == 0x9906) ||
466
		    (rdev->pdev->device == 0x9907) ||
467
		    (rdev->pdev->device == 0x9908) ||
468
		    (rdev->pdev->device == 0x9909) ||
469
		    (rdev->pdev->device == 0x9910) ||
470
		    (rdev->pdev->device == 0x9917)) {
471
			rdev->config.cayman.max_simds_per_se = 6;
472
			rdev->config.cayman.max_backends_per_se = 2;
473
		} else if ((rdev->pdev->device == 0x9903) ||
474
			   (rdev->pdev->device == 0x9904) ||
475
			   (rdev->pdev->device == 0x990A) ||
476
			   (rdev->pdev->device == 0x9913) ||
477
			   (rdev->pdev->device == 0x9918)) {
478
			rdev->config.cayman.max_simds_per_se = 4;
479
			rdev->config.cayman.max_backends_per_se = 2;
480
		} else if ((rdev->pdev->device == 0x9919) ||
481
			   (rdev->pdev->device == 0x9990) ||
482
			   (rdev->pdev->device == 0x9991) ||
483
			   (rdev->pdev->device == 0x9994) ||
484
			   (rdev->pdev->device == 0x99A0)) {
485
			rdev->config.cayman.max_simds_per_se = 3;
486
			rdev->config.cayman.max_backends_per_se = 1;
487
		} else {
488
			rdev->config.cayman.max_simds_per_se = 2;
489
			rdev->config.cayman.max_backends_per_se = 1;
490
		}
491
		rdev->config.cayman.max_texture_channel_caches = 2;
492
		rdev->config.cayman.max_gprs = 256;
493
		rdev->config.cayman.max_threads = 256;
494
		rdev->config.cayman.max_gs_threads = 32;
495
		rdev->config.cayman.max_stack_entries = 512;
496
		rdev->config.cayman.sx_num_of_sets = 8;
497
		rdev->config.cayman.sx_max_export_size = 256;
498
		rdev->config.cayman.sx_max_export_pos_size = 64;
499
		rdev->config.cayman.sx_max_export_smx_size = 192;
500
		rdev->config.cayman.max_hw_contexts = 8;
501
		rdev->config.cayman.sq_num_cf_insts = 2;
502
 
503
		rdev->config.cayman.sc_prim_fifo_size = 0x40;
504
		rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
505
		rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
506
		gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
507
		break;
1990 serge 508
	}
509
 
510
	/* Initialize HDP */
511
	for (i = 0, j = 0; i < 32; i++, j += 0x18) {
512
		WREG32((0x2c14 + j), 0x00000000);
513
		WREG32((0x2c18 + j), 0x00000000);
514
		WREG32((0x2c1c + j), 0x00000000);
515
		WREG32((0x2c20 + j), 0x00000000);
516
		WREG32((0x2c24 + j), 0x00000000);
517
	}
518
 
519
	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
520
 
2997 Serge 521
	evergreen_fix_pci_max_read_req_size(rdev);
522
 
1990 serge 523
	mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
524
	mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
525
 
526
	tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
527
	rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
528
	if (rdev->config.cayman.mem_row_size_in_kb > 4)
529
		rdev->config.cayman.mem_row_size_in_kb = 4;
530
	/* XXX use MC settings? */
531
	rdev->config.cayman.shader_engine_tile_size = 32;
532
	rdev->config.cayman.num_gpus = 1;
533
	rdev->config.cayman.multi_gpu_tile_size = 64;
534
 
535
	tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
536
	rdev->config.cayman.num_tile_pipes = (1 << tmp);
537
	tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
538
	rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
539
	tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
540
	rdev->config.cayman.num_shader_engines = tmp + 1;
541
	tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
542
	rdev->config.cayman.num_gpus = tmp + 1;
543
	tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
544
	rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
545
	tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
546
	rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
547
 
2997 Serge 548
 
1990 serge 549
	/* setup tiling info dword.  gb_addr_config is not adequate since it does
550
	 * not have bank info, so create a custom tiling dword.
551
	 * bits 3:0   num_pipes
552
	 * bits 7:4   num_banks
553
	 * bits 11:8  group_size
554
	 * bits 15:12 row_size
555
	 */
556
	rdev->config.cayman.tile_config = 0;
557
	switch (rdev->config.cayman.num_tile_pipes) {
558
	case 1:
559
	default:
560
		rdev->config.cayman.tile_config |= (0 << 0);
561
		break;
562
	case 2:
563
		rdev->config.cayman.tile_config |= (1 << 0);
564
		break;
565
	case 4:
566
		rdev->config.cayman.tile_config |= (2 << 0);
567
		break;
568
	case 8:
569
		rdev->config.cayman.tile_config |= (3 << 0);
570
		break;
571
	}
2997 Serge 572
 
573
	/* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
574
	if (rdev->flags & RADEON_IS_IGP)
575
		rdev->config.cayman.tile_config |= 1 << 4;
576
	else {
577
		switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
578
		case 0: /* four banks */
579
			rdev->config.cayman.tile_config |= 0 << 4;
580
			break;
581
		case 1: /* eight banks */
582
			rdev->config.cayman.tile_config |= 1 << 4;
583
			break;
584
		case 2: /* sixteen banks */
585
		default:
586
			rdev->config.cayman.tile_config |= 2 << 4;
587
			break;
588
		}
589
	}
1990 serge 590
	rdev->config.cayman.tile_config |=
591
		((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
592
	rdev->config.cayman.tile_config |=
593
		((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
594
 
2997 Serge 595
	tmp = 0;
596
	for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
597
		u32 rb_disable_bitmap;
598
 
599
		WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
600
		WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
601
		rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
602
		tmp <<= 4;
603
		tmp |= rb_disable_bitmap;
604
	}
605
	/* enabled rb are just the one not disabled :) */
606
	disabled_rb_mask = tmp;
607
 
608
	WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
609
	WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
610
 
1990 serge 611
	WREG32(GB_ADDR_CONFIG, gb_addr_config);
612
	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
613
	WREG32(HDP_ADDR_CONFIG, gb_addr_config);
3192 Serge 614
	WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
615
	WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1990 serge 616
 
2997 Serge 617
	tmp = gb_addr_config & NUM_PIPES_MASK;
618
	tmp = r6xx_remap_render_backend(rdev, tmp,
619
					rdev->config.cayman.max_backends_per_se *
620
					rdev->config.cayman.max_shader_engines,
621
					CAYMAN_MAX_BACKENDS, disabled_rb_mask);
622
	WREG32(GB_BACKEND_MAP, tmp);
1990 serge 623
 
2997 Serge 624
	cgts_tcc_disable = 0xffff0000;
625
	for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
626
		cgts_tcc_disable &= ~(1 << (16 + i));
1990 serge 627
	WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
628
	WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
629
	WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
630
	WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
631
 
632
	/* reprogram the shader complex */
633
	cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
634
	for (i = 0; i < 16; i++)
635
		WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
636
	WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
637
 
638
	/* set HW defaults for 3D engine */
639
	WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
640
 
641
	sx_debug_1 = RREG32(SX_DEBUG_1);
642
	sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
643
	WREG32(SX_DEBUG_1, sx_debug_1);
644
 
645
	smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
646
	smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
647
	smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
648
	WREG32(SMX_DC_CTL0, smx_dc_ctl0);
649
 
650
	WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
651
 
652
	/* need to be explicitly zero-ed */
653
	WREG32(VGT_OFFCHIP_LDS_BASE, 0);
654
	WREG32(SQ_LSTMP_RING_BASE, 0);
655
	WREG32(SQ_HSTMP_RING_BASE, 0);
656
	WREG32(SQ_ESTMP_RING_BASE, 0);
657
	WREG32(SQ_GSTMP_RING_BASE, 0);
658
	WREG32(SQ_VSTMP_RING_BASE, 0);
659
	WREG32(SQ_PSTMP_RING_BASE, 0);
660
 
661
	WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
662
 
663
	WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
664
					POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
665
					SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
666
 
667
	WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
668
				 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
669
				 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
670
 
671
 
672
	WREG32(VGT_NUM_INSTANCES, 1);
673
 
674
	WREG32(CP_PERFMON_CNTL, 0);
675
 
676
	WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
677
				  FETCH_FIFO_HIWATER(0x4) |
678
				  DONE_FIFO_HIWATER(0xe0) |
679
				  ALU_UPDATE_FIFO_HIWATER(0x8)));
680
 
681
	WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
682
	WREG32(SQ_CONFIG, (VC_ENABLE |
683
			   EXPORT_SRC_C |
684
			   GFX_PRIO(0) |
685
			   CS1_PRIO(0) |
686
			   CS2_PRIO(1)));
687
	WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
688
 
689
	WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
690
					  FORCE_EOV_MAX_REZ_CNT(255)));
691
 
692
	WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
693
	       AUTO_INVLD_EN(ES_AND_GS_AUTO));
694
 
695
	WREG32(VGT_GS_VERTEX_REUSE, 16);
696
	WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
697
 
698
	WREG32(CB_PERF_CTR0_SEL_0, 0);
699
	WREG32(CB_PERF_CTR0_SEL_1, 0);
700
	WREG32(CB_PERF_CTR1_SEL_0, 0);
701
	WREG32(CB_PERF_CTR1_SEL_1, 0);
702
	WREG32(CB_PERF_CTR2_SEL_0, 0);
703
	WREG32(CB_PERF_CTR2_SEL_1, 0);
704
	WREG32(CB_PERF_CTR3_SEL_0, 0);
705
	WREG32(CB_PERF_CTR3_SEL_1, 0);
706
 
707
	tmp = RREG32(HDP_MISC_CNTL);
708
	tmp |= HDP_FLUSH_INVALIDATE_CACHE;
709
	WREG32(HDP_MISC_CNTL, tmp);
710
 
711
	hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
712
	WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
713
 
714
	WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
715
 
716
	udelay(50);
717
}
718
 
719
/*
720
 * GART
721
 */
722
void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
723
{
724
	/* flush hdp cache */
725
	WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
726
 
727
	/* bits 0-7 are the VM contexts0-7 */
728
	WREG32(VM_INVALIDATE_REQUEST, 1);
729
}
730
 
2997 Serge 731
static int cayman_pcie_gart_enable(struct radeon_device *rdev)
1990 serge 732
{
2997 Serge 733
	int i, r;
1990 serge 734
 
2997 Serge 735
	if (rdev->gart.robj == NULL) {
1990 serge 736
		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
737
		return -EINVAL;
738
	}
739
	r = radeon_gart_table_vram_pin(rdev);
740
	if (r)
741
		return r;
742
	radeon_gart_restore(rdev);
743
	/* Setup TLB control */
2997 Serge 744
	WREG32(MC_VM_MX_L1_TLB_CNTL,
745
	       (0xA << 7) |
746
	       ENABLE_L1_TLB |
1990 serge 747
	       ENABLE_L1_FRAGMENT_PROCESSING |
748
	       SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2997 Serge 749
	       ENABLE_ADVANCED_DRIVER_MODEL |
1990 serge 750
	       SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
751
	/* Setup L2 cache */
752
	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
753
	       ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
754
	       ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
755
	       EFFECTIVE_L2_QUEUE_SIZE(7) |
756
	       CONTEXT1_IDENTITY_ACCESS_MODE(1));
757
	WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
758
	WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
759
	       L2_CACHE_BIGK_FRAGMENT_SIZE(6));
760
	/* setup context0 */
761
	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
762
	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
763
	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
764
	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
765
			(u32)(rdev->dummy_page.addr >> 12));
766
	WREG32(VM_CONTEXT0_CNTL2, 0);
767
	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
768
				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
2997 Serge 769
 
770
	WREG32(0x15D4, 0);
771
	WREG32(0x15D8, 0);
772
	WREG32(0x15DC, 0);
773
 
774
	/* empty context1-7 */
775
	/* Assign the pt base to something valid for now; the pts used for
776
	 * the VMs are determined by the application and setup and assigned
777
	 * on the fly in the vm part of radeon_gart.c
778
	 */
779
	for (i = 1; i < 8; i++) {
780
		WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
781
		WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
782
		WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
783
			rdev->gart.table_addr >> 12);
784
	}
785
 
786
	/* enable context1-7 */
787
	WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
788
	       (u32)(rdev->dummy_page.addr >> 12));
3192 Serge 789
	WREG32(VM_CONTEXT1_CNTL2, 4);
2997 Serge 790
	WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
3192 Serge 791
				RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
792
				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
793
				DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
794
				DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
795
				PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
796
				PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
797
				VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
798
				VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
799
				READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
800
				READ_PROTECTION_FAULT_ENABLE_DEFAULT |
801
				WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
802
				WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
1990 serge 803
 
804
	cayman_pcie_gart_tlb_flush(rdev);
2997 Serge 805
	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
806
		 (unsigned)(rdev->mc.gtt_size >> 20),
807
		 (unsigned long long)rdev->gart.table_addr);
1990 serge 808
	rdev->gart.ready = true;
809
	return 0;
810
}
811
 
2997 Serge 812
static void cayman_pcie_gart_disable(struct radeon_device *rdev)
1990 serge 813
{
814
	/* Disable all tables */
815
	WREG32(VM_CONTEXT0_CNTL, 0);
816
	WREG32(VM_CONTEXT1_CNTL, 0);
817
	/* Setup TLB control */
818
	WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
819
	       SYSTEM_ACCESS_MODE_NOT_IN_SYS |
820
	       SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
821
	/* Setup L2 cache */
822
	WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
823
	       ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
824
	       EFFECTIVE_L2_QUEUE_SIZE(7) |
825
	       CONTEXT1_IDENTITY_ACCESS_MODE(1));
826
	WREG32(VM_L2_CNTL2, 0);
827
	WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
828
	       L2_CACHE_BIGK_FRAGMENT_SIZE(6));
2997 Serge 829
	radeon_gart_table_vram_unpin(rdev);
1990 serge 830
}
831
 
2997 Serge 832
void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
833
			      int ring, u32 cp_int_cntl)
834
{
835
	u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
1990 serge 836
 
2997 Serge 837
	WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
838
	WREG32(CP_INT_CNTL, cp_int_cntl);
839
}
840
 
1990 serge 841
/*
842
 * CP.
843
 */
2997 Serge 844
void cayman_fence_ring_emit(struct radeon_device *rdev,
845
			    struct radeon_fence *fence)
846
{
847
	struct radeon_ring *ring = &rdev->ring[fence->ring];
848
	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
849
 
850
	/* flush read cache over gart for this vmid */
851
	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
852
	radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
853
	radeon_ring_write(ring, 0);
854
	radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
855
	radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
856
	radeon_ring_write(ring, 0xFFFFFFFF);
857
	radeon_ring_write(ring, 0);
858
	radeon_ring_write(ring, 10); /* poll interval */
859
	/* EVENT_WRITE_EOP - flush caches, send int */
860
	radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
861
	radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
862
	radeon_ring_write(ring, addr & 0xffffffff);
863
	radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
864
	radeon_ring_write(ring, fence->seq);
865
	radeon_ring_write(ring, 0);
866
}
867
 
868
void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
869
{
870
	struct radeon_ring *ring = &rdev->ring[ib->ring];
871
 
872
	/* set to DX10/11 mode */
873
	radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
874
	radeon_ring_write(ring, 1);
875
 
876
	if (ring->rptr_save_reg) {
877
		uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
878
		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
879
		radeon_ring_write(ring, ((ring->rptr_save_reg -
880
					  PACKET3_SET_CONFIG_REG_START) >> 2));
881
		radeon_ring_write(ring, next_rptr);
882
	}
883
 
884
	radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
885
	radeon_ring_write(ring,
886
#ifdef __BIG_ENDIAN
887
			  (2 << 0) |
888
#endif
889
			  (ib->gpu_addr & 0xFFFFFFFC));
890
	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
891
	radeon_ring_write(ring, ib->length_dw |
892
			  (ib->vm ? (ib->vm->id << 24) : 0));
893
 
894
	/* flush read cache over gart for this vmid */
895
	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
896
	radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
897
	radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
898
	radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
899
	radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
900
	radeon_ring_write(ring, 0xFFFFFFFF);
901
	radeon_ring_write(ring, 0);
902
	radeon_ring_write(ring, 10); /* poll interval */
903
}
904
 
1990 serge 905
static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
906
{
907
	if (enable)
908
		WREG32(CP_ME_CNTL, 0);
909
	else {
3192 Serge 910
		radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1990 serge 911
		WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
912
		WREG32(SCRATCH_UMSK, 0);
3192 Serge 913
		rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1990 serge 914
	}
915
}
916
 
917
static int cayman_cp_load_microcode(struct radeon_device *rdev)
918
{
919
	const __be32 *fw_data;
920
	int i;
921
 
922
	if (!rdev->me_fw || !rdev->pfp_fw)
923
		return -EINVAL;
924
 
925
	cayman_cp_enable(rdev, false);
926
 
927
	fw_data = (const __be32 *)rdev->pfp_fw->data;
928
	WREG32(CP_PFP_UCODE_ADDR, 0);
929
	for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
930
		WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
931
	WREG32(CP_PFP_UCODE_ADDR, 0);
932
 
933
	fw_data = (const __be32 *)rdev->me_fw->data;
934
	WREG32(CP_ME_RAM_WADDR, 0);
935
	for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
936
		WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
937
 
938
	WREG32(CP_PFP_UCODE_ADDR, 0);
939
	WREG32(CP_ME_RAM_WADDR, 0);
940
	WREG32(CP_ME_RAM_RADDR, 0);
941
	return 0;
942
}
943
 
944
static int cayman_cp_start(struct radeon_device *rdev)
945
{
2997 Serge 946
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1990 serge 947
	int r, i;
948
 
2997 Serge 949
	r = radeon_ring_lock(rdev, ring, 7);
1990 serge 950
	if (r) {
951
		DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
952
		return r;
953
	}
2997 Serge 954
	radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
955
	radeon_ring_write(ring, 0x1);
956
	radeon_ring_write(ring, 0x0);
957
	radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
958
	radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
959
	radeon_ring_write(ring, 0);
960
	radeon_ring_write(ring, 0);
961
	radeon_ring_unlock_commit(rdev, ring);
1990 serge 962
 
963
	cayman_cp_enable(rdev, true);
964
 
2997 Serge 965
	r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1990 serge 966
	if (r) {
967
		DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
968
		return r;
969
	}
970
 
971
	/* setup clear context state */
2997 Serge 972
	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
973
	radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1990 serge 974
 
975
	for (i = 0; i < cayman_default_size; i++)
2997 Serge 976
		radeon_ring_write(ring, cayman_default_state[i]);
1990 serge 977
 
2997 Serge 978
	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
979
	radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1990 serge 980
 
981
	/* set clear context state */
2997 Serge 982
	radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
983
	radeon_ring_write(ring, 0);
1990 serge 984
 
985
	/* SQ_VTX_BASE_VTX_LOC */
2997 Serge 986
	radeon_ring_write(ring, 0xc0026f00);
987
	radeon_ring_write(ring, 0x00000000);
988
	radeon_ring_write(ring, 0x00000000);
989
	radeon_ring_write(ring, 0x00000000);
1990 serge 990
 
991
	/* Clear consts */
2997 Serge 992
	radeon_ring_write(ring, 0xc0036f00);
993
	radeon_ring_write(ring, 0x00000bc4);
994
	radeon_ring_write(ring, 0xffffffff);
995
	radeon_ring_write(ring, 0xffffffff);
996
	radeon_ring_write(ring, 0xffffffff);
1990 serge 997
 
2997 Serge 998
	radeon_ring_write(ring, 0xc0026900);
999
	radeon_ring_write(ring, 0x00000316);
1000
	radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1001
	radeon_ring_write(ring, 0x00000010); /*  */
1990 serge 1002
 
2997 Serge 1003
	radeon_ring_unlock_commit(rdev, ring);
1990 serge 1004
 
1005
	/* XXX init other rings */
1006
 
1007
	return 0;
1008
}
1009
 
1010
 
2997 Serge 1011
static int cayman_cp_resume(struct radeon_device *rdev)
1990 serge 1012
{
2997 Serge 1013
	static const int ridx[] = {
1014
		RADEON_RING_TYPE_GFX_INDEX,
1015
		CAYMAN_RING_TYPE_CP1_INDEX,
1016
		CAYMAN_RING_TYPE_CP2_INDEX
1017
	};
1018
	static const unsigned cp_rb_cntl[] = {
1019
		CP_RB0_CNTL,
1020
		CP_RB1_CNTL,
1021
		CP_RB2_CNTL,
1022
	};
1023
	static const unsigned cp_rb_rptr_addr[] = {
1024
		CP_RB0_RPTR_ADDR,
1025
		CP_RB1_RPTR_ADDR,
1026
		CP_RB2_RPTR_ADDR
1027
	};
1028
	static const unsigned cp_rb_rptr_addr_hi[] = {
1029
		CP_RB0_RPTR_ADDR_HI,
1030
		CP_RB1_RPTR_ADDR_HI,
1031
		CP_RB2_RPTR_ADDR_HI
1032
	};
1033
	static const unsigned cp_rb_base[] = {
1034
		CP_RB0_BASE,
1035
		CP_RB1_BASE,
1036
		CP_RB2_BASE
1037
	};
1038
	struct radeon_ring *ring;
1039
	int i, r;
1990 serge 1040
 
1041
	/* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1042
	WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1043
				 SOFT_RESET_PA |
1044
				 SOFT_RESET_SH |
1045
				 SOFT_RESET_VGT |
2160 serge 1046
				 SOFT_RESET_SPI |
1990 serge 1047
				 SOFT_RESET_SX));
1048
	RREG32(GRBM_SOFT_RESET);
1049
	mdelay(15);
1050
	WREG32(GRBM_SOFT_RESET, 0);
1051
	RREG32(GRBM_SOFT_RESET);
1052
 
2997 Serge 1053
	WREG32(CP_SEM_WAIT_TIMER, 0x0);
1054
	WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1990 serge 1055
 
1056
	/* Set the write pointer delay */
1057
	WREG32(CP_RB_WPTR_DELAY, 0);
1058
 
1059
	WREG32(CP_DEBUG, (1 << 27));
1060
 
3120 serge 1061
	/* set the wb address whether it's enabled or not */
1990 serge 1062
	WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1063
		WREG32(SCRATCH_UMSK, 0xff);
1064
 
2997 Serge 1065
	for (i = 0; i < 3; ++i) {
1066
		uint32_t rb_cntl;
1067
		uint64_t addr;
1990 serge 1068
 
1069
	/* Set ring buffer size */
2997 Serge 1070
		ring = &rdev->ring[ridx[i]];
1071
		rb_cntl = drm_order(ring->ring_size / 8);
1072
		rb_cntl |= drm_order(RADEON_GPU_PAGE_SIZE/8) << 8;
1990 serge 1073
#ifdef __BIG_ENDIAN
2997 Serge 1074
		rb_cntl |= BUF_SWAP_32BIT;
1990 serge 1075
#endif
2997 Serge 1076
		WREG32(cp_rb_cntl[i], rb_cntl);
1990 serge 1077
 
3120 serge 1078
		/* set the wb address whether it's enabled or not */
2997 Serge 1079
		addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1080
		WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1081
		WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1082
	}
1990 serge 1083
 
2997 Serge 1084
	/* set the rb base addr, this causes an internal reset of ALL rings */
1085
	for (i = 0; i < 3; ++i) {
1086
		ring = &rdev->ring[ridx[i]];
1087
		WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1088
	}
1990 serge 1089
 
2997 Serge 1090
	for (i = 0; i < 3; ++i) {
1990 serge 1091
	/* Initialize the ring buffer's read and write pointers */
2997 Serge 1092
		ring = &rdev->ring[ridx[i]];
1093
		WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1990 serge 1094
 
2997 Serge 1095
		ring->rptr = ring->wptr = 0;
1096
		WREG32(ring->rptr_reg, ring->rptr);
1097
		WREG32(ring->wptr_reg, ring->wptr);
1990 serge 1098
 
1099
	mdelay(1);
2997 Serge 1100
		WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1101
	}
1990 serge 1102
 
1103
	/* start the rings */
1104
	cayman_cp_start(rdev);
2997 Serge 1105
	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1106
	rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1107
	rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1990 serge 1108
	/* this only test cp0 */
2997 Serge 1109
	r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1990 serge 1110
	if (r) {
2997 Serge 1111
		rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1112
		rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1113
		rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1990 serge 1114
		return r;
1115
	}
1116
 
1117
	return 0;
1118
}
1119
 
3192 Serge 1120
/*
1121
 * DMA
1122
 * Starting with R600, the GPU has an asynchronous
1123
 * DMA engine.  The programming model is very similar
1124
 * to the 3D engine (ring buffer, IBs, etc.), but the
1125
 * DMA controller has it's own packet format that is
1126
 * different form the PM4 format used by the 3D engine.
1127
 * It supports copying data, writing embedded data,
1128
 * solid fills, and a number of other things.  It also
1129
 * has support for tiling/detiling of buffers.
1130
 * Cayman and newer support two asynchronous DMA engines.
1131
 */
1132
/**
1133
 * cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine
1134
 *
1135
 * @rdev: radeon_device pointer
1136
 * @ib: IB object to schedule
1137
 *
1138
 * Schedule an IB in the DMA ring (cayman-SI).
1139
 */
1140
void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
1141
				struct radeon_ib *ib)
1990 serge 1142
{
3192 Serge 1143
	struct radeon_ring *ring = &rdev->ring[ib->ring];
1144
 
1145
	if (rdev->wb.enabled) {
1146
		u32 next_rptr = ring->wptr + 4;
1147
		while ((next_rptr & 7) != 5)
1148
			next_rptr++;
1149
		next_rptr += 3;
1150
		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
1151
		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1152
		radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
1153
		radeon_ring_write(ring, next_rptr);
1154
	}
1155
 
1156
	/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
1157
	 * Pad as necessary with NOPs.
1158
	 */
1159
	while ((ring->wptr & 7) != 5)
1160
		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1161
	radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, ib->vm ? ib->vm->id : 0, 0));
1162
	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
1163
	radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
1164
 
1165
}
1166
 
1167
/**
1168
 * cayman_dma_stop - stop the async dma engines
1169
 *
1170
 * @rdev: radeon_device pointer
1171
 *
1172
 * Stop the async dma engines (cayman-SI).
1173
 */
1174
void cayman_dma_stop(struct radeon_device *rdev)
1175
{
1176
	u32 rb_cntl;
1177
 
1178
	radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1179
 
1180
	/* dma0 */
1181
	rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1182
	rb_cntl &= ~DMA_RB_ENABLE;
1183
	WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);
1184
 
1185
	/* dma1 */
1186
	rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1187
	rb_cntl &= ~DMA_RB_ENABLE;
1188
	WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);
1189
 
1190
	rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
1191
	rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
1192
}
1193
 
1194
/**
1195
 * cayman_dma_resume - setup and start the async dma engines
1196
 *
1197
 * @rdev: radeon_device pointer
1198
 *
1199
 * Set up the DMA ring buffers and enable them. (cayman-SI).
1200
 * Returns 0 for success, error for failure.
1201
 */
1202
int cayman_dma_resume(struct radeon_device *rdev)
1203
{
1204
	struct radeon_ring *ring;
1205
	u32 rb_cntl, dma_cntl;
1206
	u32 rb_bufsz;
1207
	u32 reg_offset, wb_offset;
1208
	int i, r;
1209
 
1210
	/* Reset dma */
1211
	WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
1212
	RREG32(SRBM_SOFT_RESET);
1213
	udelay(50);
1214
	WREG32(SRBM_SOFT_RESET, 0);
1215
 
1216
	for (i = 0; i < 2; i++) {
1217
		if (i == 0) {
1218
			ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1219
			reg_offset = DMA0_REGISTER_OFFSET;
1220
			wb_offset = R600_WB_DMA_RPTR_OFFSET;
1221
		} else {
1222
			ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1223
			reg_offset = DMA1_REGISTER_OFFSET;
1224
			wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;
1225
		}
1226
 
1227
		WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
1228
		WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
1229
 
1230
		/* Set ring buffer size in dwords */
1231
		rb_bufsz = drm_order(ring->ring_size / 4);
1232
		rb_cntl = rb_bufsz << 1;
1233
#ifdef __BIG_ENDIAN
1234
		rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
1235
#endif
1236
		WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
1237
 
1238
		/* Initialize the ring buffer's read and write pointers */
1239
		WREG32(DMA_RB_RPTR + reg_offset, 0);
1240
		WREG32(DMA_RB_WPTR + reg_offset, 0);
1241
 
1242
		/* set the wb address whether it's enabled or not */
1243
		WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,
1244
		       upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);
1245
		WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,
1246
		       ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
1247
 
1248
		if (rdev->wb.enabled)
1249
			rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
1250
 
1251
		WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
1252
 
1253
		/* enable DMA IBs */
1254
		WREG32(DMA_IB_CNTL + reg_offset, DMA_IB_ENABLE | CMD_VMID_FORCE);
1255
 
1256
		dma_cntl = RREG32(DMA_CNTL + reg_offset);
1257
		dma_cntl &= ~CTXEMPTY_INT_ENABLE;
1258
		WREG32(DMA_CNTL + reg_offset, dma_cntl);
1259
 
1260
		ring->wptr = 0;
1261
		WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
1262
 
1263
		ring->rptr = RREG32(DMA_RB_RPTR + reg_offset) >> 2;
1264
 
1265
		WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);
1266
 
1267
		ring->ready = true;
1268
 
1269
		r = radeon_ring_test(rdev, ring->idx, ring);
1270
		if (r) {
1271
			ring->ready = false;
1272
			return r;
1273
		}
1274
	}
1275
 
1276
	radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1277
 
1278
	return 0;
1279
}
1280
 
1281
/**
1282
 * cayman_dma_fini - tear down the async dma engines
1283
 *
1284
 * @rdev: radeon_device pointer
1285
 *
1286
 * Stop the async dma engines and free the rings (cayman-SI).
1287
 */
1288
void cayman_dma_fini(struct radeon_device *rdev)
1289
{
1290
	cayman_dma_stop(rdev);
1291
	radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
1292
	radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
1293
}
1294
 
1295
static void cayman_gpu_soft_reset_gfx(struct radeon_device *rdev)
1296
{
1990 serge 1297
	u32 grbm_reset = 0;
1298
 
1299
	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
3192 Serge 1300
		return;
1990 serge 1301
 
3192 Serge 1302
	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
1990 serge 1303
		RREG32(GRBM_STATUS));
3192 Serge 1304
	dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
1990 serge 1305
		RREG32(GRBM_STATUS_SE0));
3192 Serge 1306
	dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
1990 serge 1307
		RREG32(GRBM_STATUS_SE1));
3192 Serge 1308
	dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
1990 serge 1309
		RREG32(SRBM_STATUS));
2997 Serge 1310
	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1311
		RREG32(CP_STALLED_STAT1));
1312
	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1313
		RREG32(CP_STALLED_STAT2));
1314
	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1315
		RREG32(CP_BUSY_STAT));
1316
	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1317
		RREG32(CP_STAT));
1318
 
1990 serge 1319
	/* Disable CP parsing/prefetching */
1320
	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1321
 
1322
	/* reset all the gfx blocks */
1323
	grbm_reset = (SOFT_RESET_CP |
1324
		      SOFT_RESET_CB |
1325
		      SOFT_RESET_DB |
1326
		      SOFT_RESET_GDS |
1327
		      SOFT_RESET_PA |
1328
		      SOFT_RESET_SC |
1329
		      SOFT_RESET_SPI |
1330
		      SOFT_RESET_SH |
1331
		      SOFT_RESET_SX |
1332
		      SOFT_RESET_TC |
1333
		      SOFT_RESET_TA |
1334
		      SOFT_RESET_VGT |
1335
		      SOFT_RESET_IA);
1336
 
1337
	dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1338
	WREG32(GRBM_SOFT_RESET, grbm_reset);
1339
	(void)RREG32(GRBM_SOFT_RESET);
1340
	udelay(50);
1341
	WREG32(GRBM_SOFT_RESET, 0);
1342
	(void)RREG32(GRBM_SOFT_RESET);
2997 Serge 1343
 
3192 Serge 1344
	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
1990 serge 1345
		RREG32(GRBM_STATUS));
3192 Serge 1346
	dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
1990 serge 1347
		RREG32(GRBM_STATUS_SE0));
3192 Serge 1348
	dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
1990 serge 1349
		RREG32(GRBM_STATUS_SE1));
3192 Serge 1350
	dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
1990 serge 1351
		RREG32(SRBM_STATUS));
2997 Serge 1352
	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1353
		RREG32(CP_STALLED_STAT1));
1354
	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1355
		RREG32(CP_STALLED_STAT2));
1356
	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1357
		RREG32(CP_BUSY_STAT));
1358
	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1359
		RREG32(CP_STAT));
3192 Serge 1360
 
1361
}
1362
 
1363
static void cayman_gpu_soft_reset_dma(struct radeon_device *rdev)
1364
{
1365
	u32 tmp;
1366
 
1367
	if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
1368
		return;
1369
 
1370
	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1371
		RREG32(DMA_STATUS_REG));
1372
 
1373
	/* dma0 */
1374
	tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1375
	tmp &= ~DMA_RB_ENABLE;
1376
	WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1377
 
1378
	/* dma1 */
1379
	tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1380
	tmp &= ~DMA_RB_ENABLE;
1381
	WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1382
 
1383
	/* Reset dma */
1384
	WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
1385
	RREG32(SRBM_SOFT_RESET);
1386
	udelay(50);
1387
	WREG32(SRBM_SOFT_RESET, 0);
1388
 
1389
	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1390
		RREG32(DMA_STATUS_REG));
1391
 
1392
}
1393
 
1394
static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1395
{
1396
	struct evergreen_mc_save save;
1397
 
1398
	if (reset_mask == 0)
1399
		return 0;
1400
 
1401
	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1402
 
1403
	dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n",
1404
		 RREG32(0x14F8));
1405
	dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1406
		 RREG32(0x14D8));
1407
	dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1408
		 RREG32(0x14FC));
1409
	dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1410
		 RREG32(0x14DC));
1411
 
1412
	evergreen_mc_stop(rdev, &save);
1413
	if (evergreen_mc_wait_for_idle(rdev)) {
1414
		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1415
	}
1416
 
1417
	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
1418
		cayman_gpu_soft_reset_gfx(rdev);
1419
 
1420
	if (reset_mask & RADEON_RESET_DMA)
1421
		cayman_gpu_soft_reset_dma(rdev);
1422
 
1423
	/* Wait a little for things to settle down */
1424
	udelay(50);
1425
 
1990 serge 1426
	evergreen_mc_resume(rdev, &save);
1427
	return 0;
1428
}
1429
 
1430
int cayman_asic_reset(struct radeon_device *rdev)
1431
{
3192 Serge 1432
	return cayman_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
1433
					    RADEON_RESET_COMPUTE |
1434
					    RADEON_RESET_DMA));
1990 serge 1435
}
1436
 
3192 Serge 1437
/**
1438
 * cayman_dma_is_lockup - Check if the DMA engine is locked up
1439
 *
1440
 * @rdev: radeon_device pointer
1441
 * @ring: radeon_ring structure holding ring information
1442
 *
1443
 * Check if the async DMA engine is locked up (cayman-SI).
1444
 * Returns true if the engine appears to be locked up, false if not.
1445
 */
1446
bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1447
{
1448
	u32 dma_status_reg;
1449
 
1450
	if (ring->idx == R600_RING_TYPE_DMA_INDEX)
1451
		dma_status_reg = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1452
	else
1453
		dma_status_reg = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1454
	if (dma_status_reg & DMA_IDLE) {
1455
		radeon_ring_lockup_update(ring);
1456
		return false;
1457
	}
1458
	/* force ring activities */
1459
	radeon_ring_force_activity(rdev, ring);
1460
	return radeon_ring_test_lockup(rdev, ring);
1461
}
1462
 
1990 serge 1463
static int cayman_startup(struct radeon_device *rdev)
1464
{
2997 Serge 1465
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1990 serge 1466
	int r;
1467
 
2997 Serge 1468
	/* enable pcie gen2 link */
1469
	evergreen_pcie_gen2_enable(rdev);
1470
 
1471
	if (rdev->flags & RADEON_IS_IGP) {
1472
		if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1473
			r = ni_init_microcode(rdev);
1474
			if (r) {
1475
				DRM_ERROR("Failed to load firmware!\n");
1476
				return r;
1477
			}
1478
		}
1479
	} else {
1990 serge 1480
	if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1481
		r = ni_init_microcode(rdev);
1482
		if (r) {
1483
			DRM_ERROR("Failed to load firmware!\n");
1484
			return r;
1485
		}
1486
	}
2997 Serge 1487
 
1990 serge 1488
	r = ni_mc_load_microcode(rdev);
1489
	if (r) {
1490
		DRM_ERROR("Failed to load MC firmware!\n");
1491
		return r;
1492
	}
2997 Serge 1493
	}
1990 serge 1494
 
2997 Serge 1495
	r = r600_vram_scratch_init(rdev);
1496
	if (r)
1497
		return r;
1498
 
1990 serge 1499
	evergreen_mc_program(rdev);
1500
	r = cayman_pcie_gart_enable(rdev);
1501
	if (r)
1502
		return r;
1503
	cayman_gpu_init(rdev);
1504
 
2005 serge 1505
	r = evergreen_blit_init(rdev);
1506
	if (r) {
2997 Serge 1507
//		r600_blit_fini(rdev);
1508
		rdev->asic->copy.copy = NULL;
2005 serge 1509
		dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1510
	}
1990 serge 1511
 
2997 Serge 1512
	/* allocate rlc buffers */
1513
	if (rdev->flags & RADEON_IS_IGP) {
1514
		r = si_rlc_init(rdev);
1515
		if (r) {
1516
			DRM_ERROR("Failed to init rlc BOs!\n");
1517
			return r;
1518
		}
1519
	}
1520
 
1990 serge 1521
	/* allocate wb buffer */
2005 serge 1522
	r = radeon_wb_init(rdev);
1523
	if (r)
1524
		return r;
1990 serge 1525
 
3192 Serge 1526
	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1527
	if (r) {
1528
		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1529
		return r;
1530
	}
1531
 
1532
	r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1533
	if (r) {
1534
		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1535
		return r;
1536
	}
1537
 
1538
	r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1539
	if (r) {
1540
		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1541
		return r;
1542
	}
1543
 
1544
	r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1545
	if (r) {
1546
		dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1547
		return r;
1548
	}
1549
 
1550
	r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
1551
	if (r) {
1552
		dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1553
		return r;
1554
	}
1555
 
1990 serge 1556
	/* Enable IRQ */
2005 serge 1557
	r = r600_irq_init(rdev);
1558
	if (r) {
1559
		DRM_ERROR("radeon: IH init failed (%d).\n", r);
1560
//		radeon_irq_kms_fini(rdev);
1561
		return r;
1562
	}
1563
	evergreen_irq_set(rdev);
1990 serge 1564
 
2997 Serge 1565
	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1566
			     CP_RB0_RPTR, CP_RB0_WPTR,
1567
			     0, 0xfffff, RADEON_CP_PACKET2);
1990 serge 1568
	if (r)
1569
		return r;
3192 Serge 1570
 
1571
	ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1572
	r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1573
			     DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
1574
			     DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
1575
			     2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1576
	if (r)
1577
		return r;
1578
 
1579
	ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1580
	r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
1581
			     DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
1582
			     DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
1583
			     2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1584
	if (r)
1585
		return r;
1586
 
1990 serge 1587
	r = cayman_cp_load_microcode(rdev);
1588
	if (r)
1589
		return r;
1590
	r = cayman_cp_resume(rdev);
1591
	if (r)
1592
		return r;
1593
 
3192 Serge 1594
	r = cayman_dma_resume(rdev);
1595
	if (r)
1596
		return r;
1597
 
1598
	r = radeon_ib_pool_init(rdev);
1599
	if (r) {
1600
		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1601
		return r;
1602
	}
1990 serge 1603
	return 0;
1604
}
1605
 
1606
 
1607
 
1608
 
1609
 
1610
/* Plan is to move initialization in that function and use
1611
 * helper function so that radeon_device_init pretty much
1612
 * do nothing more than calling asic specific function. This
1613
 * should also allow to remove a bunch of callback function
1614
 * like vram_info.
1615
 */
1616
int cayman_init(struct radeon_device *rdev)
1617
{
2997 Serge 1618
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1990 serge 1619
	int r;
1620
 
1621
	/* Read BIOS */
1622
	if (!radeon_get_bios(rdev)) {
1623
		if (ASIC_IS_AVIVO(rdev))
1624
			return -EINVAL;
1625
	}
1626
	/* Must be an ATOMBIOS */
1627
	if (!rdev->is_atom_bios) {
1628
		dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1629
		return -EINVAL;
1630
	}
1631
	r = radeon_atombios_init(rdev);
1632
	if (r)
1633
		return r;
1634
 
1635
	/* Post card if necessary */
1636
	if (!radeon_card_posted(rdev)) {
1637
		if (!rdev->bios) {
1638
			dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1639
			return -EINVAL;
1640
		}
1641
		DRM_INFO("GPU not posted. posting now...\n");
1642
		atom_asic_init(rdev->mode_info.atom_context);
1643
	}
1644
	/* Initialize scratch registers */
1645
	r600_scratch_init(rdev);
1646
	/* Initialize surface registers */
1647
	radeon_surface_init(rdev);
1648
	/* Initialize clocks */
1649
	radeon_get_clock_info(rdev->ddev);
1650
	/* Fence driver */
2005 serge 1651
	r = radeon_fence_driver_init(rdev);
1652
	if (r)
1653
		return r;
1990 serge 1654
	/* initialize memory controller */
1655
	r = evergreen_mc_init(rdev);
1656
	if (r)
1657
		return r;
1658
	/* Memory manager */
1659
	r = radeon_bo_init(rdev);
1660
	if (r)
1661
		return r;
1662
 
2005 serge 1663
	r = radeon_irq_kms_init(rdev);
1664
	if (r)
1665
		return r;
1990 serge 1666
 
2997 Serge 1667
	ring->ring_obj = NULL;
1668
	r600_ring_init(rdev, ring, 1024 * 1024);
1990 serge 1669
 
3192 Serge 1670
	ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1671
	ring->ring_obj = NULL;
1672
	r600_ring_init(rdev, ring, 64 * 1024);
1673
 
1674
	ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1675
	ring->ring_obj = NULL;
1676
	r600_ring_init(rdev, ring, 64 * 1024);
1677
 
2005 serge 1678
	rdev->ih.ring_obj = NULL;
1679
	r600_ih_ring_init(rdev, 64 * 1024);
1990 serge 1680
 
1681
	r = r600_pcie_gart_init(rdev);
1682
	if (r)
1683
		return r;
1684
 
1685
	rdev->accel_working = true;
1686
	r = cayman_startup(rdev);
1687
	if (r) {
1688
		dev_err(rdev->dev, "disabling GPU acceleration\n");
1689
		rdev->accel_working = false;
1690
	}
1691
 
1692
	/* Don't start up if the MC ucode is missing.
1693
	 * The default clocks and voltages before the MC ucode
1694
	 * is loaded are not suffient for advanced operations.
2997 Serge 1695
	 *
1696
	 * We can skip this check for TN, because there is no MC
1697
	 * ucode.
1990 serge 1698
	 */
2997 Serge 1699
	if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
1990 serge 1700
		DRM_ERROR("radeon: MC ucode required for NI+.\n");
1701
		return -EINVAL;
1702
	}
1703
 
1704
	return 0;
1705
}
1706
 
2997 Serge 1707
/*
1708
 * vm
1709
 */
1710
int cayman_vm_init(struct radeon_device *rdev)
1711
{
1712
	/* number of VMs */
1713
	rdev->vm_manager.nvm = 8;
1714
	/* base offset of vram pages */
1715
	if (rdev->flags & RADEON_IS_IGP) {
1716
		u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
1717
		tmp <<= 22;
1718
		rdev->vm_manager.vram_base_offset = tmp;
1719
	} else
1720
		rdev->vm_manager.vram_base_offset = 0;
1721
	return 0;
1722
}
1723
 
1724
void cayman_vm_fini(struct radeon_device *rdev)
1725
{
1726
}
1727
 
1728
#define R600_ENTRY_VALID   (1 << 0)
1729
#define R600_PTE_SYSTEM    (1 << 1)
1730
#define R600_PTE_SNOOPED   (1 << 2)
1731
#define R600_PTE_READABLE  (1 << 5)
1732
#define R600_PTE_WRITEABLE (1 << 6)
1733
 
1734
uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
1735
{
1736
	uint32_t r600_flags = 0;
1737
	r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0;
1738
	r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
1739
	r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
1740
	if (flags & RADEON_VM_PAGE_SYSTEM) {
1741
		r600_flags |= R600_PTE_SYSTEM;
1742
		r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
1743
	}
1744
	return r600_flags;
1745
}
1746
 
1747
/**
1748
 * cayman_vm_set_page - update the page tables using the CP
1749
 *
1750
 * @rdev: radeon_device pointer
1751
 * @pe: addr of the page entry
1752
 * @addr: dst addr to write into pe
1753
 * @count: number of page entries to update
1754
 * @incr: increase next addr by incr bytes
1755
 * @flags: access flags
1756
 *
1757
 * Update the page tables using the CP (cayman-si).
1758
 */
1759
void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
1760
			uint64_t addr, unsigned count,
1761
			uint32_t incr, uint32_t flags)
1762
{
1763
	struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
1764
	uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
3192 Serge 1765
	uint64_t value;
1766
	unsigned ndw;
2997 Serge 1767
 
3192 Serge 1768
	if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
2997 Serge 1769
	while (count) {
3192 Serge 1770
			ndw = 1 + count * 2;
2997 Serge 1771
		if (ndw > 0x3FFF)
1772
			ndw = 0x3FFF;
1773
 
1774
		radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, ndw));
1775
		radeon_ring_write(ring, pe);
1776
		radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
1777
		for (; ndw > 1; ndw -= 2, --count, pe += 8) {
1778
			if (flags & RADEON_VM_PAGE_SYSTEM) {
1779
				value = radeon_vm_map_gart(rdev, addr);
1780
				value &= 0xFFFFFFFFFFFFF000ULL;
3192 Serge 1781
				} else if (flags & RADEON_VM_PAGE_VALID) {
1782
					value = addr;
1783
				} else {
1784
					value = 0;
1785
				}
2997 Serge 1786
				addr += incr;
3192 Serge 1787
				value |= r600_flags;
1788
				radeon_ring_write(ring, value);
1789
				radeon_ring_write(ring, upper_32_bits(value));
1790
			}
1791
		}
1792
	} else {
1793
		while (count) {
1794
			ndw = count * 2;
1795
			if (ndw > 0xFFFFE)
1796
				ndw = 0xFFFFE;
2997 Serge 1797
 
3192 Serge 1798
			/* for non-physically contiguous pages (system) */
1799
			radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw));
1800
			radeon_ring_write(ring, pe);
1801
			radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
1802
			for (; ndw > 0; ndw -= 2, --count, pe += 8) {
1803
				if (flags & RADEON_VM_PAGE_SYSTEM) {
1804
					value = radeon_vm_map_gart(rdev, addr);
1805
					value &= 0xFFFFFFFFFFFFF000ULL;
2997 Serge 1806
			} else if (flags & RADEON_VM_PAGE_VALID) {
1807
				value = addr;
3192 Serge 1808
				} else {
1809
					value = 0;
1810
				}
2997 Serge 1811
				addr += incr;
1812
			value |= r600_flags;
1813
			radeon_ring_write(ring, value);
1814
			radeon_ring_write(ring, upper_32_bits(value));
1815
		}
1816
	}
3192 Serge 1817
	}
2997 Serge 1818
}
1819
 
1820
/**
1821
 * cayman_vm_flush - vm flush using the CP
1822
 *
1823
 * @rdev: radeon_device pointer
1824
 *
1825
 * Update the page table base and flush the VM TLB
1826
 * using the CP (cayman-si).
1827
 */
1828
void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
1829
{
1830
	struct radeon_ring *ring = &rdev->ring[ridx];
1831
 
1832
	if (vm == NULL)
1833
		return;
1834
 
1835
	radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
1836
	radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
1837
 
1838
	/* flush hdp cache */
1839
	radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
1840
	radeon_ring_write(ring, 0x1);
1841
 
1842
	/* bits 0-7 are the VM contexts0-7 */
1843
	radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
1844
	radeon_ring_write(ring, 1 << vm->id);
1845
 
1846
	/* sync PFP to ME, otherwise we might get invalid PFP reads */
1847
	radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
1848
	radeon_ring_write(ring, 0x0);
1849
}
3192 Serge 1850
 
1851
void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
1852
{
1853
	struct radeon_ring *ring = &rdev->ring[ridx];
1854
 
1855
	if (vm == NULL)
1856
		return;
1857
 
1858
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
1859
	radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
1860
	radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
1861
 
1862
	/* flush hdp cache */
1863
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
1864
	radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
1865
	radeon_ring_write(ring, 1);
1866
 
1867
	/* bits 0-7 are the VM contexts0-7 */
1868
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
1869
	radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
1870
	radeon_ring_write(ring, 1 << vm->id);
1871
}
1872