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1963 | serge | 1 | /* |
2 | * Copyright 2010 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | * Authors: Alex Deucher |
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23 | */ |
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24 | #ifndef EVERGREEND_H |
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25 | #define EVERGREEND_H |
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26 | |||
27 | #define EVERGREEN_MAX_SH_GPRS 256 |
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28 | #define EVERGREEN_MAX_TEMP_GPRS 16 |
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29 | #define EVERGREEN_MAX_SH_THREADS 256 |
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30 | #define EVERGREEN_MAX_SH_STACK_ENTRIES 4096 |
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31 | #define EVERGREEN_MAX_FRC_EOV_CNT 16384 |
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32 | #define EVERGREEN_MAX_BACKENDS 8 |
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33 | #define EVERGREEN_MAX_BACKENDS_MASK 0xFF |
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34 | #define EVERGREEN_MAX_SIMDS 16 |
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35 | #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF |
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36 | #define EVERGREEN_MAX_PIPES 8 |
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37 | #define EVERGREEN_MAX_PIPES_MASK 0xFF |
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38 | #define EVERGREEN_MAX_LDS_NUM 0xFFFF |
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39 | |||
2997 | Serge | 40 | #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003 |
41 | #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003 |
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42 | #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 |
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43 | #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002 |
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44 | #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002 |
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45 | #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002 |
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46 | #define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 |
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47 | #define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 |
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3192 | Serge | 48 | #define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002 |
49 | #define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002 |
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2997 | Serge | 50 | |
1963 | serge | 51 | /* Registers */ |
52 | |||
53 | #define RCU_IND_INDEX 0x100 |
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54 | #define RCU_IND_DATA 0x104 |
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55 | |||
56 | #define GRBM_GFX_INDEX 0x802C |
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57 | #define INSTANCE_INDEX(x) ((x) << 0) |
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58 | #define SE_INDEX(x) ((x) << 16) |
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59 | #define INSTANCE_BROADCAST_WRITES (1 << 30) |
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60 | #define SE_BROADCAST_WRITES (1 << 31) |
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61 | #define RLC_GFX_INDEX 0x3fC4 |
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62 | #define CC_GC_SHADER_PIPE_CONFIG 0x8950 |
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63 | #define WRITE_DIS (1 << 0) |
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64 | #define CC_RB_BACKEND_DISABLE 0x98F4 |
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65 | #define BACKEND_DISABLE(x) ((x) << 16) |
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66 | #define GB_ADDR_CONFIG 0x98F8 |
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67 | #define NUM_PIPES(x) ((x) << 0) |
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2997 | Serge | 68 | #define NUM_PIPES_MASK 0x0000000f |
1963 | serge | 69 | #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) |
70 | #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) |
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71 | #define NUM_SHADER_ENGINES(x) ((x) << 12) |
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72 | #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) |
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73 | #define NUM_GPUS(x) ((x) << 20) |
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74 | #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) |
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75 | #define ROW_SIZE(x) ((x) << 28) |
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76 | #define GB_BACKEND_MAP 0x98FC |
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77 | #define DMIF_ADDR_CONFIG 0xBD4 |
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78 | #define HDP_ADDR_CONFIG 0x2F48 |
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79 | #define HDP_MISC_CNTL 0x2F4C |
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80 | #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) |
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81 | |||
82 | #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 |
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83 | #define GC_USER_RB_BACKEND_DISABLE 0x9B7C |
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84 | |||
85 | #define CGTS_SYS_TCC_DISABLE 0x3F90 |
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86 | #define CGTS_TCC_DISABLE 0x9148 |
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87 | #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 |
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88 | #define CGTS_USER_TCC_DISABLE 0x914C |
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89 | |||
90 | #define CONFIG_MEMSIZE 0x5428 |
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91 | |||
2997 | Serge | 92 | #define BIF_FB_EN 0x5490 |
93 | #define FB_READ_EN (1 << 0) |
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94 | #define FB_WRITE_EN (1 << 1) |
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95 | |||
3031 | serge | 96 | #define CP_STRMOUT_CNTL 0x84FC |
97 | |||
98 | #define CP_COHER_CNTL 0x85F0 |
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99 | #define CP_COHER_SIZE 0x85F4 |
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2997 | Serge | 100 | #define CP_COHER_BASE 0x85F8 |
101 | #define CP_STALLED_STAT1 0x8674 |
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102 | #define CP_STALLED_STAT2 0x8678 |
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103 | #define CP_BUSY_STAT 0x867C |
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104 | #define CP_STAT 0x8680 |
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1963 | serge | 105 | #define CP_ME_CNTL 0x86D8 |
106 | #define CP_ME_HALT (1 << 28) |
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107 | #define CP_PFP_HALT (1 << 26) |
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108 | #define CP_ME_RAM_DATA 0xC160 |
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109 | #define CP_ME_RAM_RADDR 0xC158 |
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110 | #define CP_ME_RAM_WADDR 0xC15C |
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111 | #define CP_MEQ_THRESHOLDS 0x8764 |
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112 | #define STQ_SPLIT(x) ((x) << 0) |
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113 | #define CP_PERFMON_CNTL 0x87FC |
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114 | #define CP_PFP_UCODE_ADDR 0xC150 |
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115 | #define CP_PFP_UCODE_DATA 0xC154 |
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116 | #define CP_QUEUE_THRESHOLDS 0x8760 |
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117 | #define ROQ_IB1_START(x) ((x) << 0) |
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118 | #define ROQ_IB2_START(x) ((x) << 8) |
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119 | #define CP_RB_BASE 0xC100 |
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120 | #define CP_RB_CNTL 0xC104 |
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121 | #define RB_BUFSZ(x) ((x) << 0) |
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122 | #define RB_BLKSZ(x) ((x) << 8) |
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123 | #define RB_NO_UPDATE (1 << 27) |
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124 | #define RB_RPTR_WR_ENA (1 << 31) |
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125 | #define BUF_SWAP_32BIT (2 << 16) |
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126 | #define CP_RB_RPTR 0x8700 |
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127 | #define CP_RB_RPTR_ADDR 0xC10C |
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128 | #define RB_RPTR_SWAP(x) ((x) << 0) |
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129 | #define CP_RB_RPTR_ADDR_HI 0xC110 |
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130 | #define CP_RB_RPTR_WR 0xC108 |
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131 | #define CP_RB_WPTR 0xC114 |
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132 | #define CP_RB_WPTR_ADDR 0xC118 |
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133 | #define CP_RB_WPTR_ADDR_HI 0xC11C |
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134 | #define CP_RB_WPTR_DELAY 0x8704 |
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135 | #define CP_SEM_WAIT_TIMER 0x85BC |
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2997 | Serge | 136 | #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 |
1963 | serge | 137 | #define CP_DEBUG 0xC1FC |
138 | |||
2997 | Serge | 139 | /* Audio clocks */ |
140 | #define DCCG_AUDIO_DTO_SOURCE 0x05ac |
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141 | # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ |
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142 | # define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */ |
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1963 | serge | 143 | |
2997 | Serge | 144 | #define DCCG_AUDIO_DTO0_PHASE 0x05b0 |
145 | #define DCCG_AUDIO_DTO0_MODULE 0x05b4 |
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146 | #define DCCG_AUDIO_DTO0_LOAD 0x05b8 |
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147 | #define DCCG_AUDIO_DTO0_CNTL 0x05bc |
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148 | |||
149 | #define DCCG_AUDIO_DTO1_PHASE 0x05c0 |
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150 | #define DCCG_AUDIO_DTO1_MODULE 0x05c4 |
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151 | #define DCCG_AUDIO_DTO1_LOAD 0x05c8 |
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152 | #define DCCG_AUDIO_DTO1_CNTL 0x05cc |
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153 | |||
154 | /* DCE 4.0 AFMT */ |
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155 | #define HDMI_CONTROL 0x7030 |
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156 | # define HDMI_KEEPOUT_MODE (1 << 0) |
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157 | # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ |
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158 | # define HDMI_ERROR_ACK (1 << 8) |
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159 | # define HDMI_ERROR_MASK (1 << 9) |
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160 | # define HDMI_DEEP_COLOR_ENABLE (1 << 24) |
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161 | # define HDMI_DEEP_COLOR_DEPTH (((x) & 3) << 28) |
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162 | # define HDMI_24BIT_DEEP_COLOR 0 |
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163 | # define HDMI_30BIT_DEEP_COLOR 1 |
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164 | # define HDMI_36BIT_DEEP_COLOR 2 |
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165 | #define HDMI_STATUS 0x7034 |
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166 | # define HDMI_ACTIVE_AVMUTE (1 << 0) |
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167 | # define HDMI_AUDIO_PACKET_ERROR (1 << 16) |
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168 | # define HDMI_VBI_PACKET_ERROR (1 << 20) |
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169 | #define HDMI_AUDIO_PACKET_CONTROL 0x7038 |
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170 | # define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) |
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171 | # define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) |
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172 | #define HDMI_ACR_PACKET_CONTROL 0x703c |
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173 | # define HDMI_ACR_SEND (1 << 0) |
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174 | # define HDMI_ACR_CONT (1 << 1) |
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175 | # define HDMI_ACR_SELECT(x) (((x) & 3) << 4) |
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176 | # define HDMI_ACR_HW 0 |
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177 | # define HDMI_ACR_32 1 |
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178 | # define HDMI_ACR_44 2 |
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179 | # define HDMI_ACR_48 3 |
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180 | # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ |
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181 | # define HDMI_ACR_AUTO_SEND (1 << 12) |
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182 | # define HDMI_ACR_N_MULTIPLE(x) (((x) & 7) << 16) |
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183 | # define HDMI_ACR_X1 1 |
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184 | # define HDMI_ACR_X2 2 |
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185 | # define HDMI_ACR_X4 4 |
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186 | # define HDMI_ACR_AUDIO_PRIORITY (1 << 31) |
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187 | #define HDMI_VBI_PACKET_CONTROL 0x7040 |
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188 | # define HDMI_NULL_SEND (1 << 0) |
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189 | # define HDMI_GC_SEND (1 << 4) |
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190 | # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ |
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191 | #define HDMI_INFOFRAME_CONTROL0 0x7044 |
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192 | # define HDMI_AVI_INFO_SEND (1 << 0) |
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193 | # define HDMI_AVI_INFO_CONT (1 << 1) |
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194 | # define HDMI_AUDIO_INFO_SEND (1 << 4) |
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195 | # define HDMI_AUDIO_INFO_CONT (1 << 5) |
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196 | # define HDMI_MPEG_INFO_SEND (1 << 8) |
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197 | # define HDMI_MPEG_INFO_CONT (1 << 9) |
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198 | #define HDMI_INFOFRAME_CONTROL1 0x7048 |
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199 | # define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) |
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200 | # define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) |
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201 | # define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) |
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202 | #define HDMI_GENERIC_PACKET_CONTROL 0x704c |
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203 | # define HDMI_GENERIC0_SEND (1 << 0) |
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204 | # define HDMI_GENERIC0_CONT (1 << 1) |
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205 | # define HDMI_GENERIC1_SEND (1 << 4) |
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206 | # define HDMI_GENERIC1_CONT (1 << 5) |
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207 | # define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) |
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208 | # define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) |
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209 | #define HDMI_GC 0x7058 |
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210 | # define HDMI_GC_AVMUTE (1 << 0) |
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211 | # define HDMI_GC_AVMUTE_CONT (1 << 2) |
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212 | #define AFMT_AUDIO_PACKET_CONTROL2 0x705c |
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213 | # define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) |
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214 | # define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) |
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215 | # define AFMT_60958_CS_SOURCE (1 << 4) |
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216 | # define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) |
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217 | # define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) |
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218 | #define AFMT_AVI_INFO0 0x7084 |
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219 | # define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) |
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220 | # define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) |
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221 | # define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) |
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222 | # define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) |
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223 | # define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) |
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224 | # define AFMT_AVI_INFO_Y_RGB 0 |
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225 | # define AFMT_AVI_INFO_Y_YCBCR422 1 |
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226 | # define AFMT_AVI_INFO_Y_YCBCR444 2 |
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227 | # define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) |
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228 | # define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) |
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229 | # define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) |
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230 | # define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) |
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231 | # define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) |
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232 | # define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) |
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233 | # define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) |
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234 | # define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) |
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235 | # define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) |
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236 | # define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) |
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237 | #define AFMT_AVI_INFO1 0x7088 |
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238 | # define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ |
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239 | # define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ |
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240 | # define AFMT_AVI_INFO_CN(x) (((x) & 0x3) << 12) |
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241 | # define AFMT_AVI_INFO_YQ(x) (((x) & 0x3) << 14) |
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242 | # define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) |
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243 | #define AFMT_AVI_INFO2 0x708c |
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244 | # define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) |
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245 | # define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) |
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246 | #define AFMT_AVI_INFO3 0x7090 |
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247 | # define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) |
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248 | # define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) |
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249 | #define AFMT_MPEG_INFO0 0x7094 |
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250 | # define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) |
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251 | # define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) |
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252 | # define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) |
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253 | # define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) |
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254 | #define AFMT_MPEG_INFO1 0x7098 |
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255 | # define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) |
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256 | # define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) |
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257 | # define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) |
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258 | #define AFMT_GENERIC0_HDR 0x709c |
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259 | #define AFMT_GENERIC0_0 0x70a0 |
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260 | #define AFMT_GENERIC0_1 0x70a4 |
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261 | #define AFMT_GENERIC0_2 0x70a8 |
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262 | #define AFMT_GENERIC0_3 0x70ac |
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263 | #define AFMT_GENERIC0_4 0x70b0 |
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264 | #define AFMT_GENERIC0_5 0x70b4 |
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265 | #define AFMT_GENERIC0_6 0x70b8 |
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266 | #define AFMT_GENERIC1_HDR 0x70bc |
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267 | #define AFMT_GENERIC1_0 0x70c0 |
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268 | #define AFMT_GENERIC1_1 0x70c4 |
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269 | #define AFMT_GENERIC1_2 0x70c8 |
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270 | #define AFMT_GENERIC1_3 0x70cc |
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271 | #define AFMT_GENERIC1_4 0x70d0 |
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272 | #define AFMT_GENERIC1_5 0x70d4 |
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273 | #define AFMT_GENERIC1_6 0x70d8 |
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274 | #define HDMI_ACR_32_0 0x70dc |
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275 | # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) |
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276 | #define HDMI_ACR_32_1 0x70e0 |
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277 | # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) |
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278 | #define HDMI_ACR_44_0 0x70e4 |
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279 | # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) |
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280 | #define HDMI_ACR_44_1 0x70e8 |
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281 | # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) |
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282 | #define HDMI_ACR_48_0 0x70ec |
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283 | # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) |
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284 | #define HDMI_ACR_48_1 0x70f0 |
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285 | # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) |
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286 | #define HDMI_ACR_STATUS_0 0x70f4 |
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287 | #define HDMI_ACR_STATUS_1 0x70f8 |
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288 | #define AFMT_AUDIO_INFO0 0x70fc |
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289 | # define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) |
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290 | # define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) |
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291 | # define AFMT_AUDIO_INFO_CT(x) (((x) & 0xf) << 11) |
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292 | # define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) |
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293 | # define AFMT_AUDIO_INFO_CXT(x) (((x) & 0x1f) << 24) |
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294 | #define AFMT_AUDIO_INFO1 0x7100 |
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295 | # define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) |
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296 | # define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) |
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297 | # define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) |
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298 | # define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) |
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299 | # define AFMT_AUDIO_INFO_LFEBPL(x) (((x) & 3) << 16) |
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300 | #define AFMT_60958_0 0x7104 |
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301 | # define AFMT_60958_CS_A(x) (((x) & 1) << 0) |
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302 | # define AFMT_60958_CS_B(x) (((x) & 1) << 1) |
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303 | # define AFMT_60958_CS_C(x) (((x) & 1) << 2) |
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304 | # define AFMT_60958_CS_D(x) (((x) & 3) << 3) |
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305 | # define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) |
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306 | # define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) |
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307 | # define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) |
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308 | # define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) |
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309 | # define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) |
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310 | # define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) |
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311 | #define AFMT_60958_1 0x7108 |
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312 | # define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) |
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313 | # define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) |
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314 | # define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) |
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315 | # define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) |
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316 | # define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) |
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317 | #define AFMT_AUDIO_CRC_CONTROL 0x710c |
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318 | # define AFMT_AUDIO_CRC_EN (1 << 0) |
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319 | #define AFMT_RAMP_CONTROL0 0x7110 |
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320 | # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) |
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321 | # define AFMT_RAMP_DATA_SIGN (1 << 31) |
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322 | #define AFMT_RAMP_CONTROL1 0x7114 |
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323 | # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) |
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324 | # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) |
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325 | #define AFMT_RAMP_CONTROL2 0x7118 |
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326 | # define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) |
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327 | #define AFMT_RAMP_CONTROL3 0x711c |
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328 | # define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) |
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329 | #define AFMT_60958_2 0x7120 |
||
330 | # define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) |
||
331 | # define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) |
||
332 | # define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) |
||
333 | # define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) |
||
334 | # define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) |
||
335 | # define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) |
||
336 | #define AFMT_STATUS 0x7128 |
||
337 | # define AFMT_AUDIO_ENABLE (1 << 4) |
||
338 | # define AFMT_AUDIO_HBR_ENABLE (1 << 8) |
||
339 | # define AFMT_AZ_FORMAT_WTRIG (1 << 28) |
||
340 | # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) |
||
341 | # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) |
||
342 | #define AFMT_AUDIO_PACKET_CONTROL 0x712c |
||
343 | # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) |
||
344 | # define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */ |
||
345 | # define AFMT_AUDIO_TEST_EN (1 << 12) |
||
346 | # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) |
||
347 | # define AFMT_60958_CS_UPDATE (1 << 26) |
||
348 | # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) |
||
349 | # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) |
||
350 | # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) |
||
351 | # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) |
||
352 | #define AFMT_VBI_PACKET_CONTROL 0x7130 |
||
353 | # define AFMT_GENERIC0_UPDATE (1 << 2) |
||
354 | #define AFMT_INFOFRAME_CONTROL0 0x7134 |
||
355 | # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - afmt regs */ |
||
356 | # define AFMT_AUDIO_INFO_UPDATE (1 << 7) |
||
357 | # define AFMT_MPEG_INFO_UPDATE (1 << 10) |
||
358 | #define AFMT_GENERIC0_7 0x7138 |
||
359 | |||
3192 | Serge | 360 | /* DCE4/5 ELD audio interface */ |
361 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */ |
||
362 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */ |
||
363 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */ |
||
364 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */ |
||
365 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x5f94 /* MPEG2 */ |
||
366 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x5f98 /* AAC */ |
||
367 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x5f9c /* DTS */ |
||
368 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x5fa0 /* ATRAC */ |
||
369 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x5fa4 /* one bit audio - leave at 0 (default) */ |
||
370 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x5fa8 /* Dolby Digital */ |
||
371 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x5fac /* DTS-HD */ |
||
372 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x5fb0 /* MAT-MLP */ |
||
373 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x5fb4 /* DTS */ |
||
374 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x5fb8 /* WMA Pro */ |
||
375 | # define MAX_CHANNELS(x) (((x) & 0x7) << 0) |
||
376 | /* max channels minus one. 7 = 8 channels */ |
||
377 | # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) |
||
378 | # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) |
||
379 | # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ |
||
380 | /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO |
||
381 | * bit0 = 32 kHz |
||
382 | * bit1 = 44.1 kHz |
||
383 | * bit2 = 48 kHz |
||
384 | * bit3 = 88.2 kHz |
||
385 | * bit4 = 96 kHz |
||
386 | * bit5 = 176.4 kHz |
||
387 | * bit6 = 192 kHz |
||
388 | */ |
||
389 | |||
390 | #define AZ_HOT_PLUG_CONTROL 0x5e78 |
||
391 | # define AZ_FORCE_CODEC_WAKE (1 << 0) |
||
392 | # define PIN0_JACK_DETECTION_ENABLE (1 << 4) |
||
393 | # define PIN1_JACK_DETECTION_ENABLE (1 << 5) |
||
394 | # define PIN2_JACK_DETECTION_ENABLE (1 << 6) |
||
395 | # define PIN3_JACK_DETECTION_ENABLE (1 << 7) |
||
396 | # define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8) |
||
397 | # define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9) |
||
398 | # define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10) |
||
399 | # define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11) |
||
400 | # define CODEC_HOT_PLUG_ENABLE (1 << 12) |
||
401 | # define PIN0_AUDIO_ENABLED (1 << 24) |
||
402 | # define PIN1_AUDIO_ENABLED (1 << 25) |
||
403 | # define PIN2_AUDIO_ENABLED (1 << 26) |
||
404 | # define PIN3_AUDIO_ENABLED (1 << 27) |
||
405 | # define AUDIO_ENABLED (1 << 31) |
||
406 | |||
407 | |||
1963 | serge | 408 | #define GC_USER_SHADER_PIPE_CONFIG 0x8954 |
409 | #define INACTIVE_QD_PIPES(x) ((x) << 8) |
||
410 | #define INACTIVE_QD_PIPES_MASK 0x0000FF00 |
||
411 | #define INACTIVE_SIMDS(x) ((x) << 16) |
||
412 | #define INACTIVE_SIMDS_MASK 0x00FF0000 |
||
413 | |||
414 | #define GRBM_CNTL 0x8000 |
||
415 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) |
||
416 | #define GRBM_SOFT_RESET 0x8020 |
||
417 | #define SOFT_RESET_CP (1 << 0) |
||
418 | #define SOFT_RESET_CB (1 << 1) |
||
419 | #define SOFT_RESET_DB (1 << 3) |
||
420 | #define SOFT_RESET_PA (1 << 5) |
||
421 | #define SOFT_RESET_SC (1 << 6) |
||
422 | #define SOFT_RESET_SPI (1 << 8) |
||
423 | #define SOFT_RESET_SH (1 << 9) |
||
424 | #define SOFT_RESET_SX (1 << 10) |
||
425 | #define SOFT_RESET_TC (1 << 11) |
||
426 | #define SOFT_RESET_TA (1 << 12) |
||
427 | #define SOFT_RESET_VC (1 << 13) |
||
428 | #define SOFT_RESET_VGT (1 << 14) |
||
429 | |||
430 | #define GRBM_STATUS 0x8010 |
||
431 | #define CMDFIFO_AVAIL_MASK 0x0000000F |
||
432 | #define SRBM_RQ_PENDING (1 << 5) |
||
433 | #define CF_RQ_PENDING (1 << 7) |
||
434 | #define PF_RQ_PENDING (1 << 8) |
||
435 | #define GRBM_EE_BUSY (1 << 10) |
||
436 | #define SX_CLEAN (1 << 11) |
||
437 | #define DB_CLEAN (1 << 12) |
||
438 | #define CB_CLEAN (1 << 13) |
||
439 | #define TA_BUSY (1 << 14) |
||
440 | #define VGT_BUSY_NO_DMA (1 << 16) |
||
441 | #define VGT_BUSY (1 << 17) |
||
442 | #define SX_BUSY (1 << 20) |
||
443 | #define SH_BUSY (1 << 21) |
||
444 | #define SPI_BUSY (1 << 22) |
||
445 | #define SC_BUSY (1 << 24) |
||
446 | #define PA_BUSY (1 << 25) |
||
447 | #define DB_BUSY (1 << 26) |
||
448 | #define CP_COHERENCY_BUSY (1 << 28) |
||
449 | #define CP_BUSY (1 << 29) |
||
450 | #define CB_BUSY (1 << 30) |
||
451 | #define GUI_ACTIVE (1 << 31) |
||
452 | #define GRBM_STATUS_SE0 0x8014 |
||
453 | #define GRBM_STATUS_SE1 0x8018 |
||
454 | #define SE_SX_CLEAN (1 << 0) |
||
455 | #define SE_DB_CLEAN (1 << 1) |
||
456 | #define SE_CB_CLEAN (1 << 2) |
||
457 | #define SE_TA_BUSY (1 << 25) |
||
458 | #define SE_SX_BUSY (1 << 26) |
||
459 | #define SE_SPI_BUSY (1 << 27) |
||
460 | #define SE_SH_BUSY (1 << 28) |
||
461 | #define SE_SC_BUSY (1 << 29) |
||
462 | #define SE_DB_BUSY (1 << 30) |
||
463 | #define SE_CB_BUSY (1 << 31) |
||
464 | /* evergreen */ |
||
465 | #define CG_THERMAL_CTRL 0x72c |
||
466 | #define TOFFSET_MASK 0x00003FE0 |
||
467 | #define TOFFSET_SHIFT 5 |
||
468 | #define CG_MULT_THERMAL_STATUS 0x740 |
||
469 | #define ASIC_T(x) ((x) << 16) |
||
470 | #define ASIC_T_MASK 0x07FF0000 |
||
471 | #define ASIC_T_SHIFT 16 |
||
472 | #define CG_TS0_STATUS 0x760 |
||
473 | #define TS0_ADC_DOUT_MASK 0x000003FF |
||
474 | #define TS0_ADC_DOUT_SHIFT 0 |
||
475 | /* APU */ |
||
476 | #define CG_THERMAL_STATUS 0x678 |
||
477 | |||
478 | #define HDP_HOST_PATH_CNTL 0x2C00 |
||
479 | #define HDP_NONSURFACE_BASE 0x2C04 |
||
480 | #define HDP_NONSURFACE_INFO 0x2C08 |
||
481 | #define HDP_NONSURFACE_SIZE 0x2C0C |
||
482 | #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 |
||
483 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
||
484 | #define HDP_TILING_CONFIG 0x2F3C |
||
485 | |||
486 | #define MC_SHARED_CHMAP 0x2004 |
||
487 | #define NOOFCHAN_SHIFT 12 |
||
488 | #define NOOFCHAN_MASK 0x00003000 |
||
489 | #define MC_SHARED_CHREMAP 0x2008 |
||
490 | |||
2997 | Serge | 491 | #define MC_SHARED_BLACKOUT_CNTL 0x20ac |
492 | #define BLACKOUT_MODE_MASK 0x00000007 |
||
493 | |||
1963 | serge | 494 | #define MC_ARB_RAMCFG 0x2760 |
495 | #define NOOFBANK_SHIFT 0 |
||
496 | #define NOOFBANK_MASK 0x00000003 |
||
497 | #define NOOFRANK_SHIFT 2 |
||
498 | #define NOOFRANK_MASK 0x00000004 |
||
499 | #define NOOFROWS_SHIFT 3 |
||
500 | #define NOOFROWS_MASK 0x00000038 |
||
501 | #define NOOFCOLS_SHIFT 6 |
||
502 | #define NOOFCOLS_MASK 0x000000C0 |
||
503 | #define CHANSIZE_SHIFT 8 |
||
504 | #define CHANSIZE_MASK 0x00000100 |
||
505 | #define BURSTLENGTH_SHIFT 9 |
||
506 | #define BURSTLENGTH_MASK 0x00000200 |
||
507 | #define CHANSIZE_OVERRIDE (1 << 11) |
||
508 | #define FUS_MC_ARB_RAMCFG 0x2768 |
||
509 | #define MC_VM_AGP_TOP 0x2028 |
||
510 | #define MC_VM_AGP_BOT 0x202C |
||
511 | #define MC_VM_AGP_BASE 0x2030 |
||
512 | #define MC_VM_FB_LOCATION 0x2024 |
||
513 | #define MC_FUS_VM_FB_OFFSET 0x2898 |
||
514 | #define MC_VM_MB_L1_TLB0_CNTL 0x2234 |
||
515 | #define MC_VM_MB_L1_TLB1_CNTL 0x2238 |
||
516 | #define MC_VM_MB_L1_TLB2_CNTL 0x223C |
||
517 | #define MC_VM_MB_L1_TLB3_CNTL 0x2240 |
||
518 | #define ENABLE_L1_TLB (1 << 0) |
||
519 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) |
||
520 | #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) |
||
521 | #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) |
||
522 | #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) |
||
523 | #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) |
||
524 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) |
||
525 | #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) |
||
526 | #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) |
||
527 | #define MC_VM_MD_L1_TLB0_CNTL 0x2654 |
||
528 | #define MC_VM_MD_L1_TLB1_CNTL 0x2658 |
||
529 | #define MC_VM_MD_L1_TLB2_CNTL 0x265C |
||
2997 | Serge | 530 | #define MC_VM_MD_L1_TLB3_CNTL 0x2698 |
1963 | serge | 531 | |
532 | #define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C |
||
533 | #define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660 |
||
534 | #define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664 |
||
535 | |||
536 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C |
||
537 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 |
||
538 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 |
||
539 | |||
540 | #define PA_CL_ENHANCE 0x8A14 |
||
541 | #define CLIP_VTX_REORDER_ENA (1 << 0) |
||
542 | #define NUM_CLIP_SEQ(x) ((x) << 1) |
||
2997 | Serge | 543 | #define PA_SC_ENHANCE 0x8BF0 |
1963 | serge | 544 | #define PA_SC_AA_CONFIG 0x28C04 |
545 | #define MSAA_NUM_SAMPLES_SHIFT 0 |
||
546 | #define MSAA_NUM_SAMPLES_MASK 0x3 |
||
547 | #define PA_SC_CLIPRECT_RULE 0x2820C |
||
548 | #define PA_SC_EDGERULE 0x28230 |
||
549 | #define PA_SC_FIFO_SIZE 0x8BCC |
||
550 | #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) |
||
551 | #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) |
||
552 | #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) |
||
553 | #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 |
||
554 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) |
||
555 | #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) |
||
556 | #define PA_SC_LINE_STIPPLE 0x28A0C |
||
557 | #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 |
||
558 | #define PA_SC_LINE_STIPPLE_STATE 0x8B10 |
||
559 | |||
560 | #define SCRATCH_REG0 0x8500 |
||
561 | #define SCRATCH_REG1 0x8504 |
||
562 | #define SCRATCH_REG2 0x8508 |
||
563 | #define SCRATCH_REG3 0x850C |
||
564 | #define SCRATCH_REG4 0x8510 |
||
565 | #define SCRATCH_REG5 0x8514 |
||
566 | #define SCRATCH_REG6 0x8518 |
||
567 | #define SCRATCH_REG7 0x851C |
||
568 | #define SCRATCH_UMSK 0x8540 |
||
569 | #define SCRATCH_ADDR 0x8544 |
||
570 | |||
2997 | Serge | 571 | #define SMX_SAR_CTL0 0xA008 |
1963 | serge | 572 | #define SMX_DC_CTL0 0xA020 |
573 | #define USE_HASH_FUNCTION (1 << 0) |
||
574 | #define NUMBER_OF_SETS(x) ((x) << 1) |
||
575 | #define FLUSH_ALL_ON_EVENT (1 << 10) |
||
576 | #define STALL_ON_EVENT (1 << 11) |
||
577 | #define SMX_EVENT_CTL 0xA02C |
||
578 | #define ES_FLUSH_CTL(x) ((x) << 0) |
||
579 | #define GS_FLUSH_CTL(x) ((x) << 3) |
||
580 | #define ACK_FLUSH_CTL(x) ((x) << 6) |
||
581 | #define SYNC_FLUSH_CTL (1 << 8) |
||
582 | |||
583 | #define SPI_CONFIG_CNTL 0x9100 |
||
584 | #define GPR_WRITE_PRIORITY(x) ((x) << 0) |
||
585 | #define SPI_CONFIG_CNTL_1 0x913C |
||
586 | #define VTX_DONE_DELAY(x) ((x) << 0) |
||
587 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) |
||
588 | #define SPI_INPUT_Z 0x286D8 |
||
589 | #define SPI_PS_IN_CONTROL_0 0x286CC |
||
590 | #define NUM_INTERP(x) ((x)<<0) |
||
591 | #define POSITION_ENA (1<<8) |
||
592 | #define POSITION_CENTROID (1<<9) |
||
593 | #define POSITION_ADDR(x) ((x)<<10) |
||
594 | #define PARAM_GEN(x) ((x)<<15) |
||
595 | #define PARAM_GEN_ADDR(x) ((x)<<19) |
||
596 | #define BARYC_SAMPLE_CNTL(x) ((x)<<26) |
||
597 | #define PERSP_GRADIENT_ENA (1<<28) |
||
598 | #define LINEAR_GRADIENT_ENA (1<<29) |
||
599 | #define POSITION_SAMPLE (1<<30) |
||
600 | #define BARYC_AT_SAMPLE_ENA (1<<31) |
||
601 | |||
602 | #define SQ_CONFIG 0x8C00 |
||
603 | #define VC_ENABLE (1 << 0) |
||
604 | #define EXPORT_SRC_C (1 << 1) |
||
605 | #define CS_PRIO(x) ((x) << 18) |
||
606 | #define LS_PRIO(x) ((x) << 20) |
||
607 | #define HS_PRIO(x) ((x) << 22) |
||
608 | #define PS_PRIO(x) ((x) << 24) |
||
609 | #define VS_PRIO(x) ((x) << 26) |
||
610 | #define GS_PRIO(x) ((x) << 28) |
||
611 | #define ES_PRIO(x) ((x) << 30) |
||
612 | #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 |
||
613 | #define NUM_PS_GPRS(x) ((x) << 0) |
||
614 | #define NUM_VS_GPRS(x) ((x) << 16) |
||
615 | #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) |
||
616 | #define SQ_GPR_RESOURCE_MGMT_2 0x8C08 |
||
617 | #define NUM_GS_GPRS(x) ((x) << 0) |
||
618 | #define NUM_ES_GPRS(x) ((x) << 16) |
||
619 | #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C |
||
620 | #define NUM_HS_GPRS(x) ((x) << 0) |
||
621 | #define NUM_LS_GPRS(x) ((x) << 16) |
||
2997 | Serge | 622 | #define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10 |
623 | #define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14 |
||
1963 | serge | 624 | #define SQ_THREAD_RESOURCE_MGMT 0x8C18 |
625 | #define NUM_PS_THREADS(x) ((x) << 0) |
||
626 | #define NUM_VS_THREADS(x) ((x) << 8) |
||
627 | #define NUM_GS_THREADS(x) ((x) << 16) |
||
628 | #define NUM_ES_THREADS(x) ((x) << 24) |
||
629 | #define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C |
||
630 | #define NUM_HS_THREADS(x) ((x) << 0) |
||
631 | #define NUM_LS_THREADS(x) ((x) << 8) |
||
632 | #define SQ_STACK_RESOURCE_MGMT_1 0x8C20 |
||
633 | #define NUM_PS_STACK_ENTRIES(x) ((x) << 0) |
||
634 | #define NUM_VS_STACK_ENTRIES(x) ((x) << 16) |
||
635 | #define SQ_STACK_RESOURCE_MGMT_2 0x8C24 |
||
636 | #define NUM_GS_STACK_ENTRIES(x) ((x) << 0) |
||
637 | #define NUM_ES_STACK_ENTRIES(x) ((x) << 16) |
||
638 | #define SQ_STACK_RESOURCE_MGMT_3 0x8C28 |
||
639 | #define NUM_HS_STACK_ENTRIES(x) ((x) << 0) |
||
640 | #define NUM_LS_STACK_ENTRIES(x) ((x) << 16) |
||
641 | #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C |
||
2997 | Serge | 642 | #define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94 |
643 | #define SQ_STATIC_THREAD_MGMT_1 0x8E20 |
||
644 | #define SQ_STATIC_THREAD_MGMT_2 0x8E24 |
||
645 | #define SQ_STATIC_THREAD_MGMT_3 0x8E28 |
||
1963 | serge | 646 | #define SQ_LDS_RESOURCE_MGMT 0x8E2C |
647 | |||
648 | #define SQ_MS_FIFO_SIZES 0x8CF0 |
||
649 | #define CACHE_FIFO_SIZE(x) ((x) << 0) |
||
650 | #define FETCH_FIFO_HIWATER(x) ((x) << 8) |
||
651 | #define DONE_FIFO_HIWATER(x) ((x) << 16) |
||
652 | #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) |
||
653 | |||
654 | #define SX_DEBUG_1 0x9058 |
||
655 | #define ENABLE_NEW_SMX_ADDRESS (1 << 16) |
||
656 | #define SX_EXPORT_BUFFER_SIZES 0x900C |
||
657 | #define COLOR_BUFFER_SIZE(x) ((x) << 0) |
||
658 | #define POSITION_BUFFER_SIZE(x) ((x) << 8) |
||
659 | #define SMX_BUFFER_SIZE(x) ((x) << 16) |
||
2160 | serge | 660 | #define SX_MEMORY_EXPORT_BASE 0x9010 |
1963 | serge | 661 | #define SX_MISC 0x28350 |
662 | |||
663 | #define CB_PERF_CTR0_SEL_0 0x9A20 |
||
664 | #define CB_PERF_CTR0_SEL_1 0x9A24 |
||
665 | #define CB_PERF_CTR1_SEL_0 0x9A28 |
||
666 | #define CB_PERF_CTR1_SEL_1 0x9A2C |
||
667 | #define CB_PERF_CTR2_SEL_0 0x9A30 |
||
668 | #define CB_PERF_CTR2_SEL_1 0x9A34 |
||
669 | #define CB_PERF_CTR3_SEL_0 0x9A38 |
||
670 | #define CB_PERF_CTR3_SEL_1 0x9A3C |
||
671 | |||
672 | #define TA_CNTL_AUX 0x9508 |
||
673 | #define DISABLE_CUBE_WRAP (1 << 0) |
||
674 | #define DISABLE_CUBE_ANISO (1 << 1) |
||
675 | #define SYNC_GRADIENT (1 << 24) |
||
676 | #define SYNC_WALKER (1 << 25) |
||
677 | #define SYNC_ALIGNER (1 << 26) |
||
678 | |||
679 | #define TCP_CHAN_STEER_LO 0x960c |
||
680 | #define TCP_CHAN_STEER_HI 0x9610 |
||
681 | |||
682 | #define VGT_CACHE_INVALIDATION 0x88C4 |
||
683 | #define CACHE_INVALIDATION(x) ((x) << 0) |
||
684 | #define VC_ONLY 0 |
||
685 | #define TC_ONLY 1 |
||
686 | #define VC_AND_TC 2 |
||
687 | #define AUTO_INVLD_EN(x) ((x) << 6) |
||
688 | #define NO_AUTO 0 |
||
689 | #define ES_AUTO 1 |
||
690 | #define GS_AUTO 2 |
||
691 | #define ES_AND_GS_AUTO 3 |
||
692 | #define VGT_GS_VERTEX_REUSE 0x88D4 |
||
693 | #define VGT_NUM_INSTANCES 0x8974 |
||
694 | #define VGT_OUT_DEALLOC_CNTL 0x28C5C |
||
695 | #define DEALLOC_DIST_MASK 0x0000007F |
||
696 | #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 |
||
697 | #define VTX_REUSE_DEPTH_MASK 0x000000FF |
||
698 | |||
699 | #define VM_CONTEXT0_CNTL 0x1410 |
||
700 | #define ENABLE_CONTEXT (1 << 0) |
||
701 | #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) |
||
702 | #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) |
||
703 | #define VM_CONTEXT1_CNTL 0x1414 |
||
3192 | Serge | 704 | #define VM_CONTEXT1_CNTL2 0x1434 |
1963 | serge | 705 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C |
706 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C |
||
707 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C |
||
708 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 |
||
709 | #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 |
||
710 | #define REQUEST_TYPE(x) (((x) & 0xf) << 0) |
||
711 | #define RESPONSE_TYPE_MASK 0x000000F0 |
||
712 | #define RESPONSE_TYPE_SHIFT 4 |
||
713 | #define VM_L2_CNTL 0x1400 |
||
714 | #define ENABLE_L2_CACHE (1 << 0) |
||
715 | #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) |
||
716 | #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) |
||
717 | #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) |
||
718 | #define VM_L2_CNTL2 0x1404 |
||
719 | #define INVALIDATE_ALL_L1_TLBS (1 << 0) |
||
720 | #define INVALIDATE_L2_CACHE (1 << 1) |
||
721 | #define VM_L2_CNTL3 0x1408 |
||
722 | #define BANK_SELECT(x) ((x) << 0) |
||
723 | #define CACHE_UPDATE_MODE(x) ((x) << 6) |
||
724 | #define VM_L2_STATUS 0x140C |
||
725 | #define L2_BUSY (1 << 0) |
||
3192 | Serge | 726 | #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC |
727 | #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC |
||
1963 | serge | 728 | |
729 | #define WAIT_UNTIL 0x8040 |
||
730 | |||
731 | #define SRBM_STATUS 0x0E50 |
||
732 | #define SRBM_SOFT_RESET 0x0E60 |
||
733 | #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 |
||
734 | #define SOFT_RESET_BIF (1 << 1) |
||
735 | #define SOFT_RESET_CG (1 << 2) |
||
736 | #define SOFT_RESET_DC (1 << 5) |
||
737 | #define SOFT_RESET_GRBM (1 << 8) |
||
738 | #define SOFT_RESET_HDP (1 << 9) |
||
739 | #define SOFT_RESET_IH (1 << 10) |
||
740 | #define SOFT_RESET_MC (1 << 11) |
||
741 | #define SOFT_RESET_RLC (1 << 13) |
||
742 | #define SOFT_RESET_ROM (1 << 14) |
||
743 | #define SOFT_RESET_SEM (1 << 15) |
||
744 | #define SOFT_RESET_VMC (1 << 17) |
||
3192 | Serge | 745 | #define SOFT_RESET_DMA (1 << 20) |
1963 | serge | 746 | #define SOFT_RESET_TST (1 << 21) |
747 | #define SOFT_RESET_REGBB (1 << 22) |
||
748 | #define SOFT_RESET_ORB (1 << 23) |
||
749 | |||
750 | /* display watermarks */ |
||
751 | #define DC_LB_MEMORY_SPLIT 0x6b0c |
||
752 | #define PRIORITY_A_CNT 0x6b18 |
||
753 | #define PRIORITY_MARK_MASK 0x7fff |
||
754 | #define PRIORITY_OFF (1 << 16) |
||
755 | #define PRIORITY_ALWAYS_ON (1 << 20) |
||
756 | #define PRIORITY_B_CNT 0x6b1c |
||
757 | #define PIPE0_ARBITRATION_CONTROL3 0x0bf0 |
||
758 | # define LATENCY_WATERMARK_MASK(x) ((x) << 16) |
||
759 | #define PIPE0_LATENCY_CONTROL 0x0bf4 |
||
760 | # define LATENCY_LOW_WATERMARK(x) ((x) << 0) |
||
761 | # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) |
||
762 | |||
763 | #define IH_RB_CNTL 0x3e00 |
||
764 | # define IH_RB_ENABLE (1 << 0) |
||
765 | # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ |
||
766 | # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) |
||
767 | # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) |
||
768 | # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ |
||
769 | # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) |
||
770 | # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) |
||
771 | #define IH_RB_BASE 0x3e04 |
||
772 | #define IH_RB_RPTR 0x3e08 |
||
773 | #define IH_RB_WPTR 0x3e0c |
||
774 | # define RB_OVERFLOW (1 << 0) |
||
775 | # define WPTR_OFFSET_MASK 0x3fffc |
||
776 | #define IH_RB_WPTR_ADDR_HI 0x3e10 |
||
777 | #define IH_RB_WPTR_ADDR_LO 0x3e14 |
||
778 | #define IH_CNTL 0x3e18 |
||
779 | # define ENABLE_INTR (1 << 0) |
||
2004 | serge | 780 | # define IH_MC_SWAP(x) ((x) << 1) |
1963 | serge | 781 | # define IH_MC_SWAP_NONE 0 |
782 | # define IH_MC_SWAP_16BIT 1 |
||
783 | # define IH_MC_SWAP_32BIT 2 |
||
784 | # define IH_MC_SWAP_64BIT 3 |
||
785 | # define RPTR_REARM (1 << 4) |
||
786 | # define MC_WRREQ_CREDIT(x) ((x) << 15) |
||
787 | # define MC_WR_CLEAN_CNT(x) ((x) << 20) |
||
788 | |||
789 | #define CP_INT_CNTL 0xc124 |
||
790 | # define CNTX_BUSY_INT_ENABLE (1 << 19) |
||
791 | # define CNTX_EMPTY_INT_ENABLE (1 << 20) |
||
792 | # define SCRATCH_INT_ENABLE (1 << 25) |
||
793 | # define TIME_STAMP_INT_ENABLE (1 << 26) |
||
794 | # define IB2_INT_ENABLE (1 << 29) |
||
795 | # define IB1_INT_ENABLE (1 << 30) |
||
796 | # define RB_INT_ENABLE (1 << 31) |
||
797 | #define CP_INT_STATUS 0xc128 |
||
798 | # define SCRATCH_INT_STAT (1 << 25) |
||
799 | # define TIME_STAMP_INT_STAT (1 << 26) |
||
800 | # define IB2_INT_STAT (1 << 29) |
||
801 | # define IB1_INT_STAT (1 << 30) |
||
802 | # define RB_INT_STAT (1 << 31) |
||
803 | |||
804 | #define GRBM_INT_CNTL 0x8060 |
||
805 | # define RDERR_INT_ENABLE (1 << 0) |
||
806 | # define GUI_IDLE_INT_ENABLE (1 << 19) |
||
807 | |||
808 | /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ |
||
809 | #define CRTC_STATUS_FRAME_COUNT 0x6e98 |
||
810 | |||
811 | /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ |
||
812 | #define VLINE_STATUS 0x6bb8 |
||
813 | # define VLINE_OCCURRED (1 << 0) |
||
814 | # define VLINE_ACK (1 << 4) |
||
815 | # define VLINE_STAT (1 << 12) |
||
816 | # define VLINE_INTERRUPT (1 << 16) |
||
817 | # define VLINE_INTERRUPT_TYPE (1 << 17) |
||
818 | /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ |
||
819 | #define VBLANK_STATUS 0x6bbc |
||
820 | # define VBLANK_OCCURRED (1 << 0) |
||
821 | # define VBLANK_ACK (1 << 4) |
||
822 | # define VBLANK_STAT (1 << 12) |
||
823 | # define VBLANK_INTERRUPT (1 << 16) |
||
824 | # define VBLANK_INTERRUPT_TYPE (1 << 17) |
||
825 | |||
826 | /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ |
||
827 | #define INT_MASK 0x6b40 |
||
828 | # define VBLANK_INT_MASK (1 << 0) |
||
829 | # define VLINE_INT_MASK (1 << 4) |
||
830 | |||
831 | #define DISP_INTERRUPT_STATUS 0x60f4 |
||
832 | # define LB_D1_VLINE_INTERRUPT (1 << 2) |
||
833 | # define LB_D1_VBLANK_INTERRUPT (1 << 3) |
||
834 | # define DC_HPD1_INTERRUPT (1 << 17) |
||
835 | # define DC_HPD1_RX_INTERRUPT (1 << 18) |
||
836 | # define DACA_AUTODETECT_INTERRUPT (1 << 22) |
||
837 | # define DACB_AUTODETECT_INTERRUPT (1 << 23) |
||
838 | # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) |
||
839 | # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) |
||
840 | #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 |
||
841 | # define LB_D2_VLINE_INTERRUPT (1 << 2) |
||
842 | # define LB_D2_VBLANK_INTERRUPT (1 << 3) |
||
843 | # define DC_HPD2_INTERRUPT (1 << 17) |
||
844 | # define DC_HPD2_RX_INTERRUPT (1 << 18) |
||
845 | # define DISP_TIMER_INTERRUPT (1 << 24) |
||
846 | #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc |
||
847 | # define LB_D3_VLINE_INTERRUPT (1 << 2) |
||
848 | # define LB_D3_VBLANK_INTERRUPT (1 << 3) |
||
849 | # define DC_HPD3_INTERRUPT (1 << 17) |
||
850 | # define DC_HPD3_RX_INTERRUPT (1 << 18) |
||
851 | #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 |
||
852 | # define LB_D4_VLINE_INTERRUPT (1 << 2) |
||
853 | # define LB_D4_VBLANK_INTERRUPT (1 << 3) |
||
854 | # define DC_HPD4_INTERRUPT (1 << 17) |
||
855 | # define DC_HPD4_RX_INTERRUPT (1 << 18) |
||
856 | #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c |
||
857 | # define LB_D5_VLINE_INTERRUPT (1 << 2) |
||
858 | # define LB_D5_VBLANK_INTERRUPT (1 << 3) |
||
859 | # define DC_HPD5_INTERRUPT (1 << 17) |
||
860 | # define DC_HPD5_RX_INTERRUPT (1 << 18) |
||
2004 | serge | 861 | #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 |
1963 | serge | 862 | # define LB_D6_VLINE_INTERRUPT (1 << 2) |
863 | # define LB_D6_VBLANK_INTERRUPT (1 << 3) |
||
864 | # define DC_HPD6_INTERRUPT (1 << 17) |
||
865 | # define DC_HPD6_RX_INTERRUPT (1 << 18) |
||
866 | |||
867 | /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ |
||
868 | #define GRPH_INT_STATUS 0x6858 |
||
869 | # define GRPH_PFLIP_INT_OCCURRED (1 << 0) |
||
870 | # define GRPH_PFLIP_INT_CLEAR (1 << 8) |
||
871 | /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ |
||
872 | #define GRPH_INT_CONTROL 0x685c |
||
873 | # define GRPH_PFLIP_INT_MASK (1 << 0) |
||
874 | # define GRPH_PFLIP_INT_TYPE (1 << 8) |
||
875 | |||
876 | #define DACA_AUTODETECT_INT_CONTROL 0x66c8 |
||
877 | #define DACB_AUTODETECT_INT_CONTROL 0x67c8 |
||
878 | |||
879 | #define DC_HPD1_INT_STATUS 0x601c |
||
880 | #define DC_HPD2_INT_STATUS 0x6028 |
||
881 | #define DC_HPD3_INT_STATUS 0x6034 |
||
882 | #define DC_HPD4_INT_STATUS 0x6040 |
||
883 | #define DC_HPD5_INT_STATUS 0x604c |
||
884 | #define DC_HPD6_INT_STATUS 0x6058 |
||
885 | # define DC_HPDx_INT_STATUS (1 << 0) |
||
886 | # define DC_HPDx_SENSE (1 << 1) |
||
887 | # define DC_HPDx_RX_INT_STATUS (1 << 8) |
||
888 | |||
889 | #define DC_HPD1_INT_CONTROL 0x6020 |
||
890 | #define DC_HPD2_INT_CONTROL 0x602c |
||
891 | #define DC_HPD3_INT_CONTROL 0x6038 |
||
892 | #define DC_HPD4_INT_CONTROL 0x6044 |
||
893 | #define DC_HPD5_INT_CONTROL 0x6050 |
||
894 | #define DC_HPD6_INT_CONTROL 0x605c |
||
895 | # define DC_HPDx_INT_ACK (1 << 0) |
||
896 | # define DC_HPDx_INT_POLARITY (1 << 8) |
||
897 | # define DC_HPDx_INT_EN (1 << 16) |
||
898 | # define DC_HPDx_RX_INT_ACK (1 << 20) |
||
899 | # define DC_HPDx_RX_INT_EN (1 << 24) |
||
900 | |||
901 | #define DC_HPD1_CONTROL 0x6024 |
||
902 | #define DC_HPD2_CONTROL 0x6030 |
||
903 | #define DC_HPD3_CONTROL 0x603c |
||
904 | #define DC_HPD4_CONTROL 0x6048 |
||
905 | #define DC_HPD5_CONTROL 0x6054 |
||
906 | #define DC_HPD6_CONTROL 0x6060 |
||
907 | # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) |
||
908 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) |
||
909 | # define DC_HPDx_EN (1 << 28) |
||
910 | |||
3192 | Serge | 911 | /* ASYNC DMA */ |
912 | #define DMA_RB_RPTR 0xd008 |
||
913 | #define DMA_RB_WPTR 0xd00c |
||
914 | |||
915 | #define DMA_CNTL 0xd02c |
||
916 | # define TRAP_ENABLE (1 << 0) |
||
917 | # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) |
||
918 | # define SEM_WAIT_INT_ENABLE (1 << 2) |
||
919 | # define DATA_SWAP_ENABLE (1 << 3) |
||
920 | # define FENCE_SWAP_ENABLE (1 << 4) |
||
921 | # define CTXEMPTY_INT_ENABLE (1 << 28) |
||
922 | #define DMA_TILING_CONFIG 0xD0B8 |
||
923 | |||
924 | #define CAYMAN_DMA1_CNTL 0xd82c |
||
925 | |||
926 | /* async DMA packets */ |
||
927 | #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ |
||
928 | (((t) & 0x1) << 23) | \ |
||
929 | (((s) & 0x1) << 22) | \ |
||
930 | (((n) & 0xFFFFF) << 0)) |
||
931 | /* async DMA Packet types */ |
||
932 | #define DMA_PACKET_WRITE 0x2 |
||
933 | #define DMA_PACKET_COPY 0x3 |
||
934 | #define DMA_PACKET_INDIRECT_BUFFER 0x4 |
||
935 | #define DMA_PACKET_SEMAPHORE 0x5 |
||
936 | #define DMA_PACKET_FENCE 0x6 |
||
937 | #define DMA_PACKET_TRAP 0x7 |
||
938 | #define DMA_PACKET_SRBM_WRITE 0x9 |
||
939 | #define DMA_PACKET_CONSTANT_FILL 0xd |
||
940 | #define DMA_PACKET_NOP 0xf |
||
941 | |||
1963 | serge | 942 | /* PCIE link stuff */ |
943 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ |
||
944 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ |
||
945 | # define LC_LINK_WIDTH_SHIFT 0 |
||
946 | # define LC_LINK_WIDTH_MASK 0x7 |
||
947 | # define LC_LINK_WIDTH_X0 0 |
||
948 | # define LC_LINK_WIDTH_X1 1 |
||
949 | # define LC_LINK_WIDTH_X2 2 |
||
950 | # define LC_LINK_WIDTH_X4 3 |
||
951 | # define LC_LINK_WIDTH_X8 4 |
||
952 | # define LC_LINK_WIDTH_X16 6 |
||
953 | # define LC_LINK_WIDTH_RD_SHIFT 4 |
||
954 | # define LC_LINK_WIDTH_RD_MASK 0x70 |
||
955 | # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) |
||
956 | # define LC_RECONFIG_NOW (1 << 8) |
||
957 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) |
||
958 | # define LC_RENEGOTIATE_EN (1 << 10) |
||
959 | # define LC_SHORT_RECONFIG_EN (1 << 11) |
||
960 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) |
||
961 | # define LC_UPCONFIGURE_DIS (1 << 13) |
||
962 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ |
||
963 | # define LC_GEN2_EN_STRAP (1 << 0) |
||
964 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) |
||
965 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) |
||
966 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) |
||
967 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) |
||
968 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 |
||
969 | # define LC_CURRENT_DATA_RATE (1 << 11) |
||
970 | # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) |
||
971 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) |
||
972 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) |
||
973 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) |
||
974 | #define MM_CFGREGS_CNTL 0x544c |
||
975 | # define MM_WR_TO_CFG_EN (1 << 3) |
||
976 | #define LINK_CNTL2 0x88 /* F0 */ |
||
977 | # define TARGET_LINK_SPEED_MASK (0xf << 0) |
||
978 | # define SELECTABLE_DEEMPHASIS (1 << 6) |
||
979 | |||
980 | /* |
||
981 | * PM4 |
||
982 | */ |
||
983 | #define PACKET_TYPE0 0 |
||
984 | #define PACKET_TYPE1 1 |
||
985 | #define PACKET_TYPE2 2 |
||
986 | #define PACKET_TYPE3 3 |
||
987 | |||
988 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) |
||
989 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) |
||
990 | #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) |
||
991 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
||
992 | #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ |
||
993 | (((reg) >> 2) & 0xFFFF) | \ |
||
994 | ((n) & 0x3FFF) << 16) |
||
995 | #define CP_PACKET2 0x80000000 |
||
996 | #define PACKET2_PAD_SHIFT 0 |
||
997 | #define PACKET2_PAD_MASK (0x3fffffff << 0) |
||
998 | |||
999 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) |
||
1000 | |||
1001 | #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ |
||
1002 | (((op) & 0xFF) << 8) | \ |
||
1003 | ((n) & 0x3FFF) << 16) |
||
1004 | |||
1005 | /* Packet 3 types */ |
||
1006 | #define PACKET3_NOP 0x10 |
||
1007 | #define PACKET3_SET_BASE 0x11 |
||
1008 | #define PACKET3_CLEAR_STATE 0x12 |
||
1009 | #define PACKET3_INDEX_BUFFER_SIZE 0x13 |
||
1010 | #define PACKET3_DISPATCH_DIRECT 0x15 |
||
1011 | #define PACKET3_DISPATCH_INDIRECT 0x16 |
||
1012 | #define PACKET3_INDIRECT_BUFFER_END 0x17 |
||
1013 | #define PACKET3_MODE_CONTROL 0x18 |
||
1014 | #define PACKET3_SET_PREDICATION 0x20 |
||
1015 | #define PACKET3_REG_RMW 0x21 |
||
1016 | #define PACKET3_COND_EXEC 0x22 |
||
1017 | #define PACKET3_PRED_EXEC 0x23 |
||
1018 | #define PACKET3_DRAW_INDIRECT 0x24 |
||
1019 | #define PACKET3_DRAW_INDEX_INDIRECT 0x25 |
||
1020 | #define PACKET3_INDEX_BASE 0x26 |
||
1021 | #define PACKET3_DRAW_INDEX_2 0x27 |
||
1022 | #define PACKET3_CONTEXT_CONTROL 0x28 |
||
1023 | #define PACKET3_DRAW_INDEX_OFFSET 0x29 |
||
1024 | #define PACKET3_INDEX_TYPE 0x2A |
||
1025 | #define PACKET3_DRAW_INDEX 0x2B |
||
1026 | #define PACKET3_DRAW_INDEX_AUTO 0x2D |
||
1027 | #define PACKET3_DRAW_INDEX_IMMD 0x2E |
||
1028 | #define PACKET3_NUM_INSTANCES 0x2F |
||
1029 | #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 |
||
1030 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 |
||
1031 | #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 |
||
1032 | #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 |
||
1033 | #define PACKET3_MEM_SEMAPHORE 0x39 |
||
1034 | #define PACKET3_MPEG_INDEX 0x3A |
||
2997 | Serge | 1035 | #define PACKET3_COPY_DW 0x3B |
1963 | serge | 1036 | #define PACKET3_WAIT_REG_MEM 0x3C |
1037 | #define PACKET3_MEM_WRITE 0x3D |
||
1038 | #define PACKET3_INDIRECT_BUFFER 0x32 |
||
3192 | Serge | 1039 | #define PACKET3_CP_DMA 0x41 |
1040 | /* 1. header |
||
1041 | * 2. SRC_ADDR_LO or DATA [31:0] |
||
1042 | * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | |
||
1043 | * SRC_ADDR_HI [7:0] |
||
1044 | * 4. DST_ADDR_LO [31:0] |
||
1045 | * 5. DST_ADDR_HI [7:0] |
||
1046 | * 6. COMMAND [29:22] | BYTE_COUNT [20:0] |
||
1047 | */ |
||
1048 | # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) |
||
1049 | /* 0 - SRC_ADDR |
||
1050 | * 1 - GDS |
||
1051 | */ |
||
1052 | # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) |
||
1053 | /* 0 - ME |
||
1054 | * 1 - PFP |
||
1055 | */ |
||
1056 | # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) |
||
1057 | /* 0 - SRC_ADDR |
||
1058 | * 1 - GDS |
||
1059 | * 2 - DATA |
||
1060 | */ |
||
1061 | # define PACKET3_CP_DMA_CP_SYNC (1 << 31) |
||
1062 | /* COMMAND */ |
||
1063 | # define PACKET3_CP_DMA_DIS_WC (1 << 21) |
||
1064 | # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) |
||
1065 | /* 0 - none |
||
1066 | * 1 - 8 in 16 |
||
1067 | * 2 - 8 in 32 |
||
1068 | * 3 - 8 in 64 |
||
1069 | */ |
||
1070 | # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) |
||
1071 | /* 0 - none |
||
1072 | * 1 - 8 in 16 |
||
1073 | * 2 - 8 in 32 |
||
1074 | * 3 - 8 in 64 |
||
1075 | */ |
||
1076 | # define PACKET3_CP_DMA_CMD_SAS (1 << 26) |
||
1077 | /* 0 - memory |
||
1078 | * 1 - register |
||
1079 | */ |
||
1080 | # define PACKET3_CP_DMA_CMD_DAS (1 << 27) |
||
1081 | /* 0 - memory |
||
1082 | * 1 - register |
||
1083 | */ |
||
1084 | # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) |
||
1085 | # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) |
||
1963 | serge | 1086 | #define PACKET3_SURFACE_SYNC 0x43 |
1087 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
||
1088 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) |
||
1089 | # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) |
||
1090 | # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) |
||
1091 | # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) |
||
1092 | # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) |
||
1093 | # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) |
||
1094 | # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) |
||
1095 | # define PACKET3_DB_DEST_BASE_ENA (1 << 14) |
||
1096 | # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) |
||
1097 | # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) |
||
1098 | # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) |
||
1099 | # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) |
||
1100 | # define PACKET3_FULL_CACHE_ENA (1 << 20) |
||
1101 | # define PACKET3_TC_ACTION_ENA (1 << 23) |
||
1102 | # define PACKET3_VC_ACTION_ENA (1 << 24) |
||
1103 | # define PACKET3_CB_ACTION_ENA (1 << 25) |
||
1104 | # define PACKET3_DB_ACTION_ENA (1 << 26) |
||
1105 | # define PACKET3_SH_ACTION_ENA (1 << 27) |
||
1106 | # define PACKET3_SX_ACTION_ENA (1 << 28) |
||
1107 | #define PACKET3_ME_INITIALIZE 0x44 |
||
1108 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) |
||
1109 | #define PACKET3_COND_WRITE 0x45 |
||
1110 | #define PACKET3_EVENT_WRITE 0x46 |
||
1111 | #define PACKET3_EVENT_WRITE_EOP 0x47 |
||
1112 | #define PACKET3_EVENT_WRITE_EOS 0x48 |
||
1113 | #define PACKET3_PREAMBLE_CNTL 0x4A |
||
1114 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) |
||
1115 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) |
||
1116 | #define PACKET3_RB_OFFSET 0x4B |
||
1117 | #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C |
||
1118 | #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D |
||
1119 | #define PACKET3_ALU_PS_CONST_UPDATE 0x4E |
||
1120 | #define PACKET3_ALU_VS_CONST_UPDATE 0x4F |
||
1121 | #define PACKET3_ONE_REG_WRITE 0x57 |
||
1122 | #define PACKET3_SET_CONFIG_REG 0x68 |
||
1123 | #define PACKET3_SET_CONFIG_REG_START 0x00008000 |
||
1124 | #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 |
||
1125 | #define PACKET3_SET_CONTEXT_REG 0x69 |
||
1126 | #define PACKET3_SET_CONTEXT_REG_START 0x00028000 |
||
1127 | #define PACKET3_SET_CONTEXT_REG_END 0x00029000 |
||
1128 | #define PACKET3_SET_ALU_CONST 0x6A |
||
1129 | /* alu const buffers only; no reg file */ |
||
1130 | #define PACKET3_SET_BOOL_CONST 0x6B |
||
1131 | #define PACKET3_SET_BOOL_CONST_START 0x0003a500 |
||
1132 | #define PACKET3_SET_BOOL_CONST_END 0x0003a518 |
||
1133 | #define PACKET3_SET_LOOP_CONST 0x6C |
||
1134 | #define PACKET3_SET_LOOP_CONST_START 0x0003a200 |
||
1135 | #define PACKET3_SET_LOOP_CONST_END 0x0003a500 |
||
1136 | #define PACKET3_SET_RESOURCE 0x6D |
||
1137 | #define PACKET3_SET_RESOURCE_START 0x00030000 |
||
1138 | #define PACKET3_SET_RESOURCE_END 0x00038000 |
||
1139 | #define PACKET3_SET_SAMPLER 0x6E |
||
1140 | #define PACKET3_SET_SAMPLER_START 0x0003c000 |
||
1141 | #define PACKET3_SET_SAMPLER_END 0x0003c600 |
||
1142 | #define PACKET3_SET_CTL_CONST 0x6F |
||
1143 | #define PACKET3_SET_CTL_CONST_START 0x0003cff0 |
||
1144 | #define PACKET3_SET_CTL_CONST_END 0x0003ff0c |
||
1145 | #define PACKET3_SET_RESOURCE_OFFSET 0x70 |
||
1146 | #define PACKET3_SET_ALU_CONST_VS 0x71 |
||
1147 | #define PACKET3_SET_ALU_CONST_DI 0x72 |
||
1148 | #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 |
||
1149 | #define PACKET3_SET_RESOURCE_INDIRECT 0x74 |
||
1150 | #define PACKET3_SET_APPEND_CNT 0x75 |
||
1151 | |||
1152 | #define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c |
||
1153 | #define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) |
||
1154 | #define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) |
||
1155 | #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 |
||
1156 | #define SQ_TEX_VTX_INVALID_BUFFER 0x1 |
||
1157 | #define SQ_TEX_VTX_VALID_TEXTURE 0x2 |
||
1158 | #define SQ_TEX_VTX_VALID_BUFFER 0x3 |
||
1159 | |||
2997 | Serge | 1160 | #define VGT_VTX_VECT_EJECT_REG 0x88b0 |
1161 | |||
1963 | serge | 1162 | #define SQ_CONST_MEM_BASE 0x8df8 |
1163 | |||
1164 | #define SQ_ESGS_RING_BASE 0x8c40 |
||
1165 | #define SQ_ESGS_RING_SIZE 0x8c44 |
||
1166 | #define SQ_GSVS_RING_BASE 0x8c48 |
||
1167 | #define SQ_GSVS_RING_SIZE 0x8c4c |
||
1168 | #define SQ_ESTMP_RING_BASE 0x8c50 |
||
1169 | #define SQ_ESTMP_RING_SIZE 0x8c54 |
||
1170 | #define SQ_GSTMP_RING_BASE 0x8c58 |
||
1171 | #define SQ_GSTMP_RING_SIZE 0x8c5c |
||
1172 | #define SQ_VSTMP_RING_BASE 0x8c60 |
||
1173 | #define SQ_VSTMP_RING_SIZE 0x8c64 |
||
1174 | #define SQ_PSTMP_RING_BASE 0x8c68 |
||
1175 | #define SQ_PSTMP_RING_SIZE 0x8c6c |
||
1176 | #define SQ_LSTMP_RING_BASE 0x8e10 |
||
1177 | #define SQ_LSTMP_RING_SIZE 0x8e14 |
||
1178 | #define SQ_HSTMP_RING_BASE 0x8e18 |
||
1179 | #define SQ_HSTMP_RING_SIZE 0x8e1c |
||
1180 | #define VGT_TF_RING_SIZE 0x8988 |
||
1181 | |||
1182 | #define SQ_ESGS_RING_ITEMSIZE 0x28900 |
||
1183 | #define SQ_GSVS_RING_ITEMSIZE 0x28904 |
||
1184 | #define SQ_ESTMP_RING_ITEMSIZE 0x28908 |
||
1185 | #define SQ_GSTMP_RING_ITEMSIZE 0x2890c |
||
1186 | #define SQ_VSTMP_RING_ITEMSIZE 0x28910 |
||
1187 | #define SQ_PSTMP_RING_ITEMSIZE 0x28914 |
||
1188 | #define SQ_LSTMP_RING_ITEMSIZE 0x28830 |
||
1189 | #define SQ_HSTMP_RING_ITEMSIZE 0x28834 |
||
1190 | |||
1191 | #define SQ_GS_VERT_ITEMSIZE 0x2891c |
||
1192 | #define SQ_GS_VERT_ITEMSIZE_1 0x28920 |
||
1193 | #define SQ_GS_VERT_ITEMSIZE_2 0x28924 |
||
1194 | #define SQ_GS_VERT_ITEMSIZE_3 0x28928 |
||
1195 | #define SQ_GSVS_RING_OFFSET_1 0x2892c |
||
1196 | #define SQ_GSVS_RING_OFFSET_2 0x28930 |
||
1197 | #define SQ_GSVS_RING_OFFSET_3 0x28934 |
||
1198 | |||
1199 | #define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140 |
||
1200 | #define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80 |
||
1201 | |||
1202 | #define SQ_ALU_CONST_CACHE_PS_0 0x28940 |
||
1203 | #define SQ_ALU_CONST_CACHE_PS_1 0x28944 |
||
1204 | #define SQ_ALU_CONST_CACHE_PS_2 0x28948 |
||
1205 | #define SQ_ALU_CONST_CACHE_PS_3 0x2894c |
||
1206 | #define SQ_ALU_CONST_CACHE_PS_4 0x28950 |
||
1207 | #define SQ_ALU_CONST_CACHE_PS_5 0x28954 |
||
1208 | #define SQ_ALU_CONST_CACHE_PS_6 0x28958 |
||
1209 | #define SQ_ALU_CONST_CACHE_PS_7 0x2895c |
||
1210 | #define SQ_ALU_CONST_CACHE_PS_8 0x28960 |
||
1211 | #define SQ_ALU_CONST_CACHE_PS_9 0x28964 |
||
1212 | #define SQ_ALU_CONST_CACHE_PS_10 0x28968 |
||
1213 | #define SQ_ALU_CONST_CACHE_PS_11 0x2896c |
||
1214 | #define SQ_ALU_CONST_CACHE_PS_12 0x28970 |
||
1215 | #define SQ_ALU_CONST_CACHE_PS_13 0x28974 |
||
1216 | #define SQ_ALU_CONST_CACHE_PS_14 0x28978 |
||
1217 | #define SQ_ALU_CONST_CACHE_PS_15 0x2897c |
||
1218 | #define SQ_ALU_CONST_CACHE_VS_0 0x28980 |
||
1219 | #define SQ_ALU_CONST_CACHE_VS_1 0x28984 |
||
1220 | #define SQ_ALU_CONST_CACHE_VS_2 0x28988 |
||
1221 | #define SQ_ALU_CONST_CACHE_VS_3 0x2898c |
||
1222 | #define SQ_ALU_CONST_CACHE_VS_4 0x28990 |
||
1223 | #define SQ_ALU_CONST_CACHE_VS_5 0x28994 |
||
1224 | #define SQ_ALU_CONST_CACHE_VS_6 0x28998 |
||
1225 | #define SQ_ALU_CONST_CACHE_VS_7 0x2899c |
||
1226 | #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 |
||
1227 | #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 |
||
1228 | #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 |
||
1229 | #define SQ_ALU_CONST_CACHE_VS_11 0x289ac |
||
1230 | #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 |
||
1231 | #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 |
||
1232 | #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 |
||
1233 | #define SQ_ALU_CONST_CACHE_VS_15 0x289bc |
||
1234 | #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 |
||
1235 | #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 |
||
1236 | #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 |
||
1237 | #define SQ_ALU_CONST_CACHE_GS_3 0x289cc |
||
1238 | #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 |
||
1239 | #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 |
||
1240 | #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 |
||
1241 | #define SQ_ALU_CONST_CACHE_GS_7 0x289dc |
||
1242 | #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 |
||
1243 | #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 |
||
1244 | #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 |
||
1245 | #define SQ_ALU_CONST_CACHE_GS_11 0x289ec |
||
1246 | #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 |
||
1247 | #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 |
||
1248 | #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 |
||
1249 | #define SQ_ALU_CONST_CACHE_GS_15 0x289fc |
||
1250 | #define SQ_ALU_CONST_CACHE_HS_0 0x28f00 |
||
1251 | #define SQ_ALU_CONST_CACHE_HS_1 0x28f04 |
||
1252 | #define SQ_ALU_CONST_CACHE_HS_2 0x28f08 |
||
1253 | #define SQ_ALU_CONST_CACHE_HS_3 0x28f0c |
||
1254 | #define SQ_ALU_CONST_CACHE_HS_4 0x28f10 |
||
1255 | #define SQ_ALU_CONST_CACHE_HS_5 0x28f14 |
||
1256 | #define SQ_ALU_CONST_CACHE_HS_6 0x28f18 |
||
1257 | #define SQ_ALU_CONST_CACHE_HS_7 0x28f1c |
||
1258 | #define SQ_ALU_CONST_CACHE_HS_8 0x28f20 |
||
1259 | #define SQ_ALU_CONST_CACHE_HS_9 0x28f24 |
||
1260 | #define SQ_ALU_CONST_CACHE_HS_10 0x28f28 |
||
1261 | #define SQ_ALU_CONST_CACHE_HS_11 0x28f2c |
||
1262 | #define SQ_ALU_CONST_CACHE_HS_12 0x28f30 |
||
1263 | #define SQ_ALU_CONST_CACHE_HS_13 0x28f34 |
||
1264 | #define SQ_ALU_CONST_CACHE_HS_14 0x28f38 |
||
1265 | #define SQ_ALU_CONST_CACHE_HS_15 0x28f3c |
||
1266 | #define SQ_ALU_CONST_CACHE_LS_0 0x28f40 |
||
1267 | #define SQ_ALU_CONST_CACHE_LS_1 0x28f44 |
||
1268 | #define SQ_ALU_CONST_CACHE_LS_2 0x28f48 |
||
1269 | #define SQ_ALU_CONST_CACHE_LS_3 0x28f4c |
||
1270 | #define SQ_ALU_CONST_CACHE_LS_4 0x28f50 |
||
1271 | #define SQ_ALU_CONST_CACHE_LS_5 0x28f54 |
||
1272 | #define SQ_ALU_CONST_CACHE_LS_6 0x28f58 |
||
1273 | #define SQ_ALU_CONST_CACHE_LS_7 0x28f5c |
||
1274 | #define SQ_ALU_CONST_CACHE_LS_8 0x28f60 |
||
1275 | #define SQ_ALU_CONST_CACHE_LS_9 0x28f64 |
||
1276 | #define SQ_ALU_CONST_CACHE_LS_10 0x28f68 |
||
1277 | #define SQ_ALU_CONST_CACHE_LS_11 0x28f6c |
||
1278 | #define SQ_ALU_CONST_CACHE_LS_12 0x28f70 |
||
1279 | #define SQ_ALU_CONST_CACHE_LS_13 0x28f74 |
||
1280 | #define SQ_ALU_CONST_CACHE_LS_14 0x28f78 |
||
1281 | #define SQ_ALU_CONST_CACHE_LS_15 0x28f7c |
||
1282 | |||
1283 | #define PA_SC_SCREEN_SCISSOR_TL 0x28030 |
||
1284 | #define PA_SC_GENERIC_SCISSOR_TL 0x28240 |
||
1285 | #define PA_SC_WINDOW_SCISSOR_TL 0x28204 |
||
2997 | Serge | 1286 | |
1963 | serge | 1287 | #define VGT_PRIMITIVE_TYPE 0x8958 |
2997 | Serge | 1288 | #define VGT_INDEX_TYPE 0x895C |
1963 | serge | 1289 | |
2997 | Serge | 1290 | #define VGT_NUM_INDICES 0x8970 |
1291 | |||
1292 | #define VGT_COMPUTE_DIM_X 0x8990 |
||
1293 | #define VGT_COMPUTE_DIM_Y 0x8994 |
||
1294 | #define VGT_COMPUTE_DIM_Z 0x8998 |
||
1295 | #define VGT_COMPUTE_START_X 0x899C |
||
1296 | #define VGT_COMPUTE_START_Y 0x89A0 |
||
1297 | #define VGT_COMPUTE_START_Z 0x89A4 |
||
1298 | #define VGT_COMPUTE_INDEX 0x89A8 |
||
1299 | #define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC |
||
1300 | #define VGT_HS_OFFCHIP_PARAM 0x89B0 |
||
1301 | |||
1302 | #define DB_DEBUG 0x9830 |
||
1303 | #define DB_DEBUG2 0x9834 |
||
1304 | #define DB_DEBUG3 0x9838 |
||
1305 | #define DB_DEBUG4 0x983C |
||
1306 | #define DB_WATERMARKS 0x9854 |
||
1963 | serge | 1307 | #define DB_DEPTH_CONTROL 0x28800 |
2997 | Serge | 1308 | #define R_028800_DB_DEPTH_CONTROL 0x028800 |
1309 | #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) |
||
1310 | #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) |
||
1311 | #define C_028800_STENCIL_ENABLE 0xFFFFFFFE |
||
1312 | #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) |
||
1313 | #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) |
||
1314 | #define C_028800_Z_ENABLE 0xFFFFFFFD |
||
1315 | #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) |
||
1316 | #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) |
||
1317 | #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB |
||
1318 | #define S_028800_ZFUNC(x) (((x) & 0x7) << 4) |
||
1319 | #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) |
||
1320 | #define C_028800_ZFUNC 0xFFFFFF8F |
||
1321 | #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) |
||
1322 | #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) |
||
1323 | #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F |
||
1324 | #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) |
||
1325 | #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) |
||
1326 | #define C_028800_STENCILFUNC 0xFFFFF8FF |
||
1327 | #define V_028800_STENCILFUNC_NEVER 0x00000000 |
||
1328 | #define V_028800_STENCILFUNC_LESS 0x00000001 |
||
1329 | #define V_028800_STENCILFUNC_EQUAL 0x00000002 |
||
1330 | #define V_028800_STENCILFUNC_LEQUAL 0x00000003 |
||
1331 | #define V_028800_STENCILFUNC_GREATER 0x00000004 |
||
1332 | #define V_028800_STENCILFUNC_NOTEQUAL 0x00000005 |
||
1333 | #define V_028800_STENCILFUNC_GEQUAL 0x00000006 |
||
1334 | #define V_028800_STENCILFUNC_ALWAYS 0x00000007 |
||
1335 | #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) |
||
1336 | #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) |
||
1337 | #define C_028800_STENCILFAIL 0xFFFFC7FF |
||
1338 | #define V_028800_STENCIL_KEEP 0x00000000 |
||
1339 | #define V_028800_STENCIL_ZERO 0x00000001 |
||
1340 | #define V_028800_STENCIL_REPLACE 0x00000002 |
||
1341 | #define V_028800_STENCIL_INCR 0x00000003 |
||
1342 | #define V_028800_STENCIL_DECR 0x00000004 |
||
1343 | #define V_028800_STENCIL_INVERT 0x00000005 |
||
1344 | #define V_028800_STENCIL_INCR_WRAP 0x00000006 |
||
1345 | #define V_028800_STENCIL_DECR_WRAP 0x00000007 |
||
1346 | #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) |
||
1347 | #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) |
||
1348 | #define C_028800_STENCILZPASS 0xFFFE3FFF |
||
1349 | #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) |
||
1350 | #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) |
||
1351 | #define C_028800_STENCILZFAIL 0xFFF1FFFF |
||
1352 | #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) |
||
1353 | #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) |
||
1354 | #define C_028800_STENCILFUNC_BF 0xFF8FFFFF |
||
1355 | #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) |
||
1356 | #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) |
||
1357 | #define C_028800_STENCILFAIL_BF 0xFC7FFFFF |
||
1358 | #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) |
||
1359 | #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) |
||
1360 | #define C_028800_STENCILZPASS_BF 0xE3FFFFFF |
||
1361 | #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) |
||
1362 | #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) |
||
1363 | #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF |
||
1963 | serge | 1364 | #define DB_DEPTH_VIEW 0x28008 |
2997 | Serge | 1365 | #define R_028008_DB_DEPTH_VIEW 0x00028008 |
1366 | #define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0) |
||
1367 | #define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF) |
||
1368 | #define C_028008_SLICE_START 0xFFFFF800 |
||
1369 | #define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13) |
||
1370 | #define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF) |
||
1371 | #define C_028008_SLICE_MAX 0xFF001FFF |
||
1963 | serge | 1372 | #define DB_HTILE_DATA_BASE 0x28014 |
2997 | Serge | 1373 | #define DB_HTILE_SURFACE 0x28abc |
1374 | #define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0) |
||
1375 | #define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1) |
||
1376 | #define C_028ABC_HTILE_WIDTH 0xFFFFFFFE |
||
1377 | #define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1) |
||
1378 | #define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) |
||
1379 | #define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD |
||
1380 | #define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1) |
||
1963 | serge | 1381 | #define DB_Z_INFO 0x28040 |
1382 | # define Z_ARRAY_MODE(x) ((x) << 4) |
||
2997 | Serge | 1383 | # define DB_TILE_SPLIT(x) (((x) & 0x7) << 8) |
1384 | # define DB_NUM_BANKS(x) (((x) & 0x3) << 12) |
||
1385 | # define DB_BANK_WIDTH(x) (((x) & 0x3) << 16) |
||
1386 | # define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20) |
||
1387 | # define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) |
||
1388 | #define R_028040_DB_Z_INFO 0x028040 |
||
1389 | #define S_028040_FORMAT(x) (((x) & 0x3) << 0) |
||
1390 | #define G_028040_FORMAT(x) (((x) >> 0) & 0x3) |
||
1391 | #define C_028040_FORMAT 0xFFFFFFFC |
||
1392 | #define V_028040_Z_INVALID 0x00000000 |
||
1393 | #define V_028040_Z_16 0x00000001 |
||
1394 | #define V_028040_Z_24 0x00000002 |
||
1395 | #define V_028040_Z_32_FLOAT 0x00000003 |
||
1396 | #define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4) |
||
1397 | #define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF) |
||
1398 | #define C_028040_ARRAY_MODE 0xFFFFFF0F |
||
1399 | #define S_028040_READ_SIZE(x) (((x) & 0x1) << 28) |
||
1400 | #define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1) |
||
1401 | #define C_028040_READ_SIZE 0xEFFFFFFF |
||
1402 | #define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29) |
||
1403 | #define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1) |
||
1404 | #define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF |
||
1405 | #define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) |
||
1406 | #define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) |
||
1407 | #define C_028040_ZRANGE_PRECISION 0x7FFFFFFF |
||
1408 | #define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8) |
||
1409 | #define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7) |
||
1410 | #define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12) |
||
1411 | #define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3) |
||
1412 | #define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16) |
||
1413 | #define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3) |
||
1414 | #define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20) |
||
1415 | #define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3) |
||
1416 | #define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) |
||
1417 | #define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3) |
||
1963 | serge | 1418 | #define DB_STENCIL_INFO 0x28044 |
2997 | Serge | 1419 | #define R_028044_DB_STENCIL_INFO 0x028044 |
1420 | #define S_028044_FORMAT(x) (((x) & 0x1) << 0) |
||
1421 | #define G_028044_FORMAT(x) (((x) >> 0) & 0x1) |
||
1422 | #define C_028044_FORMAT 0xFFFFFFFE |
||
1423 | #define V_028044_STENCIL_INVALID 0 |
||
1424 | #define V_028044_STENCIL_8 1 |
||
1425 | #define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7) |
||
1963 | serge | 1426 | #define DB_Z_READ_BASE 0x28048 |
1427 | #define DB_STENCIL_READ_BASE 0x2804c |
||
1428 | #define DB_Z_WRITE_BASE 0x28050 |
||
1429 | #define DB_STENCIL_WRITE_BASE 0x28054 |
||
1430 | #define DB_DEPTH_SIZE 0x28058 |
||
2997 | Serge | 1431 | #define R_028058_DB_DEPTH_SIZE 0x028058 |
1432 | #define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) |
||
1433 | #define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) |
||
1434 | #define C_028058_PITCH_TILE_MAX 0xFFFFF800 |
||
1435 | #define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11) |
||
1436 | #define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF) |
||
1437 | #define C_028058_HEIGHT_TILE_MAX 0xFFC007FF |
||
1438 | #define R_02805C_DB_DEPTH_SLICE 0x02805C |
||
1439 | #define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) |
||
1440 | #define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) |
||
1441 | #define C_02805C_SLICE_TILE_MAX 0xFFC00000 |
||
1963 | serge | 1442 | |
1443 | #define SQ_PGM_START_PS 0x28840 |
||
1444 | #define SQ_PGM_START_VS 0x2885c |
||
1445 | #define SQ_PGM_START_GS 0x28874 |
||
1446 | #define SQ_PGM_START_ES 0x2888c |
||
1447 | #define SQ_PGM_START_FS 0x288a4 |
||
1448 | #define SQ_PGM_START_HS 0x288b8 |
||
1449 | #define SQ_PGM_START_LS 0x288d0 |
||
1450 | |||
2997 | Serge | 1451 | #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 |
1452 | #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 |
||
1453 | #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 |
||
1454 | #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 |
||
1455 | #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 |
||
1456 | #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 |
||
1457 | #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 |
||
1458 | #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 |
||
1963 | serge | 1459 | #define VGT_STRMOUT_CONFIG 0x28b94 |
1460 | #define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 |
||
1461 | |||
1462 | #define CB_TARGET_MASK 0x28238 |
||
1463 | #define CB_SHADER_MASK 0x2823c |
||
1464 | |||
1465 | #define GDS_ADDR_BASE 0x28720 |
||
1466 | |||
1467 | #define CB_IMMED0_BASE 0x28b9c |
||
1468 | #define CB_IMMED1_BASE 0x28ba0 |
||
1469 | #define CB_IMMED2_BASE 0x28ba4 |
||
1470 | #define CB_IMMED3_BASE 0x28ba8 |
||
1471 | #define CB_IMMED4_BASE 0x28bac |
||
1472 | #define CB_IMMED5_BASE 0x28bb0 |
||
1473 | #define CB_IMMED6_BASE 0x28bb4 |
||
1474 | #define CB_IMMED7_BASE 0x28bb8 |
||
1475 | #define CB_IMMED8_BASE 0x28bbc |
||
1476 | #define CB_IMMED9_BASE 0x28bc0 |
||
1477 | #define CB_IMMED10_BASE 0x28bc4 |
||
1478 | #define CB_IMMED11_BASE 0x28bc8 |
||
1479 | |||
1480 | /* all 12 CB blocks have these regs */ |
||
1481 | #define CB_COLOR0_BASE 0x28c60 |
||
1482 | #define CB_COLOR0_PITCH 0x28c64 |
||
1483 | #define CB_COLOR0_SLICE 0x28c68 |
||
1484 | #define CB_COLOR0_VIEW 0x28c6c |
||
2997 | Serge | 1485 | #define R_028C6C_CB_COLOR0_VIEW 0x00028C6C |
1486 | #define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0) |
||
1487 | #define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF) |
||
1488 | #define C_028C6C_SLICE_START 0xFFFFF800 |
||
1489 | #define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13) |
||
1490 | #define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF) |
||
1491 | #define C_028C6C_SLICE_MAX 0xFF001FFF |
||
1492 | #define R_028C70_CB_COLOR0_INFO 0x028C70 |
||
1493 | #define S_028C70_ENDIAN(x) (((x) & 0x3) << 0) |
||
1494 | #define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3) |
||
1495 | #define C_028C70_ENDIAN 0xFFFFFFFC |
||
1496 | #define S_028C70_FORMAT(x) (((x) & 0x3F) << 2) |
||
1497 | #define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F) |
||
1498 | #define C_028C70_FORMAT 0xFFFFFF03 |
||
1499 | #define V_028C70_COLOR_INVALID 0x00000000 |
||
1500 | #define V_028C70_COLOR_8 0x00000001 |
||
1501 | #define V_028C70_COLOR_4_4 0x00000002 |
||
1502 | #define V_028C70_COLOR_3_3_2 0x00000003 |
||
1503 | #define V_028C70_COLOR_16 0x00000005 |
||
1504 | #define V_028C70_COLOR_16_FLOAT 0x00000006 |
||
1505 | #define V_028C70_COLOR_8_8 0x00000007 |
||
1506 | #define V_028C70_COLOR_5_6_5 0x00000008 |
||
1507 | #define V_028C70_COLOR_6_5_5 0x00000009 |
||
1508 | #define V_028C70_COLOR_1_5_5_5 0x0000000A |
||
1509 | #define V_028C70_COLOR_4_4_4_4 0x0000000B |
||
1510 | #define V_028C70_COLOR_5_5_5_1 0x0000000C |
||
1511 | #define V_028C70_COLOR_32 0x0000000D |
||
1512 | #define V_028C70_COLOR_32_FLOAT 0x0000000E |
||
1513 | #define V_028C70_COLOR_16_16 0x0000000F |
||
1514 | #define V_028C70_COLOR_16_16_FLOAT 0x00000010 |
||
1515 | #define V_028C70_COLOR_8_24 0x00000011 |
||
1516 | #define V_028C70_COLOR_8_24_FLOAT 0x00000012 |
||
1517 | #define V_028C70_COLOR_24_8 0x00000013 |
||
1518 | #define V_028C70_COLOR_24_8_FLOAT 0x00000014 |
||
1519 | #define V_028C70_COLOR_10_11_11 0x00000015 |
||
1520 | #define V_028C70_COLOR_10_11_11_FLOAT 0x00000016 |
||
1521 | #define V_028C70_COLOR_11_11_10 0x00000017 |
||
1522 | #define V_028C70_COLOR_11_11_10_FLOAT 0x00000018 |
||
1523 | #define V_028C70_COLOR_2_10_10_10 0x00000019 |
||
1524 | #define V_028C70_COLOR_8_8_8_8 0x0000001A |
||
1525 | #define V_028C70_COLOR_10_10_10_2 0x0000001B |
||
1526 | #define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C |
||
1527 | #define V_028C70_COLOR_32_32 0x0000001D |
||
1528 | #define V_028C70_COLOR_32_32_FLOAT 0x0000001E |
||
1529 | #define V_028C70_COLOR_16_16_16_16 0x0000001F |
||
1530 | #define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020 |
||
1531 | #define V_028C70_COLOR_32_32_32_32 0x00000022 |
||
1532 | #define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023 |
||
1533 | #define V_028C70_COLOR_32_32_32_FLOAT 0x00000030 |
||
1534 | #define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8) |
||
1535 | #define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF) |
||
1536 | #define C_028C70_ARRAY_MODE 0xFFFFF0FF |
||
1537 | #define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000 |
||
1538 | #define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001 |
||
1539 | #define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002 |
||
1540 | #define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004 |
||
1541 | #define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12) |
||
1542 | #define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7) |
||
1543 | #define C_028C70_NUMBER_TYPE 0xFFFF8FFF |
||
1544 | #define V_028C70_NUMBER_UNORM 0x00000000 |
||
1545 | #define V_028C70_NUMBER_SNORM 0x00000001 |
||
1546 | #define V_028C70_NUMBER_USCALED 0x00000002 |
||
1547 | #define V_028C70_NUMBER_SSCALED 0x00000003 |
||
1548 | #define V_028C70_NUMBER_UINT 0x00000004 |
||
1549 | #define V_028C70_NUMBER_SINT 0x00000005 |
||
1550 | #define V_028C70_NUMBER_SRGB 0x00000006 |
||
1551 | #define V_028C70_NUMBER_FLOAT 0x00000007 |
||
1552 | #define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15) |
||
1553 | #define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3) |
||
1554 | #define C_028C70_COMP_SWAP 0xFFFE7FFF |
||
1555 | #define V_028C70_SWAP_STD 0x00000000 |
||
1556 | #define V_028C70_SWAP_ALT 0x00000001 |
||
1557 | #define V_028C70_SWAP_STD_REV 0x00000002 |
||
1558 | #define V_028C70_SWAP_ALT_REV 0x00000003 |
||
1559 | #define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17) |
||
1560 | #define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1) |
||
1561 | #define C_028C70_FAST_CLEAR 0xFFFDFFFF |
||
1562 | #define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18) |
||
1563 | #define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3) |
||
1564 | #define C_028C70_COMPRESSION 0xFFF3FFFF |
||
1565 | #define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19) |
||
1566 | #define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1) |
||
1567 | #define C_028C70_BLEND_CLAMP 0xFFF7FFFF |
||
1568 | #define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20) |
||
1569 | #define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1) |
||
1570 | #define C_028C70_BLEND_BYPASS 0xFFEFFFFF |
||
1571 | #define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21) |
||
1572 | #define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1) |
||
1573 | #define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF |
||
1574 | #define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22) |
||
1575 | #define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1) |
||
1576 | #define C_028C70_ROUND_MODE 0xFFBFFFFF |
||
1577 | #define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23) |
||
1578 | #define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1) |
||
1579 | #define C_028C70_TILE_COMPACT 0xFF7FFFFF |
||
1580 | #define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24) |
||
1581 | #define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3) |
||
1582 | #define C_028C70_SOURCE_FORMAT 0xFCFFFFFF |
||
1583 | #define V_028C70_EXPORT_4C_32BPC 0x0 |
||
1584 | #define V_028C70_EXPORT_4C_16BPC 0x1 |
||
1585 | #define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */ |
||
1586 | #define S_028C70_RAT(x) (((x) & 0x1) << 26) |
||
1587 | #define G_028C70_RAT(x) (((x) >> 26) & 0x1) |
||
1588 | #define C_028C70_RAT 0xFBFFFFFF |
||
1589 | #define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27) |
||
1590 | #define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7) |
||
1591 | #define C_028C70_RESOURCE_TYPE 0xC7FFFFFF |
||
1592 | |||
1963 | serge | 1593 | #define CB_COLOR0_INFO 0x28c70 |
2997 | Serge | 1594 | # define CB_FORMAT(x) ((x) << 2) |
1963 | serge | 1595 | # define CB_ARRAY_MODE(x) ((x) << 8) |
1596 | # define ARRAY_LINEAR_GENERAL 0 |
||
1597 | # define ARRAY_LINEAR_ALIGNED 1 |
||
1598 | # define ARRAY_1D_TILED_THIN1 2 |
||
1599 | # define ARRAY_2D_TILED_THIN1 4 |
||
2997 | Serge | 1600 | # define CB_SOURCE_FORMAT(x) ((x) << 24) |
1601 | # define CB_SF_EXPORT_FULL 0 |
||
1602 | # define CB_SF_EXPORT_NORM 1 |
||
1603 | #define R_028C74_CB_COLOR0_ATTRIB 0x028C74 |
||
1604 | #define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4) |
||
1605 | #define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1) |
||
1606 | #define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF |
||
1607 | #define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5) |
||
1608 | #define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf) |
||
1609 | #define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10) |
||
1610 | #define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3) |
||
1611 | #define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13) |
||
1612 | #define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3) |
||
1613 | #define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16) |
||
1614 | #define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3) |
||
1615 | #define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) |
||
1616 | #define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3) |
||
1963 | serge | 1617 | #define CB_COLOR0_ATTRIB 0x28c74 |
2997 | Serge | 1618 | # define CB_TILE_SPLIT(x) (((x) & 0x7) << 5) |
1619 | # define ADDR_SURF_TILE_SPLIT_64B 0 |
||
1620 | # define ADDR_SURF_TILE_SPLIT_128B 1 |
||
1621 | # define ADDR_SURF_TILE_SPLIT_256B 2 |
||
1622 | # define ADDR_SURF_TILE_SPLIT_512B 3 |
||
1623 | # define ADDR_SURF_TILE_SPLIT_1KB 4 |
||
1624 | # define ADDR_SURF_TILE_SPLIT_2KB 5 |
||
1625 | # define ADDR_SURF_TILE_SPLIT_4KB 6 |
||
1626 | # define CB_NUM_BANKS(x) (((x) & 0x3) << 10) |
||
1627 | # define ADDR_SURF_2_BANK 0 |
||
1628 | # define ADDR_SURF_4_BANK 1 |
||
1629 | # define ADDR_SURF_8_BANK 2 |
||
1630 | # define ADDR_SURF_16_BANK 3 |
||
1631 | # define CB_BANK_WIDTH(x) (((x) & 0x3) << 13) |
||
1632 | # define ADDR_SURF_BANK_WIDTH_1 0 |
||
1633 | # define ADDR_SURF_BANK_WIDTH_2 1 |
||
1634 | # define ADDR_SURF_BANK_WIDTH_4 2 |
||
1635 | # define ADDR_SURF_BANK_WIDTH_8 3 |
||
1636 | # define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16) |
||
1637 | # define ADDR_SURF_BANK_HEIGHT_1 0 |
||
1638 | # define ADDR_SURF_BANK_HEIGHT_2 1 |
||
1639 | # define ADDR_SURF_BANK_HEIGHT_4 2 |
||
1640 | # define ADDR_SURF_BANK_HEIGHT_8 3 |
||
1641 | # define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) |
||
1963 | serge | 1642 | #define CB_COLOR0_DIM 0x28c78 |
1643 | /* only CB0-7 blocks have these regs */ |
||
1644 | #define CB_COLOR0_CMASK 0x28c7c |
||
1645 | #define CB_COLOR0_CMASK_SLICE 0x28c80 |
||
1646 | #define CB_COLOR0_FMASK 0x28c84 |
||
1647 | #define CB_COLOR0_FMASK_SLICE 0x28c88 |
||
1648 | #define CB_COLOR0_CLEAR_WORD0 0x28c8c |
||
1649 | #define CB_COLOR0_CLEAR_WORD1 0x28c90 |
||
1650 | #define CB_COLOR0_CLEAR_WORD2 0x28c94 |
||
1651 | #define CB_COLOR0_CLEAR_WORD3 0x28c98 |
||
1652 | |||
1653 | #define CB_COLOR1_BASE 0x28c9c |
||
1654 | #define CB_COLOR2_BASE 0x28cd8 |
||
1655 | #define CB_COLOR3_BASE 0x28d14 |
||
1656 | #define CB_COLOR4_BASE 0x28d50 |
||
1657 | #define CB_COLOR5_BASE 0x28d8c |
||
1658 | #define CB_COLOR6_BASE 0x28dc8 |
||
1659 | #define CB_COLOR7_BASE 0x28e04 |
||
1660 | #define CB_COLOR8_BASE 0x28e40 |
||
1661 | #define CB_COLOR9_BASE 0x28e5c |
||
1662 | #define CB_COLOR10_BASE 0x28e78 |
||
1663 | #define CB_COLOR11_BASE 0x28e94 |
||
1664 | |||
1665 | #define CB_COLOR1_PITCH 0x28ca0 |
||
1666 | #define CB_COLOR2_PITCH 0x28cdc |
||
1667 | #define CB_COLOR3_PITCH 0x28d18 |
||
1668 | #define CB_COLOR4_PITCH 0x28d54 |
||
1669 | #define CB_COLOR5_PITCH 0x28d90 |
||
1670 | #define CB_COLOR6_PITCH 0x28dcc |
||
1671 | #define CB_COLOR7_PITCH 0x28e08 |
||
1672 | #define CB_COLOR8_PITCH 0x28e44 |
||
1673 | #define CB_COLOR9_PITCH 0x28e60 |
||
1674 | #define CB_COLOR10_PITCH 0x28e7c |
||
1675 | #define CB_COLOR11_PITCH 0x28e98 |
||
1676 | |||
1677 | #define CB_COLOR1_SLICE 0x28ca4 |
||
1678 | #define CB_COLOR2_SLICE 0x28ce0 |
||
1679 | #define CB_COLOR3_SLICE 0x28d1c |
||
1680 | #define CB_COLOR4_SLICE 0x28d58 |
||
1681 | #define CB_COLOR5_SLICE 0x28d94 |
||
1682 | #define CB_COLOR6_SLICE 0x28dd0 |
||
1683 | #define CB_COLOR7_SLICE 0x28e0c |
||
1684 | #define CB_COLOR8_SLICE 0x28e48 |
||
1685 | #define CB_COLOR9_SLICE 0x28e64 |
||
1686 | #define CB_COLOR10_SLICE 0x28e80 |
||
1687 | #define CB_COLOR11_SLICE 0x28e9c |
||
1688 | |||
1689 | #define CB_COLOR1_VIEW 0x28ca8 |
||
1690 | #define CB_COLOR2_VIEW 0x28ce4 |
||
1691 | #define CB_COLOR3_VIEW 0x28d20 |
||
1692 | #define CB_COLOR4_VIEW 0x28d5c |
||
1693 | #define CB_COLOR5_VIEW 0x28d98 |
||
1694 | #define CB_COLOR6_VIEW 0x28dd4 |
||
1695 | #define CB_COLOR7_VIEW 0x28e10 |
||
1696 | #define CB_COLOR8_VIEW 0x28e4c |
||
1697 | #define CB_COLOR9_VIEW 0x28e68 |
||
1698 | #define CB_COLOR10_VIEW 0x28e84 |
||
1699 | #define CB_COLOR11_VIEW 0x28ea0 |
||
1700 | |||
1701 | #define CB_COLOR1_INFO 0x28cac |
||
1702 | #define CB_COLOR2_INFO 0x28ce8 |
||
1703 | #define CB_COLOR3_INFO 0x28d24 |
||
1704 | #define CB_COLOR4_INFO 0x28d60 |
||
1705 | #define CB_COLOR5_INFO 0x28d9c |
||
1706 | #define CB_COLOR6_INFO 0x28dd8 |
||
1707 | #define CB_COLOR7_INFO 0x28e14 |
||
1708 | #define CB_COLOR8_INFO 0x28e50 |
||
1709 | #define CB_COLOR9_INFO 0x28e6c |
||
1710 | #define CB_COLOR10_INFO 0x28e88 |
||
1711 | #define CB_COLOR11_INFO 0x28ea4 |
||
1712 | |||
1713 | #define CB_COLOR1_ATTRIB 0x28cb0 |
||
1714 | #define CB_COLOR2_ATTRIB 0x28cec |
||
1715 | #define CB_COLOR3_ATTRIB 0x28d28 |
||
1716 | #define CB_COLOR4_ATTRIB 0x28d64 |
||
1717 | #define CB_COLOR5_ATTRIB 0x28da0 |
||
1718 | #define CB_COLOR6_ATTRIB 0x28ddc |
||
1719 | #define CB_COLOR7_ATTRIB 0x28e18 |
||
1720 | #define CB_COLOR8_ATTRIB 0x28e54 |
||
1721 | #define CB_COLOR9_ATTRIB 0x28e70 |
||
1722 | #define CB_COLOR10_ATTRIB 0x28e8c |
||
1723 | #define CB_COLOR11_ATTRIB 0x28ea8 |
||
1724 | |||
1725 | #define CB_COLOR1_DIM 0x28cb4 |
||
1726 | #define CB_COLOR2_DIM 0x28cf0 |
||
1727 | #define CB_COLOR3_DIM 0x28d2c |
||
1728 | #define CB_COLOR4_DIM 0x28d68 |
||
1729 | #define CB_COLOR5_DIM 0x28da4 |
||
1730 | #define CB_COLOR6_DIM 0x28de0 |
||
1731 | #define CB_COLOR7_DIM 0x28e1c |
||
1732 | #define CB_COLOR8_DIM 0x28e58 |
||
1733 | #define CB_COLOR9_DIM 0x28e74 |
||
1734 | #define CB_COLOR10_DIM 0x28e90 |
||
1735 | #define CB_COLOR11_DIM 0x28eac |
||
1736 | |||
1737 | #define CB_COLOR1_CMASK 0x28cb8 |
||
1738 | #define CB_COLOR2_CMASK 0x28cf4 |
||
1739 | #define CB_COLOR3_CMASK 0x28d30 |
||
1740 | #define CB_COLOR4_CMASK 0x28d6c |
||
1741 | #define CB_COLOR5_CMASK 0x28da8 |
||
1742 | #define CB_COLOR6_CMASK 0x28de4 |
||
1743 | #define CB_COLOR7_CMASK 0x28e20 |
||
1744 | |||
1745 | #define CB_COLOR1_CMASK_SLICE 0x28cbc |
||
1746 | #define CB_COLOR2_CMASK_SLICE 0x28cf8 |
||
1747 | #define CB_COLOR3_CMASK_SLICE 0x28d34 |
||
1748 | #define CB_COLOR4_CMASK_SLICE 0x28d70 |
||
1749 | #define CB_COLOR5_CMASK_SLICE 0x28dac |
||
1750 | #define CB_COLOR6_CMASK_SLICE 0x28de8 |
||
1751 | #define CB_COLOR7_CMASK_SLICE 0x28e24 |
||
1752 | |||
1753 | #define CB_COLOR1_FMASK 0x28cc0 |
||
1754 | #define CB_COLOR2_FMASK 0x28cfc |
||
1755 | #define CB_COLOR3_FMASK 0x28d38 |
||
1756 | #define CB_COLOR4_FMASK 0x28d74 |
||
1757 | #define CB_COLOR5_FMASK 0x28db0 |
||
1758 | #define CB_COLOR6_FMASK 0x28dec |
||
1759 | #define CB_COLOR7_FMASK 0x28e28 |
||
1760 | |||
1761 | #define CB_COLOR1_FMASK_SLICE 0x28cc4 |
||
1762 | #define CB_COLOR2_FMASK_SLICE 0x28d00 |
||
1763 | #define CB_COLOR3_FMASK_SLICE 0x28d3c |
||
1764 | #define CB_COLOR4_FMASK_SLICE 0x28d78 |
||
1765 | #define CB_COLOR5_FMASK_SLICE 0x28db4 |
||
1766 | #define CB_COLOR6_FMASK_SLICE 0x28df0 |
||
1767 | #define CB_COLOR7_FMASK_SLICE 0x28e2c |
||
1768 | |||
1769 | #define CB_COLOR1_CLEAR_WORD0 0x28cc8 |
||
1770 | #define CB_COLOR2_CLEAR_WORD0 0x28d04 |
||
1771 | #define CB_COLOR3_CLEAR_WORD0 0x28d40 |
||
1772 | #define CB_COLOR4_CLEAR_WORD0 0x28d7c |
||
1773 | #define CB_COLOR5_CLEAR_WORD0 0x28db8 |
||
1774 | #define CB_COLOR6_CLEAR_WORD0 0x28df4 |
||
1775 | #define CB_COLOR7_CLEAR_WORD0 0x28e30 |
||
1776 | |||
1777 | #define CB_COLOR1_CLEAR_WORD1 0x28ccc |
||
1778 | #define CB_COLOR2_CLEAR_WORD1 0x28d08 |
||
1779 | #define CB_COLOR3_CLEAR_WORD1 0x28d44 |
||
1780 | #define CB_COLOR4_CLEAR_WORD1 0x28d80 |
||
1781 | #define CB_COLOR5_CLEAR_WORD1 0x28dbc |
||
1782 | #define CB_COLOR6_CLEAR_WORD1 0x28df8 |
||
1783 | #define CB_COLOR7_CLEAR_WORD1 0x28e34 |
||
1784 | |||
1785 | #define CB_COLOR1_CLEAR_WORD2 0x28cd0 |
||
1786 | #define CB_COLOR2_CLEAR_WORD2 0x28d0c |
||
1787 | #define CB_COLOR3_CLEAR_WORD2 0x28d48 |
||
1788 | #define CB_COLOR4_CLEAR_WORD2 0x28d84 |
||
1789 | #define CB_COLOR5_CLEAR_WORD2 0x28dc0 |
||
1790 | #define CB_COLOR6_CLEAR_WORD2 0x28dfc |
||
1791 | #define CB_COLOR7_CLEAR_WORD2 0x28e38 |
||
1792 | |||
1793 | #define CB_COLOR1_CLEAR_WORD3 0x28cd4 |
||
1794 | #define CB_COLOR2_CLEAR_WORD3 0x28d10 |
||
1795 | #define CB_COLOR3_CLEAR_WORD3 0x28d4c |
||
1796 | #define CB_COLOR4_CLEAR_WORD3 0x28d88 |
||
1797 | #define CB_COLOR5_CLEAR_WORD3 0x28dc4 |
||
1798 | #define CB_COLOR6_CLEAR_WORD3 0x28e00 |
||
1799 | #define CB_COLOR7_CLEAR_WORD3 0x28e3c |
||
1800 | |||
1801 | #define SQ_TEX_RESOURCE_WORD0_0 0x30000 |
||
2997 | Serge | 1802 | # define TEX_DIM(x) ((x) << 0) |
1803 | # define SQ_TEX_DIM_1D 0 |
||
1804 | # define SQ_TEX_DIM_2D 1 |
||
1805 | # define SQ_TEX_DIM_3D 2 |
||
1806 | # define SQ_TEX_DIM_CUBEMAP 3 |
||
1807 | # define SQ_TEX_DIM_1D_ARRAY 4 |
||
1808 | # define SQ_TEX_DIM_2D_ARRAY 5 |
||
1809 | # define SQ_TEX_DIM_2D_MSAA 6 |
||
1810 | # define SQ_TEX_DIM_2D_ARRAY_MSAA 7 |
||
1963 | serge | 1811 | #define SQ_TEX_RESOURCE_WORD1_0 0x30004 |
1812 | # define TEX_ARRAY_MODE(x) ((x) << 28) |
||
1813 | #define SQ_TEX_RESOURCE_WORD2_0 0x30008 |
||
1814 | #define SQ_TEX_RESOURCE_WORD3_0 0x3000C |
||
1815 | #define SQ_TEX_RESOURCE_WORD4_0 0x30010 |
||
2997 | Serge | 1816 | # define TEX_DST_SEL_X(x) ((x) << 16) |
1817 | # define TEX_DST_SEL_Y(x) ((x) << 19) |
||
1818 | # define TEX_DST_SEL_Z(x) ((x) << 22) |
||
1819 | # define TEX_DST_SEL_W(x) ((x) << 25) |
||
1820 | # define SQ_SEL_X 0 |
||
1821 | # define SQ_SEL_Y 1 |
||
1822 | # define SQ_SEL_Z 2 |
||
1823 | # define SQ_SEL_W 3 |
||
1824 | # define SQ_SEL_0 4 |
||
1825 | # define SQ_SEL_1 5 |
||
1963 | serge | 1826 | #define SQ_TEX_RESOURCE_WORD5_0 0x30014 |
1827 | #define SQ_TEX_RESOURCE_WORD6_0 0x30018 |
||
2997 | Serge | 1828 | # define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29) |
1963 | serge | 1829 | #define SQ_TEX_RESOURCE_WORD7_0 0x3001c |
2997 | Serge | 1830 | # define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) |
1831 | # define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8) |
||
1832 | # define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10) |
||
1833 | # define TEX_NUM_BANKS(x) (((x) & 0x3) << 16) |
||
1834 | #define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000 |
||
1835 | #define S_030000_DIM(x) (((x) & 0x7) << 0) |
||
1836 | #define G_030000_DIM(x) (((x) >> 0) & 0x7) |
||
1837 | #define C_030000_DIM 0xFFFFFFF8 |
||
1838 | #define V_030000_SQ_TEX_DIM_1D 0x00000000 |
||
1839 | #define V_030000_SQ_TEX_DIM_2D 0x00000001 |
||
1840 | #define V_030000_SQ_TEX_DIM_3D 0x00000002 |
||
1841 | #define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003 |
||
1842 | #define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004 |
||
1843 | #define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005 |
||
1844 | #define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006 |
||
1845 | #define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 |
||
1846 | #define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5) |
||
1847 | #define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1) |
||
1848 | #define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF |
||
1849 | #define S_030000_PITCH(x) (((x) & 0xFFF) << 6) |
||
1850 | #define G_030000_PITCH(x) (((x) >> 6) & 0xFFF) |
||
1851 | #define C_030000_PITCH 0xFFFC003F |
||
1852 | #define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18) |
||
1853 | #define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF) |
||
1854 | #define C_030000_TEX_WIDTH 0x0003FFFF |
||
1855 | #define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004 |
||
1856 | #define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0) |
||
1857 | #define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF) |
||
1858 | #define C_030004_TEX_HEIGHT 0xFFFFC000 |
||
1859 | #define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14) |
||
1860 | #define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF) |
||
1861 | #define C_030004_TEX_DEPTH 0xF8003FFF |
||
1862 | #define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28) |
||
1863 | #define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF) |
||
1864 | #define C_030004_ARRAY_MODE 0x0FFFFFFF |
||
1865 | #define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008 |
||
1866 | #define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) |
||
1867 | #define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) |
||
1868 | #define C_030008_BASE_ADDRESS 0x00000000 |
||
1869 | #define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C |
||
1870 | #define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) |
||
1871 | #define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) |
||
1872 | #define C_03000C_MIP_ADDRESS 0x00000000 |
||
1873 | #define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010 |
||
1874 | #define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) |
||
1875 | #define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) |
||
1876 | #define C_030010_FORMAT_COMP_X 0xFFFFFFFC |
||
1877 | #define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000 |
||
1878 | #define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001 |
||
1879 | #define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002 |
||
1880 | #define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) |
||
1881 | #define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) |
||
1882 | #define C_030010_FORMAT_COMP_Y 0xFFFFFFF3 |
||
1883 | #define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) |
||
1884 | #define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) |
||
1885 | #define C_030010_FORMAT_COMP_Z 0xFFFFFFCF |
||
1886 | #define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) |
||
1887 | #define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) |
||
1888 | #define C_030010_FORMAT_COMP_W 0xFFFFFF3F |
||
1889 | #define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) |
||
1890 | #define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) |
||
1891 | #define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF |
||
1892 | #define V_030010_SQ_NUM_FORMAT_NORM 0x00000000 |
||
1893 | #define V_030010_SQ_NUM_FORMAT_INT 0x00000001 |
||
1894 | #define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002 |
||
1895 | #define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) |
||
1896 | #define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) |
||
1897 | #define C_030010_SRF_MODE_ALL 0xFFFFFBFF |
||
1898 | #define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000 |
||
1899 | #define V_030010_SRF_MODE_NO_ZERO 0x00000001 |
||
1900 | #define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) |
||
1901 | #define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) |
||
1902 | #define C_030010_FORCE_DEGAMMA 0xFFFFF7FF |
||
1903 | #define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) |
||
1904 | #define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) |
||
1905 | #define C_030010_ENDIAN_SWAP 0xFFFFCFFF |
||
1906 | #define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16) |
||
1907 | #define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7) |
||
1908 | #define C_030010_DST_SEL_X 0xFFF8FFFF |
||
1909 | #define V_030010_SQ_SEL_X 0x00000000 |
||
1910 | #define V_030010_SQ_SEL_Y 0x00000001 |
||
1911 | #define V_030010_SQ_SEL_Z 0x00000002 |
||
1912 | #define V_030010_SQ_SEL_W 0x00000003 |
||
1913 | #define V_030010_SQ_SEL_0 0x00000004 |
||
1914 | #define V_030010_SQ_SEL_1 0x00000005 |
||
1915 | #define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19) |
||
1916 | #define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7) |
||
1917 | #define C_030010_DST_SEL_Y 0xFFC7FFFF |
||
1918 | #define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22) |
||
1919 | #define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7) |
||
1920 | #define C_030010_DST_SEL_Z 0xFE3FFFFF |
||
1921 | #define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25) |
||
1922 | #define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7) |
||
1923 | #define C_030010_DST_SEL_W 0xF1FFFFFF |
||
1924 | #define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28) |
||
1925 | #define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF) |
||
1926 | #define C_030010_BASE_LEVEL 0x0FFFFFFF |
||
1927 | #define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014 |
||
1928 | #define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0) |
||
1929 | #define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF) |
||
1930 | #define C_030014_LAST_LEVEL 0xFFFFFFF0 |
||
1931 | #define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) |
||
1932 | #define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) |
||
1933 | #define C_030014_BASE_ARRAY 0xFFFE000F |
||
1934 | #define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) |
||
1935 | #define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) |
||
1936 | #define C_030014_LAST_ARRAY 0xC001FFFF |
||
1937 | #define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018 |
||
1938 | #define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0) |
||
1939 | #define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7) |
||
1940 | #define C_030018_MAX_ANISO 0xFFFFFFF8 |
||
1941 | #define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3) |
||
1942 | #define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7) |
||
1943 | #define C_030018_PERF_MODULATION 0xFFFFFFC7 |
||
1944 | #define S_030018_INTERLACED(x) (((x) & 0x1) << 6) |
||
1945 | #define G_030018_INTERLACED(x) (((x) >> 6) & 0x1) |
||
1946 | #define C_030018_INTERLACED 0xFFFFFFBF |
||
1947 | #define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29) |
||
1948 | #define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7) |
||
1949 | #define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C |
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1950 | #define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) |
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1951 | #define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3) |
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1952 | #define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8) |
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1953 | #define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3) |
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1954 | #define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10) |
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1955 | #define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3) |
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1956 | #define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16) |
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1957 | #define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3) |
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1958 | #define S_03001C_TYPE(x) (((x) & 0x3) << 30) |
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1959 | #define G_03001C_TYPE(x) (((x) >> 30) & 0x3) |
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1960 | #define C_03001C_TYPE 0x3FFFFFFF |
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1961 | #define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000 |
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1962 | #define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001 |
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1963 | #define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002 |
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1964 | #define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003 |
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1965 | #define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0) |
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1966 | #define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F) |
||
1967 | #define C_03001C_DATA_FORMAT 0xFFFFFFC0 |
||
1963 | serge | 1968 | |
2997 | Serge | 1969 | #define SQ_VTX_CONSTANT_WORD0_0 0x30000 |
1970 | #define SQ_VTX_CONSTANT_WORD1_0 0x30004 |
||
1971 | #define SQ_VTX_CONSTANT_WORD2_0 0x30008 |
||
1972 | # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) |
||
1973 | # define SQ_VTXC_STRIDE(x) ((x) << 8) |
||
1974 | # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) |
||
1975 | # define SQ_ENDIAN_NONE 0 |
||
1976 | # define SQ_ENDIAN_8IN16 1 |
||
1977 | # define SQ_ENDIAN_8IN32 2 |
||
1978 | #define SQ_VTX_CONSTANT_WORD3_0 0x3000C |
||
1979 | # define SQ_VTCX_SEL_X(x) ((x) << 3) |
||
1980 | # define SQ_VTCX_SEL_Y(x) ((x) << 6) |
||
1981 | # define SQ_VTCX_SEL_Z(x) ((x) << 9) |
||
1982 | # define SQ_VTCX_SEL_W(x) ((x) << 12) |
||
1983 | #define SQ_VTX_CONSTANT_WORD4_0 0x30010 |
||
1984 | #define SQ_VTX_CONSTANT_WORD5_0 0x30014 |
||
1985 | #define SQ_VTX_CONSTANT_WORD6_0 0x30018 |
||
1986 | #define SQ_VTX_CONSTANT_WORD7_0 0x3001c |
||
1987 | |||
1988 | #define TD_PS_BORDER_COLOR_INDEX 0xA400 |
||
1989 | #define TD_PS_BORDER_COLOR_RED 0xA404 |
||
1990 | #define TD_PS_BORDER_COLOR_GREEN 0xA408 |
||
1991 | #define TD_PS_BORDER_COLOR_BLUE 0xA40C |
||
1992 | #define TD_PS_BORDER_COLOR_ALPHA 0xA410 |
||
1993 | #define TD_VS_BORDER_COLOR_INDEX 0xA414 |
||
1994 | #define TD_VS_BORDER_COLOR_RED 0xA418 |
||
1995 | #define TD_VS_BORDER_COLOR_GREEN 0xA41C |
||
1996 | #define TD_VS_BORDER_COLOR_BLUE 0xA420 |
||
1997 | #define TD_VS_BORDER_COLOR_ALPHA 0xA424 |
||
1998 | #define TD_GS_BORDER_COLOR_INDEX 0xA428 |
||
1999 | #define TD_GS_BORDER_COLOR_RED 0xA42C |
||
2000 | #define TD_GS_BORDER_COLOR_GREEN 0xA430 |
||
2001 | #define TD_GS_BORDER_COLOR_BLUE 0xA434 |
||
2002 | #define TD_GS_BORDER_COLOR_ALPHA 0xA438 |
||
2003 | #define TD_HS_BORDER_COLOR_INDEX 0xA43C |
||
2004 | #define TD_HS_BORDER_COLOR_RED 0xA440 |
||
2005 | #define TD_HS_BORDER_COLOR_GREEN 0xA444 |
||
2006 | #define TD_HS_BORDER_COLOR_BLUE 0xA448 |
||
2007 | #define TD_HS_BORDER_COLOR_ALPHA 0xA44C |
||
2008 | #define TD_LS_BORDER_COLOR_INDEX 0xA450 |
||
2009 | #define TD_LS_BORDER_COLOR_RED 0xA454 |
||
2010 | #define TD_LS_BORDER_COLOR_GREEN 0xA458 |
||
2011 | #define TD_LS_BORDER_COLOR_BLUE 0xA45C |
||
2012 | #define TD_LS_BORDER_COLOR_ALPHA 0xA460 |
||
2013 | #define TD_CS_BORDER_COLOR_INDEX 0xA464 |
||
2014 | #define TD_CS_BORDER_COLOR_RED 0xA468 |
||
2015 | #define TD_CS_BORDER_COLOR_GREEN 0xA46C |
||
2016 | #define TD_CS_BORDER_COLOR_BLUE 0xA470 |
||
2017 | #define TD_CS_BORDER_COLOR_ALPHA 0xA474 |
||
2018 | |||
1963 | serge | 2019 | /* cayman 3D regs */ |
2997 | Serge | 2020 | #define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4 |
2021 | #define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48 |
||
1963 | serge | 2022 | #define CAYMAN_DB_EQAA 0x28804 |
2023 | #define CAYMAN_DB_DEPTH_INFO 0x2803C |
||
2024 | #define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 |
||
2025 | #define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0 |
||
2026 | #define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7 |
||
2160 | serge | 2027 | #define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358 |
1963 | serge | 2028 | /* cayman packet3 addition */ |
2029 | #define CAYMAN_PACKET3_DEALLOC_STATE 0x14 |
||
2030 | |||
3192 | Serge | 2031 | /* DMA regs common on r6xx/r7xx/evergreen/ni */ |
2032 | #define DMA_RB_CNTL 0xd000 |
||
2033 | # define DMA_RB_ENABLE (1 << 0) |
||
2034 | # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ |
||
2035 | # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ |
||
2036 | # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) |
||
2037 | # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ |
||
2038 | # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ |
||
2039 | #define DMA_STATUS_REG 0xd034 |
||
2040 | # define DMA_IDLE (1 << 0) |
||
2041 | |||
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